Class / Patent application number | Description | Number of patent applications / Date published |
712020000 | Multimode (e.g., MIMD to SIMD, etc.) | 26 |
20080250226 | Multi-Mode Register Rename Mechanism for a Highly Threaded Simultaneous Multi-Threaded Microprocessor - A multi-mode register rename mechanism which allows a simultaneous multi-threaded processor to support full out-of-order thread execution when the number of threads is low and in-order thread execution when the number of threads increases. Responsive to changing an execution mode of a processor to operate in in-order thread execution mode, the illustrative embodiments switch a physical register in the data processing system to an architected facility, thereby forming a switched physical register. When an instruction is issued to an execution unit, wherein the issued instruction comprises a thread bit, the thread bit is examined to determine if the instruction accesses an architected facility. If the issued instruction accesses an architected facility, the instruction is executed, and the results of the executed instruction are written to the switched physical register. | 10-09-2008 |
20080263317 | DATAPIPE DESTINATION AND SOURCE DEVICES - An integrated circuit ( | 10-23-2008 |
20080270746 | Method and Device for Performing Switchover Operations and for Comparing Signals in a Computer System Having at Least Two Processing Units - A method and a device for performing switchover operations and for comparing signals in a computer system having at least two processing units, a switchover device being provided, and switchover operations being carried out between at least two operating modes, a comparator being provided, and a first operating mode corresponding to a comparison mode, and a second operating mode corresponding to a performance mode. At least two analog signals of the processing units are compared in such a way that, as a function of these signals, a difference is formed. | 10-30-2008 |
20080270747 | Method and Device for Switching Over Between Operating Modes of a Multi-Processor System Using at Least One External Signal - A method for a switchover in a computer system having at least two execution units, a switchover being performed between at least two operating modes, and a first operating mode corresponding to a comparison mode, and a second operating mode corresponding to a performance mode, wherein the switchover is triggered by at least one signal, which is generated outside the computer system. | 10-30-2008 |
20080270748 | HARDWARE SIMULATION ACCELERATOR DESIGN AND METHOD THAT EXPLOITS A PARALLEL STRUCTURE OF USER MODELS TO SUPPORT A LARGER USER MODEL SIZE - A system and method for design verification and, more particularly, a hardware simulation accelerator design and method that exploits a parallel structure of user models to support a large user model size. The method includes a computer including N number of logic evaluation units (LEUs) that share a common pool of instruction memory (IM). The computer infrastructure is operable to: partition a number of parallel operations in a netlist; and send a same instruction stream of the partitioned number of parallel operations to N number of LEUs from a single IM. The system is a hardware simulation accelerator having a computer infrastructure operable to provide a stream of instructions to multiple LEUs from a single IM. The multiple LEUs are clustered together with multiple IMs such that each LEU is configured to use instructions from any of the multiple IMs thereby allowing a same instruction stream to drive the multiple LEUs. | 10-30-2008 |
20080276068 | IMS network architecture with integrated network elements - An IP multimedia subsystem (IMS) network includes (i) a plurality of network elements that are directly or indirectly interconnected for carrying out communications and (ii) an integrated IMS network control unit interfaced with the other network elements. The control unit integrates three IMS network functions into one network node: a multimedia resource function (MRF) module, which incorporates a multimedia resource function controller (MRFC) and/or one or more multimedia resource function processors (MRFP), e.g., media servers; a media gateway control function (MGCF); and a media gateway (MGW). The external physical interface of the control unit mimics the typical interfaces of the MRF/MRFC, MGCF, and MGW, were they to be provided as separate network elements/nodes. As such, the control unit is both physically and logically transparent to the rest of the network, as relating to the integrated MRF, MGCF, and MGW functions. | 11-06-2008 |
20080282062 | Method and apparatus for loading data and instructions into a computer - A computer array ( | 11-13-2008 |
20080288746 | Executing Multiple Instructions Multiple Data ('MIMD') Programs on a Single Instruction Multiple Data ('SIMD') Machine - Executing MIMD programs on a SIMD machine, the SIMD machine including a plurality of compute nodes, each compute node capable of executing only a single thread of execution, the compute nodes initially configured exclusively for SIMD operations, the SIMD machine further comprising a data communications network, the network comprising synchronous data communications links among the compute nodes, including establishing one or more SIMD partitions, booting one or more SIMD partitions in MIMD mode; establishing a MIMD partition; executing by launcher programs a plurality of MIMD programs on two or more of the compute nodes of the MIMD partition; and re-executing a launcher program by an operating system on a compute node in the MIMD partition upon termination of the MIMD program executed by the launcher program. | 11-20-2008 |
20080288747 | Executing Multiple Instructions Multiple Data ('MIMD') Programs on a Single Instruction Multiple Data ('SIMD') Machine - Executing MIMD programs on a SIMD machine, including establishing SIMD partitions on the SIMD machine; booting SIMD partitions in MIMD mode; executing MIMD programs on the compute nodes of a first SIMD partition booted in MIMD mode; re-executing a launcher program by an operating system on a compute node in the first SIMD partition booted in MIMD mode upon termination of the MIMD program executed by the launcher program; determining by a scheduler that the first SIMD partition booted in MIMD mode is required to establish a new SIMD partition large enough to run a SIMD program that is scheduled for execution; moving by the scheduler data processing operations from the first SIMD partition booted in MIMD mode to the second SIMD partition booted in MIMD mode; and establishing by the scheduler the new SIMD partition. | 11-20-2008 |
20080288748 | Dynamic core switching - A core switching system includes a mode switching module that receives a switch signal to switch operation between a first mode and a second mode. During the first mode, instructions associated with applications are executed by a first asymmetric core, and a second asymmetric core is inactive. During the second mode, the instructions are executed by the second asymmetric core, and the first asymmetric core is inactive. A core activation module stops processing of the applications by the first asymmetric core after interrupts are disabled. A state transfer module transfers a state of the first asymmetric core to the second asymmetric core. The core activation module allows the second asymmetric core to resume execution of the instructions and the interrupts are enabled. | 11-20-2008 |
20090024830 | Executing Multiple Instructions Multiple Data ('MIMD') Programs on a Single Instruction Multiple Data ('SIMD') Machine - Executing Multiple Instructions Multiple Data (‘MIMD’) programs on a Single Instruction Multiple Data (‘SIMD’) machine, the SIMD machine including a plurality of compute nodes, each compute node capable of executing only a single thread of execution, the compute nodes initially configured exclusively for SIMD operations, the SIMD machine further comprising a data communications network, the network comprising synchronous data communications links among the compute nodes, including establishing a SIMD partition comprising a plurality of the compute nodes; booting the SIMD partition in MIMD mode; executing by launcher programs a plurality of MIMD programs on compute nodes in the SIMD partition; and re-executing a launcher program by an operating system on a compute node in the SIMD partition upon termination of the MIMD program executed by the launcher program. | 01-22-2009 |
20090024831 | Executing Multiple Instructions Multiple Data ('MIMD') Programs on a Single Instruction Multiple Data ('SIMD') Machine - Executing MIMD programs on a SIMD machine, including establishing on the SIMD machine a plurality of SIMD partitions; booting a first SIMD partition in MIMD mode; executing, on a compute node of the first SIMD partition booted in MIMD mode, a MIMD accelerator program; executing a SIMD program in a second SIMD partition, one instance of the SIMD program executing on each compute node of the second SIMD partition, each instance of the SIMD program carrying out a portion of the data processing effected by the SIMD program; and accelerating, by an instance of the SIMD program through the MIMD accelerator program, a portion of the data processing of the instance of the SIMD program. | 01-22-2009 |
20090049275 | PROCESSING ELEMENTS, MIXED MODE PARALLEL PROCESSOR SYSTEM, PROCESSING METHOD BY PROCESSING ELEMENTS, MIXED MODE PARALLEL PROCESSOR METHOD, PROCESSING PROGRAM BY PROCESSING ELEMENTS AND MIXED MODE PARALLEL PROCESSING PROGRAM - Disclosed is a mixed mode parallel processor system in which N number of processing elements PEs, capable of performing SIMD operation, are grouped into M (=N÷S) processing units PUs performing MIMD operation. In MIMD operation, P out of S memories in each PU, which S memories inherently belong to the PEs, where P02-19-2009 | |
20100088489 | DATA TRANSFER NETWORK AND CONTROL APPARATUS FOR A SYSTEM WITH AN ARRAY OF PROCESSING ELEMENTS EACH EITHER SELF-OR COMMON CONTROLLED - A processor of SIMD/MIMD dual mode architecture comprises common controlled first processing elements, self-controlled second processing elements and a pipelined (ring) network connecting the first PEs and the second PEs sequentially. An access controller has access control lines, each access control line being connected to each PE of the first and second PEs to control data access timing between each PE and the network. Each PE can be self-controlled or common controlled, such as dual mode SIMD/MIMD architectures, reducing the wiring area requirement. | 04-08-2010 |
20100268912 | THREAD MAPPING IN MULTI-CORE PROCESSORS - Techniques for thread mapping in multi-core processors are disclosed. An example computing system is disclosed having a multi-core processor with a plurality of processor cores. A performance counter may be configured to collect data relating to the performance of the multi-core processor. A core controller may be configured to map threads of execution to the processor cores based at least in part on the data collected by the performance counter. | 10-21-2010 |
20110047348 | PROCESSING ELEMENTS, MIXED MODE PARALLEL PROCESSOR SYSTEM, PROCESSING METHOD BY PROCESSING ELEMENTS, MIXED MODE PARALLEL PROCESSOR METHOD, PROCESSING PROGRAM BY PROCESSING ELEMENTS AND MIXED MODE PARALLEL PROCESSING PROGRAM - Disclosed is a mixed mode parallel processor system in which N number of processing elements PEs, capable of performing SIMD operation, are grouped into M (=N÷S) processing units PUs performing MIMD operation. In MIMD operation, P out of S memories in each PU, which S memories inherently belong to the PEs, where P02-24-2011 | |
20110138151 | PROCESSING ELEMENTS, MIXED MODE PARALLEL PROCESSOR SYSTEM, PROCESSING METHOD BY PROCESSING ELEMENTS, MIXED MODE PARALLEL PROCESSOR METHOD, PROCESSING PROGRAM BY PROCESSING ELEMENTS AND MIXED MODE PARALLEL PROCESSING PROGRAM - Disclosed is a mixed mode parallel processor system in which N number of processing elements PEs, capable of performing SIMD operation, are grouped into M (=N÷S) processing units PUs performing MIMD operation. In MIMD operation, P out of S memories in each PU, which S memories inherently belong to the PEs, where P06-09-2011 | |
20110271076 | Optimizing Task Management - An electronic device includes a processing component and a task manager. The processing component is configurable for one of a single-core processing mode and a multi-core processing mode. The task manager determines a number of tasks running on the electronic device. The processor is configured to one of the single-core processing mode and the multi-core processing mode as a function of the number of tasks. | 11-03-2011 |
20120036336 | INFORMATION PROCESSOR - The present invention provides an information processing apparatus and an integrated circuit which realize parallel execution of different processing systems, and which do not require the provision of a dedicated memory storing instructions for common processing The information processing apparatus comprises: a plurality of processor elements; an instruction memory storing a first program and a second program; and an arbiter interposed between the processor elements and the instruction memory, the arbiter receiving, from each of the processor elements, a request for an instruction, from among instructions included in the first program and the second program, and controlling access to the instruction memory by the processor elements, wherein the arbiter arbitrates requests made by the processor elements when the requests are (i) simultaneous requests for different instructions included in one of the first program and the second program or (ii) simultaneous requests for an instruction included in the first program and an instruction included in the second program, and when two or more of the processor elements simultaneously request a same instruction included in one of the first program and the second program, the arbiter, when judging that the instruction memory is available to the two or more processor elements, outputs the same instruction to the two or more processor elements. | 02-09-2012 |
20120166762 | COMPUTING APPARATUS AND METHOD BASED ON A RECONFIGURABLE SINGLE INSTRUCTION MULTIPLE DATA (SIMD) ARCHITECTURE - Provided are a computing apparatus and method based on SIMD architecture capable of supporting various SIMD widths without wasting resources. The computing apparatus includes a plurality of configurable execution cores (CECs) that have a plurality of execution modes, and a controller for detecting a loop region from a program, determining a Single Instruction Multiple Data (SIMD) width for the detected loop region, and determining an execution mode of the processor according to the determined SIMD width. | 06-28-2012 |
20130091340 | Apparatus and Method for Processing an Instruction Matrix Specifying Parallel and Dependent Operations - A matrix of execution blocks form a set of rows and columns. The rows support parallel execution of instructions and the columns support execution of dependent instructions. The matrix of execution blocks process a single block of instructions specifying parallel and dependent instructions. | 04-11-2013 |
20130166877 | SHAPED REGISTER FILE READS - One embodiment of the present invention sets forth a technique for performing a shaped access of a register file that includes a set of N registers, wherein N is greater than or equal to two. The technique involves, for at least one thread included in a group of threads, receiving a request to access a first amount of data from each register in the set of N registers, and configuring a crossbar to allow the at least one thread to access the first amount of data from each register in the set of N registers. | 06-27-2013 |
20130212356 | METHOD FOR DETERMINING THE STRUCTURE OF A HYBRID COMPUTING SYSTEM - A method comprises measuring the execution time T | 08-15-2013 |
20140331025 | RECONFIGURABLE PROCESSOR AND OPERATION METHOD THEREOF - A reconfigurable processor and an operation method thereof are provided. The reconfigurable processor may include: a controller configured to control operations of a first mode, in which a first portion of a program that does not utilize loop acceleration is processed, and a second mode, in which a second portion for the program that utilizes the loop acceleration is processed, based on whether an instruction to control parallel operations of the first mode and the second mode is executed; and a shared register file configured to transfer data between the first mode and the second mode. | 11-06-2014 |
20150100757 | INCORPORATING A SPATIAL ARRAY INTO ONE OR MORE PROGRAMMABLE PROCESSOR CORES - Functional units disposed in one or more processor cores are communicatively coupled using both a shared bypass network and a switched network. The shared bypass network enables the functional units to be operated conventionally for general processing while the switched network enables specialized processing in which the functional units are configured as a spatial array. In the spatial array configuration, operands produced by one functional unit can only be sent to a subset of functional units to which dependent instructions have been mapped a priori. The functional units may be dynamically reconfigured at runtime to toggle between operating in the general configuration and operating as the spatial array. Information to control the toggling between operating configurations may be provided in instructions received by the functional units. | 04-09-2015 |
20150143081 | PROCESSOR CAPABLE OF SUPPORTING MULTIMODE AND MULTIMODE SUPPORTING METHOD THEREOF - Embodiments include a processor capable of supporting multi-mode and corresponding methods. The processor includes front end units, a number of processing elements more than a number of the front end units; and a controller configured to determine if thread divergence occurs due to conditional branching. If there is thread divergence, the processor may set control information to control processing elements using currently activated front end units. If there is not, the processor may set control information to control processing elements using a currently activated front end unit. | 05-21-2015 |