Class / Patent application number | Description | Number of patent applications / Date published |
712017000 | Application specific | 12 |
20090113170 | Apparatus and Method for Processing an Instruction Matrix Specifying Parallel and Dependent Operations - A matrix of execution blocks form a set of rows and columns. The rows support parallel execution of instructions and the columns support execution of dependent instructions. The matrix of execution blocks process a single block of instructions specifying parallel and dependent instructions. | 04-30-2009 |
20090300324 | ARRAY TYPE PROCESSOR AND DATA PROCESSING SYSTEM - In data path means, processor elements individually execute data processing in accordance with command codes described in a computer program, and switching elements individually control a connection relationship to switch among a plurality of processor elements in accordance with the command codes. When an access to an external memory is made from the data path means, slave memory means generates event data indicative of a task change while temporarily holding access information for executing the access with a delay, and executes the access in place of the data path means. Task changing means changes a task to be executed by the data path means when event data indicative of a task change is generated by the slave memory means. | 12-03-2009 |
20090319755 | Method and Apparatus for High Speed Data Stream Splitter on an Array of Processors - A method and apparatus for processing a stream of data. The apparatus includes an array of processors connected to one another by single drop busses. The data stream is inputed to one of the processors | 12-24-2009 |
20100138633 | Variable clocked heterogeneous serial array processor - A serial array processor may have an execution unit, which is comprised of a multiplicity of single bit arithmetic logic units (ALUs), and which may perform parallel operations on a subset of all the words in memory by serially accessing and processing them, one bit at a time, while an instruction unit of the processor is pre-fetching the next instruction, a word at a time, in a manner orthogonal to the execution unit. | 06-03-2010 |
20100235608 | METHOD AND APPARATUS FOR GAME PHYSICS CONCURRENT COMPUTATIONS - An apparatus for physical properties computation comprising an array processor. The array processor comprises of a plurality of processing elements, said processing elements arranged in a grid. A processing unit (PU) is coupled to the array processor. A local memory is coupled to the PU. The PU broadcasts data to rows of said processing elements in said grid, and performs physical computations in an order of complexity of O((√N) log N). | 09-16-2010 |
20100281236 | APPARATUS AND METHOD FOR TRANSFERRING DATA WITHIN A VECTOR PROCESSOR - An apparatus for processing data may include an array of processing elements (such as an n×m or n×n array of processing elements) configured to simultaneously perform operations on a plurality of data elements using a single instruction. Each processing element in the array may be configured to transfer data directly to at least one neighboring processing element within the array. In selected embodiments, the apparatus may include exchange registers to temporarily store data transferred between neighboring processing elements. | 11-04-2010 |
20110314256 | Data Parallel Programming Model - Described herein are techniques for enabling a programmer to express a call for a data parallel call-site function in a way that is accessible and usable to the typical programmer. With some of the described techniques, an executable program is generated based upon expressions of those data parallel tasks. During execution of the executable program, data is exchanged between non-data parallel (non-DP) capable hardware and DP capable hardware for the invocation of data parallel functions. | 12-22-2011 |
20120047349 | DATA TRANSFER SYSTEM - A data transfer system includes: a plurality of processors; and a plurality of data transfer units that executes a data transfer from one processor to other processor via a plurality of input ports and a plurality of output ports. The data transfer unit includes: an arbitration unit that executes arbitration of conflicting data sent to a same next destination; and a strength information notification unit that sends strength information indicating a number of conflicts of the arbitrated conflicting data to the next destination. The arbitration unit decides a selection ratio, which is a ratio of selecting each of the input ports and receiving the conflicting data from the selected input port, according to a ratio between the input ports in relation to magnitude of the number of conflicts indicated by the strength information received from each of the input ports. | 02-23-2012 |
20120144155 | System Of Rotating Data In A Plurality Of Processing Elements - A method of rotating data in a plurality of processing elements comprises a plurality of shifting operations and a plurality of storing operations, with the shifting and storing operations coordinated to enable a three shears operation to be performed on the data. The plurality of storing operations is responsive to the processing element's positions. | 06-07-2012 |
20120210097 | PROCESSOR, COMPUTATIONAL NODE, PARALLEL COMPUTER SYSTEM, AND ARITHMETIC PROCESSING METHOD - A management unit causes a plurality of processing units to execute a calculation process. A determining unit determines whether a communication time for a communication process of exchanging a calculation result obtained from the calculation process is longer than a calculation time for the calculation process, the communication process being executed between a first computational node including the processor and a second computational node being a different computational node from the first computational node. A control unit limits number of processing units when the determining unit has determined that the communication time is longer than the calculation time. | 08-16-2012 |
20140244972 | METHOD AND APPARATUS FOR GAME PHYSICS CONCURRENT COMPUTATIONS - An apparatus for physical properties computation comprising an array processor. The array processor comprises of a plurality of processing elements, said processing elements arranged in a grid. A processing unit (PU) is coupled to the array processor. A local memory is coupled to the PU. The PU broadcasts data to rows of said processing elements in said grid, and performs physical computations in an order of complexity of O((√N) log N). | 08-28-2014 |
20160055120 | Integrated data processing core and array data processor and method for processing algorithms - An integrated data processing core and a data processor are provided on a single integrated circuit and command sequences are forwarded from the data processing core to be executed on the array data processor wherein the command sequences comprise a group of instructions defining an algorithm. | 02-25-2016 |