Class / Patent application number | Description | Number of patent applications / Date published |
711211000 | Address multiplexing or address bus manipulation | 18 |
20090077344 | Method for bus testing and addressing in mass memory components - A method and apparatus for addressing a plurality of mass memory components coupled to a host device. The memory components can be arranged in a chain or in a ring configuration. In a ring, each memory component receives a bit pattern from the preceding stage and sends a bit pattern to the next stage in consecutive clock periods. Based on the received bit pattern, a recipient component knows the bus width between itself and the sending component. In a chain, each memory component also sends the received bit pattern back to the preceding stage. The memory component can generate its own address by counting clock periods. Alternatively, a recipient component changes its received bit pattern before sending the bit pattern to the next stage. As such, the recipient component knows its address based on the received bit pattern. | 03-19-2009 |
20090089538 | Synchronous Address And Data Multiplexed Mode For SRAM - A synchronous memory system configurable in a multiplexed or non-multiplexed mode. In the multiplexed mode, address and data are provided on a shared bus, and accesses to the memory system are qualified by memory access control signals, including an address strobe signal, a counter enable signal and a counter repeat signal. A read/write control signal is maintained for one cycle after the last valid access command to avoid bus turn-around problems. In the multiplexed mode, chip enable and output enable signals may be constantly activated, thereby simplifying associated printed circuit board design. Different ports of the synchronous memory system can be independently configured to operate in either the multiplexed or non-multiplexed mode. | 04-02-2009 |
20090138673 | INTERNAL MEMORY MAPPED EXTERNAL MEMORY INTERFACE - This is directed to allowing a processor of a device to use ordinary internal memory read and write instructions that read and write to external memory. Thus, the complexities associated with the existing methods of accessing external memory can be avoided. More specifically, an address space portion that does not correspond to any existing internal memory can be defined as associated with an external memory. When access to the external memory is required, the processor can simply issue ordinary internal memory read/write instructions that are addressed to the above mentioned address space. An interface controller can receive the read and write instructions and communicate with an external memory in order to execute them. The controller can then send a result back to the processor (if required) in the format that would be expected from an internal memory access operation. | 05-28-2009 |
20100125716 | RESISTANCE VARIABLE MEMORY DEVICE - A resistance variable memory device includes a resistance variable memory cell array, a data register that prefetches read data of the resistance variable memory cell array, a data output unit that receives the prefetched read data from the data register and outputs the received data, and a page mode setting unit that sets one of a first page mode and a second page mode as a page mode. In the first page mode, the data output unit sequentially reads the read data prefetched in the data register as page addresses are sequentially received, and in the second page mode, the data output unit sequentially reads the read data prefetched in the data register after a start page address among a plurality of page addresses has been received | 05-20-2010 |
20110225390 | Micro-Tile Memory Interfaces - In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control logic is coupled to a plurality of address signal lines, the address decoder, and the mode register. In response to the enable bit and the at least one sub-channel select bit, the control logic selects one or more of the address signal lines to capture independent address information to support independent sub-channel memory accesses into the memory array. The control logic couples the independent address information into the address decoder. | 09-15-2011 |
20120042148 | LINE TERMINATION METHODS AND APPARATUS - Methods and apparatus for termination of signal lines coupled to a number of memory devices are disclosed. One such method includes adjusting an input impedance of one or more terminals of an interface of a memory device in response to the memory device receiving a particular address. One such apparatus includes memory devices configured to selectively adjust an input impedance seen by one or more of the signal lines in response to receiving a particular address. | 02-16-2012 |
20120191943 | DYNAMIC PROTOCOL FOR COMMUNICATING COMMAND AND ADDRESS INFORMATION - A dynamic serialized command and address (CA) protocol with cycle-accurate matching between the PHY interface and the DFI interface is described. This CA protocol facilitates the use of a common memory-controller control logic with different CA bus configurations. With this CA protocol, CA packets for different memory operations have different formats. The size and the position of the CA packets vary relative to boundaries of DFI clock cycles, and the CA packets can extend beyond DFI clock cycle boundaries. In addition, there are at least two possible formats for a read or write memory operation. The appropriate format is selected based on the immediately preceding memory operation. | 07-26-2012 |
20130054937 | APPARATUSES AND METHODS FOR PROVIDING DATA FROM MULTIPLE MEMORIES - Apparatuses and methods for providing data are disclosed. An example apparatus includes a plurality of memories coupled to a data bus. The memories are configured to provide data to the data bus responsive, at least in part, to a first address. The plurality of memories are further configured to provide at least a portion of the data corresponding to the first address to the data bus during a sense operation for a second address provided to the plurality of memories after the first address. Each of the plurality of memories provides data to the data bus corresponding to the first address at different times. Moreover, a plurality of memories may be configured to provide at least 2N bits of data to the data bus responsive, at least in part, to an address, each of the plurality of memories configured to provide N bits of data to the data bus at different times. | 02-28-2013 |
20130073831 | SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM HAVING A REDUCED NUMBER OF TERMINALS ALLOCATED FOR EXTERNALLY ACCESSED ADDRESS - There is provided a semiconductor device having a reduced number of external terminals allocated for address input to receive access from outside, while realizing a high-speed response to an access from outside. The semiconductor device employs, in order to allow other external devices to directly access resources it possesses in its own address space, in an external interface circuit, external terminals which input a part of the address signal required for access from outside, a supplementary register which supplements the upper portion of address information that has been input from the external terminals, a mode register accessible from outside, and an address control circuit which generates an address signal to access the address space in a form based on information input from the external terminals, required supplementary information, and mode information of the mode register. | 03-21-2013 |
20130132705 | DE-INTERLEAVING DEVICE, DE-INTERLEAVING METHOD, DATA TRANSMISSION SYSTEM, AND DATA TRANSMISSION METHOD - A de-interleaving device for de-interleaving an input data block interleaved by storing data of an original data block including R×C′ portions (C′ represents any divisor of R×C) of data in a matrix of R columns×C rows in row-major order and reading the data of the original data block in column-major order includes a memory configured to store R×C portions of data, a write address generator configured to generate write addresses based on a first incremental value, a read address generator configured to generate read addresses other than other than (n×R)+1th read addresses based on the first incremental value and to generate the (n×R)+1th read addresses based on a second incremental value, and a memory interface configured to successively read data from a read address and to successively write data of an input data block to a write address. | 05-23-2013 |
20130132706 | TABLE LOOKUP OPERATION ON MASKED DATA - Processing of masked data using table lookups is described. A mask is applied to input data to generate masked input data. The mask and the masked input data are used in combination to locate an entry in a lookup table. The entry corresponds to a transformed version of the input data. | 05-23-2013 |
20130166875 | WRITE DATA MASK METHOD AND SYSTEM - In various embodiments, dedicated mask pins are eliminated by sending a data mask on address lines of the interface. A memory controller receives a request for a memory write operation from a memory client and determines the granularity of the write data from a write data mask sent by the client. Granularity, as used herein, indicates a quantity of write data to which each bit of the received write data mask applies. In an embodiment, the memory controller generates a particular write command and a particular write data mask based on the granularity of the write data. The write command generated is typically the most efficient of several write commands available, but embodiments are not so limited. The write command is transmitted on command lines of the interface, and the write data mask is transmitted on address lines of the interface. | 06-27-2013 |
20140136812 | TRANSACTIONAL MEMORY THAT PERFORMS AN ALUT 32-BIT LOOKUP OPERATION - A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a memory address, a starting bit position, and a mask size. In response to the command, the TM pulls an input value (IV). The memory address is used to read a word containing multiple result values (RVs) and multiple key values from memory. Each key value is indicates a single RV to be output by the TM. A selecting circuit within the TM uses the starting bit position and mask size to select a portion of the IV. The portion of the IV is a key selector value. A key value is selected based upon the key selector value. A RV is selected based upon the key value. The key value is selected by a key selection circuit. The RV is selected by a result value selection circuit. | 05-15-2014 |
20140195773 | LINE TERMINATION METHODS AND APPARATUS - Methods and apparatus for termination of signal lines coupled to a number of memory devices are disclosed. One such method includes adjusting an input impedance of one or more terminals of an interface of a memory device in response to the memory device receiving a particular address. One such apparatus includes memory devices configured to selectively adjust an input impedance seen by one or more of the signal lines in response to receiving a particular address. | 07-10-2014 |
20140215179 | ADDRESS GENERATOR, ADDRESS GENERATION METHOD, AND ENCAPSULATION-DECAPSULATION DEVICE - An address generator includes a storage device in which one or more second-protocol-family address prefixes are stored, the one or more second-protocol-family address prefixes each corresponding to a corresponding combination of at least a multiplexing identifier and a first-protocol-family address, and a controller configured to read, from the storage device, the second-protocol-family address prefix corresponding to a combination of at least the multiplexing identifier and the first-protocol-family address that is contained in a data block to be transferred via a backbone network to a destination network which uses the first protocol family, the read second-protocol-family address prefix serving as an address prefix for a network that is overlaid with the destination network, and configured to generate a second-protocol-family address containing the first-protocol-family address, the multiplexing identifier, and the read second-protocol-family address prefix, the generated second-protocol-family address serving as a destination address within the backbone network. | 07-31-2014 |
20140215180 | ADAPTABLE DATAPATH FOR A DIGITAL PROCESSING SYSTEM - The present invention includes an adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with minimal, or no, register stores by reconfiguration of the data path. Predetermined kernels can be configured during a setup phase so that the RXN can efficiently execute, e.g., Discrete Cosine Transform (DCT), Fast-Fourier Transform (FFT) and other operations. Other features are provided. | 07-31-2014 |
20140258676 | APPARATUSES AND METHODS FOR PROVIDING DATA FROM MULTIPLE MEMORIES - Apparatuses and methods for providing data are disclosed. An example apparatus includes a plurality of memories coupled to a data bus. The memories provide data to the data bus responsive, at least in part, to a first address. The plurality of memories further provide at least a portion of the data corresponding to the first address to the data bus during a sense operation for a second address provided to the plurality of memories after the first address. Each of the plurality of memories provides data to the data bus corresponding to the first address at different times. Moreover, a plurality of memories may provide at least 2N bits of data to the data bus responsive, at least in part, to an address, each of the plurality of memories provide N bits of data to the data bus at different times. | 09-11-2014 |
20140310503 | MEMORY INTERLEAVING ON MEMORY CHANNELS - A memory interleaver includes a channel selection unit to receive a system memory address for a memory request. The interleaver also includes a local memory address computation unit and a de-multiplexer. The channel selection unit examines a predetermined plurality (n) of bits in a memory address of a memory transaction and assigns the memory transaction to one of a plurality of memory channels in a multi-channel memory unit based on a state of the predetermined plurality of bits. Preferably, 2 | 10-16-2014 |