Class / Patent application number | Description | Number of patent applications / Date published |
711209000 | Including plural logical address spaces, pages, segments, blocks | 74 |
20080244218 | SYSTEM AND PROGRAM PRODUCT FOR CACHING WEB CONTENT - The invention provides a system and program product for caching dynamic portal pages without changing the existing caching proxy infrastructure or the transportation protocol used by providing an advanced caching component. An advanced caching component provides the functionality that additional dynamic page specific cache information is provided as part of the response including the portal page. Each component in the portal that dynamically contributes page fragments to be aggregated to a portal page provides dynamic component specific cache information which includes component specific cache scope and expiration values. | 10-02-2008 |
20080250223 | FLASH MEMORY ALLOCATION FOR IMPROVED PERFORMANCE AND ENDURANCE - A flash storage device having improved write performance is provided. The device includes a storage block having a plurality of physical pages and a controller for mapping the plurality of physical pages to a plurality of logical addresses and for writing data to the plurality of physical pages. When updating data previously written to one of the plurality of logical addresses, the controller is configured to write the updated data to a second physical page which is mapped to the logical address. Each of the logical addresses may be associated with a pointer field, which is for storing a pointer value indicating the invalidity of a physical page and/or the location of another physical page. | 10-09-2008 |
20080270742 | SYSTEM AND METHOD FOR STORAGE STRUCTURE REORGANIZATION - A method and system to reorganize a storage structure by generating correlation data that represents relationships between storage blocks of a storage structure, generating a block allocation scheme for the storage structure, determining a block reorganization operation, performing the block reorganization operation, and updating a virtual map. In certain embodiments, the system may include multiple host computers, a data storage subsystem, and multiple storage structures. The storage structures may include a hard disk, an array of hard disks, an IBM TotalStorage™ system, and a hierarchical storage system with RAID. | 10-30-2008 |
20080294869 | Systems For Optimizing Page Selection In Flash-Memory Devices - The present invention discloses a computer-readable storage medium having computer-readable code embodied on the computer-readable storage medium, the computer-readable code including: program code for interleaving fast-reading data and filler data in fast pages and slow pages, respectively. A computer-readable storage medium having computer-readable code embodied on the computer-readable storage medium, the computer-readable code including: program code for reconstructing a data object from data stored only in designated pages. Preferably, the designated pages are fast pages or slow pages. A computer-readable storage medium having computer-readable code embodied on the computer-readable storage medium, the computer-readable code including: program code for at least one data object configured to be stored in fast pages and slow pages, wherein initial pages of at least one data object are stored only in primary pages, and the subsequent pages of at least one data object are stored only in secondary pages. | 11-27-2008 |
20080307191 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR MANAGING THE STORAGE OF DATA - The present invention provides for a method, system, and computer program product for managing the storage of data. Data is selectively compressed based on a pre-defined compression policy and metadata is stored for physical storage blocks. A stored compression policy identifies at least one criterion for compression, and physical blocks of data meeting the compression policy are identified. A physical block is selected as a source block for data compression, and one or more physical locations are selected as target locations. Data is read from the source block, compressed, and written to the target locations. Metadata is updated to indicate a mapping between the target locations and the virtual blocks previously mapped to the source block. Extra storage capacity can be freed up until more physical storage is ordered and installed, while more important data, such as recently or frequently accessed data, is retained in an uncompressed and accessible state. | 12-11-2008 |
20080320270 | Data read-and-write controlling device - In a data read-and-write controlling device, without waiting for confirmation that data is written in a RAM, data is written in a WER and an ADR, and at the same time, address information of the data is written in the RAM write-information table. That is, the data read-and-write controlling device associates an address retained at a data register of a write controlling unit with the value (a write request is present=“1”) of a write request that makes a request for writing data in the RAM, the value being retained in a write request register, and then causes the result to be stored in the RAM write-information table as the address information. | 12-25-2008 |
20090019256 | Memory transaction handling in a data processing apparatus - A data processing apparatus is provided comprising a memory, memory management unit and identification circuitry for identifying a predetermined type of data access transaction within a plurality of received data access transactions. The memory management unit is responsive to the predetermined type of data access transaction to both permit completion of a data access and to cause an exception to be raised despite completion of the data access having been permitted. | 01-15-2009 |
20090063810 | Computing Device with Automated Page Based RAM Shadowing, and Method of Operation - Where a computing device is provided with executable programs in relatively slow non-volatile memory, such as ROM, the device performance can be improved by shadowing, a process by which those programs are copied into relatively fast volatile memory, such as RAM. Shadowing is often inefficient because code is copied that is too infrequently used to benefit from the procedure, wasting processing time and memory. The present invention determines which parts of the slow memory are most frequently accessed, either by profiling or by intimate knowledge of the working of the device, and then shadows only those pages of executable programs whose frequent use warrants it. In a preferred embodiment the most frequently used code areas are clustered together onto certain pages of the non-volatile memory and the least frequently used code areas are clustered onto other pages of non-volatile memory. | 03-05-2009 |
20090070547 | METHOD AND APPARATUS FOR PERFORMING ADDRESS MAPPING IN VIRTUAL FILE SYSTEM OF STORAGE UNIT HAVING A PLURALITY OF NON-VOLATILE DATA STORAGE MEDIA - Provided are a method and apparatus capable of reducing a metadata processing time associated with address mapping performed to input/output burst data at a high speed in a virtual file system of a storage unit having a plurality of non-volatile data storage media. The method includes: determining a block group including a block included in each of a plurality of the non-volatile data storage media; determining an access unit including each page included in the determined block group; and mapping an address of input/output data to the determined block group and the access unit. Therefore, it is possible to significantly reduce an address mapping processing time in the virtual file system that may function as a bottleneck in high-speed input/output in a large-capacity storage unit. | 03-12-2009 |
20090150644 | APPARATUS AND METHOD FOR REDUCING MEMORY ACCESS CONFLICT - Provided are an apparatus and a method of reducing memory access conflict. An apparatus for reducing memory access conflict when a plurality of data processing elements perform simultaneous access to a memory including a plurality of pages, each of which includes a plurality of subpages, the apparatus comprising: an access arbiter mapping a subpage division address corresponding to least significant bits of a memory access address received from each of the data processing elements to another address having a same number of bits as the subpage division address in order for data to be output from each of the subpages in a corresponding page at a time of the simultaneous access; and a selector, prepared for each of the pages, selecting to output one of the data output from the subpages using the mapped results. | 06-11-2009 |
20090150645 | Data processing apparatus and address space protection method - a data processing apparatus includes: an instruction execution section; an instruction protection information storage section that stores instruction protection information for specifying at least one partial address space in an instruction address space for storing instructions executed by the instruction execution section; a data protection information storage section that stores data protection information for specifying multiple partial address spaces in a data address space for storing operands for use in an operation of the instruction execution section; and a protection violation determination section that determines whether to permit access from the instruction execution section based on setting of the instruction and data protection information storage sections. The data processing apparatus selectively invalidates protection of the instruction address space using the instruction protection information storage section, independently of protection of the data address space using the data protection information storage section. | 06-11-2009 |
20090164750 | DATA COMMIT ON MULTICYCLE PASS COMPLETE WITHOUT ERROR - A system and methodology that can prevent errors during data commit on multicycle pass complete associated with a memory is provided. The system employs a transaction buffer component in the memory that receives and temporarily stores information associated with a transaction. A controller component programs subsets of data to respective memory locations once the entire transaction is completed based on the information stored in the transaction buffer component. Thus, if the transaction is interrupted during the transfer of the user data into the buffer, the data stored in the memory is not affected and can still contain the original data when power is regained. If the data transfer between the transaction buffer component and memory array is interrupted, the controller component can complete the transfer from the point of interruption on regaining power and can avoid partial storage of data. | 06-25-2009 |
20090172347 | Data storage device - A storage device includes a memory for storing data in a plurality of logical volumes; a controlling unit for controlling an access to data in accordance with a process comprising the steps of: generating mapping information indicative of a correspondence between logical volume information and recognition information; generating a pseudo logical volume and pseudo logical volume information associated with the pseudo logical volume, the pseudo logical volume being another of the logical volumes; and upon receipt of a command for canceling an assignment of one of the logical volumes to the corresponding recognition information, modifying the mapping information so that recognition information that has been indicative of said one of the logical volumes becomes indicative of the pseudo logical volume information associated with the pseudo logical volume. | 07-02-2009 |
20090193222 | Maintaining Processor Resources During Architectural Events - In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced. | 07-30-2009 |
20090204786 | Storage system, release method, and secondary storage apparatus - The storage system includes page area association information that associates a page area that partitions a storage area in a real volume into predetermined storage areas with a page area that partitions a storage area in a virtual volume into predetermined storage areas; a pair setting unit for pairing a primary virtual volume that stores data from a host computer and a secondary virtual volume to store a copy of the data stored in the primary virtual volume; and a page release unit for releasing association between a page area in the secondary virtual volume and a page area in the secondary real volume associated in advance with the page area in the secondary virtual volume. | 08-13-2009 |
20090222643 | BLOCK MANAGEMENT METHOD FOR FLASH MEMORY AND CONTROLLER AND STORAGE SYSETM USING THE SAME - A block management method for managing a mapping relationship between a plurality of logical blocks and a plurality of physical blocks of a flash memory is provided. The block management method includes: grouping the logical blocks into a plurality of logical zones; recording the mapping relationship between each logical block in each logical zone and all the data physical blocks among the physical blocks in a corresponding logical zone table in unit of the logical zones; and recording all the no-data physical blocks among the physical blocks with a single no-data physical block table. Thereby, the logical blocks can be mapped to all the physical blocks so that frequent access to specific physical blocks can be avoided when a user writes data into a specific logical zone frequently, and accordingly the lifespan of the flash memory can be prolonged. | 09-03-2009 |
20090276605 | Retaining an Association Between a Virtual Address Based Buffer and a User Space Application that Owns the Buffer - Registering memory space for an application is performed. One or more open calls are received from an application to access one or more input/output (I/O) devices. Responsive to receiving the one or more open calls, one or more I/O map and pin calls are sent in order to register memory space for the one or more I/O devices within at least one storage area that will be accessed by the application. A verification is made as to whether the memory space to be registered is associated with the application. Responsive to the memory space being associated with the application, at least one virtual I/O bus address is received for each registered memory space of the one or more I/O devices. At least one I/O command is executed using the at least one virtual I/O bus address without intervention by an operating system or operating system image. | 11-05-2009 |
20100005271 | MEMORY CONTROLLER - A memory controller, on receiving a write request to write write-data into an address of a second memory region issued by a processor, determines whether read-data requested to be read from an address of a first memory region by the processor is matched with the write-data requested to be written into the address of the second memory region, and if the read-data is matched with the write-data, prevents the write-data from being written into the address of the second memory region. | 01-07-2010 |
20100161936 | METHOD AND SYSTEM FOR QUEUING TRANSFERS OF MULTIPLE NON-CONTIGUOUS ADDRESS RANGES WITH A SINGLE COMMAND - Methods and systems for queuing transfers of multiple non-contiguous address ranges within a single command are disclosed. Embodiments of systems include system processors, memory to store data and executable software, and storage devices to receive transfer commands stored in system memory. A host controller interface driver is executed by one or more system processors and collects multiple non-continuous address ranges from storage-device transfer requests and records starting addresses and quantities of data to transfer for each non-continuous range in a tagged command list. It records the number of address ranges in the tagged command list, and a tagged-transfer opcode in a command, and stores the command and the tagged command list in a command table for the storage device. It records a base address for the command table in memory and an offset for the tagged command list into a command header, which is stored in a command queue. | 06-24-2010 |
20100161937 | MEMORY SYSTEM AND COMPUTER SYSTEM - A memory system of the present invention comprises a plurality of first blocks provided for storing user information therein, to which first physical addresses which are not duplicate are assigned, respectively, a plurality of second blocks provided for individually storing therein the first physical addresses of initial defective blocks out of the plurality of first blocks, and a plurality of third blocks provided for individually storing therein the first physical addresses of late defective blocks out of the plurality of first blocks. The memory system further comprises a computing device for obtaining the first physical address corresponding to a logical address on the basis of the logical address, information stored in the second blocks, and information stored in the third blocks. | 06-24-2010 |
20100199065 | METHODS AND APPARATUS FOR PERFORMING EFFICIENT DATA DEDUPLICATION BY METADATA GROUPING - The system is composed of: identifier generation program or logic, identifier confirm program or logic, plural identifier table and metadata mapping table. Data streams or data blocks, files are stored in the data storage system with metadata. The metadata includes additional information of the data and files. For example application, creator, timestamp, OS type, and the like. Data storage system or backup appliance with this invention can have plural groups which are related to the metadata. Each group has an identifier table so that eliminating duplicated data is executed within the group. | 08-05-2010 |
20100217952 | Remapping of Data Addresses for a Large Capacity Victim Cache - Method and apparatus for remapping addresses for a victim cache used in a storage system is provided. The storage system may store data blocks having associated storage system addresses. Blocks may be stored to a main cache and blocks evicted from main cache may be stored in the victim cache, each evicted block having a storage system address and a victim cache address where it is stored in the victim cache. Remapping data for remapping between storage system addresses to victim cache addresses may be stored in remapping data structures. The victim cache may be sub-divided into two or more sub-sections, each sub-section having an associated remapping data structure for storing its remapping data. By sub-dividing the victim cache, the bit size of victim cache addresses stored in the remapping data structures may be reduced, thus reducing the overall storage size of the remapping data for the victim cache. | 08-26-2010 |
20100228946 | METHOD FOR ASSOCIATING PHYSICAL ADDRESS WITH LOGICAL COMMUNICATION ADDRESS IN A MEDIA LIBRARY ASSEMBLY - A method for associating a physical address with a logical communication address for an Ethernet-connected media drive ( | 09-09-2010 |
20100306500 | METHOD AND APPARATUS FOR MANAGING THIN PROVISIONING VOLUME BY USING FILE STORAGE SYSTEM - In one embodiment, a method of operating block-based thin provisioning disk volumes in a system including a first storage system which is connected via a network to a second storage system comprises, in response to a volume creation request to create a thin provisioning disk volume in the first storage system, recording in the first storage system attribute information of the block-based thin provisioning disk volume; specifying a directory path for the block-based thin provisioning disk volume in a file system in the second storage system; and creating a directory for the block-based thin provisioning disk volume under the specified directory path. | 12-02-2010 |
20100325384 | DATA STORAGE MEDIUM ACCESSING METHOD, DATA STORAGE DEVICE AND RECORDING MEDIUM TO PERFORM THE DATA STORAGE MEDIUM ACCESSING METHOD - Provided are a data storage medium accessing method of accessing a data storage medium of a data storage device according to a virtual address (VA), the data storage device to access the data storage medium according to the VA, and a computer readable recording medium having recorded thereon a program to access the data storage medium accessing method. The data storage medium accessing method includes the operations of converting a logical block address (LBA) included in a command received from a host into a VA and converting the VA into a real address of a data storage medium included in a data storage device, and accessing the data storage medium using the real address, wherein the VA is an address that is based on a reserved block of the data storage medium in a data write operation, wherein the reserved block is a valid block that is ready to have data written thereto, and wherein a current location of a head included in the data storage device during the data write operation is set according to the reserved block. | 12-23-2010 |
20110047347 | MAPPING ALIGNMENT - In general, this disclosure is directed to techniques for adjusting a mapping between a logical block address (LBA) space and a physical block address (PBA) space based on offset data associated with a plurality of access requests. According to one aspect, a method includes defining a translation map between a plurality of LBAs and a plurality of PBAs for a data storage device. Each PBA is associated with a sequence of storage slots. The translation map maps each of the LBAs to a PBA and to an index of a storage slot associated with the PBA. The method further includes obtaining offset data for a plurality of access requests associated with the plurality of LBAs. The offset data includes information relating to the indices to which starting LBAs of the access requests are mapped. The method further includes adjusting the translation map based on the offset data. | 02-24-2011 |
20110060888 | STACKED DEVICE REMAPPING AND REPAIR - Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described. | 03-10-2011 |
20110066824 | Method and System for Combining Page Buffer List Entries to Optimize Caching of Translated Addresses - Certain aspects of a method and system for combining page buffer list entries (PBLEs) to optimize caching of translated addresses are disclosed. Aspects of a method may include encoding at least two page buffer list entries in a remote direct memory access (RDMA) memory map into at least two contiguous memory locations by utilizing a remainder of a physical address corresponding to the two page buffer list entries. The first memory location of the two contiguous memory locations may comprise a base address and a contiguous length of the first page buffer list entry. The second memory location of the two contiguous memory locations may comprise a virtual address and a contiguous length of the second page buffer list entry. | 03-17-2011 |
20110099350 | BLOCK BOUNDARY RESOLUTION FOR MISMATCHED LOGICAL AND PHYSICAL BLOCK SIZES - The present disclosure describes various techniques resolving block boundary issues and reconstructing logical blocks in a block access storage device when there are resulting mismatches between logical and physical block sizes or alignments, such that logical blocks span multiple physical block boundaries in irregular ways. In one example, a method comprises the following features: receiving logical block addresses that are associated with a sequence of logical blocks; and locating a first portion of a logical block within a first physical block that is stored in a block access storage device based upon a logical block address of the logical block, wherein the logical block is part of the sequence of logical blocks, and wherein at least two logical blocks within the sequence of logical blocks have different sizes. | 04-28-2011 |
20110131390 | Deduplication of Data on Disk Devices Using Low-Latency Random Read Memory - Deduplication of data using a low-latency random read memory (LLRRM) is described herein. Upon receiving a block, if a matching block stored on a disk device is found, the received block is deduplicated by producing an index to the address location of the matching block. In some embodiments, a matching block having a predetermined threshold number of associated indexes that reference the matching block is transferred to LLRRM, the threshold number being one or greater. Associated indexes may be modified to reflect the new address location in LLRRM. Deduplication may be performed using a mapping mechanism containing mappings of deduplicated blocks to matching blocks, the mappings being used for performing read requests. Deduplication described herein may reduce read latency as LLRRM has relatively low latency in performing random read requests relative to disk devices. | 06-02-2011 |
20110138150 | DATA ALLOCATION IN A DISTRIBUTED STORAGE SYSTEM - A method for data distribution, including distributing logical addresses among an initial set of devices so as provide balanced access, and transferring the data to the devices in accordance with the logical addresses. If a device is added to the initial set, forming an extended set, the logical addresses are redistributed among the extended set so as to cause some logical addresses to be transferred from the devices in the initial set to the additional device. There is substantially no transfer of the logical addresses among the initial set. If a surplus device is removed from the initial set, forming a depleted set, the logical addresses of the surplus device are redistributed among the depleted set. There is substantially no transfer of the logical addresses among the depleted set. In both cases the balanced access is maintained. | 06-09-2011 |
20110153979 | MODIFIED B+ TREE TO STORE NAND MEMORY INDIRECTION MAPS - Embodiments of the invention generally pertain to memory devices and more specifically to reducing the write amplification of memory devices without increasing cache requirements. Embodiments of the present invention may be represented as a modified B+ tree in that said tree comprises a multi-level tree in which all data items are stored in the leaf nodes of the tree. Each non-leaf node in the tree will reference a large number of nodes in the next level down from the tree. Modified B+ trees described herein may be represented as data structures used to map memory device page addresses. The entire modified B+ tree used to map said pages may be stored on the same memory device requiring limited amounts of cache. These embodiments may be utilized by low cost controllers that require good sequential read and write performance without large amounts of cache. | 06-23-2011 |
20110179250 | I/O CONVERSION METHOD AND APPARATUS FOR STORAGE SYSTEM - A storage system comprises a storage apparatus which includes a processor, storage disks, and a memory storing a page mapping table, a page mapping program, and a page-filename mapping program. A file system manages a file tree of files with filenames. The page mapping table specifies a relationship between data volumes in the storage apparatus and the storage disks and the file system, the data volumes each including pages, each page including segments, each segment including sectors. The file tree has for each storage apparatus a hierarchy of directories and files based on relationships among the data volumes, the pages, and the segments. The page mapping program and the page-filename mapping program are executable by the processor to specify, by page, a location of data contained in the I/O request by referring to the page mapping table and the file tree. | 07-21-2011 |
20110219206 | DISPOSITION INSTRUCTIONS FOR EXTENDED ACCESS COMMANDS - A computer system that generates a disposition instruction and an associated access command directed to a block of data at a logical address is described. The disposition instruction and the access command are communicated to a memory system in the computer system via a communication link. Note that the memory system includes different types of memory having different performance characteristics, and the disposition instruction is generated based on the different performance characteristics. In response to the access command, the memory system accesses the block of data at the logical address in a first type of memory in the different types of memory. Furthermore, based on the disposition instruction, the memory system moves the block of data to a second type of memory in the different types of memory to facilitate subsequent accesses to the block of data. | 09-08-2011 |
20110231631 | I/O CONVERSION METHOD AND APPARATUS FOR STORAGE SYSTEM - An aspect of the invention relates to a method of managing data location of plural files in a storage system having a mixed volume which includes plural pages having a fixed page size, the pages belonging to different tiers. The method comprises mapping pages of different tiers to storage devices of different speeds in the storage system, the storage devices including at least a high speed storage device corresponding to a high tier page and a low speed storage device corresponding to a low tier page; and for each file that is a large file which is larger in size than the page size, performing sub-file tiered management on the large file to assign the large file among pages of different tiers according to access characteristics of different portions of the large file by matching the access characteristics of each portion of the large file with a corresponding tier of the assigned page of the mixed volume. | 09-22-2011 |
20110246745 | MANAGEMENT SYSTEM AND COMPUTER SYSTEM MANAGEMENT METHOD - A management system detects a peak time period during which accesses are concentrated on a logical page included in a logical volume, and reallocates this logical page to an appropriate physical page. A management server detects an access variation of each logical volume, and selects a volume with a large access variation as a target volume. The management server measures the access status of each logical page in the target volume, and allocates a logical page to a more appropriate physical page. | 10-06-2011 |
20110252218 | Method and apparatus for choosing storage components within a tier - A method for a storage controller to write a data block to one of a plurality of storage components is provided. The storage controller receives a write request from a host computer, and determines at least a portion of the data block includes a Logical Block Address (LBA) that is not currently mapped to a physical page of storage. The storage controller calculates availability for each storage component within the plurality of storage components, and selects the storage component with a highest calculated availability from the plurality of storage components. The storage controller next determines a next available physical page within the selected storage component. Finally, the storage controller writes the at least a portion of the data block including LBAs that are not currently mapped to a physical page of storage to the next available physical page. | 10-13-2011 |
20110276779 | MEMORY MAPPED INPUT/OUTPUT BUS ADDRESS RANGE TRANSLATION - In an embodiment, a north chip receives a secondary bus identifier that identifies a bus that is immediately downstream from a bridge in a south chip, a subordinate bus identifier that identifies a highest bus identifier of all of buses reachable downstream of the bridge, and an MMIO bus address range that comprises a memory base and a memory limit. The north chip writes a translation of a bridge identifier and a south chip identifier to the secondary bus identifier, the subordinate bus identifier, and the MMIO bus address range. The north chip sends the secondary bus identifier, the subordinate bus identifier, the memory base, and the memory limit to the bridge. The bridge stores the secondary bus identifier, the subordinate bus identifier, the memory base, and the memory limit in the bridge. | 11-10-2011 |
20110289296 | STORAGE APPARATUS AND CONTROL METHOD THEREOF - In order to prevent the degradation of performance of a storage apparatus caused by dynamic reallocation, the storage apparatus performs reassigning to a logical page the first physical page which is the physical page provided by the physical drive in Tier 1 which is the higher hierarchy than Tier 2 which is the hierarchy of the physical drive which provides the second physical page which is the physical page currently assigned to the logical page and, at the same time, by making the contents of the second physical page identical to the contents of the first physical page, performs the first migration for the logical page, associating and managing the second physical page and the first physical page and, when performing the second migration by reassigning the physical page provided by the physical drive in Tier 2 to the logical page to which the first physical page is assigned, and performs the second migration by reassigning the relevant second physical page to the logical page again when the second physical page is associated with the first physical page. | 11-24-2011 |
20110307682 | BLOCK MANAGEMENT FOR MASS STORAGE - An embodiment of the present invention includes a nonvolatile memory system comprising nonvolatile memory for storing sector information, the nonvolatile memory being organized into blocks with each block including a plurality of sectors, each sector identified by a logical block address and for storing sector information. A controller is coupled to the nonvolatile memory for writing sector information to the latter and for updating the sector information, wherein upon updating sector information, the controller writes to the next free or available sector(s) of a block such that upon multiple re-writes or updating of sector information, a plurality of blocks are substantially filled with sector information and upon such time, the controller rearranges the updated sector information in sequential order based on their respective logical block addresses thereby increasing system performance and improving manufacturing costs of the controller. | 12-15-2011 |
20120096237 | METHOD OF IMPROVING PERFORMANCE OF A DATA STORAGE DEVICE - Methods are provided for efficiently storing data to a data storage device or subsystem. The data storage device may be a Solid-State Device (SSD), and may be implemented as part of a RAID (Redundant Array of Independent Disks) or other subsystem. When existing data is read and updated, and must be re-stored, the data is assembled and stored as if it were new data, and is written in a sequential manner, instead of being written to the same storage location. A newer generation number distinguishes it from the previous version. If the storage subsystem employs data striping, stripe size may be matched with the size of a logical collection of data (e.g., an extent), so that each such logical collection of data is wholly stored on just device in the storage subsystem. Concurrent device access may be supported by concurrently writing substripes of data to each device/extent. | 04-19-2012 |
20120102297 | Storing Corresponding Data Units in a Common Storage Unit - A storage device controller may segregate data units that are typically accessed together to a common storage unit. In one example, a storage device includes a control unit configured to receive a plurality of logical blocks to be stored in the storage device, wherein a first set of addresses comprises logical block addresses (LBAs) of the plurality of logical blocks, and a non-volatile memory configured to store logical blocks in a plurality of storage units, wherein one of the plurality of storage units includes logical blocks corresponding to a second set of addresses. The control unit may determine an intersection of the first set of addresses with the second set of addresses and to store each of the logical blocks having LBAs in the determined intersection of addresses in a common storage unit of the storage device, wherein the common storage unit comprises one of the plurality of storage units. | 04-26-2012 |
20120110300 | DATA MANAGEMENT METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS - A data management method, a memory controller and a memory storage apparatus are provided. The method includes grouping physical units of a rewritable non-volatile memory module into at least a data area and a free area. The method also includes configuring logical units for mapping to the physical units of the data area and writing update data belonging to the logical pages of the logical units orderly into the physical pages of physical units gotten from the free area. The method further includes configuring root units for the logical pages, configuring an entry chain for each of the root units and building entries on the entry chains for recording update information of the updated logical pages, wherein each of the logical pages corresponds to a root unit. Accordingly, the table size for storing the update information is effectively reduced and the time for searching valid data is effectively shortened. | 05-03-2012 |
20120110301 | METHOD OF CREATING A VIRTUAL ADDRESS FOR A DAUGHTER SOFTWARE ENTITY RELATED TO THE CONTEXT OF A MOTHER SOFTWARE ENTITY - A process for creates a virtual address for a software entity called a “daughter” belonging to the context of a software entity called the “mother.” This virtual address includes a series of fields allowing retrieval of the series of fields of the virtual address of the mother software entity and a field unique in the context of the mother software entity. Each series of fields is associated with a single software entity which it defines completely. | 05-03-2012 |
20120124330 | MEMORY SYSTEM - A memory system according to an embodiment of the present invention comprises: a data managing unit | 05-17-2012 |
20120124331 | DATA PROCESSING SYSTEM - The system includes first and second storage systems. The first storage system includes a first control unit managing a plurality of logical units (LUs) and a plurality of first storage devices being controlled to store data by the first control unit, the plurality of LUs including a first type LU and a second type LU, the first type LU corresponding to at least one of the plurality of first storage devices of the first storage system so that data to be stored to the first type LU is stored to the at least one of the plurality of first storage devices of the first storage system, the second type LU mapping to an LU which is managed by a second storage system so that data to be stored to the second type LU is transferred to the LU managed by the second storage system. | 05-17-2012 |
20120137107 | METHOD OF DECAYING HOT DATA - Reserve a plurality of blocks in a flash. Write a plurality of hot data into the plurality of blocks in a cyclic and sequential manner. After completing a cycle of writing data and hot data is to be written into the plurality of blocks, send a logic block address corresponding to hot data of a page to a cold/hot data identifying engine if the hot data of the page of a decay block are not updated. And the cold/hot data identifying engine decays a count of a counter corresponding to the logic block address according to the logic block address. | 05-31-2012 |
20120151180 | DATA WRITING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS - A data writing method for writing updated data from a host into a memory module is provided. Herein, some physical units of the memory module are gotten to be global random physical units for storing data from the host. The method includes determining whether the updated data is sequential data and determining whether a logical page corresponding to the updated data is a start logical page. The method further includes getting a blank physical unit from the physical units as a new global random physical unit and writing the updated data into the new global random physical unit when the updated data is the sequential data and the logical page corresponding to the updated data is the start logical page. Accordingly, the method can write updated data belonging to the same logical unit into the same physical unit, thereby shortening the time for executing write commands. | 06-14-2012 |
20120151181 | INTEGRATED DEVICE, LAYOUT METHOD THEREOF, AND PROGRAM - An integrated device includes at least one data processing device and at least one memory macro accessible by the data processing device. The data processing device and the memory macro are laid out so that a memory address and a power consumption have a correlation. | 06-14-2012 |
20120159117 | DISPLAYING VALUES OF VARIABLES IN A FIRST THREAD MODIFIED BY ANOTHER THREAD - In an embodiment, an address watch is established on a memory address while the execution of a first thread of a program is halted. In response to a second thread modifying memory contents at the memory address, encountering the address watch and halting, a determination is made whether a first variable in the program that represents the memory address is displayed on a user interface for the first thread. If the first variable in the program that represents the memory address is displayed on the user interface for the first thread, the value of the first variable is read and displayed on the user interface of the first thread. | 06-21-2012 |
20120185669 | PROGRAM INSPECTION METHOD AND NON-TRANSITORY, COMPUTER READABLE STORAGE MEDIUM STORING INSPECTION PROGRAM - A method has generating an access address information file from an access-destination address list including addresses of access destinations accessed by a program and access types indicating whether write access or read access is made to the individual addresses, generating a configuration-map constraint information file that includes the plurality of address ranges being included in a memory map that includes access attributes indicating whether read access or write access is permitted in the individual memory areas of the target apparatus, a page ID serving as identification information of the certain address range represented by the page and a constraint represented by an access attribute of the page, and inspecting, for each page ID, whether or not the access type for the page ID included in the access address information file contradicts the constraint represented by the access attribute for the page ID included in the configuration-map constraint information file. | 07-19-2012 |
20120210096 | ARCHITECTURE TO FACILITATE REUSE IN MULTIPLE APPLICATIONS - A method includes generating, from a representation of a first integrated circuit, a representation of a second integrated circuit. The representation of the first integrated circuit includes a plurality of representations of operative memory channel interfaces including a representation of a first operative memory channel physical interface. The representation of the second integrated circuit includes a representation of a pseudo-memory channel physical interface and at least a representation of a second operative memory channel physical interface. The generating includes replacing an instantiation of a first circuit of the representation of the first operative memory channel physical interface with an instantiation of a second circuit. The instantiation of the second circuit is a representation of a circuit that is logically equivalent to a first circuit represented by the instantiation of the first circuit. | 08-16-2012 |
20120246442 | STORAGE DEVICE AND METHOD FOR UPDATING DATA IN A PARTITION OF THE STORAGE DEVICE - A storage device and method for updating data stored in a partition of the storage device are provided. In one embodiment, a storage device is provided that contains a logical-to-physical address map and a memory with a first partition storing original data and a second partition. The storage device receives from a host device (i) a command to write updated data to a first logical address and (ii) a signature for verifying integrity of the updated data, wherein the first logical address is mapped to a physical address of the first partition. The storage device then stores the updated data in the second partition instead of the first partition and attempts to verify the signature of the updated data. If the attempt to verify the signature is successful, the storage device updates the logical-to-physical address map to map the first logical address to a physical address of the second partition. | 09-27-2012 |
20120246443 | INDEPENDENT MANAGEMENT OF DATA AND PARITY LOGICAL BLOCK ADDRESSES - A data storage method includes identifying, in a set of data items associated with respective logical addresses for storage in a memory, a first subset of the logical addresses associated with the data items containing application data, and a second subset of the logical addresses associated with the data items containing parity information that has been calculated over the application data. The data items associated with the first identified subset are stored in one or more first physical memory areas of the memory, and the data items associated with the second identified subset are stored in one or more second physical memory areas of the memory, different from the first physical memory areas. A memory management task is performed independently in the first physical memory areas and in the second physical memory areas. | 09-27-2012 |
20120272039 | RETENTION-VALUE ASSOCITED MEMORY - A memory component or subsystem is provided. The memory comprises one or more memory devices and one or more write controllers within each of the one or more memory devices that each controls memory-device components to write input data values into a plurality of memory cells within a memory device that represents a unit of stored data addressed by a logical-address-space address, the write controller applying a current to the plurality of memory cells during a WRITE operation with a magnitude that corresponds to a retention value associated with the logical-address-space address. | 10-25-2012 |
20120303931 | MEMORY BLOCK SELECTION - The present disclosure includes methods and devices for memory block selection. In one or more embodiments, a memory controller includes control circuitry coupled to one or more memory devices having multiple Groups of planes associated therewith, each Group including at least two planes of physical blocks organized into Super Blocks, with each Super Block including a physical block from each of the at least two planes. The control circuitry is configured to receive a first unassigned logical block address (LBA) associated with a write operation and determine a particular free Super Block within a selected one of the multiple Groups to receive data associated with the write operation. | 11-29-2012 |
20120331267 | METHOD FOR MANAGING A MEMORY APPARATUS - A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: receiving a first access command from a host; analyzing the first access command to obtain a first host address; linking the first host address to a physical block; receiving a second access command from the host; and analyzing the second access command to obtain a second host address. For example, the method may further include: linking the second host address to the physical block, wherein a difference value of the first host address and the second host address is greater than a number of pages of the physical block. In another example, the method may further include: linking the first host address to at least a page of the physical block; and linking the second host address to at least a page of another physical block. | 12-27-2012 |
20130007410 | MULTIPATH STORAGE SYSTEM AND METHOD OF OPERATING THEREOF - There is provided a method of operating a multipath storage system, the method comprises: identifying a primary storage control port configured to be responsible for a given LBA range and a secondary storage control port configured to have secondary responsibility for the given LBA range; reducing, in a manner unaffecting respective inbound I/O operation, outbound I/O operation related to the given LBA range and occurring at the primary storage control port, thereby causing a situation requiring switching all respective I/O requests to an alternating path; analyzing responsive changes in outbound I/O operation related to the given LBA range and occurring at the secondary storage control port, and verifying operability of switching to the alternating path in accordance with the obtained results. Outbound I/O operation can be reduced with the help of a routine configured to identify inbound I/O requests directed to the given LBA range and to put these requests on hold for a delay period, thus giving rise to delayed I/O requests, wherein the delay period is configured to be long enough to enable switching to an alternating path. | 01-03-2013 |
20130024650 | DYNAMIC STORAGE TIERING - A method for dynamic storage tiering may include, but is not limited to: receiving an input/output (I/O) request from a host device; determining whether the I/O request results in a cache hit; and relocating data associated with the I/O request between a higher-performance storage device and lower-performance storage device according to the determination whether the data associated with the I/O request is stored in a cache. | 01-24-2013 |
20130054936 | REMAPPING INOPERABLE MEMORY BLOCKS USING POINTERS - Inoperable bits are determined in a memory block. Rather than abandon the block as inoperable, a data structure is generated that includes at least one memory page pointer that identifies the location of the inoperable bits in the memory block. The data structure is stored in one of a group of memory blocks that are reserved for the data structures. A pointer to the data structure is stored in metadata associated with the memory block with the inoperable bits. When a later memory operation is received for the memory block, the pointer is retrieved from the metadata and the memory page pointers are used to avoid the inoperable bits. | 02-28-2013 |
20130219147 | Multi-Core Online Patching Method and Apparatus - A multi-core online patching method and an apparatus for mapping patch data to a patch area of a shared memory are disclosed. A method of the embodiment of the present invention includes: separating shared global variables and private global variables defined in a patch; mapping the shared global variables to a shared data segment in a patch area by using a mapping mode of a direct memory address, and mapping the private global variables to private data segments in the patch area by using a mapping mode of a variable address specified by a user. The embodiments of the present invention may be used in a multi-core DSP system of telecom-grade software. | 08-22-2013 |
20130254514 | WEAR-LEVELING METHOD, STORAGE DEVICE, AND INFORMATION SYSTEM - Embodiments of the present invention provide a wear-leveling method, a storage device, and an information system, where a storage region is divided into a plurality of storage sub-regions of the same size. The method includes: recording the accumulated number of write operations of each storage sub-region; and when the accumulated number of write operations of any one storage sub-region of the plurality of storage sub-regions reaches a predetermined remapping rate, mapping a logical address of the storage sub-region to a remapping physical address. With the wear-leveling method, the storage device, and the information system in the embodiments of the present invention, a logical address of a local data block on which too many write operations are performed may be evenly mapped to an overall physical storage region, thereby avoiding that local data is too hot and prolonging a service life of a storage medium. | 09-26-2013 |
20130332700 | Cloud Storage Arrangement and Method of Operating Thereof - There is provided a storage arrangement and a method of operating thereof. The storage arrangement comprises a first storage system and one or more second storage systems operatively coupled to the first storage system. First control layer is operable to handle a first logical address space comprising a first logical group characterized by a plurality of logical block addresses; first control layer comprises a first mapping module handling a first mapping structure associated with first logical group. Each second control layer comprises, respectively, a second mapping module handling a second mapping structure associated with first logical group. The first mapping structure is configured to provide mapping between logical addresses related to first logical group and corresponding addresses related to first physical address spaces, and/or to point to respective second mapping structure configured to provide mapping between these logical addresses and corresponding addresses related to respective second physical address spaces. | 12-12-2013 |
20140025924 | STORAGE SYSTEM INCLUDING MULTIPLE STORAGE APPARATUSES AND POOL VIRTUALIZATION METHOD - There are a plurality of storage apparatuses including a first storage apparatus and a second storage apparatus. The first storage apparatus has a virtual volume composed of a plurality of virtual segments. At least the second storage apparatus has a pool composed of a plurality of real pages (real storage areas). The plurality of storage apparatuses each manage one or more pools including at least the pool in the second storage apparatus as one virtual pool. The virtual pool is composed of a plurality of virtual pages, and each virtual page corresponds to any of the real pages. The first storage apparatus receives a write command that specifies an address belonging to an unallocated virtual segment to which no virtual page is allocated, allocates a free virtual page from the virtual pool to the unallocated virtual segment, and writes data accompanying the write command to the real page corresponding to the allocated virtual page. | 01-23-2014 |
20140201496 | RESERVING FIXED AREAS IN REAL STORAGE INCREMENTS - Embodiments of the disclosure include a method for reserving large pages in a large frame area (LFAREA) of a main memory. The method includes pre-scanning a plurality of storage increments and counting a number of available large pages that are online and issuing a message that indicates the number of available large pages. The method also includes receiving and parsing an LFAREA request including a target number of large pages to be reserved. The method further includes calculating an optimal number of large pages to be reserved, based upon the target number of available pages and a system limit. The method includes determining if the LFAREA request is valid and if the LFAREA request can be satisfied and scanning the plurality of the storage increments and reserving the optimal number of pages in the LFAREA. | 07-17-2014 |
20140331024 | Method of Dynamically Adjusting Mapping Manner in Non-Volatile Memory and Non-Volatile Storage Device Using the Same - A method of dynamically adjusting a mapping manner for a non-volatile memory includes mapping a plurality of logical addresses to a plurality of physical addresses by a first mapping unit; storing data in the non-volatile memory by the first mapping unit; and mapping at least one logical address to at least one physical address by a second mapping unit according to the stored data. | 11-06-2014 |
20150106587 | DATA REMAPPING FOR HETEROGENEOUS PROCESSOR - A processor remaps stored data and the corresponding memory addresses of the data for different processing units of a heterogeneous processor. The processor includes a data remap engine that changes the format of the data (that is, how the data is physically arranged in segments of memory) in response to a transfer of the data from system memory to a local memory hierarchy of an accelerated processing module (APM) of the processor. The APM's local memory hierarchy includes an address remap engine that remaps the memory addresses of the data at the local memory hierarchy so that the data can be accessed by routines at the APM that are unaware of the data remapping. By remapping the data, and the corresponding memory addresses, the APM can perform operations on the data more efficiently. | 04-16-2015 |
20150378932 | SYSTEM AND METHOD FOR EXECUTING NATIVE CLIENT CODE IN A STORAGE DEVICE - A system and method for executing user-provided code securely on a solid state drive (SSD) to perform data processing on the SSD. In one embodiment, a user uses a security-oriented cross-compiler to compile user-provided source code for a data processing task on a host computer containing, or otherwise connected to, an SSD. The resulting binary is combined with lists of input and output file identifiers and sent to the SSD. A central processing unit (CPU) on the SSD extracts the binary and the lists of file identifiers. The CPU obtains from the host file system the addresses of storage areas in the SSD containing the data in the input files, reads the input data, executes the binary using a container, and writes the results of the data processing task back to the SSD, in areas corresponding to the output file identifiers. | 12-31-2015 |
20160077975 | PROVISIONING OF EXTERNAL MEMORY - Dynamically provisionable and allocatable memory external to a requesting apparatus may be provided. A request for primary memory may be made by an application executing on a client. An allocation logic unit may determine an allocation strategy in response to the request. As part of the allocation strategy, the allocation logic unit may identify memory appliances on which memory regions are to be allocated. The allocated memory regions may form the primary memory that is allocated to the requesting application. The allocation logic unit may send region allocation requests to region access unit of the respective memory appliances. The memory appliances on which the memory regions are allocated may be external to the client. The application may access the allocated memory regions via client-side access in which one or more processors in the client and/or the memory appliances are bypassed. | 03-17-2016 |
20160085684 | MULTI-LEVEL PAGING AND ADDRESS TRANSLATION IN A NETWORK ENVIRONMENT - An example method for facilitating multi-level paging and address translation in a network environment is provided and includes receiving a request for memory in a physical memory of a network element, associating the request with a first virtual address space, mapping a memory region located in the physical memory to a first window in the first virtual address space, the memory region being also mapped to a second window in a different, second virtual address space, remapping the first window in the first virtual address space to the second window in the second virtual address space, and responding to the request with addresses of the second window in the second virtual address space. | 03-24-2016 |
20160117257 | HARDWARE-BASED ARRAY COMPRESSION - Technologies are generally described herein for compressing an array using hardware-based compression and performing various instructions on the compressed array. Some example technologies may receive an instruction adapted to access an address in an array. The technologies may determine whether address is compressible. If the address is compressible, then the technologies may determine a compressed address of a compressed array based on the address. The compressed array may represent a compressed layout of the array where a reduced size of each compressed element in the compressed array is smaller than an original size of each element in the array. The technologies may access the compressed array at the compressed address in accordance with the instruction. | 04-28-2016 |
20160163381 | MEMORY SYSTEM INCLUDING SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device and a method of operating the same are provided. The method includes determining the number of valid pages of a first memory block as a first count value, determining the number of valid pages of a second memory block as a second count value, applying a weight to the first count value and generating a comparison count value which is greater than the first count value, and defining the first and second memory blocks as a victim block by comparing the comparison count value and the second count value with a threshold value. | 06-09-2016 |
20160378680 | FILE ACCESS METHOD AND RELATED DEVICE - Embodiments of the application provide a file access method. A computing node receives a file open request that carries a file identifier. The computing node obtains an index node of a file that is identified by the file identifier. The computing node further obtains, based on the index node, a physical address space of a memory area in a file storage area, in which the file is stored. The computing node allocates a virtual address space to the file, and recodes a virtual-physical address mapping relationship by using a memory page table. The virtual-physical address mapping relationship includes a mapping relationship between the virtual address space and the physical address space. | 12-29-2016 |
20220138097 | TRANSACTIONAL ALLOCATION AND DEALLOCATION OF BLOCKS IN A BLOCK STORE - Various embodiments set forth techniques for transactional allocation and deallocation of blocks in a block store. A first technique includes sending a first request that causes a non-persistent allocation of a block. The first technique also includes adding a first entry in a log recording the allocation as tentative, sending a second request that causes persistence of the allocation, and adding a second entry in a log recording the allocation as finalized. A second technique includes adding a first entry in a log recording a deallocation of a block, sending a first request that causes the deallocation of the block and causes the block to be unavailable for reallocation in a non-persistent manner, adding a second entry in the log recording that the deallocation is finalized, and sending a second request that causes the block to be made available for reallocation. | 05-05-2022 |