Entries |
Document | Title | Date |
20080209161 | Storage device and method of mapping a nonvolatile memory based on a map history - A non-volatile memory may include a plurality of map blocks for storing a plurality of map units, the map units representing mapping information between physical addresses and logical addresses. A storage device may include such a non-volatile memory. A method of mapping such a non-volatile memory may include writing historical information regarding locations of valid map units among the map units included in map blocks previously allocated among the map blocks when a new map block among the map blocks is allocated, the valid map units representing valid mapping information, and constructing a map table including all of the valid mapping information based on the historical information and a result of searching a map block recently allocated among the map blocks. | 08-28-2008 |
20080215848 | Method and System For Caching Address Translations From Multiple Address Spaces In Virtual Machines - A method of virtualizing memory through shadow page tables that cache translations from multiple guest address spaces in a virtual machine includes a software version of a hardware tagged translation look-aside buffer. Edits to guest page tables are detected by intercepting the creation of guest-writable mappings to guest page tables with translations cached in shadow page tables. The affected cached translations are marked as stale and purged upon an address space switch or an indiscriminate flush of translations by the guest. Thereby, non-stale translations remain cached but stale translations are discarded. The method includes tracking the guest-writable mappings to guest page tables, deferring discovery of such mappings to a guest page table for the first time until a purge of all cached translations when the number of untracked guest page tables exceeds a threshold, and sharing shadow page tables between shadow address spaces and between virtual processors. | 09-04-2008 |
20080222383 | Efficient On-Chip Accelerator Interfaces to Reduce Software Overhead - In one embodiment, a processor comprises execution circuitry and a translation lookaside buffer (TLB) coupled to the execution circuitry. The execution circuitry is configured to execute a store instruction having a data operand; and the execution circuitry is configured to generate a virtual address as part of executing the store instruction. The TLB is coupled to receive the virtual address and configured to translate the virtual address to a first physical address. Additionally, the TLB is coupled to receive the data operand and to translate the data operand to a second physical address. A hardware accelerator is also contemplated in various embodiments, as is a processor coupled to the hardware accelerator, a method, and a computer readable medium storing instruction which, when executed, implement a portion of the method. | 09-11-2008 |
20080222384 | APPARATUS AND METHOD FOR EXECUTING RAPID MEMORY MANAGEMENT UNIT EMULATION AND FULL-SYSTEM SIMULATOR - A method for performing rapid memory management unit emulation of a computer program in a computer system, wherein address injection space of predefined size is allocated in the computer system and a virtual page number and a corresponding physical page number are stored in said address injection space, said method comprising steps of: comparing the virtual page number of the virtual address of a load/store instruction in a code segment in said computer program with the virtual address page number stored in said address injection space; if the two virtual page numbers are the same, then obtaining the corresponding physical address according to the physical page number stored in said address injection space; otherwise, performing address translation lookaside buffer search, that is, TLB search to obtain the corresponding physical address; and reading/writing data from/to said obtained corresponding physical address. The present invention also provides an apparatus and computer program product for implementing the method described above. | 09-11-2008 |
20080222385 | PARAMETER SETTING METHOD AND APPARATUS FOR NETWORK CONTROLLER - A method for setting at least one of parameters of a peripheral device coupled to a host includes: executing a program code stored in a first storage unit of a host to obtain setting data corresponding to the at least one of the parameters; storing the setting data into a second storage unit of the host; generating an indication signal to the peripheral device to indicate that the setting data has been stored in the second storage unit; transferring the setting data from the second storage unit of the host to the peripheral device; and performing a function of the peripheral device according to the setting data. | 09-11-2008 |
20080235487 | Applying quality of service (QoS) to a translation lookaside buffer (TLB) - In one embodiment, the present invention includes a translation lookaside buffer (TLB) having storage locations each including a priority indicator field to store a priority level associated with an agent that requested storage of the data in the TLB, and an identifier field to store an identifier of the agent, where the TLB is apportioned according to a plurality of priority levels. Other embodiments are described and claimed. | 09-25-2008 |
20080256327 | System and Method for Maintaining Page Tables Used During a Logical Partition Migration - An apparatus, program product and method maintains data integrity for a logical partition by enabling nonintrusive switching of page tables used during a migration of the logical partition from a source computer system to a target computer system. A first page table may be configured to store a plurality of page entries made within a logically partitioned environment. A second page table may be used during migration to store one or more page entries generated during the migration. After migration, the processor page table pointer may be transparently switched to point to the first page table. A page entry in the second page table corresponding to a page entry made to the first page table by the logical partition may be invalidated in response to a page table hypervisor call made by the logical partition. In parallel, a plurality of entries generated during the migration of the logical partition in the second page table may be read through and invalidated. This reading through of the entries may be accomplished concurrently with the invalidation of the corresponding page entry in the second page table in response to a page table call made by the logical partition. Moreover, the reading of the entries may be accomplished in intervals and with portions of the plurality of entries. | 10-16-2008 |
20080256328 | Customizable memory indexing functions - Methods and apparatus related to memory indexing. Receiving indications of an indexing function for use with a memory. Performing indexing functions with a processor before addressing a memory location. Referencing a customizable lookup table to determine a memory location. Translating a computer program to control a computer system to use a desired indexing function. Determining desired indexing functions based on performance of a computer system. | 10-16-2008 |
20080282055 | Virtual Translation Lookaside Buffer - A virtual page number lookup request is received at a virtual Translation Lookaside Buffer (TLB), wherein the virtual TLB includes an instruction TLB and a data TLB. A lookup of the virtual page number in the virtual TLB is performed. A physical page number corresponding to the virtual page number in the virtual TLB is returned. | 11-13-2008 |
20080282056 | Hardware memory management unit simulation - Various technologies and techniques are disclosed for concurrently performing address translation data lookups for use by an emulator. On a first thread, a first lookup is performed for address translation data for use by an emulator. On a second thread, a second lookup for the address translation data is concurrently and speculatively performed. The address translation data from a successful lookup from either the first lookup or the second lookup is used to map a simulated physical address to a virtual address of the emulator. For example, the first thread can perform a translation lookaside buffer lookup while the second thread concurrently and speculatively performs a page table entry lookup for the address translation data. | 11-13-2008 |
20080294868 | SYSTEM AND METHOD FOR IDENTIFYING TLB ENTRIES ASSOCIATED WITH A PHYSICAL ADDRESS OF A SPECIFIED RANGE - A system and method for identifying a TLB entry having a physical address that is within a specified range are disclosed. The method includes obtaining a tentative TLB entry from a page table entry and accessing a physical address associated with the tentative TLB entry. The method further includes comparing the physical address of the tentative TLB entry with a predetermined range of addresses. If the physical address is within the finite range of addresses, an exception is invoked. In response to the exception, the physical address and/or an attribute of the tentative TLB entry can be modified. The tentative TLB entry can then be stored in a TLB. | 11-27-2008 |
20080313420 | Managing working set use of a cache via page coloring - A processor cache is indexed by a group of distinct page colors. The use of this cache by different working sets is controlled using page coloring. Translations of virtual addresses of the instructions and/or data of a working set are constrained to physical addresses the page colors of which are in a subgroup of the group of distinct page colors. | 12-18-2008 |
20090006805 | Method and apparatus for supporting address translation in a virtual machine environment - In one embodiment, a method includes receiving control transitioned from a virtual machine (VM) due to a privileged event pertaining to a translation-lookaside buffer (TLB), and determining which entries in a guest translation data structure were modified by the VM. The determination is made based on metadata extracted from a shadow translation data structure maintained by a virtual machine monitor (VMM) and attributes associated with entries in the shadow translation data structure. The method further includes synchronizing entries in the shadow translation data structure that correspond to the modified entries in the guest translation data structure with the modified entries in the guest translation data structure. | 01-01-2009 |
20090013149 | METHOD AND APPARATUS FOR CACHING OF PAGE TRANSLATIONS FOR VIRTUAL MACHINES - A method for caching of page translations for virtual machines includes managing a number of virtual machines using a guest page table of a guest operating system, which provides a first translation from a guest-virtual memory address to a first guest-physical memory address or an invalid entry, and a host page table of a host operating system, which provides a second translation from the first guest-physical memory address to a host-physical memory address or an invalid entry, and managing a cache page table, wherein the cache page table selectively provides a third translation from the guest-virtual memory address to the host-physical memory address, a second guest-physical memory address or an invalid entry. | 01-08-2009 |
20090019253 | PROCESSING SYSTEM IMPLEMENTING VARIABLE PAGE SIZE MEMORY ORGANIZATION - A processing system includes memory management software responsive to changes in a page table. The memory management software consolidates contiguous page table entries into one or more page table entries that have larger memory page sizes. The memory management software updates the entries of a translation lookaside buffer that correspond to the consolidated contiguous page table entries. | 01-15-2009 |
20090019254 | PROCESSING SYSTEM IMPLEMENTING MULTIPLE PAGE SIZE MEMORY ORGANIZATION WITH MULTIPLE TRANSLATION LOOKASIDE BUFFERS HAVING DIFFERING CHARACTERISTICS - A processing system includes memory management software responsive to a translation lookaside buffer miss. The memory management software updates translation lookaside buffer information based on one or more missed virtual addresses. Entries of a first translation lookaside buffer are updated by the memory management software with information corresponding to the missed virtual addresses if memory page size information for the missed virtual addresses meet a first criterion. Entries of a second translation lookaside buffer are updated by the memory management software with information corresponding to the missed virtual addresses if memory page size information for the missed virtual addresses meet a second criterion. The first and second criterion may correspond to first and second memory page sizes supported by the respective translation lookaside buffers. | 01-15-2009 |
20090049272 | METHOD FOR IMPROVING THE PERFORMANCE OF SOFTWARE-MANAGED TLB - Exemplary embodiments of the present invention comprise a method for the utilization of entry-replacement index hint information within a software-managed TLB. The method comprises receiving an address translation request at a TLB and retrieving the address translation information from a page table in the event of a miss lookup event at the TLB. The method further comprises retrieving index replacement hint information from a hardware component, wherein the hardware component is configured to execute a predetermined replacement algorithm and writing the address translation information to a TLB index referenced within the index replacement hint information. | 02-19-2009 |
20090049273 | PHYSICALLY-TAGGED CACHE WITH VIRTUAL FILL BUFFERS - A virtually indexed, physically-tagged cache is combined with one or more virtually-tagged fill-buffers. | 02-19-2009 |
20090070546 | System and Method for Generating Fast Instruction and Data Interrupts for Processor Design Verification and Validation - A system and method for intentionally invaliding translation entry valid bits in order to provoke storage interrupts when executing a test case is presented. Prior to executing the test case, an interrupt handler pseudo-randomly invalidates a number of translation entries included in a translation lookaside buffer (TLB) by changing particular valid bits in order to provoke initial storage interrupts, such as an instruction storage interrupt (ISI) or a data storage interrupt (DSI). Once the processor executes the test case that, in turn, triggers a storage interrupt, the interrupt handler uses an index counter to validate particular valid bits and invalidate other valid bits, thus provoking subsequent storage interrupts. In one embodiment, the interrupt handler also changes valid bits in a page table when the processor executes in a mode that accesses the page table in addition to the TLB. | 03-12-2009 |
20090094434 | NONVOLATILE PROGRAMMABLE LOGIC CIRCUIT - A nonvolatile programmable logic circuit using a ferroelectric memory performs a nonvolatile memory function and an operation function without additional memory devices, thereby reducing power consumption. Also, a nonvolatile ferroelectric memory is applied to a FPGA (Field Programmable Gate Array), thereby preventing leakage of internal data and reducing the area of a chip. | 04-09-2009 |
20090119477 | Configurable Translation Lookaside Buffer - The disclosure includes a method and system of configuring a translation lookaside buffer (TLB). In an embodiment, the TLB includes a first portion and a second portion. The first portion or the second portion may be selectively disabled in response to a value of a TLB configuration indicator. | 05-07-2009 |
20090144519 | Multithreaded Processor with Lock Indicator - Systems and methods including a multithreaded processor with a lock indicator are disclosed. In an embodiment, a system includes means for indicating a lock status of a shared resource in a multithreaded processor. The system includes means for automatically locking the shared resource before processing exception handling instructions associated with the shared resource. The system further includes means for unlocking the shared resource. | 06-04-2009 |
20090158004 | TLB Virtualization Method of Machine Virtualization Device, and Machine Virtualization Program - A TLB virtualization method of a machine virtualization device which, in the case where a TLB is shadowed in a virtualization environment, avoids TLB entry conflicts and is capable of improving the performance of a virtualization environment; wherein a hypervisor is executed on a real machine, an OS is operated on a plurality of virtual machines generated by means of processing based on the hypervisor, TLB entry calculations are carried out using RID values in the virtual machines by means of hypervisor processing, the RID values in the virtual machines used in the TLB entry calculations in the real machine are translated into different values in said plurality of virtual machines, and, further, the values of the bit strings of translated RID values are modified. | 06-18-2009 |
20090172343 | USING A TRANSLATION LOOKASIDE BUFFER TO MANAGE PROTECTED MICRO-CONTEXTS - Embodiments of an invention for using a translation lookaside buffer to manage protected micro-contexts are disclosed. In one embodiment, an apparatus includes an interface and memory management logic. The interface is to perform a transaction to fetch information from a memory. The memory management logic is to translate an untranslated address to a memory address. The memory management logic includes a storage location, a series of translation stages, determination logic, and a translation lookaside buffer. The storage location is to store an address of a data structure for the first translation stage. Each of the translation stages includes translation logic to find an entry in a data structure based on a portion of the untranslated address. Each entry is to store an address of a different data structure for the first translation stage, an address of a data structure for a successive translation stage, or the physical address. The determination logic is to determine whether an entry is storing an address of a different data structure for the first translation stage. The translation lookaside buffer is to store translations. | 07-02-2009 |
20090172344 | METHOD, SYSTEM, AND APPARATUS FOR PAGE SIZING EXTENSION - A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed. | 07-02-2009 |
20090187730 | MAINFRAME STORAGE CONTROLLER AND MAINFRAME VOLUME VIRTUALIZATION METHOD - A storage controller of the present invention is capable of providing a plurality of external volumes to a mainframe as a single virtual volume without lowering write performance. A virtual volume inside a main storage apparatus is associated with a plurality of external volumes inside an external storage apparatus. When the mainframe formats the virtual volume, a control information creation unit of the main storage apparatus creates and stores control information related to the virtual volume. Consequently, it is possible to enhance processing performance when the write size specified by the mainframe coincides with the data size set in the write destination, that is, during a so-called isometric write. | 07-23-2009 |
20090187731 | Method for Address Translation in Virtual Machines - The invention relates to a method for address translation in a system running multiple levels of virtual machines containing a hierarchically organized translation lookaside buffer comprising at least two linked hierarchical sub-units, a first sub-unit comprising a lookaside buffer for some higher level address translation levels, and the second sub-unit comprising a lookaside buffer for some lower level address translation levels, and said second sub-unit being arranged to store TLB index address information of the upper level sub-unit as tag information in its lower level TLB structure, comprising the steps of collecting intermediate address translation results on different virtual machine levels; and buffering the intermediate translation results in the translation lookaside buffer. | 07-23-2009 |
20090210650 | METHOD FOR SERIALIZING TRANSLATION LOOKASIDE BUFFER ACCESS AROUND ADDRESS TRANSLATION PARAMETER MODIFICATION - Embodiments of the invention include a method of synchronizing translation changes in a processor including a translation lookaside buffer, the method including setting a control bit to enable blocking of all fetch requests that miss the translation lookaside buffer without changing a translation state of the current process; if there is at least one pending translation, then waiting for completion of the at least one pending translation; and resetting the control bit. A processor and a computer program product are provided. | 08-20-2009 |
20090216994 | PROCESSOR, METHOD AND COMPUTER PROGRAM PRODUCT FOR FAST SELECTIVE INVALIDATION OF TRANSLATION LOOKASIDE BUFFER - A processor including a microarchitecture adapted for invalidating mapping of at least one logical address to at least one absolute address, includes: at least one translation lookaside buffer (TLB) and a plurality of copies thereof; logic for independent indexing of each copy of the TLB; a plurality of comparators, each comparator associated with a respective output of each TLB set output for each TLB port, wherein each of the comparators is adapted for identifying mappings for invalidation; and logic for invalidating each identified mapping. A method and a computer program product are provided. | 08-27-2009 |
20090216995 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING QUIESCE FILTERING FOR SHARED MEMORY - A system, method and computer program product for providing quiesce filtering for shared memory. The method includes receiving a shared-memory quiesce request at a processor. The request includes a donor zone. The processor includes translation look aside buffer one (TLB | 08-27-2009 |
20090292899 | Data processing apparatus and method for handling address translation for access requests issued by processing circuitry - A data processing apparatus has address translation circuitry which is responsive to an access request specifying a virtual address, to perform a multi-stage address translation process to produce, via at least one intermediate address, a physical address in memory corresponding to the virtual address. The address translation circuitry references a storage unit, with each entry of the storage unit storing address translation information for one or more virtual addresses. Each entry has a field indicating whether the address translation information is consolidated address translation information or partial address translation information. If when processing an access request, it is determined that the relevant entry in the storage unit provides consolidated address translation information, the address translation circuitry produces a physical address directly from the consolidated address translation information. If on the other hand the relevant entry stores partial address translation information, the address translation circuitry produces an intermediate address from the partial address translation information and then performs the remainder of the multi-stage address translation process. Such an approach provides the performance benefits associated with a consolidated entry mechanism within the storage unit, whilst also allowing certain problem cases to be handled correctly and in an efficient manner. | 11-26-2009 |
20090300319 | APPARATUS AND METHOD FOR MEMORY STRUCTURE TO HANDLE TWO LOAD OPERATIONS - An apparatus and method to increase memory bandwidth is presented. In one embodiment, the apparatus comprises a load array having: a first array to store a plurality of load operation entries and a second array to store a second plurality of load operation entries. The apparatus further comprises: a store array having a plurality of store operation entries; a first address generation unit coupled to send a linear address of a first load operation to the first array and to send a linear address of a first store operation to the store array; and a second address generation unit coupled to send a linear address of a second load operation to the second array and to send a linear address of a second store operation to the store array. | 12-03-2009 |
20090327646 | Minimizing TLB Comparison Size - In one embodiment, a system comprises one or more registers configured to store a plurality of values that identify a virtual address space (collectively a tag), a translation lookaside buffer (TLB), and a control unit coupled to the TLB and the one or more registers. The control unit is configured to detect whether or not the tag has changed and in response to a change in the tag, map the changed tag to an identifier having fewer bits than the total number of bits in the tag, and provide the current identifier to the TLB. The TLB is configured to detect a hit/miss in response to the identifier. A similar method is also contemplated. | 12-31-2009 |
20090327647 | Memory Management Unit Directed Access to System Interfaces - A memory management unit (MMU) for servicing transaction requests from one or more processor threads is described. The MMU can include a translation lookaside buffer (TLB). The TLB can include a storage module and a logic circuit. The storage module can store a bit indicating one of a plurality of interfaces. The bit can be associated with a physical address range. The logic circuit can route a physical address within the physical address range to the one of the plurality of interfaces. | 12-31-2009 |
20090327648 | GENERATING MULTIPLE ADDRESS SPACE IDENTIFIERS PER VIRTUAL MACHINE TO SWITCH BETWEEN PROTECTED MICRO-CONTEXTS - Embodiments of an invention for generating multiple address space identifiers per virtual machine to switch between protected micro-contexts are disclosed. In one embodiment, an apparatus includes privileged mode logic, an interface, and memory management logic. The privileged mode logic is to transfer control of the processor among a plurality of virtual machines. The interface is to perform a transaction to fetch information from a memory. The memory management logic is to translate an untranslated address to a memory address. The memory management logic includes a storage location, a series of translation stages, determination logic, and a translation lookaside buffer. The storage location is to store an address of a data structure for the first translation stage. Each of the translation stages includes translation logic to find an entry in a data structure based on a portion of the untranslated address. Each entry is to store an address of a different data structure for the first translation stage, an address of a data structure for a successive translation stage, or the physical address. The determination logic is to determine whether an entry is storing an address of a different data structure for the first translation stage. The translation lookaside buffer is to store translations. Each translation lookaside buffer entry includes an address source identifiers. Each address source identifier is to identify a unique micro-context. Each address source identifier is based on a virtual partition identifier. At least two of the of virtual partition identifiers are associated with one of the virtual machines | 12-31-2009 |
20090327649 | Three-Tiered Translation Lookaside Buffer Hierarchy in a Multithreading Microprocessor - A three-tiered TLB architecture in a multithreading processor that concurrently executes multiple instruction threads is provided. A macro-TLB caches address translation information for memory pages for all the threads. A micro-TLB caches the translation information for a subset of the memory pages cached in the macro-TLB. A respective nano-TLB for each of the threads caches translation information only for the respective thread. The nano-TLBs also include replacement information to indicate which entries in the nano-TLB/micro-TLB hold recently used translation information for the respective thread. Based on the replacement information, recently used information is copied to the nano-TLB if evicted from the micro-TLB. | 12-31-2009 |
20100011188 | MICROPROCESSOR THAT PERFORMS SPECULATIVE TABLEWALKS - A microprocessor performs a speculative page tablewalk. The microprocessor includes a tablewalk engine that determines whether at least one of a predetermined set of conditions exists with respect to characteristics of the page of memory whose physical address specified by a memory access instruction is missing in the TLB, performs operations of the tablewalk in an out-of-order manner with respect to the execution of unretired program instructions older than the memory access instruction while none of the predetermined set of conditions exists, and waits to perform the operations of the tablewalk until the microprocessor has retired all program instructions older than the memory access instruction when at least one of the predetermined set of conditions exists. The predetermined set of conditions may include the tablewalk needing to load information from a strongly-ordered page, update page mapping information, or access a global page. | 01-14-2010 |
20100058025 | METHOD, APPARATUS AND SOFTWARE PRODUCT FOR DISTRIBUTED ADDRESS-CHANNEL CALCULATOR FOR MULTI-CHANNEL MEMORY - A method, apparatus, and computer program product are used for reading from a table that splits a plurality of physical addresses between a plurality of channels. One of the physical addresses is determined based at least partly on a virtual address used by an execution device such as the hardware environment, and based at least partly on information about a channel. Then, the physical address is provided to the execution device. | 03-04-2010 |
20100058026 | LOADING ENTRIES INTO A TLB IN HARDWARE VIA INDIRECT TLB ENTRIES - An enhanced mechanism for loading entries into a translation lookaside buffer (TLB) in hardware via indirect TLB entries. In one embodiment, if no direct TLB entry associated with the given virtual address is found in the TLB, the TLB is checked for an indirect TLB entry associated with the given virtual address. Each indirect TLB entry provides the real address of a page table associated with a specified range of virtual addresses and comprises an array of page table entries. If an indirect TLB entry associated with the given virtual address is found in the TLB, a computed address is generated by combining a real address field from the indirect TLB entry and bits from the given virtual address, a page table entry (PTE) is obtained by reading a word from a memory at the computed address, and the PTE is loaded into the TLB as a direct TLB entry. | 03-04-2010 |
20100095085 | DMA Address Translation in an IOMMU - In an embodiment, an input/output (I/O) memory management unit (IOMMU) comprises at least one memory configured to store translation data; and control logic coupled to the memory and configured to translate an I/O device-generated memory request using the translation data. The translation data corresponds to one or more device table entries in a device table stored in a memory system of a computer system that includes the IOMMU, wherein the device table entry for a given request is selected by an identifier corresponding to the I/O device that generates the request. The translation data further corresponds to one or more I/O page tables, wherein the selected device table entry for the given request includes a pointer to a set of I/O page tables to be used to translate the given request. | 04-15-2010 |
20100100702 | Arithmetic processing apparatus, TLB control method, and information processing apparatus - An arithmetic processing apparatus includes a main TLB that stores therein, as a page table, entries indicating correspondences between virtual and physical addresses, and a micro TLB that stores therein part of the table. The apparatus associates together the physical address stored in the main TLB, the virtual address associated with the physical address, and a context ID included in an address-translation request and registers these associated together in the micro TLB as an entry. When receiving the request, the apparatus does not translate the context ID included in the request into a context value but searches for an entry matching the virtual address and the context ID included in the request. When the entry is searched for and found, the response is the physical address included in the entry. When the entry is searched for and not found, the request is transmitted to the main TLB. | 04-22-2010 |
20100106937 | INDEXING A TRANSLATION LOOKASIDE BUFFER (TLB) - A processor is to comprise a central processing unit (CPU), an address generation unit (AGU), an index generation unit and a translation look-aside buffer (TLB). The CPU of the processor is to generate signal to retrieve instructions from a memory. The AGU is to generate a final linear address and an initial linear address after receiving at least three input source values. An index generation unit coupled to the AGU is to generate a set-index value using the bits of at least the three input source values or the bits of the initial linear address even before the bits of the initial linear address are adjusted for carry. A TLB is to generate a physical address using the final linear address and an entry indexed by the set-index value. | 04-29-2010 |
20100106938 | Arithmetic processing unit and entry control method - An arithmetic processing apparatus includes: a plurality of TLBs holding as entries a portion of a conversion table for conversion of virtual addresses into physical addresses that has been placed in a main memory unit; an entry registration determining unit that, while registering an entry output from the main memory unit in any one of a plurality of TLBs, determines whether an entry has already been registered in an area of a TLB as registration destination; and a relocation control unit that, when the entry registration determining unit determines that an entry has already been registered in the area of the TLB as registration destination, evicts the entry that has already been registered and registers evicted entry in other TLB. | 04-29-2010 |
20100115229 | System And Method For On-the-fly TLB Coalescing - An apparatus and method for coalescing TLB entries on-the-fly at virtual address translation time is disclosed. A search is made for a requested virtual address translation in the VHPT. Further searching is performed for additional VHPT entries meeting certain coalescing and compatibility criteria. The compatible VHPT entries are coalesced and stored in the TLB into a single combined TLB entry. | 05-06-2010 |
20100161935 | RAPID MEMORY BUFFER WRITE STORAGE SYSTEM AND METHOD - Efficient and convenient storage systems and methods are presented. In one embodiment a storage system includes a host for processing information, a memory controller and a memory. The memory controller controls communication of the information between the host and the memory, wherein the memory controller routes data rapidly to a buffer of the memory without buffering in the memory controller. The memory stores the information. The memory includes a buffer for temporarily storing the data while corresponding address information is determined. | 06-24-2010 |
20100185831 | SEMICONDUCTOR INTEGRATED CIRCUIT AND ADDRESS TRANSLATION METHOD - A semiconductor integrated circuit incorporating an address translation section has a micro TLB, a main TLB and a CPU. The CPU reads out, at the time of process switching, a TLB entry having a private mapping of a pre-switching process from the micro TLB, stores the read TLB entry in a corresponding TLB entry storage area in a TLB context storage section having a plurality of TLB context storage areas in each of which a TLB entry having a private mapping of each of a plurality of processes is stored as a context of a TLB, reads out a TLB entry having a private mapping of a post-switching process from the TLB context storage section, and writes the read TLB entry into the main TLB. | 07-22-2010 |
20100199064 | Fast Address Translation for Linear and Circular Modes - The core of this invention is the application of a fast comparison circuit to the problem of address translation. Traditional implementations generate the virtual address and the physical address in series. This invention generates the physical address and virtual address simultaneously. A bitwise operation on the base address, the offset address and each stored virtual address determines whether the base address and offset address sum equals the virtual address without requiring a carry propagate. Circular addressing is implemented in the match determination by masking bits corresponding to the circular address limit. | 08-05-2010 |
20100228944 | Apparatus and Method to Translate Virtual Addresses to Physical Addresses in a Base Plus Offset Addressing Mode - An apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode are disclosed. In an embodiment, a method includes performing a first translation lookaside buffer (TLB) lookup based on a base address value to retrieve a speculative physical address. While performing the TLB lookup based on the base address value, the base address value is added to an offset value to generate an effective address value. The method also includes performing a comparison of the base address value and the effective address value based on a variable page size to determine whether the speculative physical address corresponds to the effective address. | 09-09-2010 |
20100228945 | ACCESS MANAGEMENT TECHNIQUE WITH OPERATION TRANSLATION CAPABILITY - Access management techniques have been developed to specify and facilitate mappings between I/O and host domains in ways that provide flexibility in the form, granularity and/or extent of mappings, attributes and access controls coded relative to a particular I/O domain. In some embodiments of the present invention, operation translations coded relative to a particular logical I/O device, domain or sub-window seek to optimize functionality, isolation or some other figure of merit without regard to needs or limitations of another. In this way, operation translations need not be uniform and need not reduce supported operation semantics to correspond to that of a lowest common denominator I/O device. In some embodiments, the form of mappings (e.g., of operation translations) may be specialized on a per-logical-device basis (or even a per-sub-window basis), thereby offering individual logical I/O devices (or sub-windows thereof) immediate, indexed, and/or untranslated operation mapping frameworks appropriate to their individual requirements or needs. In general, flexibilities and efficiencies afforded in some embodiments of the present invention can be desirable, particularly as the diversity of I/O device types and richness of transaction semantics supported in interconnect fabrics increase. Some embodiments may be leveraged in support of sophisticated system partitions or I/O virtualizations. | 09-09-2010 |
20100241822 | METHOD AND APPARATUS FOR MANAGING TLB - An apparatus and method for managing a translation look-aside buffer (TLB). The TLB is shared by a plurality of jobs. The method including the steps of: obtaining at least one attribute of each job of the plurality of jobs; assigning a priority level to each job according to at least one attribute of each job; and managing the related TLB entries of each job according to the priority level of each job. The present invention also provides an apparatus for managing TLB corresponding to the above method. The method and apparatus according to the present invention provide an efficient use of the shared TLB. | 09-23-2010 |
20100250894 | Explicit data segment boundaries with SCSI I/O referrals - A method for communication between an initiator system and a block storage cluster may include receiving a first command at a first storage system included in a plurality of storage systems of the block storage cluster. The method may also include transmitting a referral response from the first storage system to the initiator system when at least a portion of the data associated in the first command is stored by a second storage system. The method may further include obtaining a segment start value and a corresponding port identifier based on the referral response, and directing a second command to at least a second storage system included in the plurality of storage systems of the block cluster. | 09-30-2010 |
20100250895 | HARDWARE ASSISTANCE FOR SHADOW PAGE TABLE COHERENCE WITH GUEST PAGE MAPPINGS - Some embodiments of the present invention include an execution unit of a processor and a memory management unit interposed between the execution unit and an interface to memory suitable for storage of both guest page tables maintained by a guest operating system and shadow page tables maintained generally in correspondence with the guest page tables by virtualization software. The memory management unit is configured to walk in-memory data structures that encode the shadow page tables, to access entries of the shadow page tables and, based thereon or on a cached representation of page mappings therein, to perform virtual-to-physical address translations relative to memory targets of instructions executed by the execution unit. The memory management unit is responsive to a shadowed write indication coded in association with either an entry of the shadow page tables or a cached representation of a page mapping therein used to perform the virtual-to-physical address translation for a write-type one of the instructions that targets an entry of one of the guest page tables. The memory management unit is configured to complete the memory access of the write-type instruction that targets the guest page table entry and to store in a buffer, information sufficient to allow the virtualization software to later update an entry of the shadow page tables in correspondence therewith. | 09-30-2010 |
20100274987 | MAINTAINING VALIDITY OF CACHED ADDRESS MAPPINGS - A method is provided for creating and maintaining the validity of a cache group including one or more cache elements. Each of the cache elements corresponds to a different address space in a virtual memory of a computer system. Each of the cache elements include one or more caches that store mappings from virtual addresses to data or values that are functions of or dependent upon physical addresses that correspond to the virtual addresses. When there is an address space switch from a first address space to a second address space, the cache group is searched to find the cache element corresponding to the second address space, and that found cache element is made the current cache element for virtual memory access through the cache element. Changes in the page tables are also detected and reflected in the caches of the cache group to maintain the caches up-to-date. | 10-28-2010 |
20100287355 | Dynamic Translation in the Presence of Intermixed Code and Data - A system for translating software in a first format into a second format includes a memory containing the software in the first format and an emulator coupled to the memory configured to translate the software from the first format to the second format. The system also includes a host engine coupled to the emulator and configured to perform instructions in the second format. The emulator is configured to determine whether a store command in the first format stores information to a memory page that includes instructions and to convert the store instruction to a special store instruction in the event that the target of the store instruction does not contain an instruction. | 11-11-2010 |
20100287356 | LARGE MEMORY PAGES FOR SHARED LIBRARIES - A method for loading shared libraries. The method includes receiving an indication of a requirement to load the shared library into the virtual memory and determining that the shared library is a candidate for using shared large pages. Further, the method includes, in response to the determination, storing a text section of the shared library in a shared large page of the virtual memory and storing a data section of the shared library in a page of the virtual memory, where the virtual memory is mapped to a physical memory of the computer, where, within an address space of the virtual memory, a starting address of the text section of the shared library is separated from a starting address of the data section of the shared library by a predefined distance, and where the predefined distance is larger than a size of the large page. | 11-11-2010 |
20100306499 | Translation Lookaside Buffer (TLB) with Reserved Areas for Specific Sources - In an embodiment, a TLB is partitioned into regions. The TLB may be set associative, and each section may include a portion of the locations in each way of the set associative memory. The TLB may reserve at least one of the sections for access by a subset of the request sources that use the TLB. For requests from the subset, the reserved section may be used and a location in the reserved section may be allocated to store a translation for a request from the subset that misses in the TLB. For requests for other request sources, the non-reserved section or sections may be used. In one embodiment, each way of the reserved section may be assigned to a different one of the request sources in the subset. | 12-02-2010 |
20100318761 | PROCESSOR AND METHOD FOR DYNAMIC AND SELECTIVE ALTERATION OF ADDRESS TRANSLATION - Non-intrusive techniques have been developed to dynamically and selectively alter address translations performed by, or for, a processor. For example, in some embodiments, a memory management unit is configured to map from effective addresses in respective effective (or virtual) address spaces to physical addresses in the memory, wherein the mappings performed by the memory management unit are based on address translation entries of an address translation table. For a subset of less than all processes, entry selection logic selects from amongst plural alternative mappings coded in respective ones of the address translation entries. For at least some effective addresses mapped for a particular process of the subset, selection of a particular address translation entry is based on an externally sourced value. In some embodiments, only a subset of effective addresses mapped for the particular process are subject to dynamic runtime alteration of the address translation entry selection. | 12-16-2010 |
20100318762 | Synchronizing A Translation Lookaside Buffer with Page Tables - The translation lookaside buffer (TLB) of a processor is kept in synchronization with a guest page table by use of an indicator referred to as a “T” bit. The T bit of the NPT/EPT entries mapping the guest page table are set when a page walk is performed on the NPT/EPT. When modifications are made to pages mapped by NPT/EPT entries with their T bit set, changes to the TLB are made so that the TLB remains in synchronization with the guest page table. Accordingly, record/replay of virtual machines of virtualized computer systems may be performed reliably with no non-determinism introduced by stale TLBs that fall out of synchronization with the guest page table. | 12-16-2010 |
20100318763 | SYSTEMS AND METHODS FOR UTILIZING AN EXTENDED TRANSLATION LOOK-ASIDE BUFFER HAVING A HYBRID MEMORY STRUCTURE - Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a number of virtual memory addresses corresponding with the physical addresses, the virtual memory address storage including, a set associative memory structure (SAM), and a content addressable memory (CAM) structure; and comparison circuitry for determining whether a requested address is present in the virtual memory address storage, wherein the eTLB is configured to receive an index register for identifying the SAM structure and the CAM structure, and wherein the eTLB is configured to receive an entry register for providing a virtual page number corresponding with the plurality of virtual memory addresses. | 12-16-2010 |
20100332786 | System and Method to Invalidate Obsolete Address Translations - A system and method for invalidating obsolete virtual/real address to physical address translations may employ translation lookaside buffers to cache translations. TLB entries may be invalidated in response to changes in the virtual memory space, and thus may need to be demapped. A non-cacheable unit (NCU) residing on a processor may be configured to receive and manage a global TLB demap request from a thread executing on a core residing on the processor. The NCU may send the request to local cores and/or to NCUs of external processors in a multiprocessor system using a hardware instruction to broadcast to all cores and/or processors or to multicast to designated cores and/or processors. The NCU may track completion of the demap operation across the cores and/or processors using one or more counters, and may send an acknowledgement to the initiator of the demap request when the global demap request has been satisfied. | 12-30-2010 |
20100332787 | System and Method to Manage Address Translation Requests - A system and method for servicing translation lookaside buffer (TLB) misses may manage separate input and output pipelines within a memory management unit. A pending request queue (PRQ) in the input pipeline may include an instruction-related portion storing entries for instruction TLB (ITLB) misses and a data-related portion storing entries for potential or actual data TLB (DTLB) misses. A DTLB PRQ entry may be allocated to each load/store instruction selected from the pick queue. The system may select an ITLB- or DTLB-related entry for servicing dependent on prior PRQ entry selection(s). A corresponding entry may be held in a translation table entry return queue (TTERQ) in the output pipeline until a matching address translation is received from system memory. PRQ and/or TTERQ entries may be deallocated when a corresponding TLB miss is serviced. PRQ and/or TTERQ entries associated with a thread may be deallocated in response to a thread flush. | 12-30-2010 |
20100332788 | AUTOMATICALLY USING SUPERPAGES FOR STACK MEMORY ALLOCATION - In one embodiment, the present invention includes a page fault handler to create page table entries and TLB entries in response to a page fault, the page fault handler to determine if a page fault resulted from a stack access, to create a superpage table entry if the page fault did result from a stack access, and to create a TLB entry for the superpage. Other embodiments are described and claimed. | 12-30-2010 |
20100332789 | Network Use of Virtual Addresses Without Pinning or Registration - A system comprising a compute node and coupled network adapter (NA) that allows the NA to directly use CPU virtual addresses without pinning pages in system memory. The NA performs memory accesses in response to requests from various sources. Each request source is assigned to context. Each context has a descriptor that controls the address translation performed by the NA. When the CPU wants to update translation information it sends a synchronization request to the NA that causes the NA to stop fetching a category of requests associated with the information update. The category may be requests associated with a context or a page address. Once the NA determines that all the fetched requests in the category have completed it notifies the CPU and the CPU performs the information update. Once the update is complete, the CPU clears the synchronization request and the NA starts fetching requests in the category. | 12-30-2010 |
20100332790 | PROCESSOR AND ADDRESS TRANSLATING METHOD - An address translation buffer of a processor including a memory unit that has a first area with first entries storing first address translation pairs of a virtual address and a physical address corresponding to the virtual address, each of the first address translation pairs is subjected to a index tag which is a part of the virtual address, and a second area with second entries storing second address translation pairs, each of the second address translation pairs is subjected to a whole part of the virtual address, and a search unit that searches the first area for an address translation pair by using a index tag included in a virtual address to be translated, and searches the second area for the address translation pair by using a whole part of the virtual address when the address translation pair is not found in the first area. | 12-30-2010 |
20110004739 | EXTENDED PAGE SIZE USING AGGREGATED SMALL PAGES - A processor including a virtual memory paging mechanism. The virtual memory paging mechanism enables an operating system operating on the processor to use pages of a first size and a second size, the second size being greater than the first size. The mechanism further enables the operating system to use superpages including two or more contiguous pages of the first size. The size of a superpage is less than the second size. The processor further includes a page table having a separate entry for each of the pages included in each superpage. The operating system accesses each superpage using a single virtual address. The mechanism interprets a single entry in a translation lookaside buffer TLB as referring to a region of memory comprising a set of pages that correspond to a superpage in response to detecting a superpage enable indicator associated with the entry in the TLB is asserted. | 01-06-2011 |
20110010521 | TLB Prefetching - In an embodiment, a memory management unit (MMU) is configured to retain a block of data that includes multiple page table entries. The MMU is configured to check the block in response to TLB misses, and to supply a translation from the block if the translation is found in the block without generating a memory read for the translation. In some embodiments, the MMU may also maintain a history of the TLB misses that have used translations from the block, and may generate a prefetch of a second block based on the history. For example, the history may be a list of the most recently used Q page table entries, and the history may show a pattern of access that are nearing an end of the block. In another embodiment, the history may comprise a count of the number of page table entries in the block that have been used. | 01-13-2011 |
20110016290 | Method and Apparatus for Supporting Address Translation in a Multiprocessor Virtual Machine Environment - In one embodiment, a method includes receiving control of a first processor transitioned from a virtual machine due to a privileged event pertaining to a translation-lookaside buffer, and determining which entries in a guest translation data structure were modified by the virtual machine. The determination is made based on metadata extracted from a shadow translation data structure maintained by a virtual machine monitor and attributes associated with entries in the shadow translation data structure. The metadata includes an active entry list identifying mappings that map pages used by a guest operating system in forming the guest translation data structure. The method further includes synchronizing entries in the shadow translation data structure that correspond to the modified entries in the guest translation data structure with the modified entries in the guest translation data structure, and determining which entries to keep in the active entry list, based at least in part on attributes associated with corresponding entries in the shadow translation data structure identifying which of the plurality of processors owns each entry in the active entry list. | 01-20-2011 |
20110022819 | INDEX CACHE TREE - Memory mapping techniques for non-volatile memory are disclosed where logical sectors are mapped into physical pages using data structures in volatile and non-volatile memory. In some implementations, a first lookup table in non-volatile memory maps logical sectors directly into physical pages. A second lookup table in volatile memory holds the location of the first lookup table in non-volatile memory. An index cache tree in volatile memory holds the physical addresses of the most recently written or accessed logical sectors in a compressed format. | 01-27-2011 |
20110055515 | REDUCING BROADCASTS IN MULTIPROCESSORS - Disclosed is an apparatus to reduce broadcasts in multiprocessors including a plurality of processors; a plurality of memory caches associated with the processors; a plurality of translation lookaside buffers (TLBs) associated with the processors; and a physical memory shared with the processors memory caches and TLBs; wherein each TLB includes a plurality of entries for translation of a page of addresses from virtual memory to physical memory, each TLB entry having page characterization information indicating whether the page is private to one processor or shared with more than one processor. Also disclosed is a computer program product and method to reduce broadcasts in multiprocessors. | 03-03-2011 |
20110072234 | Providing Hardware Support For Shared Virtual Memory Between Local And Remote Physical Memory - In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed. | 03-24-2011 |
20110072235 | EFFICIENT MEMORY TRANSLATOR WITH VARIABLE SIZE CACHE LINE COVERAGE - One embodiment of the present invention sets forth a system and method for supporting high-throughput virtual to physical address translation using compressed TLB cache lines with variable address range coverage. The amount of memory covered by a TLB cache line depends on the page size and page table entry (PTE) compression level. When a TLB miss occurs, a cache line is allocated with an assumed address range that may be larger or smaller than the address range of the PTE data actually returned. Subsequent requests that hit a cache line with a fill pending are queued until the fill completes. When the fill completes, the cache line's address range is set to the address range of the PTE data returned. Queued requests are replayed and any that fall outside the actual address range are reissued, potentially generating additional misses and fills. | 03-24-2011 |
20110107057 | ADDRESS TRANSLATION UNIT WITH MULTIPLE VIRTUAL QUEUES - An address translation unit includes a translation lookaside buffer (TLB), a miss queue, and a control unit. The TLB may store a plurality of address translations. The miss queue may store received address translation requests that missed in the TLB. The miss queue includes a plurality of entries. At least some entries may each store a respective address translation request and a corresponding identifier. The corresponding identifier of a given entry identifies another entry in the miss queue that stores another respective address translation request having a process ordering constraint that is the same as a process ordering constraint of the respective address translation request in the given entry. Address translations having a same ordering constraint that are linked together via the identifier belong to the same virtual miss queue. The control unit may process the received address translation requests in an order dependent upon the identifier. | 05-05-2011 |
20110125983 | Processing System Implementing Variable Page Size Memory Organization Using a Multiple Page Per Entry Translation Lookaside Buffer - A processing system includes a page table including a plurality of page table entries. Each of the plurality of page table entries includes information for translating a virtual address page to a corresponding physical address page. The processing system also includes a translation lookaside buffer adapted to cache page table information. The processing system also includes memory management software responsive to changes in the page table to consolidate a run of contiguous page table entries into one or more page table entries having a larger memory page size, Y. The memory management software further determines whether the run of contiguous page table entries may be cached in an entry of the translation lookaside buffer that caches multiple page table entries, X, in a single translation lookaside buffer entry. | 05-26-2011 |
20110138149 | PREVENTING DUPLICATE ENTRIES IN A NON-BLOCKING TLB STRUCTURE THAT SUPPORTS MULTIPLE PAGE SIZES - One embodiment provides a system that prevents duplicate entries in a non-blocking TLB that supports multiple page sizes and speculative execution. During operation, after a request for translation of a virtual address misses in the non-blocking TLB, the system receives a TLB fill. Next, the system determines a page size associated with the TLB fill, and uses this page size to determine a set of bits in the virtual address that identify the virtual page associated with the TLB fill. The system then compares this set of bits with the corresponding bits of other virtual addresses associated with pending translation requests. If the system detects that a second virtual address for another pending translation request is also satisfied by the TLB fill, the system invalidates the duplicate translation request associated with the second virtual address. | 06-09-2011 |
20110145542 | Apparatuses, Systems, and Methods for Reducing Translation Lookaside Buffer (TLB) Lookups - Circuits and related systems and methods for providing virtual address translation are disclosed. In one embodiment, a circuit comprises a comparator configured to receive as an input a current virtual address and a current attribute associated with the current virtual address, and a prior physical address and a prior virtual address each associated with the current attribute. The comparator is further configured to cause the prior physical address to be provided as a current physical address if the current virtual address matches the prior virtual address associated with the current attribute. As an example, the circuit may be a TLB suppression circuit configured to reduce TLB lookups. Reducing TLB lookups can reduce power dissipation. In this regard, the circuit may also be further configured to suppress a TLB lookup to reduce power dissipation when the current virtual address matches the prior virtual address. | 06-16-2011 |
20110161619 | SYSTEMS AND METHODS IMPLEMENTING NON-SHARED PAGE TABLES FOR SHARING MEMORY RESOURCES MANAGED BY A MAIN OPERATING SYSTEM WITH ACCELERATOR DEVICES - Systems and methods are provided that utilize non-shared page tables to allow an accelerator device to share physical memory of a computer system that is managed by and operates under control of an operating system. The computer system can include a multi-core central processor unit. The accelerator device can be, for example, an isolated core processor device of the multi-core central processor unit that is sequestered for use independently of the operating system, or an external device that is communicatively coupled to the computer system. | 06-30-2011 |
20110161620 | SYSTEMS AND METHODS IMPLEMENTING SHARED PAGE TABLES FOR SHARING MEMORY RESOURCES MANAGED BY A MAIN OPERATING SYSTEM WITH ACCELERATOR DEVICES - Systems and methods are provided that utilize shared page tables to allow an accelerator device to share physical memory of a computer system that is managed by and operates under control of an operating system. The computer system can include a multi-core central processor unit. The accelerator device can be, for example, an isolated core processor device of the multi-core central processor unit that is sequestered for use independently of the operating system, or an external device that is communicatively coupled to the computer system. | 06-30-2011 |
20110161621 | MICRO-UPDATE ARCHITECTURE FOR ADDRESS TABLES - Methods of maintaining an address table for mapping logical addresses to physical addresses include continuously consolidating main address maps and an update address map, and periodically compacting the update address map. Consolidating includes selecting a main address map, reading valid mapping entries from the main and update address maps, constructing a mapping set including the valid mapping entries, and writing the mapping set to a second main address map. The update address map is compacted if a criterion is met, and includes copying the valid mapping entries to an unwritten block or metablock and assigning the unwritten block or metablock as a new update address map. The length of consolidation may depend on the average length of compacted mapping entries following a compaction operation. Increased performance due to lower maintenance overhead may result by using these methods. | 06-30-2011 |
20110161622 | MEMORY ACCESS CONTROL DEVICE, INTEGRATED CIRCUIT, MEMORY ACCESS CONTROL METHOD, AND DATA PROCESSING DEVICE - A memory access control unit is provided with a storage unit for storing a page table that stores a correspondence between a piece of data, a virtual page number, and a physical page number for all pages, and a conversion unit that includes a buffer for storing, for each of a subset of the pages, the virtual page number and the physical page number in correspondence, and a conversion processing unit operable to convert a virtual address into a physical address in accordance with content stored in the buffer. When the virtual page number of the virtual address included in the access request does not exist in the buffer, the conversion processing unit overwrites, in the buffer, (i) the virtual page number and the physical page number of a page for which a completed conversion count, indicating a number of times the virtual address of the page has been converted to the physical address, has reached a planned conversion count, with (ii) the virtual page number of the virtual address included in the access request and the physical page number corresponding, in the storage unit, to the virtual page number. | 06-30-2011 |
20110173411 | TLB EXCLUSION RANGE - A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises at least a virtual page number and a physical page number; a logic circuit for receiving a virtual address from said processor, said logic circuit for matching the virtual address to the virtual page number in one of the page table entries to select the physical page number in the same page table entry, said page table entry having one or more bits set to exclude a memory range from a page. | 07-14-2011 |
20110208944 | Providing Metadata In A Translation Lookaside Buffer (TLB) - In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA) translation and a second portion to store bits for a memory page associated with the VA-to-PA translation, where the bits indicate attributes of information in the memory page. Other embodiments are described and claimed. | 08-25-2011 |
20110231630 | ADDRESS MAPPING IN VIRTUALIZED PROCESSING SYSTEM - A processing system has one or more processors that implement a plurality of virtual machines that are managed by a hypervisor. Each virtual machine provides a secure and isolated hardware-emulation environment for execution of one or more corresponding guest operating systems (OSs). Each guest OS, as well as the hypervisor itself, has an associated address space, identified with a corresponding “WorldID.” Further, each virtual machine and the hypervisor can manage multiple lower-level address spaces, identified with a corresponding “address space identifier” or “ASID”. The address translation logic of the processing system translates the WorldID and ASID of the current address space context of the processing system to corresponding WorldID and ASID search keys, which have fewer bits than the original identifiers and thus require less complex translation lookaside buffer (TLB) hit logic. The resulting WorldID and ASID search keys are used to perform one or more TLB lookups to obtain address mapping information related to the particular address space represented by the WorldID/ASID combination. | 09-22-2011 |
20110238947 | Memory management apparatus, memory management method and non-transitory computer readable storage medium - A memory management apparatus has an ASID conversion table, an actual ASID use table, and a TLB flush control section. The ASID conversion table and the actual ASID use table manage virtual ASID, actual ASID and an overlap flag so that they are related for each VM. The TLB flush control section reads actual ASIDs allocated to VM as a switching target at the time of switching VM as a switching source into the VM as the switching target, determines whether the read actual ASID is allocated to the plurality of VMs in an overlapped manner with reference to the overlap flag, and sets the actual ASID in the read actual ASIDs determined being allocated in the overlapped manner as a target for the TLB flush. | 09-29-2011 |
20110276778 | EFFICIENT SUPPORT OF MULTIPLE PAGE SIZE SEGMENTS - An apparatus, system, and method are disclosed for improved support of MPS segments in a microprocessor. The virtual address is used to generate possible TLB index values for each of the supported page sizes of the MPS segment associated with the virtual address. The possible TLB index values may be a hash generated using the virtual address and one of the supported page sizes. The TLB is searched for actual TLB index values that match the possible TLB index values calculated using the different supported page sizes. TLB entries associated with those actual TLB index values are checked to determine whether any TLB entry is associated with the virtual address. If no match is found, the real address is retrieved from the PT. The actual page size in the PT is used to generate an actual TLB index value for the virtual address and the TLB entry is inserted into the TLB. | 11-10-2011 |
20110296136 | Locking Entries Into Translation Lookaside Buffers - Two translation lookaside buffers may be provided for simpler operation in some embodiments. A hardware managed lookaside buffer may handle traditional operations. A software managed lookaside buffer may be particularly involved in locking particular translations. As a result, the software's job is made simpler since it has a relatively simpler, software managed translation lookaside buffer to manage for locking translations. | 12-01-2011 |
20110320762 | REGION BASED TECHNIQUE FOR ACCURATELY PREDICTING MEMORY ACCESSES - In one embodiment, the present invention includes a processor comprising a page tracker buffer (PTB), the PTB including a plurality of entries to store an address to a cache page and to store a signature to track an access to each cache line of the cache page, and a PTB handler, the PTB handler to load entries into the PTB and to update the signature. Other embodiments are also described and claimed. | 12-29-2011 |
20120005453 | INFORMATION PROCESSING DEVICE AND DATA SHREDDING METHOD - An object is to enable efficient shredding of recording media in association with migration. An information processing device (a server device | 01-05-2012 |
20120005454 | Data processing apparatus for storing address translations - Memory address translation buffering circuitry is provided comprising a primary storage bank and a secondary storage bank. Storage bank accessing circuitry is provided to perform a parallel lookup of the primary storage bank and the secondary storage bank for virtual to physical address translation entries. Buffering management circuitry is configured to transfer an address translation entry between the primary storage bank and the secondary storage bank dependent upon an occupancy level of at least one of the primary storage bank and secondary storage bank. | 01-05-2012 |
20120011342 | System and Method to Manage a Translation Lookaside Buffer - A system and method to manage a translation lookaside buffer (TLB) is disclosed. In a particular embodiment, a method of managing a first TLB includes in response to starting execution of a memory instruction, setting a first field associated with an entry of the first TLB to indicate use of the entry. The method also includes setting a second field to indicate that the entry in the first TLB matches a corresponding entry in a second TLB. | 01-12-2012 |
20120030445 | ADVANCED PROCESSOR TRANSLATION LOOKASIDE BUFFER MANAGEMENT IN A MULTITHREADED SYSTEM - An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner. | 02-02-2012 |
20120066474 | Real Address Accessing in a Coprocessor Executing on Behalf of an Unprivileged Process - A coprocessor performs operations on behalf of processes executing in processors coupled thereto, and accesses data operands in memory using real addresses. A process executing in a processor generates an effective address for a coprocessor request, invokes the processor's address translation mechanisms to generate a corresponding real address, and passes this real address is the coprocessor. Preferably, the real address references a block of additional real addresses, each for a respective data operand. The coprocessor uses the real address to access the data operands to perform the operation. An address context detection mechanism detects the occurrence of certain events which could alter the context of real addresses used by the coprocessor or the real addresses themselves. | 03-15-2012 |
20120066475 | TRANSLATION LOOKASIDE BUFFER - A translation lookaside buffer (TLB) is disclosed formed using RAM and synthesisable logic circuits. The TLB provides logic within the synthesisable logic for pairing down a number of memory locations that must be searched to find a translation to a physical address from a received virtual address. The logic provides a hashing circuit for hashing the received virtual address and uses the hashed virtual address to index the RAM to locate a line within the RAM that provides the translation. | 03-15-2012 |
20120072697 | SYSTEM AND METHOD FOR IDENTIFYING TLB ENTRIES ASSOCIATED WITH A PHYSICAL ADDRESS OF A SPECIFIED RANGE - A system and method for identifying a TLB entry having a physical address that is within a specified range are disclosed. The method includes obtaining a tentative TLB entry from a page table entry and accessing a physical address associated with the tentative TLB entry. The method further includes comparing the physical address of the tentative TLB entry with a predetermined range of addresses. If the physical address is within the finite range of addresses, an exception is invoked. In response to the exception, the physical address and/or an attribute of the tentative TLB entry can be modified. The tentative TLB entry can then be stored in a TLB. | 03-22-2012 |
20120072698 | MEMORY MANAGEMENT DEVICE AND METHOD FOR MANAGING ACCESS TO A NONVOLATILE SEMICONDUCTOR MEMORY - According to one embodiment, a memory management device includes a history management unit, an address translation table, an address management unit, and a data management unit. The history management unit manages an access history for data stored in a nonvolatile semiconductor memory. The address translation table includes a translation table of a logical address and a physical address corresponding to the data. The address management unit specifies, based on the access history, second data to be accessed after access to first data being stored in the nonvolatile semiconductor memory, and registers a second physical address corresponding to the second data in the address translation table in association with a first logical address corresponding to the first data. The data management unit reads out the second data from the nonvolatile semiconductor memory to a buffer. | 03-22-2012 |
20120079232 | APPARATUS, METHOD, AND SYSTEM FOR IMPLEMENTING MICRO PAGE TABLES - An apparatus, method, machine-readable medium, and system are disclosed. In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries. The micro-page table engine allows the TLB to be an agent that determines whether data in a two-level memory hierarchy is in a hot region of memory or in a cold region of memory. When data is in the cold region of memory, the micro-page table engine fetches the data to the hot memory and a hot memory block is then pushed out to the cold memory area. | 03-29-2012 |
20120089810 | Apparatus and Method for Formatting and Preselecting Trace Data - The invention relates to a method and apparatus for formatting and preselecting trace data, and includes a trace message generator, an address checker, and a memory connected to the trace message generator and address checker. The trace message generator is configured to receive an address and associated data and generate a trace message with the associated data for the received address. The address checker is configured to receive the address, check the received address with the aid of the memory, and generate an output signal that indicates whether or not the trace message generated for the address is intended to be stored. The memory is configured to receive the trace message generated by the trace message generator, receive the output signal generated by the address checker, and store the received trace message if the output signal indicates that the trace message is intended to be stored. | 04-12-2012 |
20120089811 | ADDRESS CONVERSION APPARATUS - An address conversion apparatus includes a TLB, and an address conversion control section configured to count a consecutive address number indicating the number of consecutive addresses from a pair of a logical address and a physical address stored in the TLB with reference to an address conversion table, store the consecutive address number in association with the pair of the logical address and the physical address, determine whether a conversion target address is included in a range of the consecutive address number from the logical address stored in the TLB or not, and add, if the conversion target address is included in the range, a difference between the logical address and the conversion target address to the physical address which forms a pair with the logical address to calculate a converted physical address. | 04-12-2012 |
20120102296 | Translation Lookaside Buffer (TLB) with Reserved Areas for Specific Sources - In an embodiment, a TLB is partitioned into regions. The TLB may be set associative, and each section may include a portion of the locations in each way of the set associative memory. The TLB may reserve at least one of the sections for access by a subset of the request sources that use the TLB. For requests from the subset, the reserved section may be used and a location in the reserved section may be allocated to store a translation for a request from the subset that misses in the TLB. For requests for other request sources, the non-reserved section or sections may be used. In one embodiment, each way of the reserved section may be assigned to a different one of the request sources in the subset. | 04-26-2012 |
20120117356 | Invalidating a Range of Two ro More Translation Table Entries and Instruction Therefore - An instruction is provided to perform invalidation of an instruction specified range of segment table entries or region table entries. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof. | 05-10-2012 |
20120124325 | METHOD AND APPARATUS FOR CONTROLLING A TRANSLATION LOOKASIDE BUFFER - A method and apparatus are provided for controlling a translation lookaside buffer in connection with the execution of an atomic instruction. The method comprises identifying load instructions within a plurality of instructions to be executed, and placing the identified load instructions in a queue prior to execution. An atomic instruction identified in the queue is prevented from executing until the atomic instruction is the oldest instruction in the queue. The apparatus comprises a queue and a translation lookaside buffer. The queue is adapted to: identify an atomic instruction within a plurality of instructions to be executed; prevent execution of the atomic instruction until it is the oldest instruction in the queue; and send a virtual address corresponding to the atomic instruction and an atomic load signal in response to determining that the atomic instruction is the oldest instruction in the queue. The translation lookaside buffer is adapted for maintaining at least one virtual to physical address translation, and is adapted to force a miss in the translation lookaside buffer in response to receiving the atomic load signal. | 05-17-2012 |
20120124326 | Translation Lookaside Buffer Structure Including a Data Array Sense Amplifier and Fast Compare Unit - A translation lookaside buffer (TLB) includes a data array including a number of memory storage cells arranged to form a plurality of entries. The memory storage cells of each entry may be configured to store the respective bits of a translated physical address. The data array further includes a number of sense amplifiers, each coupled to a respective memory storage cell. In response to a read access to a given entry, the sense amplifiers corresponding to the memory storage cells of the given entry may be configured to output respective bit representations of the translated physical address. The TLB also includes a compare unit coupled to the sense amplifier outputs and configured to perform a bit-wise compare of each bit representation of the translated physical address with a corresponding respective bit of each of a plurality of additional addresses. | 05-17-2012 |
20120124327 | Translation Lookaside Buffer Structure Including a Data Array Storing an Address Selection Signal - A translation lookaside buffer (TLB) includes a data array unit with a data array having a plurality of entries. Each entry may store a respective translated physical address and an address selection indication. The address selection indication may select as an output of the data array unit one of the respective translated physical address stored within a particular entry or another address provided to the data array unit in response to the particular entry being read. | 05-17-2012 |
20120124328 | Translation Lookaside Buffer Structure Including an Output Comparator - A processor includes a translation lookaside buffer (TLB) including a data array and a compare unit. The data array includes a number of entries each configured to store a respective translated physical address. In response to a read access to a given entry of the TLB, the data array is configured to output within a particular clock cycle, the respective translated physical address stored in the given entry. In addition the compare unit may be configured to compare the respective translated physical address output by the data array with a number of additional addresses. The compare unit may also be configured to provide a hit indication for each of the additional addresses within the particular clock cycle. | 05-17-2012 |
20120124329 | Translation Lookaside Buffer Structure Including a Data Array Having an Integrated Multiplexer - A translation lookaside buffer (TLB) includes a data array including memory storage cells arranged to form a number of entries. Each entry may store a translated physical address. The data array also includes an integrated multiplexer that may be coupled to an output of the data array. The integrated multiplexer may include a respective first bit select transistor that may be coupled between an output of each of at least some of the memory storage cells and the output of the data array. In addition, the integrated multiplexer may bit-wise select as the output of the data array, one of the translated physical address or another address provided to the data array from external to the TLB in response to a given entry being accessed. | 05-17-2012 |
20120131307 | DATA STRUCTURE FOR ENFORCING CONSISTENT PER-PHYSICAL PAGE CACHEABILITY ATTRIBUTES - A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state. | 05-24-2012 |
20120137105 | MEMORY SYSTEM AND RELATED METHOD OF OPERATION - A memory system comprises a translation lookaside buffer (TLB) configured to receive a virtual address and to search for a TLB entry matching the virtual address, and a translation information buffer (TIB) configured to be connected to the TLB and determine whether a physical address corresponding to the virtual address falls into a continuous mapping area if the TLB entry matching the virtual address is not found. | 05-31-2012 |
20120137106 | Dynamic Address Translation With Translation Table Entry Format Control for Identifying Format of the Translation Table Entry - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory. | 05-31-2012 |
20120144153 | Dynamic Address Translation With Change Record Override - A translation table entry contains a change recording override field for controlling whether a change bit is to be set on a store or not. Each 4K byte block of main storage has an associated storage key comprising a change bit. The change recording override field controls whether the change bit of the storage key associated with the desired 4K byte block of main storage is set to 1 for a store operation. | 06-07-2012 |
20120144154 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING A PROGRAMMABLE QUIESCE FILTERING REGISTER - Storing translation lookaside buffer (TLB) entries are in a TLB | 06-07-2012 |
20120173842 | Operating System Management of Address-Translation-Related Data Structures and Hardware Lookasides - An approach is provided in a hypervised computer system where a page table request is at an operating system running in the hypervised computer system. The operating system determines whether the page table request requires the hypervisor to process. If the determination reveals that the page table request requires the hypervisor, then the hypervisor is used to handle the request. However, if the determination reveals that the page table request does not require the hypervisor, then an indicator included in a page table entry corresponding to the request is read to determine if the page table entry is controlled by the operating system or the hypervisor. The operating system is able to update the page table entry if the indicator identifies the page table entry as being operating system controlled. | 07-05-2012 |
20120173843 | TRANSLATION LOOK-ASIDE BUFFER INCLUDING HAZARD STATE - A system may include a storage medium with multiple entries, each entry of the configured to store a respective address of a memory write request that has not yet been committed to memory. The system may further include a translation lookaside buffer (TLB) including a multiple TLB entries, each TLB entry having an associated address field and associated one or more hazard status fields. The address field may store a translated physical memory address. Each hazard status field may correspond to a respective storage entry of the storage medium, and contain respective information indicating whether the translated physical memory address matches the respective address in the respective storage entry. The system may also include hazard detection logic to receive the respective information from the TLB, and use the respective information to prevent a hazard from occurring when the translated physical memory address is associated with a memory write request that has not yet been committed to memory. | 07-05-2012 |
20120179892 | SYSTEM AND METHOD FOR FILTERING RECEIVED DATA UNITS - A system for filtering received data units comprises a memory structure adapted to store a plurality of P tables, each table comprising a plurality of filter-keys and corresponding indices, each filter-key comprising one or more key-bits each corresponding to a filter configurable by a corresponding filter configuration value; and at least one processing element connected to the memory structure and comprising a digesting module adapted to generate the one or more key-bits of each of the filter-keys of the tables by splitting the corresponding filter configuration value into P configuration-pieces each having a number of bits, and to use each configuration-piece as a first index for setting a corresponding key-bit in the corresponding table; and a filtering module adapted to receive and split the data units into P data-pieces each having the number of bits, for each data-piece use the data-piece as a second index for reading the corresponding filter-key from the corresponding table, and generate a pass-indication key from a bitwise logical conjunction between the read filter-keys. | 07-12-2012 |
20120185668 | MEMORY MANAGEMENT UNIT AND APPARATUSES HAVING SAME - The memory management unit includes a page table correlating respective virtual addresses with corresponding physical addresses, first translation lookaside buffer (TLB) lookup logic that provides one of a first virtual address and a first physical address according to whether a page number of the first virtual address matches a frame number of the first physical address, a first queue buffer that stores and provides the first virtual address, and second TLB lookup logic that determines and provides a first page physical address using the first virtual address to access the page table when the page number of the first virtual address does not match the frame number of the first physical address. | 07-19-2012 |
20120226888 | Memory Management Unit With Pre-Filling Capability - Systems and method for memory management units (MMUs) configured to automatically pre-fill a translation lookaside buffer (TLB) with address translation entries expected to be used in the future, thereby reducing TLB miss rate and improving performance. The TLB may be pre-filled with translation entries, wherein addresses corresponding to the pre-fill may be selected based on predictions. Predictions may be derived from external devices, or based on stride values, wherein the stride values may be a predetermined constant or dynamically altered based on access patterns. Pre-filling the TLB may effectively remove latency involved in determining address translations for TLB misses from the critical path. | 09-06-2012 |
20120239904 | SEAMLESS INTERFACE FOR MULTI-THREADED CORE ACCELERATORS - A method, system and computer program product are disclosed for interfacing between a multi-threaded processing core and an accelerator. In one embodiment, the method comprises copying from the processing core to the hardware accelerator memory address translations for each of multiple threads operating on the processing core, and simultaneously storing on the hardware accelerator one or more of the memory address translations for each of the threads. Whenever any one of the multiple threads operating on the processing core instructs the hardware accelerator to perform a specified operation, the hardware accelerator has stored thereon one or more of the memory address translations for the any one of the threads. This facilitates starting that specified operation without memory translation faults. In an embodiment, the copying includes, each time one of the memory address translations is updated on the processing core, copying the updated one of the memory address translations to the hardware accelerator. | 09-20-2012 |
20120246441 | INFORMATION PROCESSOR AND MULTI-CORE SYSTEM - According to one embodiment, an information processor includes an operator and an address protector. The address protector includes a register access interface, an address table, and an access determination module. The register access interface is configured to receive address protection information from the operator. The address table is configured to store the received address protection information. The access determination module is configured to determine whether an access to an address specified by the operator is allowable based on the address protection information, and configured to output an interrupt signal to the operator when the access is unallowable. | 09-27-2012 |
20120254584 | SYSTEM AND METHOD FOR IDENTIFYING TLB ENTRIES ASSOCIATED WITH A PHYSICAL ADDRESS OF A SPECIFIED RANGE - A system and method for identifying a TLB entry having a physical address that is within a specified range are disclosed. The method includes obtaining a tentative TLB entry from a page table entry and accessing a physical address associated with the tentative TLB entry. The method further includes comparing the physical address of the tentative TLB entry with a predetermined range of addresses. If the physical address is within the finite range of addresses, an exception is invoked. In response to the exception, the physical address and/or an attribute of the tentative TLB entry can be modified. The tentative TLB entry can then be stored in a TLB. | 10-04-2012 |
20120265963 | LARGE-PAGE OPTIMIZATION IN VIRTUAL MEMORY PAGING SYSTEMS - A computer system that is programmed with virtual memory accesses to physical memory employs multi-bit counters associated with its page table entries. When a page walker visits a page table entry, the multi-bit counter associated with that page table entry is incremented by one. The computer operating system uses the counts in the multi-bit counters of different page table entries to determine where large pages can be deployed effectively. In a virtualized computer system having a nested paging system, multi-bit counters associated with both its primary page table entries and its nested page table entries are used. These multi-bit counters are incremented during nested page walks. Subsequently, the guest operating systems and the virtual machine monitors use the counts in the appropriate multi-bit counters to determine where large pages can be deployed effectively. | 10-18-2012 |
20120297161 | Providing Metadata In A Translation Lookaside Buffer (TLB) - In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA) translation and a second portion to store bits for a memory page associated with the VA-to-PA translation, where the bits indicate attributes of information in the memory page. Other embodiments are described and claimed. | 11-22-2012 |
20120303930 | Indirection memory architecture with reduced memory requirements for shingled magnetic recording devices - An indirection system in a shingled storage device is described that uses an efficient algorithm to map LBAs to DBAs based on a predetermined rule or assumption and then handles as exceptions LBAs that are not mapped according to the rule. The assumed rule is that a fixed-length set of sequential host LBAs are located at the start of an I-track. Embodiments of the invention use two tables to provide the mapping of LBAs to DBAs. The mapping assumed by the rule is embodied in the LBA Block Address Table (LBAT) which gives the corresponding I-track address for each LBA Block. The LBA exceptions are recorded using an Exception Pointer Table (EPT), which gives the pointer to the corresponding variable length Exception List for each LBA Block. The indexing into the LBAT and the EPT is made efficient by deriving the index from the LBA by a simple arithmetic operation. | 11-29-2012 |
20120331264 | Point-in-Time Copying of Virtual Storage and Point-in-Time Dumping - A method includes copying a first virtual storage by making, a point-in-time copy of a first page content stored in a first structure by creating a second page content in a second structure, the second page content pointing to actual data pointed to by the first page content, storing the second page content in the second data structure, marking the first page content in the first structure with a bit, copying the virtual page in the event the first page content in the first structure is marked with the bit, storing the copied virtual page in a second virtual storage, altering the second page content to point to the stored virtual page, and using the second virtual storage to perform the core dump process, wherein the second virtual storage is referenced via the second page content stored in the real storage. | 12-27-2012 |
20120331265 | Apparatus and Method for Accelerated Hardware Page Table Walk - A method of walking page tables includes comparing a virtual address to a plurality of virtual address bit segments to identify a match. Each virtual address bit segment is associated with a page table level that has a page table base address. A designated page table base address is received in response to the match. The page table walk starts at the designated page table, thereby skipping over earlier page tables. | 12-27-2012 |
20120331266 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD AND MEDIUM STORING PROGRAM - Disclosed is an information processing device provided with: a plurality of processing units each having a TLB (Translation Lookaside Buffer); a means for acquiring a designation of a processing unit, from among the plurality of processing units, where TLB information is to be collected, and for acquiring a designation of the timing at which the TLB information is to be collected; and a means for collecting the TLB information from the designated processing unit at the designated timing. | 12-27-2012 |
20130007406 | DYNAMIC PINNING OF VIRTUAL PAGES SHARED BETWEEN DIFFERENT TYPE PROCESSORS OF A HETEROGENEOUS COMPUTING PLATFORM - A computer system may support one or more techniques to allow dynamic pinning of the memory pages accessed by a non-CPU device (e.g., a graphics processing unit, GPU). The non-CPU may support virtual to physical address mapping and may thus be aware of the memory pages, which may not be pinned but may be accessed by the non-CPU. The non-CPU may notify or send such information to a run-time component such as a device driver associated with the CPU. In one embodiment, the device driver may, dynamically, perform pinning of such memory pages, which may be accessed by the non-CPU. The device driver may even unpin the memory pages, which may be no longer accessed by the non-CPU. Such an approach may allow the memory pages, which may be no longer accessed by the non-CPU to be available for allocation to the other CPUs and/or non-CPUs. | 01-03-2013 |
20130007407 | Extending Processor MMU for Shared Address Spaces - A system and a method are disclosed for more efficiently handling shared code stored in memory, comprising a modified memory management unit containing a new shared address space identifier register, and a modified TLB entry containing a new shared bit. | 01-03-2013 |
20130007408 | METHOD AND APPARATUS FOR MANAGING SOFTWARE CONTROLLED CACHE OF TRANSLATING THE PHYSICAL MEMORY ACCESS OF A VIRTUAL MACHINE BETWEEN DIFFERENT LEVELS OF TRANSLATION ENTITIES - A method and a system for allowing a guest operating system (guest OS) to modify an entry in a TLB directly without an involvement of a hypervisor are disclosed. Upon receiving a guest TLB miss exception, a guest OS issues a TLBWE (TLB Write Entry) instruction to logic. The logic runs the TLBWE instruction at a supervisor mode without invoking a hypervisor. The TLB may incorporate entries in a guest page table and entries in a host page table. | 01-03-2013 |
20130013889 | Memory management unit using stream identifiers - A memory management unit includes a translation buffer unit for storing memory management attribute entries that originate from a plurality of different memory management contexts. Context disambiguation circuitry responds to one or more characteristics of a received memory transaction to form a stream identifier and to determine which of the memory management context matches that memory transaction. In this way, memory management attribute entries stored within the translation lookaside buffer are formed under control of the appropriate matching context. When the translation buffer unit receives a further transaction, then a further stream identifier is formed therefrom and if this matches the stream identifier of stored memory management attribute entries then those memory management attribute entries may be used (if appropriate) for that further memory transaction. | 01-10-2013 |
20130013890 | DATABASE SYSTEM - Operating a database system comprises: storing a database table comprising a plurality of rows, each row comprising a key value and one or more attributes; storing a primary index for the database table, the primary index comprising a plurality of leaf nodes, each leaf node comprising one or more key values and respective memory addresses, each memory address defining the storage location of the respective key value; creating a new leaf node comprising one or more key values and respective memory addresses; performing a memory allocation analysis based upon the lowest key value of the new leaf node to identify a non-full memory page storing a leaf node whose lowest key value is similar to the lowest key value of the new leaf node; and storing the new leaf node in the identified non-full memory page. | 01-10-2013 |
20130024647 | CACHE BACKED VECTOR REGISTERS - A processor, method, and medium for utilizing a shared cache to store vector registers. Each thread of a multithreaded processor utilizes a plurality of virtual vector registers to perform vector operations. Virtual vector registers are allocated for each thread, and each virtual vector register is mapped into the shared cache on the processor. The cache is shared between multiple threads such that if one thread is not using vector registers, there is more space in the cache for other threads to use vector registers. | 01-24-2013 |
20130024648 | TLB EXCLUSION RANGE - A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises at least a virtual page number and a physical page number; a logic circuit for receiving a virtual address from said processor, said logic circuit for matching the virtual address to the virtual page number in one of the page table entries to select the physical page number in the same page table entry, said page table entry having one or more bits set to exclude a memory range from a page. | 01-24-2013 |
20130024649 | METHOD AND DEVICE FOR STORING ROUTING TABLE ENTRY - The present invention discloses a method and a device for storing a routing table entry. The method includes: splitting a routing table entry into two points according to a range matching policy; obtaining a storage location of the routing table entry in a hierarchical binary tree; and adding each segment related to the routing table entry to the binary tree of each segment according to the storage location. According to the present invention, the routing table entry is stored in the hierarchical binary tree in segments, which significantly reduces the total amount of memory required to be occupied by storage of the routing table entry. | 01-24-2013 |
20130031332 | MULTI-CORE SHARED PAGE MISS HANDLER - Methods and apparatus are disclosed for using a shared page miss handler device to satisfy page miss requests of a plurality of devices in a multi-core system. One embodiment of such a method comprises receiving one or more page miss requests from one or more respective requesting devices of the plurality of devices in the multi-core system, and arbitrating to identify a first page miss requests of the one or more requesting devices A page table walk is performed to generate a physical address responsive to the first page miss request. Then the physical address is sent to the corresponding requesting device, or a fault is signaled to an operating system for the corresponding requesting device responsive to the first page miss request. | 01-31-2013 |
20130031333 | METHOD AND APPARATUS FOR TLB SHOOT-DOWN IN A HETEROGENEOUS COMPUTING SYSTEM SUPPORTING SHARED VIRTUAL MEMORY - Methods and apparatus are disclosed for efficient TLB (translation look-aside buffer) shoot-downs for heterogeneous devices sharing virtual memory in a multi-core system. Embodiments of an apparatus for efficient TLB shoot-downs may include a TLB to store virtual address translation entries, and a memory management unit, coupled with the TLB, to maintain PASID (process address space identifier) state entries corresponding to the virtual address translation entries. The PASID state entries may include an active reference state and a lazy-invalidation state. The memory management unit may perform atomic modification of PASID state entries responsive to receiving PASID state update requests from devices in the multi-core system and read the lazy-invalidation state of the PASID state entries. The memory management unit may send PASID state update responses to the devices to synchronize TLB entries prior to activation responsive to the respective lazy-invalidation state. | 01-31-2013 |
20130036291 | GENERATING MULTIPLE ADDRESS SPACE IDENTIFIERS PER VIRTUAL MACHINE TO SWITCH BETWEEN PROTECTED MICRO-CONTEXTS - Embodiments of an invention for generating multiple address space identifiers per virtual machine to switch between protected micro-contexts are disclosed. In one embodiment, a method includes receiving an instruction requiring an address translation; initiating, in response to receiving the instruction, a page walk from a page table pointed to by the contents of a page table pointer storage location; finding, during the page walk, a transition entry; storing the address translation and one of a plurality of address source identifiers in a translation lookaside buffer, the one of the plurality of address source identifiers based on one of a plurality of a virtual partition identifiers, at least two of the plurality of virtual partition identifiers associated with one of a plurality of virtual machines; and re-initiating the page walk. | 02-07-2013 |
20130054935 | SYNCHRONIZING A TRANSLATION LOOKASIDE BUFFER WITH AN EXTENDED PAGING TABLE - A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system. | 02-28-2013 |
20130067195 | CONTEXT-SPECIFIC STORAGE IN MULTI-PROCESSOR OR MULTI-THREADED ENVIRONMENTS USING TRANSLATION LOOK-ASIDE BUFFERS - A method for maintaining context-specific symbols in a multi-core or multi-threaded processing environment may include, but is not limited to: partitioning a virtual address space into at least one portion associated with the storage of one or more context-specific symbols accessible by at least a first processing core and a second processing core; defining at least one context-specific symbol; storing the at least one context specific symbol to the at least one portion of the virtual address space; and mapping the virtual address of the at least one context-specific symbol to both a physical address associated with the first processing core and a physical address associated with the second processing core. | 03-14-2013 |
20130080733 | PROCESSOR AND CONTROL METHOD OF PROCESSOR - A processor connected to a storage device including a buffer area where an address translation pair is stored includes: an LRU register that holds a number of a plurality of real address registers, the real address register being the oldest in a use history; a reading unit that reads the number of the real address register held in the LRU register when a real address included in an access request to the storage device does not fall within a range of a real address space from a lower limit real address held in a lower limit real address register to an upper limit real address held in an upper limit real address register; and a setting unit that invalidates the real address register corresponding to the read number and sets a real address space corresponding to the real address included in the access request to the invalided real address register. | 03-28-2013 |
20130080734 | ADDRESS TRANSLATION UNIT, METHOD OF CONTROLLING ADDRESS TRANSLATION UNIT AND PROCESSOR - Disclosed herein is a micro TLB which includes a CAM section having a plurality of CAM circuits, each stores address information which represents correlation between a virtual address and a physical address; and a write control section which directs writing of the address information into each CAM circuit pointed by a write pointer, when a new address information is requested to be stored, wherein the micro TLB being configured to increment the write pointer, if the address information stored in each CAM circuit pointed by the write pointer has been used for address translation, so as to hold a recently-used address information while preventing the CAM circuit, having indication of use of the address information, from being overwritten with the new address information. | 03-28-2013 |
20130080735 | ADDRESS TRANSLATION DEVICE, PROCESSING DEVICE AND CONTROL METHOD OF PROCESSING DEVICE - An address translation buffer (TLB) which holds pairs of virtual addresses and physical addresses by respective page sizes and performs an address translation, a storage unit which holds a pair of a virtual address removed from the TLB and page size corresponding thereto when a pair of a new virtual address and physical address read from a page table is registered to the TLB, base registers which hold a base address by each page size are held. The TLB is searched based on a translation object virtual address included in a memory access request, and when a TLB miss occurs, a main storage is searched based on a pointer address generated from information held by the storage unit and the base register, and the translation object virtual address is translated into the physical address. | 03-28-2013 |
20130103923 | MEMORY MANAGEMENT UNIT SPECULATIVE HARDWARE TABLE WALK SCHEME - A system and method for efficiently handling translation look-aside buffer (TLB) misses. A memory management unit (MMU) detects when a given virtual address misses in each available translation-lookaside-buffer (TLB). The MMU determines whether a memory access operation associated with the given virtual address is the oldest, uncompleted memory access operation in a scheduler. If this is the case, a demand table walk (TW) request may be stored in an available entry in a TW queue. During this time, the utilization of the memory subsystem resources may be low. While a demand TW request is stored in the TW queue, subsequent speculative TW requests may be stored in the TW queue. When the TW queue does not store a demand TW request, no more entries of the TW queue may be allocated to store TW requests. | 04-25-2013 |
20130111184 | METHOD AND SYSTEM FOR CACHING ATTRIBUTE DATA FOR MATCHING ATTRIBUTES WITH PHYSICAL ADDRESSES | 05-02-2013 |
20130117531 | METHOD, SYSTEM, AND APPARATUS FOR PAGE SIZING EXTENSION - A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed. | 05-09-2013 |
20130159664 | Infrastructure Support for Accelerated Processing Device Memory Paging Without Operating System Integration - In a CPU of the combined CPU/APD architecture system, the CPU having multiple CPU cores, each core having a first machine specific register for receiving a physical page table/page directory base address, a second machine specific register for receiving a physical address pointing to a location controlled by an IOMMUv2 that is communicatively coupled to an APD, and microcode which when executed causes a write notification to be issued to the physical address contained in the second machine specific register; receiving in the first machine specific register of a CPU core, a physical page table/page directory base address, receiving in the second machine specific register of the CPU core, a physical address pointing to a location controlled by the IOMMUv2, determining that a control register of the CPU core has been updated, and responsive to the determination that the control register has been updated, executing microcode in the CPU core that causes a write notification to be issued to the physical address contained in the second machine specific register, wherein the physical address is able to receive writes that affect IOMMUv2 page table invalidations. | 06-20-2013 |
20130173882 | INSTRUCTION FETCH TRANSLATION LOOKASIDE BUFFER MANAGEMENT TO SUPPORT HOST AND GUEST O/S TRANSLATIONS - A translation lookaside buffer (TLB) configured for use in a multiple operating system environment includes a plurality of storage locations, each storage location being configured to store a page translation entry configured to relate a virtual address range to a physical address range, each page translation entry having an address space identifier (ASID) associated with an operating system. The TLB also includes flush logic configured to receive a TLB flush request from an operating system having an operating system ASID and flush only TLB page translation entries having a stored ASID that matches the operating system ASID. | 07-04-2013 |
20130173883 | APPLICATION PROCESSOR AND A COMPUTING SYSTEM HAVING THE SAME - An application processor includes a system memory unit, peripheral devices, a control unit and a central processing unit (CPU). The system memory unit includes one page table. The peripheral devices share the page table and perform a DMA (Direct Memory Access) operation on the system memory unit using the page table, where each of the peripheral devices includes a memory management unit having a translation lookaside buffer. The control unit divides a total virtual address space corresponding to the page table into sub virtual address spaces, assigns the sub virtual address spaces to the peripheral devices, respectively, allocates and releases a DMA buffer in the system memory unit, and updates the page table, where at least two of the sub virtual address spaces have different sizes from each other. The CPU controls the peripheral devices and the control unit. The application processor reduces memory consumption. | 07-04-2013 |
20130205114 | OBJECT-BASED MEMORY STORAGE - The method includes receiving an object operation from an application at a hardware device manager. The object operation includes an object identifier. The method includes performing the object operation directly on a storage device. A physical address for the object corresponding to the object identifier is mapped directly to the object identifier in an index managed by the hardware device manager. | 08-08-2013 |
20130227248 | SYSTEM AND METHOD FOR SUPPORTING FINER-GRAINED COPY-ON-WRITE PAGE SIZES - In a computer system having virtual machines, one or more unused bits of a guest virtual address range are allocated for aliasing so that multiple virtually addressed sub-pages can be mapped to a common memory page. When one bit is allocated for aliasing, sub-pages can be virtually addressed at a granularity that is one-half of a memory page. When M bits are allocated for aliasing, sub-pages can be virtually addressed at a granularity that is 1/(2 | 08-29-2013 |
20130232316 | MAINTAINING PROCESSOR RESOURCES DURING ARCHITECTURAL EVENS - In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced. | 09-05-2013 |
20130238874 | SYSTEMS AND METHODS FOR ACCESSING A UNIFIED TRANSLATION LOOKASIDE BUFFER - Systems and methods for accessing a unified translation lookaside buffer (TLB) are disclosed. A method includes receiving an indicator of a level one translation lookaside buffer (L | 09-12-2013 |
20130238875 | MULTIPLE PAGE SIZE MEMORY MANAGEMENT UNIT - A memory management unit can receive an address associated with a page size that is unknown to the MMU. The MMU can concurrently determine whether a translation lookaside buffer data array stores a physical address associated with the address based on different portions of the address, where each of the different portions is associated with a different possible page size. This provides for efficient translation lookaside buffer data array access when different programs, employing different page sizes, are concurrently executed at a data processing device. | 09-12-2013 |
20130262815 | HYBRID ADDRESS TRANSLATION - Embodiments of the invention relate to hybrid address translation. An aspect of the invention includes receiving a first address, the first address referencing a location in a first address space. The computer searches a segment lookaside buffer (SLB) for a SLB entry corresponding to the first address; the SLB entry comprising a type field and an address field and determines whether a value of the type field in the SLB entry indicates a hashed page table (HPT) search or a radix tree search. Based on determining that the value of the type field indicates the HPT search, a HPT is searched to determine a second address, the second address comprising a translation of the first address into a second address space; and based on determining that the value of the type field indicates the radix tree search, a radix tree is searched to determine the second address. | 10-03-2013 |
20130262816 | TRANSLATION LOOKASIDE BUFFER FOR MULTIPLE CONTEXT COMPUTE ENGINE - Some implementations disclosed herein provide techniques and arrangements for an specialized logic engine that includes translation lookaside buffer to support multiple threads executing on multiple cores. The translation lookaside buffer enables the specialized logic engine to directly access a virtual address of a thread executing on one of the plurality of processing cores. For example, an acceleration compute engine may receive one or more instructions from a thread executed by a processing core. The acceleration compute engine may retrieve, based on an address space identifier associated with the one or more instructions, a physical address associated with the one or more instructions from the translation lookaside buffer to execute the one or more instructions using the physical address. | 10-03-2013 |
20130275716 | PROGRAM EXECUTION DEVICE AND COMPILER SYSTEM - A program execution device includes a program loader reading a machine language program including a machine language code and access frequency information; an address conversion table creator creating an address conversion table including entries, each of which indicates a relation between a logical address range and a physical address range; and a TLB register registering, in a TLB, an entry of the address conversion table storing a logical address range accessed according to the machine language code. When determining that the frequency of access to a logical address range is high based on the access frequency information, the address conversion table creator adjusts the size of an entry storing this logical address range to an appropriate size. | 10-17-2013 |
20130318323 | APPARATUS AND METHOD FOR ACCELERATING OPERATIONS IN A PROCESSOR WHICH USES SHARED VIRTUAL MEMORY - An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory. | 11-28-2013 |
20130339655 | TRANSLATION LOOK-ASIDE TABLE MANAGEMENT - A computer system includes a translation look-aside (TLB) buffer and a processing unit. The TLB is configured to store an entry that comprises virtual address information, real address information associated with the virtual address information, and additional information corresponding to at least one of the virtual address information and the real address information. The processing unit is configured to control the TLB to modify the additional information while maintaining the entry in a valid state accessible by the processing unit for a translation look-aside operation corresponding to the virtual address information and the real address information. | 12-19-2013 |
20130339656 | Compare and Replace DAT Table Entry - A first and a second operand are compared. If they are equal, the contents of register R | 12-19-2013 |
20130339657 | LOCAL CLEARING CONTROL - A computer implemented instruction is executed. One or more translation table entry locations (TLB) are specified by the instruction. Based on a local-clearing (LC) control specified by the instruction being a first value, the processor selectively clears TLBs in a plurality of the CPUs in a configuration of entries corresponding to the determined translation table entry location. Based on the local-clearing (LC) being a second value, the processor selectively clears only the TLBs of the CPU executing the instruction of entries corresponding to the determined translation table entry location. A computer program product, computer system and computer implemented method are provided. | 12-19-2013 |
20130339658 | MANAGING PAGE TABLE ENTRIES - A method includes identifying, by a processor, a first page table entry (PTE) of a page table for translating virtual addresses to main storage addresses, the page table comprising a second page table entry contiguous with the second page table entry, determining with the processor whether the first PTE may be joined with the second PTE, the determining based on the respective pages of main storage being contiguous, and setting a marker in the page table for indicating that the main storage pages of identified by the first PTE and second PTEs are contiguous. | 12-19-2013 |
20130339659 | MANAGING ACCESSING PAGE TABLE ENTRIES - A method for accessing memory locations includes translating, by a processor, a virtual address to locate a first page table entry (PTE) in a page table. The first PTE includes a marker and an address of a page of main storage. It is determined, by the processor, whether a marker is set in the first PTE. A large page size of a large page associated with the first PTE is identified based on determining that the marker is set in the first PTE. The large page is made up of contiguous pages of main storage. An origin address of the large page is determined based on determining that the marker is set in the first PTE. The virtual address is used to index into the large page at the origin address to access main storage. | 12-19-2013 |
20140006747 | SYSTEMS AND METHODS FOR PROCESSING INSTRUCTIONS WHEN UTILIZING AN EXTENDED TRANSLATION LOOK-ASIDE BUFFER HAVING A HYBRID MEMORY STRUCTURE | 01-02-2014 |
20140013074 | COMBINING A REMOTE TLB LOOKUP AND A SUBSEQUENT CACHE MISS INTO A SINGLE COHERENCE OPERATION - The disclosed embodiments provide techniques for reducing address-translation latency and the serialization latency of combined TLB and data cache misses in a coherent shared-memory system. For instance, the last-level TLB structures of two or more multiprocessor nodes can be configured to act together as either a distributed shared last-level TLB or a directory-based shared last-level TLB. Such TLB-sharing techniques increase the total amount of useful translations that are cached by the system, thereby reducing the number of page-table walks and improving performance. Furthermore, a coherent shared-memory system with a shared last-level TLB can be further configured to fuse TLB and cache misses such that some of the latency of data coherence operations is overlapped with address translation and data cache access latencies, thereby further improving the performance of memory operations. | 01-09-2014 |
20140025923 | MEMORY MANAGEMENT FOR A HIERARCHICAL MEMORY SYSTEM - Disclosed are systems and methods for managing memory. A memory management system may include a table having multiple virtual memory addresses. Each virtual memory address may correspond to a physical memory address and data that identifies a type of memory device corresponding to the physical memory address. The physical memory device can be used to access the memory device when a table hit occurs. | 01-23-2014 |
20140059321 | Load Page Table Entry Address Instruction Execution Based on an Address Tralsnation Format Control Field - What is provided is a load page table entry address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which contains an opcode indicating that a load page table entry address function is to be performed. The machine instruction contains an M field, a first field identifying a first general register, and a second field identifying a second general register. Based on the contents of the M field, an initial origin address of a hierarchy of address translation tables having at least one segment table is obtained. Based on the obtained initial origin address, dynamic address translation is performed until a page table entry is obtained. The page table entry address is saved in the identified first general register. | 02-27-2014 |
20140068225 | CONFIGURABLE TRANSLATION LOOKASIDE BUFFER - A particular method includes receiving at least one translation lookaside buffer (TLB) configuration indicator. The at least one TLB configuration indicator indicates a specific number of entries to be enabled at a TLB. The method further includes modifying a number of searchable entries of the TLB in response to the at least one TLB configuration indicator. | 03-06-2014 |
20140075151 | DETECTION OF CONFLICTS BETWEEN TRANSACTIONS AND PAGE SHOOTDOWNS - There is provided a method for detecting a conflict between a transaction and a TLB (Translation Lookaside Buffer) shootdown in a transactional memory in which a TLB shootdown operation message is received by a processor to invalidate at least one entry in a TLB of the processor corresponding to at least one page. The processor tracks pages touched by the transaction. The processor determines whether the received TLB shootdown operation message is associated with one of the touched pages. The processor aborts the transaction in response to determining that the received TLB shootdown operation message is associated with one of the touched pages. | 03-13-2014 |
20140075152 | METHOD FOR GENERATING A DELTA FOR COMPRESSED DATA - A translation table has entries that each include a share bit and a delta bit, with pointers that point to a memory block that includes reuse bits. The share bit is set to indicate a translation table entry is sharing its memory block with another translation table entry. In addition, a translation table entry may include a private delta in the form of a pointer that references a memory fragment in the memory block that is not shared with other translation table entries, wherein the private delta references previously-stored content. When a translation table has a private delta, its delta bit is set. The private delta is generated by analyzing a data buffer for content that is similar to previously-stored content. | 03-13-2014 |
20140082323 | ADDRESS MAPPING - The present disclosure includes methods, memory units, and apparatuses for address mapping. One method includes providing a mapping unit having logical to physical mapping data corresponding to a number of logical addresses. The mapping unit has a variable data unit type associated therewith and comprises a first portion comprising mapping data indicating locations on a memory of a number of physical data units having a size defined by the variable data unit type, and a second portion comprising mapping data indicating locations on the memory of a number of other mapping units of a mapping unit group to which the mapping unit belongs. | 03-20-2014 |
20140089631 | POWER SAVINGS VIA DYNAMIC PAGE TYPE SELECTION - An operating system monitors a performance metric of a direct memory access (DMA) engine on an I/O adapter to update a translation table used during DMA operations. The translation table is used during a DMA operation to map a virtual address provided by the I/O adapter to a physical address of a data page in the memory modules. If the DMA engine is being underutilized, the operating system updates the translation table such that a virtual address maps to physical address corresponding to a memory location in a more energy efficient memory module. However, if the DMA engine is over-utilized, the operating system may update the translation table such that the data used in the DMA engine is stored in memory modules that provide quicker access times—e.g., the operating system may map virtual addresses to physical addresses in DRAM rather than phase change memory. | 03-27-2014 |
20140101405 | REDUCING COLD TLB MISSES IN A HETEROGENEOUS COMPUTING SYSTEM - Methods and apparatuses are provided for avoiding cold translation lookaside buffer (TLB) misses in a computer system. A typical system is configured as a heterogeneous computing system having at least one central processing unit (CPU) and one or more graphic processing units (GPUs) that share a common memory address space. Each processing unit (CPU and GPU) has an independent TLB. When offloading a task from a particular CPU to a particular GPU, translation information is sent along with the task assignment. The translation information allows the GPU to load the address translation data into the TLB associated with the one or more GPUs prior to executing the task. Preloading the TLB of the GPUs reduces or avoids cold TLB misses that could otherwise occur without the benefits offered by the present disclosure. | 04-10-2014 |
20140101406 | ADJUNCT COMPONENT TO PROVIDE FULL VIRTUALIZATION USING PARAVIRTUALIZED HYPERVISORS - A system configuration is provided with a paravirtualizing hypervisor that supports different types of guests, including those that use a single level of translation and those that use a nested level of translation. When an address translation fault occurs during a nested level of translation, an indication of the fault is received by an adjunct component. The adjunct component addresses the address translation fault, at least in part, on behalf of the guest. | 04-10-2014 |
20140101407 | SELECTABLE ADDRESS TRANSLATION MECHANISMS - An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration, and the use of a particular translation structure format in translating an address is selectable. | 04-10-2014 |
20140101408 | ASYMMETRIC CO-EXISTENT ADDRESS TRANSLATION STRUCTURE FORMATS - An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration. This facilitates provision of guest access in virtualized operating systems, and/or the mixing of translation formats to better match the data access patterns being translated. | 04-10-2014 |
20140115297 | DETECTION OF CONFLICTS BETWEEN TRANSACTIONS AND PAGE SHOOTDOWNS - There is provided a system and a computer program product for detecting a conflict between a transaction and a TLB (Translation Lookaside Buffer) shootdown in a transactional memory in which a TLB shootdown operation message is received by a processor to invalidate at least one entry in a TLB of the processor corresponding to at least one page. The processor tracks pages touched by the transaction. The processor determines whether the received TLB shootdown operation message is associated with one of the touched pages. The processor aborts the transaction in response to determining that the received TLB shootdown operation message is associated with one of the touched pages. | 04-24-2014 |
20140122829 | EFFICIENT MEMORY VIRTUALIZATION IN MULTI-THREADED PROCESSING UNITS - A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches. | 05-01-2014 |
20140122830 | Operational Efficiency of Virtual TLBs - Various mechanisms are disclosed for improving the operational efficiency of a virtual translation look-aside buffer (TLB) in a virtual machine environment. For example, one mechanism fills in entries in a shadow page table (SPT) and additionally, speculatively fills in other entries in the SPT based on various heuristics. Another mechanism allows virtual TLBs (translation look-aside buffers) to cache partial walks in a guest page table tree. Still another mechanism allows for dynamic resizing of the virtual TLB to optimize for run-time characteristics of active workloads. Still another mechanism allows virtual machine monitors (VMMs) to support legacy and enlightened modes of virtual TLB operation. Finally, another mechanism allows the VMM to remove only the stale entries in SPTs when linking or switching address spaces. All these mechanisms, together or in part, increase the operational efficiency of the virtual TLB. | 05-01-2014 |
20140129798 | REDUCING MICROPROCESSOR PERFORMANCE LOSS DUE TO TRANSLATION TABLE COHERENCY IN A MULTI-PROCESSOR SYSTEM - A translation lookaside buffer coherency unit with Emulated Purge (TCUEP) translates a first virtual address for a first instruction into a first physical address. The TCUEP detects a multi-processor coherency operation that will cause hit suppression for certain entries in a TLB and purging of certain entries in the TLB. The TCUEP translates a second virtual address for a second instruction into a second physical address and stores the second physical address in a second entry in the TLB. The TCUEP configures a second marker in the second entry to indicate that the hit suppression is not allowed for the second entry, and that the purging is not allowed for the second entry. The TCUEP receives a first address translation request that indicates a hit in the second entry. The TCUEP resolves the first address translation request by returning the second physical address. | 05-08-2014 |
20140129799 | ADDRESS GENERATION IN AN ACTIVE MEMORY DEVICE - Embodiments relate to address generation in an active memory device that includes memory and a processing element. An aspect includes a method for address generation in the active memory device. The method includes reading a base address value and an offset address value from a register file group of the processing element. The processing element determines a virtual address based on the base address value and the offset address value. The processing element translates the virtual address into a physical address and accesses a location in the memory based on the physical address. | 05-08-2014 |
20140129800 | REDUCING MICROPROCESSOR PERFORMANCE LOSS DUE TO TRANSLATION TABLE COHERENCY IN A MULTI-PROCESSOR SYSTEM - Some embodiments include a method that can store a first physical address in a first entry in a translation lookaside buffer (TLB). The method can configure a first marker in the first entry in the TLB to indicate that hit suppression is allowed for the first entry. The method can detect a multi-processor coherency operation that will cause hit suppression for certain entries in a TLB, and cause purging of certain entries in the TLB. The method can translate a second virtual address for a second instruction into a second physical address. The method can store the second physical address in a second entry. The method can configure a second marker in the second entry in the TLB to indicate that the hit suppression is not allowed for the second entry in the TLB, and that the purging is not allowed for the second entry in the TLB. | 05-08-2014 |
20140136811 | ACTIVE MEMORY DEVICE GATHER, SCATTER, AND FILTER - Embodiments relate to loading and storing of data. An aspect includes a method for transferring data in an active memory device that includes memory and a processing element. An instruction is fetched and decoded for execution by the processing element. Based on determining that the instruction is a gather instruction, the processing element determines a plurality of source addresses in the memory from which to gather data elements and a destination address in the memory. One or more gathered data elements are transferred from the source addresses to contiguous locations in the memory starting at the destination address. Based on determining that the instruction is a scatter instruction, a source address in the memory from which to read data elements at contiguous locations and one or more destination addresses in the memory to store the data elements at non-contiguous locations are determined, and the data elements are transferred. | 05-15-2014 |
20140143518 | MEMORY SYSTEM AND METHOD FOR OPERATING THE SAME - A memory system comprises a central processing unit. A memory management unit receives a virtual address from the central processing unit. The memory management unit converts the virtual address into a physical address. A main memory is assessed based on the physical address. The main memory stores data used the central processing unit. The main memory includes a first area including a non-volatile memory. First file data having a first characteristic is included in the first area of the main memory. The main memory includes a second area including a volatile memory. Second file data having a second characteristic different from the first characteristic is included in the second area of the main memory. A management table manages only the first area of the first and second areas of the main memory. | 05-22-2014 |
20140156968 | FLEXIBLE PAGE SIZES FOR VIRTUAL MEMORY - A method for translating a virtual memory address into a physical memory address includes parsing the virtual memory address into a page directory entry offset, a page table entry offset, and an access offset. The page directory entry offset is combined with a virtual memory base address to locate a page directory entry in a page directory block, wherein the page directory entry includes a native page table size field and a page table block base address. The page table entry offset and the page table block base address are combined to locate a page table entry, wherein the page table entry includes a physical memory page base address and a size of the physical memory page is indicated by the native page table size field. The access offset and the physical memory page base address are combined to determine the physical memory address. | 06-05-2014 |
20140164732 | TRANSLATION MANAGEMENT INSTRUCTIONS FOR UPDATING ADDRESS TRANSLATION DATA STRUCTURES IN REMOTE PROCESSING NODES - Translation management instructions are used in a multi-node data processing system to facilitate remote management of address translation data structures distributed throughout such a system. Thus, in multi-node data processing systems where multiple processing nodes collectively handle a workload, the address translation data structures for such nodes may be collectively managed to minimize translation misses and the performance penalties typically associated therewith. | 06-12-2014 |
20140173244 | FILTERING REQUESTS FOR A TRANSLATION LOOKASIDE BUFFER - The present application describes a method and apparatus for filtering requests to a translation lookaside buffer (TLB). Some embodiments of the method include receiving, from a first translation lookaside buffer (TLB), an indication of a first virtual address associated with a request to a second TLB for a page table entry in response to a miss in the first TLB. Some embodiments of the method also include filtering the request based on a comparison of the first virtual address and one or more second virtual addresses associated with one or more previous requests to the second TLB. | 06-19-2014 |
20140181459 | SPECULATIVE ADDRESSING USING A VIRTUAL ADDRESS-TO-PHYSICAL ADDRESS PAGE CROSSING BUFFER - A method includes receiving an instruction to be executed by a processor. The method further includes performing a lookup in a page crossing buffer that includes one or more entries to determine if the instruction has an entry in the page crossing buffer. Each of the entries includes a physical address. The method further includes, when the page crossing buffer has the entry in the page crossing buffer, retrieving a particular physical address from the entry in the page crossing buffer. | 06-26-2014 |
20140181460 | PROCESSING DEVICE WITH ADDRESS TRANSLATION PROBING AND METHODS - A data processing device is provided that employs multiple translation look-aside buffers (TLBs) associated with respective processors that are configured to store selected address translations of a page table of a memory shared by the processors. The processing device is configured such that when an address translation is requested by a processor and is not found in the TLB associated with that processor, another TLB is probed for the requested address translation. The probe across to the other TLB may occur in advance of a walk of the page table for the requested address or alternatively a walk can be initiated concurrently with the probe. Where the probe successfully finds the requested address translation, the page table walk can be avoided or discontinued. | 06-26-2014 |
20140181461 | REPORTING ACCESS AND DIRTY PAGES - A method and apparatus for reporting events into at least one event log are presented. An “access” event entry may be added to an event log stored in memory when a peripheral device accesses an address of a memory page described by a page table entry (PTE). A “dirty” event entry may be added to an event log stored in memory when a page writes to a memory page. The event log may reside in an input/output memory management unit (IOMMU) that includes a translation lookaside buffer (TLB). The IOMMU may report the event log entries to system memory. When there is no entry in the TLB and a direct memory access (DMA) read operation enters the IOMMU, a PTE may be loaded into the TLB after updating an access log to calculate an address. If the DMA operation is not a read operation, both dirty and access logs may be updated. | 06-26-2014 |
20140181462 | VIRTUAL ADDRESS BASED MEMORY REORDERING - A method for detecting an instruction ordering violation in a CPU. The method includes receiving a reordered stream of instructions and detecting whether an ordering violation has occurred by using virtual addresses. The method further includes transferring results of the reordered stream of instructions from a load store buffer into a cache and detecting whether an ordering violation has occurred by using physical addresses. Subsequently, a recovery is initiated upon detection of an ordering violation. | 06-26-2014 |
20140181463 | Dynamic Address Translation with Translation Table Entry Format Control for Identifying Format of the Translation Table Entry - An enhanced dynamic address translation facility is provided. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory. | 06-26-2014 |
20140189285 | Apparatus and Method For Tracking TLB Flushes On A Per Thread Basis - A method is described that includes recognizing that TLB information of one or more hardware threads is to be invalidated. The method also includes determining which ones of the one or more hardware threads are in a state in which TLB information is flushed. The method also includes directing a TLB shootdown to those of the or more hardware threads that are in a state in which TLB information is not flushed. | 07-03-2014 |
20140201494 | OVERLAP CHECKING FOR A TRANSLATION LOOKASIDE BUFFER (TLB) - An apparatus includes a translation lookaside buffer (TLB). The TLB includes at least one entry that includes an entry virtual address and an entry page size indication corresponding to an entry page. The apparatus also includes input logic configured to receive an input page size indication and an input virtual address corresponding to an input page. The apparatus further includes overlap checking logic configured to determine, based at least in part on the entry page size indication and the input page size indication, whether the input page overlaps the entry page. | 07-17-2014 |
20140201495 | PAGE MISS HANDLER INCLUDING WEAR LEVELING LOGIC - Embodiments of the invention describe an apparatus, system and method for utilizing a page miss handler having wear leveling logic/modules for memory devices. Embodiments of the invention may track an amount of writes directed towards cells of a memory device, and determine whether a linear address specified by a system write transaction is included in a translation-lookaside buffer (TLB). In response to determining the linear address is not included in the TLB, resulting in a TLB miss, embodiments of the invention may perform a page table walk to obtain a corresponding physical address, and convert the physical address to a device address for accessing the memory device based the tracked amount of writes. Thus, embodiments of the invention are more efficient compared to prior art solutions, as instead of all memory operations, only those that miss in the TLB incur additional wear leveling address translation overhead. | 07-17-2014 |
20140208064 | Virtual Memory Management System with Reduced Latency - A computer system using virtual memory provides hybrid memory access either through a conventional translation between virtual memory and physical memory using a page table possibly with a translation lookaside buffer, or a high-speed translation using a fixed offset value between virtual memory and physical memory. Selection between these modes of access may be encoded into the address space of virtual memory eliminating the need for a separate tagging operation of specific memory addresses. | 07-24-2014 |
20140223137 | STORING A SYSTEM-ABSOLUTE ADDRESS (SAA) IN A FIRST LEVEL TRANSLATION LOOK-ASIDE BUFFER (TLB) - Embodiments relate to a method, system and computer program product for storing a system-absolute address (SAA) in a first level look-aside buffer (TLB). In one embodiment, the system includes a central processor including the TLB and general purpose registers (GPRS). The TLB is configured for storing the SAA. The central processor is configured for issuing a load system-absolute address (LSAA) instruction. The system includes a translation unit that is in communication with the TLB of the central processor. The system is configured to perform a method including determining, based on the LSAA instruction being issued, whether the SAA is stored in the TLB. The method includes sending a translation request to the translation unit from the central processor based on the SAA not being stored in the TLB. The method includes determining the SAA by the translation unit based on receiving the translation request. | 08-07-2014 |
20140281363 | MULTI-THREADED MEMORY MANAGEMENT - Memory management includes maintaining a first mapping structure for each thread of a multi-threaded process. A second mapping structure is maintained for each core of a multi-core processing device. A global mapping structure for shared memory mappings is maintained. During thread context switches, copying thread context entries without modifying a page-mapping base address register of each core of the multi-core processing device. | 09-18-2014 |
20140281364 | MICROCONTROLLER FOR MEMORY MANAGEMENT UNIT - One embodiment of the present invention includes a microcontroller coupled to a memory management unit (MMU). The MMU is coupled to a page table included in a physical memory, and the microcontroller is configured to perform one or more virtual memory operations associated with the physical memory and the page table. In operation, the microcontroller receives a page fault generated by the MMU in response to an invalid memory access via a virtual memory address. To remedy such a page fault, the microcontroller performs actions to map the virtual memory address to an appropriate location in the physical memory. By contrast, in prior-art systems, a fault handler would typically remedy the page fault. Advantageously, because the microcontroller executes these tasks locally with respect to the MMU and the physical memory, latency associated with remedying page faults may be decreased. Consequently, overall system performance may be increased. | 09-18-2014 |
20140281365 | FRAME BUFFER ACCESS TRACKING VIA A SLIDING WINDOW IN A UNIFIED VIRTUAL MEMORY SYSTEM - One embodiment of the present invention is a memory subsystem that includes a sliding window tracker that tracks memory accesses associated with a sliding window of memory page groups. When the sliding window tracker detects an access operation associated with a memory page group within the sliding window, the sliding window tracker sets a reference bit that is associated with the memory page group and is included in a reference vector that represents accesses to the memory page groups within the sliding window. Based on the values of the reference bits, the sliding window tracker causes the selection a memory page in a memory page group that has fallen into disuse from a first memory to a second memory. Because the sliding window tracker tunes the memory pages that are resident in the first memory to reflect memory access patterns, the overall performance of the memory subsystem is improved. | 09-18-2014 |
20140281366 | ADDRESS TRANSLATION IN A SYSTEM USING MEMORY STRIPING - A system and associated methods are disclosed for translating virtual memory addresses to physical memory addresses in a parallel computing system using memory striping. One method comprises: receiving a virtual memory address, comparing a portion of the received virtual memory address to each of a plurality of entries of a virtual memory address matching table, determining a matching row of the virtual memory address matching table for the portion of the received virtual memory address, shifting a contiguous set of bits of the received virtual memory address, wherein the shifting is performed in accordance with information from the matching row, and combining the shifted contiguous set of bits of the received virtual memory address with high-order physical memory address bits associated with the determined matching row of the virtual memory address matching table, and with low-order bits of the received virtual memory address, to produce a physical memory address. | 09-18-2014 |
20140304488 | LINEAR TO PHYSICAL ADDRESS TRANSLATION WITH SUPPORT FOR PAGE ATTRIBUTES - Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed. | 10-09-2014 |
20140310502 | MEMORY MANAGEMENT APPARATUS AND MEMORY MANAGEMENT METHOD THEREOF - A memory management apparatus and method thereof are disclosed. The memory management apparatus includes a micro translation look-aside buffers, a main translation look-aside buffer, a page address history table and a controller. The page address history table is used to record the space size information for a plurality of page table entry which are written to the main translation look-aside buffer. The controller decides to whether access a page table entry or not from the main translation look-aside buffer according to the page address history table. | 10-16-2014 |
20140337600 | PROVIDING METADATA IN A TRANSLATION LOOKASIDE BUFFER (TLB) - In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA) translation and a second portion to store bits for a memory page associated with the VA-to-PA translation, where the bits indicate attributes of information in the memory page. Other embodiments are described and claimed. | 11-13-2014 |
20140351553 | LINEAR TO PHYSICAL ADDRESS TRANSLATION WITH SUPPORT FOR PAGE ATTRIBUTES - Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed. | 11-27-2014 |
20140351554 | LINEAR TO PHYSICAL ADDRESS TRANSLATION WITH SUPPORT FOR PAGE ATTRIBUTES - Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed. | 11-27-2014 |
20150039850 | SYNCHRONIZING A TRANSLATION LOOKASIDE BUFFER WITH AN EXTENDED PAGING TABLE - A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system. | 02-05-2015 |
20150046670 | STORAGE SYSTEM AND WRITING METHOD THEREOF - A writing method of a storage system which includes a host and a storage connected to the host, includes receiving journal data during a generation of a data writing transaction; inserting in a first map table, a plurality of entries, each entry including a first logical address of a first logical area of the storage and a second logical address of a second logical area of the storage; writing the journal data to a physical area of the storage corresponding to the first logical address; and remapping the physical area from the first logical address onto the second logical address using the plurality of entries when a size of a usable space of the first logical area is less than a desired value. | 02-12-2015 |
20150052329 | MEMORY CONTROL DEVICE, HOST COMPUTER, INFORMATION PROCESSING SYSTEM AND METHOD OF CONTROLLING MEMORY CONTROL DEVICE - A memory control device includes an address translation information holding portion that holds a portion of entries that are selected from address translation information containing a plurality of entries that associate a logical address with a physical address of a memory device; an address translation information acquisition unit that, when the entry containing the logical address specified by a host computer is not held in the address translation information holding portion, acquires the entry that is not held from the host computer and causes the address translation information holding portion to hold the entry; an address translation unit that translates the specified logical address into the physical address on the basis of the entries that are held in the address translation information holding portion; and a data transfer unit that executes a data transfer process in which transfer data is transferred using the translated physical address. | 02-19-2015 |
20150089185 | Managing Mirror Copies without Blocking Application I/O - Mechanisms, in a data processing system comprising a processor and an address translation cache, for caching address translations in the address translation cache are provided. The mechanisms receive an address translation from a server computing device to be cached in the data processing system. The mechanisms generate a cache key based on a current valid number of mirror copies of data maintained by the server computing device. The mechanisms allocate a buffer of the address translation cache, corresponding to the cache key, for storing the address translation and store the address translation in the allocated buffer. Furthermore, the mechanisms perform an input/output operation using the address translation stored in the allocated buffer. | 03-26-2015 |
20150095610 | MULTI-STAGE ADDRESS TRANSLATION FOR A COMPUTING DEVICE - Providing for address translation in a virtualized system environment is disclosed herein. By way of example, a memory management apparatus is provided that comprises a shared translation look-aside buffer (TLB) that includes a plurality of translation types, each supporting a plurality of page sizes, one or more processors, and a memory management controller configured to work with the one or more processors. The memory management controller includes logic configured for caching virtual address to physical address translations and intermediate physical address to physical address translations in the shared TLB, logic configured to receive a virtual address for translation from a requester, logic configured to conduct a table walk of a translation table in the shared TLB to determine a translated physical address in accordance with the virtual address, and logic configured to transmit the translated physical address to the requester. | 04-02-2015 |
20150095611 | METHOD AND PROCESSOR FOR REDUCING CODE AND LATENCY OF TLB MAINTENANCE OPERATIONS IN A CONFIGURABLE PROCESSOR - A memory management unit (MMU) is disclosed for storing mappings between virtual addresses and physical addresses. The MMU includes a translation look-aside buffer (TLB) and a memory management unit controller. The TLB stores mappings between a virtual address and a physical address. The MMU controller receives a request to insert an entry into the TLB and performs a set of operations based on the received request. The MMU controller determines whether an entry stored in the TLB is associated with the virtual address of the request, removes the entry stored in the TLB that is associated with the virtual address and inserts the requested entry into the TLB. | 04-02-2015 |
20150095612 | TECHNIQUES FOR HANDLING MEMORY ACCESSES BY PROCESSOR-INDEPENDENT EXECUTABLE CODE IN A MULTI-PROCESSOR ENVIRONMENT - A method and apparatus for virtual address mapping are provided. The method includes determining an offset value respective of at least a first portion of code stored on a code memory unit, generating a first virtual code respective of the first portion of code and a second virtual code respective of a second portion of code stored on the code memory unit; mapping the first virtual code to a first virtual code address and the second virtual code to a second virtual code address; generating a first virtual data respective of the first portion of data and a second virtual data respective of the second portion of data; and mapping the first virtual data to a first virtual data address and the second virtual data to a second virtual data address. | 04-02-2015 |
20150100753 | MULTI-CORE HETEROGENEOUS SYSTEM TRANSLATION LOOKASIDE BUFFER COHERENCY - Methods, devices, and instructions for performing a reverse translation lookaside buffer (TLB) look-up using a physical address input, including obtaining with a first processor the physical address input, wherein the physical address input indicates a physical address corresponding to a shared memory, obtaining a first mask associated with a first virtual address from a first TLB entry within a TLB associated with the first processor, wherein the obtained first mask is a bit pattern, obtaining from the first TLB entry a first page frame number associated with the shared memory, applying the obtained first mask to the obtained first page frame number to generate a first value, applying the obtained first mask to the obtained physical address input to generate a second value, and comparing the first value and the second value to determine whether the first value and the second value match. | 04-09-2015 |
20150106586 | METHOD AND A DEVICE FOR CONTROLLING MEMORY-USAGE OF A FUNCTIONAL COMPONENT - The invention relates to controlling memory-usage of a functional component, e.g. a network interface of a router or a switch. A portion of a virtual memory organized to comprise virtual memory pages is reserved ( | 04-16-2015 |
20150121033 | INFORMATION PROCESSING APPARATUS AND DATA TRANSFER CONTROL METHOD - An address translation table stores therein an association relation between a logical address and a physical address, change information indicating a change in the association relation when the association relation is changed such that a physical address having been associated with each logical address is associated with a different logical address, and the different logical address. A table control unit, when receiving a command to move data between logical addresses from a CPU, changes the association relation in the address translation table such that a movement-destination logical address is associated with a physical address in which the data is stored, sets change information in a movement-source logical address, and stores the movement-destination logical address as a different logical address associated with the movement-source logical address. | 04-30-2015 |
20150149743 | MANAGEMENT METHOD OF VIRTUAL-TO-PHYSICAL ADDRESS TRANSLATION SYSTEM USING PART OF BITS OF VIRTUAL ADDRESS AS INDEX - A management method of a virtual-to-physical address translation system includes the following steps: providing a first storage space, wherein the first storage space includes a plurality of buffer entries; providing a second storage space, wherein the second storage space includes a plurality of translation entries, and the translation entries correspond to a plurality of translation indices; and when receiving a write instruction to write a first virtual-to-physical address translation into a specific buffer entry of the buffer entries, storing the first virtual-to-physical address translation in a write translation entry of the translation entries according to a first part of bits of a first virtual address corresponding to the first virtual-to-physical address translation, and storing the first virtual address and a write translation index corresponding to the write translation entry in the specific buffer entry. | 05-28-2015 |
20150301939 | MANAGING TRANSLATIONS ACROSS MULTIPLE CONTEXTS USING A TLB WITH ENTRIES DIRECTED TO MULTIPLE PRIVILEGE LEVELS AND TO MULTIPLE TYPES OF ADDRESS SPACES - For a current context in control of a processor requesting access to a particular address, a translation lookaside buffer (TLB) controller specifies a virtual address with a logical partition identifier value indicating a privilege setting of the current context, a process identifier value indicating whether the address is within shared address space, and an effective address comprising at least a portion of the particular address. In response to the virtual address not matching at least one entry within a TLB comprising at least one entry stored for at least one previous translation of at least one previous address, the TLB controller translates the virtual address into a real page number using at least one page table and adding a new entry to the TLB with the virtual address and the real page number, wherein each at least one entry within the TLB identifies a separate privilege setting from among a plurality of privilege settings and a separate indicator of whether the address is within the shared address space. | 10-22-2015 |
20150301950 | MANAGING TRANSLATION OF A SAME ADDRESS ACROSS MULTIPLE CONTEXTS USING A SAME ENTRY IN A TRANSLATION LOOKASIDE BUFFER - In response to a current context, with a particular process currently in control of a processor requesting access to a shared address space, a translation lookaside buffer (TLB) controller sets a process identifier field in a virtual address to be looked up in a TLB to a clamped value different from an identifier for the process, wherein the virtual address comprises at least the process identifier field and an effective address field set to an address in the requested shared address space. In response to the TLB controller comparing the virtual address for the current context to a particular entry of at least one entry within the TLB comprising the at least one entry stored for a previous translation of a previous virtual address, the TLB controller only indicates a match between the process identifier field and a translation process identifier field within the particular entry of the TLB if the translation process identifier field is also set to the clamped value. | 10-22-2015 |
20150301951 | MANAGING TRANSLATIONS ACROSS MULTIPLE CONTEXTS USING A TLB WITH ENTRIES DIRECTED TO MULTIPLE PRIVILEGE LEVELS AND TO MULTIPLE TYPES OF ADDRESS SPACES - For a current context in control of a processor requesting access to a particular address, a translation lookaside buffer (TLB) controller specifies a virtual address with a logical partition identifier value indicating a privilege setting of the current context, a process identifier value indicating whether the address is within shared address space, and an effective address comprising at least a portion of the particular address. In response to the virtual address not matching at least one entry within a TLB comprising at least one entry stored for at least one previous translation of at least one previous address, the TLB controller translates the virtual address into a real page number using at least one page table and adding a new entry to the TLB with the virtual address and the real page number, wherein each at least one entry within the TLB identifies a separate privilege setting from among a plurality of privilege settings and a separate indicator of whether the address is within the shared address space. | 10-22-2015 |
20150301952 | MULTIPLEXED MEMORY FOR SEGMENTS AND PAGES - Disclosed herein are systems and methods for paging to a direct segment maintained by a multiplexed TLB. The multiplexed TLB defines a direct segment to directly map a virtual address range to a physical address range, which increases the reach of the multiplexed TLB. A partition code is maintained in the multiplexed TLB to indicate usage of the direct segment by an associated process. A management process, such as a system pager, uses the unused part of the direct segment for storing paged data. As the process continues to use more of the direct segment, paged data stored in the previously unused part of the direct segment can be evicted from memory or moved elsewhere in memory so that the process can continue to use the direct segment. | 10-22-2015 |
20150301953 | MANAGING TRANSLATION OF A SAME ADDRESS ACROSS MULTIPLE CONTEXTS USING A SAME ENTRY IN A TRANSLATION LOOKASIDE BUFFER - In response to a current context, with a particular process currently in control of a processor requesting access to a shared address space, a translation lookaside buffer (TLB) controller sets a process identifier field in a virtual address to be looked up in a TLB to a clamped value different from an identifier for the process, wherein the virtual address comprises at least the process identifier field and an effective address field set to an address in the requested shared address space. In response to the TLB controller comparing the virtual address for the current context to a particular entry of at least one entry within the TLB comprising the at least one entry stored for a previous translation of a previous virtual address, the TLB controller only indicates a match between the process identifier field and a translation process identifier field within the particular entry of the TLB if the translation process identifier field is also set to the clamped value. | 10-22-2015 |
20150339226 | Creating A Dynamic Address Translation With Translation Exception Qualifiers - An enhanced dynamic address translation facility product is created such that, in one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Dynamic address translation of the virtual address proceeds. In response to a translation interruption having occurred during dynamic address translation, bits are stored in a translation exception qualifier (TXQ) field to indicate that the exception was either a host DAT exception having occurred while running a host program or a host DAT exception having occurred while running a guest program. The TXQ is further capable of indicating that the exception was associated with a host virtual address derived from a guest page frame real address or a guest segment frame absolute address. The TXQ is further capable of indicating that a larger or smaller host frame size is preferred to back a guest frame. | 11-26-2015 |
20150356022 | VIRTUAL ADDRESS TABLE - The present disclosure includes apparatuses and methods related to virtual address tables. An example method comprises generating an object file that comprises: an instruction comprising a number of arguments; and an address table comprising a number of indexed address elements. Each one of the number of indexed address elements can correspond to a virtual address of a respective one of the number of arguments, wherein the address table can serves as a target for the number of arguments. The method can include storing the object file in a memory. | 12-10-2015 |
20150363329 | MEMORY ADDRESS TRANSLATION - In one example, a device includes at least one processor, a transceiver configured to send and receive data, and at least one memory device. The at least one memory device includes a range of physical memory addresses divided into a plurality of physical memory partitions that each includes a sub-range of the range of physical memory addresses and corresponds to a range of virtual memory addresses. Instructions encoded in the at least one memory device cause the at least one processor to receive a memory address request configured to request access to a requested physical memory address within the range of physical memory addresses, determine that the requested physical memory address is associated with one of the plurality of physical memory partitions, determine a virtual memory address corresponding to the requested physical memory address, and access the requested physical memory address via the determined virtual memory address. | 12-17-2015 |
20150378930 | VALIDATING VIRTUAL ADDRESS TRANSLATION - Systems and methods for validating virtual address translation. An example processing system comprises: a processing core to execute a first application associated with a first privilege level and a second application associated with a second privilege level, wherein a first set of privileges associated with the first privilege level includes a second set of privileges associated with the second privilege level; and an address validation component to validate, in view of an address translation data structure maintained by the first application, a mapping of a first address defined in a first address space of the second application to a second address defined in a second address space of the second application. | 12-31-2015 |
20160011986 | MAINTAINING PROCESSOR RESOURCES DURING ARCHITECTURAL EVENTS | 01-14-2016 |
20160019162 | SYNCHRONIZING A TRANSLATION LOOKASIDE BUFFER WITH AN EXTENDED PAGING TABLE - A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system. | 01-21-2016 |
20160019163 | SYNCHRONIZING A TRANSLATION LOOKASIDE BUFFER WITH AN EXTENDED PAGING TABLE - A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system. | 01-21-2016 |
20160041921 | LINEAR TO PHYSICAL ADDRESS TRANSLATION WITH SUPPORT FOR PAGE ATTRIBUTES - Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed. | 02-11-2016 |
20160041922 | EFFICIENT ADDRESS TRANSLATION CACHING IN A PROCESSOR THAT SUPPORTS A LARGE NUMBER OF DIFFERENT ADDRESS SPACES - A processor includes translation-lookaside buffer (TLB) and a mapping module. The TLB includes a plurality of entries, wherein each entry of the plurality of entries is configured to hold an address translation and a valid bit vector, wherein each bit of the valid bit vector indicates, for a respective address translation context, the address translation is valid if set and invalid if clear. The TLB also includes an invalidation bit vector having bits corresponding to the bits of the valid bit vector of the plurality of entries, wherein a set bit of the invalidation bit vector indicates to simultaneously clear the corresponding bit of the valid bit vector of each entry of the plurality of entries. The mapping module generates the invalidation bit vector. | 02-11-2016 |
20160048454 | VIRTUALIZATION OF MEMORY FOR PROGRAMMABLE LOGIC - A processing sub-system is configured to execute a program using a set of virtual memory addresses to reference memory locations for storage of variables of the program. A programmable logic sub-system is configured to implement a set of I/O circuits specified in a configuration data stream, each of the I/O circuits having a respective ID and configured to access one of the variables. A memory management circuit is configured to map the virtual memory addresses to physical memory addresses of a memory and map IDs to the physical address used to store the corresponding variables. A TLB is configured to receive a memory access request, from the I/O circuits, each request indicating an ID and provide, to the memory, a memory access request indicating the physical memory address that is mapped to the | 02-18-2016 |
20160062909 | SYSTEMS AND METHODS FOR ACCESSING MEMORY - Methods of mapping memory cells to applications, methods of accessing memory cells, systems, and memory controllers are described. In some embodiments, a memory system including multiple physical channels is mapped into regions, such that any region spans each physical channel of the memory system. Applications are allocated memory in the regions, and performance and power requirements of the applications are associated with the regions. Additional methods and systems are also described. | 03-03-2016 |
20160077976 | ADDRESS TRANSLATION SERVICES FOR DIRECT ACCESSING OF LOCAL MEMORY OVER A NETWORK FABRIC - A method in a system that includes first and second devices that communicate with one another over a fabric that operates in accordance with a fabric address space, and in which the second device accesses a local memory via a local connection and not over the fabric, includes sending from the first device to a translation agent (TA) a translation request that specifies an untranslated address in an address space according to which the first device operates, for directly accessing the local memory of the second device. A translation response that specifies a respective translated address in the fabric address space, which the first device is to use instead of the untranslated address is received by the first device. The local memory of the second device is directly accessed by the first device over the fabric by converting the untranslated address to the translated address. | 03-17-2016 |
20160085685 | INSTRUCTION AND LOGIC FOR SUPPORT OF CODE MODIFICATION IN TRANSLATION LOOKASIDE BUFFERS - A processor includes a core with logic to execute a translated instruction. The translated instruction is translated from an instruction stored in a memory location. The processor further includes a translation lookaside buffer including logic to store translation indicators from a physical map. Each translation indicator indicates whether a corresponding memory location includes translated code to be protected. The processor further includes a translation indicator agent including logic to determine whether the buffer indicates whether the memory location has been modified subsequent to translation of the instruction. | 03-24-2016 |
20160085686 | SYNCHRONIZING A TRANSLATION LOOKASIDE BUFFER WITH PAGE TABLES - The translation lookaside buffer (TLB) of a processor is kept in synchronization with a guest page table by use of an indicator referred to as a “T” bit. The T bit of the NPT/EPT entries mapping the guest page table are set when a page walk is performed on the NPT/EPT. When modifications are made to pages mapped by NPT/EPT entries with their T bit set, changes to the TLB are made so that the TLB remains in synchronization with the guest page table. Accordingly, record/replay of virtual machines of virtualized computer systems may be performed reliably with no non-determinism introduced by stale TLBs that fall out of synchronization with the guest page table. | 03-24-2016 |
20160092371 | Method and Apparatus For Deterministic Translation Lookaside Buffer (TLB) Miss Handling - An apparatus and method are described for translation lookaside buffer (TLB) miss handling. For example, one embodiment of a processor comprises: a translation lookaside buffer (TLB) to store virtual-to-physical address translations; a page miss handler (PMH) to process TLB misses when a desired virtual-to-physical address translation is not present in the TLB; and a compressed page table to be managed by the PMH, the compressed page table to store specified portions of page tables, wherein in response to a TLB miss for a first address translation, the PMH is to check the compressed page table to determine if a page table entry corresponding to the first address translation is stored therein and, if so, to provide the first address translation from the compressed page table. | 03-31-2016 |
20160098357 | METHOD AND APPARATUS FOR DETERMINING PHYSICAL ADDRESS - A method and an apparatus for determining a physical address are disclosed. According to the present disclosure, a page size is obtained according to the higher-order N bits of a linear address, where N is greater than 0 and less than a quantity of bits of the linear address; an index number of a translation lookaside buffer TLB is obtained according to the page size; a mask is obtained according to the page size and a supported minimum page size; a label of the TLB is obtained according to the mask; the higher-order MAC1 bits of a physical address corresponding to the linear address are obtained by searching the TLB according to the index number and the label; and the physical address is obtained according to the mask, the supported minimum page, and the higher-order MAC1 bits of the physical address. | 04-07-2016 |
20160124862 | Method and Device for Storing Direct Table - Provides are a method and device for storing a direct table. The method includes that: it is determined that an internal table entry storage space of a chip is exhausted; a plurality of table entries of a direct table is stored in an internal statistics storage space of the chip, wherein the direct table can be directly accessed via a storage medium. The disclosure solves the problem of degraded forwarding performance caused by modes of storing the table entry in the prior art, and improves the forwarding performance. | 05-05-2016 |
20160140047 | TRANSLATION LOOKASIDE BUFFER MANAGEMENT - Each of multiple translation lookaside buffers (TLBs) is associated with a corresponding processing element. A first TLB invalidation (TLBI) instruction is issued at a first processing element, and sent to a second processing element. An element-specific synchronization instruction is issued at the first processing element. A synchronization command is broadcast, and received at the second processing element. The element-specific synchronization instruction prevents issuance of additional TLBI instructions at the first processing element until an acknowledgement in response to the synchronization command is received at the first processing element. After completion of any TLBI instructions issued at the second processing element before the synchronization command was received, the acknowledgement is sent from the second processing element to the first processing element, indicating that any TLBI instructions issued at the second processing element before the synchronization command was received at the second processing element are complete. | 05-19-2016 |
20160170897 | DATA STORAGE BASED ON MEMORY PERSISTENCY | 06-16-2016 |
20160170904 | Method and Apparatus for Querying Physical Memory Address | 06-16-2016 |
20160179694 | TRACKING MEMORY ACCESSES WHEN INVALIDATING EFFECTIVE ADDRESS TO REAL ADDRESS TRANSLATIONS | 06-23-2016 |
20160179695 | Local Page Translation and Permissions Storage for the Page Window in Program Memory Controller | 06-23-2016 |
20160179698 | TRACKING MEMORY ACCESSES WHEN INVALIDATING EFFECTIVE ADDRESS TO REAL ADDRESS TRANSLATIONS | 06-23-2016 |
20160179699 | HIDING PAGE TRANSLATION MISS LATENCY IN PROGRAM MEMORY CONTROLLER BY NEXT PAGE PREFETCH ON CROSSING PAGE BOUNDARY | 06-23-2016 |
20160188488 | STORING A SYSTEM-ABSOLUTE ADDRESS (SAA) IN A FIRST LEVEL TRANSLATION LOOK-ASIDE BUFFER (TLB) - Embodiments relate to a method, system and computer program product for storing a system-absolute address (SAA) in a first level look-aside buffer (TLB). In one embodiment, the system includes a central processor including the TLB and general purpose registers (GPRS). The TLB is configured for storing the SAA. The central processor is configured for issuing a load system-absolute address (LSAA) instruction. The system includes a translation unit that is in communication with the TLB of the central processor. The system is configured to perform a method including determining, based on the LSAA instruction being issued, whether the SAA is stored in the TLB. The method includes sending a translation request to the translation unit from the central processor based on the SAA not being stored in the TLB. The method includes determining the SAA by the translation unit based on receiving the translation request. | 06-30-2016 |
20160196217 | Updatable Address Lookup Application Program Interface | 07-07-2016 |
20170235678 | MAINTAINING PROCESSOR RESOURCES DURING ARCHITECTURAL EVENTS | 08-17-2017 |
20180024940 | SYSTEMS AND METHODS FOR ACCESSING A UNIFIED TRANSLATION LOOKASIDE BUFFER | 01-25-2018 |
20190146928 | OPTIMIZING PAGE TABLE MANIPULATIONS | 05-16-2019 |