Entries |
Document | Title | Date |
20080244191 | Processor system management mode caching - In some embodiments, an apparatus comprises one or more processors supporting a system management mode, system management memory, and software controllable caching of memory, one or more memory modules, a memory controller, and a communication bus to couple the one or more memory modules to the memory controller. Other embodiments may be described. | 10-02-2008 |
20080270707 | DATA PROCESSOR - A data processor arranged so that a block transfer control unit ( | 10-30-2008 |
20080307167 | Converting Victim Writeback to a Fill - In one embodiment, a processor may be configured to write ECC granular stores into the data cache, while non-ECC granular stores may be merged with cache data in a memory request buffer. In one embodiment, a processor may be configured to detect that a victim block writeback hits one or more stores in a memory request buffer (or vice versa) and may convert the victim block writeback to a fill. In one embodiment, a processor may speculatively issue stores that are subsequent to a load from a load/store queue, but prevent the update for the stores in response to a snoop hit on the load. | 12-11-2008 |
20080320232 | Preventing Writeback Race in Multiple Core Processors - A processor prevents writeback race condition errors by maintaining responsibility for data until the writeback request is confirmed by an intervention message from a cache coherency manager. If a request for the same data arrives before the intervention message, the processor core unit provides the requested data and cancels the pending writeback request. The cache coherency data associated with cache lines indicates whether a request for data has been received prior to the intervention message associated with the writeback request. The cache coherency data of a cache line has a value of “modified” when the writeback request is initiated. When the intervention message associated with the writeback request is received, the cache lines's cache coherency data is examined. A change in the cache coherency data from the value of “modified” indicates that the request for data has been received prior to the intervention and the writeback request should be cancelled. | 12-25-2008 |
20080320233 | Reduced Handling of Writeback Data - The complexity of the logic of the cache coherency manager unit is reduced by leveraging the data path for intervention messages and responses to carry data associated with writeback requests. A processor core unit sends a writeback request to the cache coherency manager unit. The request does not include the writeback data. Upon receiving an intervention message associated with the writeback request, the processor core unit provides an intervention message response to the cache coherency manager unit indicating that the writeback operation should not be cancelled. The intervention message response includes the writeback data. Because the cache coherency manager already requires a data path to handle data transfers between processor core units, little or no additional overhead needs to be added to the cache coherency manager to handle data associated with writeback request. | 12-25-2008 |
20080320234 | Information processing apparatus and data transfer method - One aspect of the embodiments utilizes an information processing apparatus having a plurality of system boards connected via a bus, each system board including a CPU having a cache memory, a main memory that forms a shared memory, and a system controller that manages the CPU and the main memory as well as controls a data transfer of at least one of the cache memory and the main memory by a memory access request, wherein each system controller including a snoop controller that selects a transfer source CPU from transfer source candidate CPUs each having cache memory including a data requested by the memory access request when the data is available in a plurality of cache memories. | 12-25-2008 |
20090019235 | APPARATUS AND METHOD FOR CACHING DATA IN A COMPUTER MEMORY - A memory apparatus that exclusive ORs, for validity data having an array of logical values indicative of whether the sectors are valid, each bit of the validity data with the next bit, masks a bit string having an array of the exclusive ORs except the first bit of bits whose logical values are true in a preset detection range, detects the position of a bit whose logical value is true in the masked bit string, and every time the bit position is detected, executes the process of setting the bit position adjacent to the end with respect to the bit position as the detection range and repeats it until no bit position is detected, calculates the address of the main memory corresponding to each area of consecutive invalid sectors according to the bit position detected in sequence, issues a read command to the calculated address, and writes back the cache segment. | 01-15-2009 |
20090037666 | CACHE LOCKING DEVICE AND METHODS THEREOF - A method and device for locking a cache line of a cache is disclosed. The method includes automatically changing a state of a cache line from a valid locked state to an invalid locked state in response to receiving an indication that a memory location external to the cache and corresponding to the cache line is associated with an access request by a processor or other data access module. Thus, the locked state of a cache line is maintained even after data in the locked cache line is invalidated. By maintaining the invalid locked state, the cache line is not available for reallocation by the cache. This allows locked cache lines that become invalidated to remain locked without additional software overhead to periodically determine whether the lock has been lost due to invalidation of the cache line. | 02-05-2009 |
20090083495 | MEMORY CIRCUIT WITH ECC BASED WRITEBACK - Provided herein are circuits incorporating a dynamic technique to minimize power overhead with writeback. In some embodiments, error-correction-code (ECC) is used to dynamically detect bit failures and use that information to identify memory sub-sections to be enabled for writeback. | 03-26-2009 |
20090089511 | HYBRID CACHE COHERENCE USING FINE-GRAINED HARDWARE MESSAGE PASSING - Multiprocessor systems conducting operations utilizing global shared memory must ensure that the memory is coherent. A hybrid system that combines hardware memory transactions with that of direct messaging provides memory coherence with minimal overhead requirement or bandwidth demands. Memory access transactions are intercepted and converted to direct messages which are then communicated to a target and/or remote node. Thereafter the message invokes a software handler which implements the cache coherence protocol. The handler uses additional messages to invalidate or fetch data in other caches, as well as to return data to the requesting processor. These additional messages are converted to appropriate hardware transactions by the destination system interface hardware. | 04-02-2009 |
20090106501 | Data cache management mechanism for packet forwarding - There is provided a method of managing a cache memory. The method comprising resetting a flag indicative of lack of incoming data for generating a packet for forwarding; receiving the incoming data; storing the incoming data in the main memory; transferring the incoming data from the main memory into a cache buffer within the cache memory, the cache buffer having a buffer size; setting the flag indicative of the incoming data received for generating the packet for forwarding; processing the incoming data to generate the packet in the cache buffer for forwarding, the packet having a packet size; writing back the packet from the cache buffer into the main memory; first invalidating a portion of the cache buffer; transmitting the packet after the first invalidating; and second invalidating, after the transmitting, the cache buffer for the buffer size if the flag is not set by the setting. | 04-23-2009 |
20090138663 | Cache memory capable of adjusting burst length of write-back data in write-back operation - A cache memory includes a write-back determination unit and a burst length determination unit. The write-back determination unit determines whether a block is a write-back block based on an n-bit dirty value of the block. The burst length determination unit determines a burst length of write-back data included in the write-back block based on the n-bit dirty value and an minimum burst length, when the block is the write-back block. | 05-28-2009 |
20090172296 | Cache Memory System and Cache Memory Control Method - A cache memory system including a processing unit and a cache memory which is connected to the processing unit, wherein when a store instruction of storing write data into a certain address is executed, the cache memory system executes selectively one of, a first operation mode of allocating an area of the address to the cache memory in response to a generation of a cache miss due to an access to the address, copying data of the address of the main memory unit to the cache memory and then rewriting the copied data on the cache memory using the write data, and a second operation mode in response to a generation of a cache miss due to the access to the address and storing the write data to the cache memory without copying data of the address of the main memory unit to the allocated area on the cache memory. | 07-02-2009 |
20090172297 | CACHE MEMORY SYSTEM AND CACHE MEMORY CONTROL METHOD - A cache memory system that is connected to a computation device and a memory device includes: a data array that includes a plurality of blocks composed of a plurality of words; a storage unit that, with respect to a block, which stores data in at least one of said words, from among the plurality of blocks, stores an address group of the memory device that is placed in correspondence with that block; a write unit that, when an address from the computation device is not in the storage unit on receiving a write instruction from the computation device, allocates any of the plurality of blocks as a block for writing, and writes the data from the computation device to any word in the block for writing; a word state storage unit that stores word information indicating one or more words, to which the data have been written by the write unit, from among words in the block for writing; and a read unit that, upon having read the data from words indicated by the word information when receiving a read instruction from the computation device, deletes the word information. | 07-02-2009 |
20090287885 | Administering Non-Cacheable Memory Load Instructions - Administering non-cacheable memory load instructions in a computing environment where cacheable data is produced and consumed in a coherent manner without harming performance of a producer, the environment including a hierarchy of computer memory that includes one or more caches backed by main memory, the caches controlled by a cache controller, at least one of the caches configured as a write-back cache. Embodiments of the present invention include receiving, by the cache controller, a non-cacheable memory load instruction for data stored at a memory address, the data treated by the producer as cacheable; determining by the cache controller from a cache directory whether the data is cached; if the data is cached, returning the data in the memory address from the write-back cache without affecting the write-back cache's state; and if the data is not cached, returning the data from main memory without affecting the write-back cache's state. | 11-19-2009 |
20100005245 | SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL WRITES AND NON-SNOOP ACCESSES - A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, when a conflict associated with a partial memory access, such as a partial write, is detected, a write-back phase is inserted at the conflict phase to write-back the partial data to a home agent. Examples messages to initiate a write-back phase at a conflict phase include: an Acknowledge Conflict Write-back message to acknowledge a conflict and provide a write-back marker at the beginning of the conflict phase, a write-back marker message before the conflict phase, a write-back marker message within the conflict phase, a write-back marker message after the conflict phase, and a postable message after the conflict phase. | 01-07-2010 |
20100030974 | SYSTEM AND METHOD FOR FETCHING INFORMATION TO A CACHE MODULE USING A WRITE BACK ALLOCATE ALGORITHM - A write back allocate system that includes: (i) a store request circuit; (ii) a processor, adapted to generate a store request that comprises an information unit and an information unit address; and (iii) a cache module, connected to the store request circuit and to a high level memory unit. A single cache module line includes multiple segments, each segment is adapted to store a single information unit. A content of a cache module line is retrieved from the high level memory unit by generating a fetch burst that includes multiple segment fetch operations. The store request circuit includes a snooper and a controller. The snooper detects a portion of an address of a cache segment of a cache line that is being fetched during a fetch burst. The controller is adapted to request from the cache module to receive the information unit before a completion of the fetch burst if the portion of the address of the cache segment matches a corresponding portion of the information unit address. | 02-04-2010 |
20100088473 | VECTOR COMPUTER SYSTEM WITH CACHE MEMORY AND OPERATION METHOD THEREOF - A vector computer system includes a vector processor configured to issue a vector store instruction which includes a plurality of store requests; a cache memory of a write back system provided between the vector processor and a main memory; and a write allocate determining section configured to generate an allocation control signal which specifies whether the cache memory operates based on a write allocate system or a non-write allocate system. When the vector processor issues the vector store instruction, the write allocate determining section generates the allocation control signal to each of the plurality of store requests based on a write pattern as a pattern of target addresses of the plurality of store requests. The cache memory executes each store request based on one of the write allocate system and the non-write allocate system which is specified based on the allocation control signal. | 04-08-2010 |
20100106914 | CONSISTENCY MODELS IN A DISTRIBUTED STORE - Systems and methods that designate read/write consistency models based on requirements of a distributed store to increase performance or scale. Such sever loads can be determined via a plurality of mechanisms, including delays in responses by the primary node; setting predetermined threshold limits that if exceeded results in contacting secondary nodes; polling services of the distributed cache periodically and maintaining track of loads on the servers, and the like. The weak or scalable read can occur when read requests are directed to a secondary node, and upon over loading of the primary node. | 04-29-2010 |
20100174870 | SYSTEM AND METHOD TO PRESERVE AND RECOVER UNWRITTEN DATA PRESENT IN DATA CACHE OF A DISK SUBSYSTEM ACROSS POWER OUTAGES - Disclosed are a system and method to preserve and recover unwritten data present in data cache of a disk subsystem across power outages. In one embodiment, a method of a controller is described. The method includes applying a write-back technique between a host server and a data store, accessing a dirty data in a cache memory during a power outage. The method may apply an algorithm for efficiently offloading the dirty data to a non-volatile storage device during the power outage. In addition the method may apply the algorithm to efficiently transfer the dirty data from the non-volatile storage device to the data store when power is restored. | 07-08-2010 |
20100174871 | INPUT/OUTPUT CONTROL SYSTEM, INPUT/OUTPUT CONTROL METHOD AND INPUT/OUTPUT CONTROL PROGRAM - An input/output control system of an information processing apparatus that includes a first storage area and a second storage area and carries out an input/output processing using a part or whole of the first storage area as a cache. The input/output control system includes: a cache managing unit | 07-08-2010 |
20100211746 | CACHE DEVICE - A cache device interposed between a processor and a memory device, including: a cache memory storing data from the memory device; a buffer holding output data output from the processor; a control circuit determining, on the basis of a request to access the memory device, whether a cache hit has occurred or not and, if a cache miss has occurred, storing the output data in the buffer in response to the access request, outputting a read request for reading the data in a line containing data requested by the access request from the memory device, storing data output from the line of the memory device into the cache memory, and storing the output data from the buffer into the cache memory. | 08-19-2010 |
20100325367 | Write-Back Coherency Data Cache for Resolving Read/Write Conflicts - A write-back coherency data cache for temporarily holding cache lines. Upon receiving a processor request for data, a determination is made from a coherency directory whether a copy of the data is cached in a write-back cache located in a memory controller hardware. The write-back cache holds data being written back to main memory for a period of time prior to writing the data to main memory. If the data is cached in the write-back cache, the data is removed from the write-back cache and forwarded to the requesting processor. The cache coherency state in the coherency directory entry for the data is updated to reflect the current cache coherency state of the data based on the requesting processor's intended use of the data. | 12-23-2010 |
20110047335 | MULTIPROCESSOR, CACHE SYNCHRONIZATION CONTROL METHOD AND PROGRAM THEREFOR - There is provided a cache synchronization control method by which contents of a plurality of caches can be synchronized without a programmer explicitly setting a synchronization point, and the contents of the caches can be synchronized without scanning all cache blocks. A cache synchronization control method for a multiprocessor that has a plurality of processors having a cache, and a storage device shared by the plurality of processors, the method comprises: before a task is executed, a first step of writing back input data of the task to the storage device by a processor that manages the task and deleting data corresponding to the input data from its own cache by a processor other than the processor; and after the task is executed, a second step of writing back output data of the task to the storage device by a processor that has executed the task and deleting data corresponding to the output data from its own cache by a processor other than the processor. | 02-24-2011 |
20110047336 | Converting Victim Writeback to a Fill - In one embodiment, a processor may be configured to write ECC granular stores into the data cache, while non-ECC granular stores may be merged with cache data in a memory request buffer. In one embodiment, a processor may be configured to detect that a victim block writeback hits one or more stores in a memory request buffer (or vice versa) and may convert the victim block writeback to a fill. In one embodiment, a processor may speculatively issue stores that are subsequent to a load from a load/store queue, but prevent the update for the stores in response to a snoop hit on the load. | 02-24-2011 |
20110078384 | MEMORY MIRRORING AND MIGRATION AT HOME AGENT - Methods and apparatus relating to memory mirroring and migration at a Home Agent (HA) are described. In one embodiment, a home agent may mirror its data at a slave agent. In some embodiments, a bit in a directory may indicate status of cache lines. Other embodiments are also disclosed. | 03-31-2011 |
20110093661 | MULTIPROCESSOR SYSTEM WITH MIXED SOFTWARE HARDWARE CONTROLLED CACHE MANAGEMENT - A multiprocessor system has a background memory and a plurality of processing elements ( | 04-21-2011 |
20110099336 | CACHE MEMORY CONTROL CIRCUIT AND CACHE MEMORY CONTROL METHOD - A cache memory control circuit has a plurality of counters, each of which is provided per set and per memory space and configured to count how many pieces of data of a corresponding memory space is stored in a corresponding set. The cache memory control circuit controls activation of a tag memory and a data memory of each of a plurality of sets according to a count value of each of the plurality of counters. | 04-28-2011 |
20110099337 | PROCESSING CIRCUIT WITH CACHE CIRCUIT AND DETECTION OF RUNS OF UPDATED ADDRESSES IN CACHE LINES - A circuit that comprises a processor core ( | 04-28-2011 |
20110213933 | INFORMATION PROCESSING APPARATUS AND MEMORY CONTROL APPARATUS - A memory control apparatus, in a case of receiving from a processor, under a condition where the number of cache memories retaining a copy of data stored in a main storage device is one, a notification to the effect that data retained in the cache memory is purged, updates directory information on a directory cache without accessing the main storage device when the data is not modified by the processor, and the directory information on the directory cache and directory information on the main storage device is determined to be different and the directory information on the main storage device is determined to be in a state indicating that the copy of the data is not retained by any processor in the state of coherence. | 09-01-2011 |
20110246723 | CACHE MANAGEMENT POLICY AND CORRESPONDING DEVICE - A cache management policy is provided, comprising a method for writing back to a memory ( | 10-06-2011 |
20120042133 | MULTI-CORE PROCESSOR SYSTEM AND MULTI-CORE PROCESSOR - According to one embodiment, a state manager classifies an area allocated to the multi-core processor in a first memory area into one of a first state in which allocation to processor cores is not performed, a second state in which allocation to one of the processor cores is performed and read and write are performed, and a third state in which allocation to one or more of the processor cores is performed and read and write are prohibited, and further performs a transition from one of the first state, the second state, and the third state to another. A cache/memory manager writes back a corresponding cache when the state manager performs the transition from the second state to the third state. | 02-16-2012 |
20120079210 | OPTIMIZED RING PROTOCOLS AND TECHNIQUES - Methods and apparatus relating to optimized ring protocols and techniques are described. In one embodiment, a first agent generates a request to write to a cache line of a cache over a first ring of a computing platform. A second agent that receives the write request forwards it to a third agent over the first ring of the computing platform. In turn, a third agent (e.g., a home agent) receives data corresponding to the write request over a second, different ring of the computing platform and writes the data to the cache. Other embodiments are also disclosed. | 03-29-2012 |
20120079211 | Coherency control with writeback ordering - Interconnect circuitry configured to provide routes for interconnecting several initiator devices and at least one recipient device including a memory. At least one of the initiator devices has a cache for storing a local copy of a subset of data items stored in the memory. The interconnect circuitry includes: a plurality of input ports and at least one output port; a plurality of paths for transmitting the transaction requests between the inputs and the at least one output; coherency control circuitry for maintaining an order in which at least some of the transaction requests to a same data storage location proceed through the interconnect circuitry. The interconnect circuitry is configured not to control the writeback transaction requests with the coherency control circuitry, such that the writeback transaction requests proceed independently of transaction requests routed through the coherency control circuitry. | 03-29-2012 |
20120102273 | MEMORY AGENT TO ACCESS MEMORY BLADE AS PART OF THE CACHE COHERENCY DOMAIN - A system and method is shown wherein a memory agent module to identify a memory command related to virtual memory pages associated with a memory blade and maintain and optimize cache coherency for such pages. The system and method also includes a memory module, operatively connected to the memory agent that includes a page cache used by the memory agent to manage the virtual memory page. Further, the system and method includes a transmission module to transmit the memory command to the memory blade, as well as data structures to facilitate the page migration between the compute blade's local memory and remote memory on the memory blade. | 04-26-2012 |
20120159085 | METHODS AND SYSTEM FOR VERIFYING MEMORY DEVICE INTEGRITY - A method for validating an eligibility for verification of a memory device within an embedded demand paged memory operating system environment is provided. The method includes receiving a request from an application being executed by a processor coupled to the memory device, the request to utilize at least one memory location. The method includes identifying, by the processor, at least one memory block corresponding to at least one memory location within the memory device, determining, by the processor, whether the at least one memory block is eligible for verification, and producing an eligibility result based on the determination by the processor. A system for validating an eligibility for verifying memory device integrity is also disclosed. | 06-21-2012 |
20120215987 | BROADCAST PROTOCOL FOR A NETWORK OF CACHES - A method for managing caches, including: broadcasting, by a first cache agent operatively connected to a first cache and using a first physical network, a first peer-to-peer (P2P) request for a memory address; issuing, by a second cache agent operatively connected to a second cache and using a second physical network, a first response to the first P2P request based on a type of the first P2P request and a state of a cacheline in the second cache corresponding to the memory address; issuing, by a third cache agent operatively connected to a third cache, a second response to the first P2P request; and upgrading, by the first cache agent and based on the first response and the second response, a state of a cacheline in the first cache corresponding to the memory address. | 08-23-2012 |
20120215988 | Administering Non-Cacheable Memory Load Instructions - Administering non-cacheable memory load instructions in a computing environment where cacheable data is produced and consumed in a coherent manner without harming performance of a producer, the environment including a hierarchy of computer memory that includes one or more caches backed by main memory, the caches controlled by a cache controller, at least one of the caches configured as a write-back cache. Embodiments of the present invention include receiving, by the cache controller, a non-cacheable memory load instruction for data stored at a memory address, the data treated by the producer as cacheable; determining by the cache controller from a cache directory whether the data is cached; if the data is cached, returning the data in the memory address from the write-back cache without affecting the write-back cache's state; and if the data is not cached, returning the data from main memory without affecting the write-back cache's state. | 08-23-2012 |
20120254551 | METHOD OF GENERATING CODE EXECUTABLE BY PROCESSOR - It is provided a method of generating a code by a compiler, including the steps of: analyzing a program executed by a processor; analyzing data necessary to execute respective tasks included in a program; determining whether a boundary of the data used by divided tasks is consistent with a management unit of a cache memory based on results of the analyzing; and generating a code for providing a non-cacheable area from which the data to be stored in the management unit including the boundary is not temporarily stored into the cache memory and a code for storing an arithmetic processing result stored in the management unit including the boundary into a non-cacheable area in a case where it is determined that the boundary of the data used by the divided tasks is not consistent with the management unit of the cache memory. | 10-04-2012 |
20120297147 | Caching Operations for a Non-Volatile Memory Array - A method includes receiving in conjunction with data to be written at a non-volatile memory device an indication from a host that is descriptive of a write-back requirement for the data; and storing the data in a cache memory of the non-volatile memory device and selectively, depending on the indication, controlling whether the data is or is not written back from the cache memory to a non-volatile memory array that comprises a part of the non-volatile memory device. | 11-22-2012 |
20120317367 | WRITING DATA TO SYSTEM MEMORY IN A DATA PROCESSING SYSTEM - A state indicator associated with a cache line is stored, wherein the cache line is one of a plurality of cache lines each associated with a corresponding unique section of a region of system memory. The state indicator comprises a dirty indication indicating that the cache line is a candidate for writing data stored in the cache line to the associated section of the region of system memory. The state indicator is one of a plurality of state indicators each associated with a corresponding cache line. For the region of system memory, a number of the plurality of state indicators that comprises the dirty indication is determined, and if a threshold is exceeded, data stored in a selected cache line is written to the associated section of the region of system memory, and a clean indication is stored in the state indicator corresponding to the cache line. | 12-13-2012 |
20120331236 | DATA PROCESSING APPARATUS AND IMAGE FORMING APPARATUS - A data processing apparatus includes an operation unit, a writable and readable volatile register, a writable and readable nonvolatile memory, first and second writing units and a write-back unit. The operation unit performs an arithmetic operation and a logical operation. The writable and readable volatile register stores data used in the operations performed by the operation unit. The writable and readable nonvolatile memory stores the data in parallel with the volatile register. The data stored in the nonvolatile memory is the data stored in the volatile register. The first writing unit writes the data in the volatile register. The second writing unit writes the data in the nonvolatile memory in parallel with the first writing unit every time the data is written in the volatile register. The write-back unit writes back the data stored in the nonvolatile memory to the volatile register when a power supply is turned on. | 12-27-2012 |
20130019066 | CACHE DEVICE - A cache device interposed between a processor and a memory device, including: a cache memory storing data from the memory device; a buffer holding output data output from the processor; a control circuit determining, on the basis of a request to access the memory device, whether a cache hit has occurred or not and, if a cache miss has occurred, storing the output data in the buffer in response to the access request, outputting a read request for reading the data in a line containing data requested by the access request from the memory device, storing data output from the line of the memory device into the cache memory, and storing the output data from the buffer into the cache memory. | 01-17-2013 |
20130080709 | System and Method for Performing Memory Operations In A Computing System - A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line are not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded. | 03-28-2013 |
20130086330 | Write-Back Storage Cache Based On Fast Persistent Memory - A storage device uses non-volatile memory devices for caching. The storage device operates in a mode referred to herein as write-back mode. In write-back mode, a storage device responds to a request to write data by persistently writing the data to a cache in a non-volatile memory device and acknowledges to the requestor that the data is written persistently in the storage device. The acknowledgement is sent without necessarily having written the data that was requested to be written to primary storage. Instead, the data is written to primary storage later. | 04-04-2013 |
20130091331 | METHODS, APPARATUS, AND ARTICLES OF MANUFACTURE TO MANAGE MEMORY - Methods, apparatus, and articles of manufacture to manage memory are disclosed. An example method includes mapping a cache memory to a random access memory, incrementing a counter in response to a data write to a cache line of the cache memory, decrementing the counter in response to a write-back of the data from the cache line, and committing the data to the RAM when the counter is equal to a threshold. | 04-11-2013 |
20130132682 | Push Mechanism for Quality of Service (QoS) Support in Coherency Port - In an embodiment, a memory port controller (MPC) is coupled to a memory port and receives transactions from processors and a coherency port (ACP) used by one or more peripheral devices that may be cache coherent. The transactions include various QoS parameters. If a high priority QoS transaction is received on the ACP, the MPC may push previous (lower priority) transactions until the high priority transaction may be completed. The MPC may maintain a count of outstanding high priority QoS transactions. The L2 interface controller and ACP controller may push increment and decrement events based on processing the high priority QoS transactions, and the MPC may push the memory transactions when the count is non-zero. In an embodiment, the MPC may continue pushing transactions until the L2 interface controller informs the MPC that the earlier transactions have been completed (e.g. by passing an upgrade token to the MPC). | 05-23-2013 |
20130159632 | MEMORY SHARING BY PROCESSORS - A method of memory sharing implemented by logic of a computer memory control unit, the control unit comprising at least one first interface and second interfaces and is adapted to be connected with a main physical memory via the first interface, and a set of N≧2 non-cooperative processors via the second interfaces, the logic operatively coupled to the first and second interfaces. The method includes receiving, via the second interfaces, a request to access data of the main physical memory from a first processor of the set; evaluating if a second processor has previously accessed the data requested by the first processor; and deferring the request from the first processor when the evaluation is positive, or, granting the request from the first processor when the evaluation is negative. | 06-20-2013 |
20130166848 | VIRTUAL COMPUTER SYSTEM, VIRTUAL COMPUTER CONTROL METHOD, VIRTUAL COMPUTER CONTROL PROGRAM, RECORDING MEDIUM, AND INTEGRATED CIRCUIT - A virtual machine system comprises: a processor for executing a secure operating system and a normal operating system; and a cache memory. The cache memory stores data in a manner that allows for identification of whether the data has been read from a secure storage area of an external main memory. The cache memory writes back data to the main memory in a manner that reduces the number of times data is intermittently written back to the secure storage area which occurs when the processor is executing the normal operating system. | 06-27-2013 |
20130254493 | CACHE MEMORY CAPABLE OF ADJUSTING BURST LENGTH OF WRITE-BACK DATA IN WRITE-BACK OPERATION - A cache memory includes a write-back determination unit and a burst length determination unit. The write-back determination unit determines whether a block is a write-back block based on an n-bit dirty value of the block. The burst length determination unit determines a burst length of write-back data included in the write-back block based on the n-bit dirty value and an minimum burst length, when the block is the write-back block. | 09-26-2013 |
20130262781 | OPTIMIZED RING PROTOCOLS AND TECHNIQUES - Methods and apparatus relating to optimized ring protocols and techniques are described. In one embodiment, a first agent generates a request to write to a cache line of a cache over a first ring of a computing platform. A second agent that receives the write request forwards it to a third agent over the first ring of the computing platform. In turn, a third agent (e.g., a home agent) receives data corresponding to the write request over a second, different ring of the computing platform and writes the data to the cache. Other embodiments are also disclosed. | 10-03-2013 |
20130326155 | SYSTEM AND METHOD OF OPTIMIZED USER COHERENCE FOR A CACHE BLOCK WITH SPARSE DIRTY LINES - A system and method of optimized user coherence for a cache block with sparse dirty lines is disclosed wherein valid and dirty bits of each set are logically AND'ed together and the result for multiple sets are logically OR'ed together resulting in an indication whether a particular block has any dirty lines. If the result indicates that a block does not have dirty lines, then that entire block can be skipped from being written back without affecting coherency. | 12-05-2013 |
20130339626 | PRIORITIZING REQUESTS TO MEMORY - According to an embodiment, a computer system for cache management includes a processor and a cache, the computer system configured to perform a method including receiving a first store request for a first address in the cache and receiving a first fetch request for the first address in the cache. The method also includes executing the first store request and the first fetch request, latching the first store request in a store write-back pipeline in the cache, detecting, in the processor, a conflict following execution of the first store request and the first fetch request and receiving the first store request from a recycle path including the store write-back pipeline and executing the first store request a second time. | 12-19-2013 |
20140032856 | SYSTEMS AND METHODS FOR MAINTAINING THE COHERENCY OF A STORE COALESCING CACHE AND A LOAD CACHE - A method for maintaining the coherency of a store coalescing cache and a load cache is disclosed. As a part of the method, responsive to a write-back of an entry from a level one store coalescing cache to a level two cache, the entry is written into the level two cache and into the level one load cache. The writing of the entry into the level two cache and into the level one load cache is executed at the speed of access of the level two cache. | 01-30-2014 |
20140052931 | Data Type Dependent Memory Scrubbing - A method for controlling a memory scrubbing rate based on content of the status bit of a tag array of a cache memory. More specifically, the tag array of a cache memory is scrubbed at smaller interval than the scrubbing rate of the storage arrays of the cache. This increased scrubbing rate is in appreciation for the importance of maintaining integrity of tag data. Based on the content of the status bit of the tag array which indicates modified, the corresponding data entry in the cache storage array is scrubbed accordingly. If the modified bit is set, then the entry in the storage array is scrubbed after processing the tag entry. If the modified bit is not set, then the storage array is scrubbed at a predetermined scrubbing interval. | 02-20-2014 |
20140068199 | PROCESSOR AND INFORMATION PROCESSING APPARATUS - A processor includes a first transmitting unit that transmits, when receiving from a second processor a transmission request indicating transmission of target data which is read from a main storage unit and stored in the first processor, a transfer instruction to the first processor, the transfer instruction indicating transfer of the target data and state information to the second processor, the state information indicating a state of the target data used when the second processor reads and stores the target data. The processor includes a second transmitting unit that transmits acquisition information indicating acquisition of the target data to the second processor before receiving a response to the transfer instruction transmitted by the first transmitting unit from the first processor. | 03-06-2014 |
20140095803 | MEMORY SYSTEM CONFIGURED TO PERFORM SEGMENT CLEANING AND RELATED METHOD OF OPERATION - A host configured to interact with a storage device comprises a write-back (WB) cache configured to write data to the storage device, a cache managing module configured to manage the WB cache, and a file system module configured to determine whether live blocks in victim segments among a plurality of segments stored in the storage device are stored in the WB cache, to read the live blocks from the storage device as a consequence of determining that the live blocks are not stored in the WB cache, to load the read live blocks to the WB cache, and to request the cache managing module to set dirty flags for the stored live blocks. | 04-03-2014 |
20140143504 | HYPERVISOR I/O STAGING ON EXTERNAL CACHE DEVICES - A management technique for input/output operations (JO) leverages a hypervisor's position as an intermediary between virtual machines (VMs) and storage devices servicing the VMs to facilitate improvements in overall I/O performance for the VMs. According to this new I/O management technique, the hypervisor sends write requests from VMs destined for storage devices to an I/O staging device that provides higher I/O performance than the storage devices, for caching in the I/O staging device in a write-back mode. Once the I/O staging device has received and acknowledged the write request, the hypervisor immediately provides an acknowledgement to the requesting VM. Later on and asynchronously with respect to the write requests from the VMs, the hypervisor reads the write data from the I/O staging device and sends it over to the storage devices for storage therein. | 05-22-2014 |
20140143505 | Dynamically Configuring Regions of a Main Memory in a Write-Back Mode or a Write-Through Mode - The described embodiments include a main memory and a cache memory (or “cache”) with a cache controller that includes a mode-setting mechanism. In some embodiments, the mode-setting mechanism is configured to dynamically determine an access pattern for the main memory. Based on the determined access pattern, the mode-setting mechanism configures at least one region of the main memory in a write-back mode and configures other regions of the main memory in a write-through mode. In these embodiments, when performing a write operation in the cache memory, the cache controller determines whether a region in the main memory where the cache block is from is configured in the write-back mode or the write-through mode and then performs a corresponding write operation in the cache memory | 05-22-2014 |
20140143506 | LOCALLY CACHING DATA FROM A SHARED STORAGE - Systems, methods, and other embodiments associated with controlling when data blocks are cached at hosts from a shared storage are described. According to one embodiment, an apparatus includes a request logic configured to receive, from a first host of a plurality of hosts, a request to cache a data block at the first host. The data block is part of a plurality of data blocks that are stored in a network storage. The network storage is shared by the plurality of hosts. The apparatus also includes a lock logic configured to control access to the data block by issuing a lock for the data block identified by the request in response to determining that the data block is available. The lock provides exclusive access to the data block for the first host to permit the first host to cache the data block locally at the first host. | 05-22-2014 |
20140156948 | APPARATUSES AND METHODS FOR PRE-FETCHING AND WRITE-BACK FOR A SEGMENTED CACHE MEMORY - Apparatuses and methods for a cache memory are described. In an example method, a transaction history associated with a cache block is referenced, and requested information is read from memory. Additional information is read from memory based on the transaction history, wherein the requested information and the additional information are read together from memory. The requested information is cached in a segment of a cache line of the cache block and the additional information in cached another segment of the cache line. In another example, the transaction history is also updated to reflect the caching of the requested information and the additional information. In another example, read masks associated with the cache tag are referenced for the transaction history, the read masks identifying segments of a cache line previously accessed. | 06-05-2014 |
20140164715 | METHODS AND STRUCTURE FOR USING REGION LOCKS TO DIVERT I/O REQUESTS IN A STORAGE CONTROLLER HAVING MULTIPLE PROCESSING STACKS - Methods and structure within a storage controller for using region locks to efficiently divert an I/O request received from an attached host system to one of multiple processing stacks in the controller. A region lock module within the controller allows each processing stack to request a region lock for a range of block addresses of the storage devices. A divert-type lock request may be established to identify a range of block addresses for which I/O requests should be diverted to a particular one of the multiple processing stacks. | 06-12-2014 |
20140173221 | CACHE MANAGEMENT - The present disclosure provides techniques for cache management. A data block may be received from an IO interface. After receiving the data block, the occupancy level of a cache memory may be determined. The data block may be directed to a main memory if the occupancy level exceeds a threshold. The data block may be directed to a cache memory if the occupancy level is below a threshold. | 06-19-2014 |
20140201463 | HIGH PERFORMANCE INTERCONNECT COHERENCE PROTOCOL - A request is received that is to reference a first agent and to request a particular line of memory to be cached in an exclusive state. A snoop request is sent intended for one or more other agents. A snoop response is received that is to reference a second agent, the snoop response to include a writeback to memory of a modified cache line that is to correspond to the particular line of memory. A complete is sent to be addressed to the first agent, wherein the complete is to include data of the particular line of memory based on the writeback. | 07-17-2014 |
20140201464 | EPOCH-BASED RECOVERY FOR COHERENT ATTACHED PROCESSOR PROXY - A coherent attached processor proxy (CAPP) participates in coherence communication in a primary coherent system on behalf of an attached processor external to the primary coherent system. The CAPP includes an epoch timer that advances at regular intervals to define epochs of operation of the CAPP. Each of one or more entries in a data structure in the CAPP are associated with a respective epoch. Recovery operations for the CAPP are initiated based on a comparison of an epoch indicated by the epoch timer and the epoch associated with one of the one or more entries in the data structure. | 07-17-2014 |
20140201465 | ACCELERATED RECOVERY FOR SNOOPED ADDRESSES IN A COHERENT ATTACHED PROCESSOR PROXY - A coherent attached processor proxy (CAPP) that participates in coherence communication in a primary coherent system on behalf of an external attached processor maintains, in each of a plurality of entries of a CAPP directory, information regarding a respective associated cache line of data from the primary coherent system cached by the attached processor. In response to initiation of recovery operations, the CAPP transmits, in a generally sequential order with respect to the CAPP directory, multiple memory access requests indicating an error for addresses indicated by the plurality of entries. In response to a snooped memory access request that targets a particular address hitting in the CAPP directory during the transmitting, the CAPP performs a coherence recovery operation for the particular address prior to a time indicated by the generally sequential order. | 07-17-2014 |
20140215163 | PROCESSING READ AND WRITE REQUESTS IN A STORAGE CONTROLLER - Provided are a method, system, and computer program product for processing read and write requests in a storage controller. A host adaptor in the storage controller receives a write request from a host system for a storage address in a storage device. The host adaptor sends write information indicating the storage address updated by the write request to a device adaptor in the storage controller. The host adaptor writes the write data to a cache in the storage controller. The device adaptor indicates the storage address indicated in the write information to a modified storage address list stored in the device adaptor, wherein the modified storage address list indicates modified data in the cache for storage addresses in the storage device. | 07-31-2014 |
20140281270 | MECHANISM TO IMPROVE INPUT/OUTPUT WRITE BANDWIDTH IN SCALABLE SYSTEMS UTILIZING DIRECTORY BASED COHERECY - Methods and apparatus relating to directory based coherency to improve input/output write bandwidth in scalable systems are described. In one embodiment, a first agent receives a request to write data from a second agent via a link and logic causes the first agent to write the directory state to an Input/Output Directory Cache (IODC) of the first agent. Additionally, the logic causes the second agent to send data from a modified state to an exclusive state using write back to the first agent, while allowing the data to remain cached exclusively in the second agent and also enabling the deallocation of the IODC entry in the first agent. Other embodiments are also disclosed. | 09-18-2014 |
20140281271 | CACHE CONTROL DEVICE, PROCESSOR, INFORMATION PROCESSING SYSTEM, AND CACHE CONTROL METHOD - A cache control device includes: a tag storage section configured to manage, for each cache line of a cache memory, whether or not the cache line is valid, and whether or not a write-back instruction to a shared storage section is provided; and a tag control section configured not to invalidate a cache line for which the write-back instruction is already provided, and to invalidate a cache line for which the write-back instruction is not provided, when a predetermined instruction is provided. | 09-18-2014 |
20140289480 | PROCESSOR, INFORMATION PROCESSING APPARATUS, AND CONTROL METHOD OF PROCESSOR - A processor includes: a primary cache memory; an instruction control unit that issues a store request to the primary cache memory; a pipeline processing unit that, upon receiving the store request, writes data to the primary cache memory; a buffer unit that obtains an address output to the primary cache memory from the pipeline processing unit during an output period of the store request regarding certain data to hold the obtained address in an entry, and when the output period ends, issues a write-back request for writing the data indicated by the address held in the entry to a memory; and a secondary cache memory that, upon receiving the write-back request from the buffer unit, writes the data of the primary cache memory to the memory, the certain data is quickly written back to the memory from the primary cache memory. | 09-25-2014 |
20140289481 | OPERATION PROCESSING APPARATUS, INFORMATION PROCESSING APPARATUS AND METHOD OF CONTROLLING INFORMATION PROCESSING APPARATUS - An operation processing apparatus includes an operation processing unit configured to perform an operation process using first data administered by the own operation processing apparatus and second data administered by and acquired from another operation processing apparatus, a main memory configured to store the first data and third data, and a control unit configured to include a setting unit which sets the operation processing unit to an operating state or a non-operating state and a cache memory which holds the first, second and third data, wherein when the setting unit sets the operation processing unit to the non-operating state and the third data is requested from another operation processing apparatus, which triggers cache miss in the cache memory, the control unit reads the requested data from the main memory and holds the requested data in the cache memory and sends the read data to another operation processing apparatus. | 09-25-2014 |
20140337584 | CONTROL APPARATUS, ANALYSIS APPARATUS, ANALYSIS METHOD, AND COMPUTER PRODUCT - A cache controller receives a reference request from a CPU executing a program in which information indicative of a reference request specifying in shared memory, an area not having an update request and information indicative of a snoop reference request are distinguished from one another. When the reference request specifying an area not having the update request is received, the cache controller acquires from the shared memory and without performing a snoop process, information stored in the specified area. The cache controller stores the information acquired from the shared memory to the cache memory of the CPU executing the program. | 11-13-2014 |
20140359229 | Lightweight Remote Replication of a Local Write-Back Cache - Techniques for replicating a write-back cache are provided. In one embodiment, a first computer system can receive a write request from a virtual machine (VM) that includes data to be written to a shared storage device. The first computer system can further save the data in a local cache device and transmit, via a network interface controller (NIC), a data packet including the data to a second computer system. Upon determining that the data packet has been transmitted via the NIC, the first computer system can communicate an acknowledgment to the VM indicating that the write request has been successfully processed. | 12-04-2014 |
20140372710 | SYSTEM AND METHOD FOR RECOVERING FROM AN UNEXPECTED SHUTDOWN IN A WRITE-BACK CACHING ENVIRONMENT - An invention is provided for recovering from an unexpected shutdown in a write-back caching environment. The invention includes storing a logical block address (LBA) mapping table on a caching device. The LBA mapping table maps logical block addresses of a target storage device to logical block addresses of the caching device. In addition, a LBA mapping table change log is maintained on the caching device. The LBA mapping table change log includes changes to the LBA mapping table since the LBA mapping table was last written to the caching device. During startup after an unexpected shutdown, the unexpected shutdown is detected using a header stored on a caching device. Among other data, the header includes an indicia indicating whether or not a clean shutdown occurred. When the unexpected shutdown is detected, a recovered LBA mapping table is generated based on the LBA mapping table, which is stored on the caching device, and the LBA mapping table change log. | 12-18-2014 |
20150032972 | METHODS AND APPARATUS FOR SUPPORTING PERSISTENT MEMORY - A processing device features a processing unit, a memory management system, and persistent memory in a persistent memory domain. The processing device provides an enhanced write-back (WB-E) memory space for an application running on the processing unit. The memory management system maps the WB-E memory space to the persistent memory. The application creates WB-E data by executing an instruction to store data to an address in the WB-E memory space. The WB-E data is automatically stored in a cache associated with the processing unit in response to creation of the WB-E data by the application. In response to execution of a commit instruction by the application after the application has created WB-E data for multiple memory addresses, the memory management system automatically ensures that all of the WB-E data for the application has been saved to the persistent memory domain. Other embodiments are described and claimed. | 01-29-2015 |
20150067271 | SELECTIVELY ENABLING WRITE CACHING IN A STORAGE SYSTEM BASED ON PERFORMANCE METRICS - According to a method of cache management in a data storage system including a write cache and bulk storage media, a storage controller of the data storage system caches, in the write cache, write data of write input/output operations (IOPs) received at the storage controller. In response to a first performance-related metric for the data storage system satisfying a first threshold, the storage controller decreases a percentage of write IOPs for which write data is cached in the write cache of the data storage system and increases a percentage of write IOPs for which write data is stored directly in the bulk storage media in lieu of the write cache. In response to a second performance-related metric for the data storage system satisfying a second threshold, the storage controller increases the percentage of write IOPs for which write data is cached in the write cache of the data storage system. | 03-05-2015 |
20150081984 | HIGH PERFORMANCE INTERCONNECT COHERENCE PROTOCOL - A request is received that is to reference a first agent and to request a particular line of memory to be cached in an exclusive state. A snoop request is sent intended for one or more other agents. A snoop response is received that is to reference a second agent, the snoop response to include a writeback to memory of a modified cache line that is to correspond to the particular line of memory. A complete is sent to be addressed to the first agent, wherein the complete is to include data of the particular line of memory based on the writeback. | 03-19-2015 |
20150113228 | PROCESSOR, CACHE MEMORY OF THE PROCESSOR AND CONTROL METHOD OF THE PROCESSOR - A processor capable of storing trace data is disclosed. The processor includes a core adapted to execute programs, as well as a cache memory electrically connected to the core. The cache memory includes a core way and a trace way. The core way is adapted to store data that is required when the core executes the programs. The trace way is adapted to store data that is generated during debugging operations of the core. A control method of the processor is also disclosed. | 04-23-2015 |
20150143059 | DYNAMIC WRITE PRIORITY BASED ON VIRTUAL WRITE QUEUE HIGH WATER MARK - A set associative cache is managed by a memory controller which places writeback instructions for modified (dirty) cache lines into a virtual write queue, determines when the number of the sets containing a modified cache line is greater than a high water mark, and elevates a priority of the writeback instructions over read operations. The controller can return the priority to normal when the number of modified sets is less than a low water mark. In an embodiment wherein the system memory device includes rank groups, the congruence classes can be mapped based on the rank groups. The number of writes pending in a rank group exceeding a different threshold can additionally be a requirement to trigger elevation of writeback priority. A dirty vector can be used to provide an indication that corresponding sets contain a modified cache line, particularly in least-recently used segments of the corresponding sets. | 05-21-2015 |
20150301942 | WRITE-BACK CACHING-BASED ATOMICITY IN A DISTRIBUTED STORAGE SYSTEM - A method includes receiving an atomic operation for execution, wherein the execution of the atomic operation is to access a data container stored in more than one data store device of a plurality of data store devices in a distributed storage system. The method includes executing, in response to receiving the atomic operation, a write-back cache operation for the data container to preclude access of the data container by a different operation prior to completion of the atomic operation. The method also includes executing the atomic operation, wherein executing the atomic operation comprises accessing the data container stored in the more than one data store device of the distributed storage system. | 10-22-2015 |
20150301944 | STORAGE UNIT CONTROLLER AND CONTROL METHOD THEREOF, AND STORAGE DEVICE - A storage unit controller and a control method thereof, and a storage device are provided. The storage unit controller includes an address mapping unit, a nonvolatile buffer and an update indicator. The update indicator sets an indicated flag according to whether a first data saved in the nonvolatile buffer is written to a storage unit. The address mapping unit checks the indicated flag when power is on. When the checked indicated flag indicates that writing the first data is not completed, the address mapping unit enables an update operation mode so as to perform background operations: the first data has not yet been successfully addressed to the storage unit previously, but saved in a simulated address of the nonvolatile buffer to transfer the first data from the simulated address to an actual address of the storage unit. | 10-22-2015 |
20160085674 | METHODS AND SYSTEMS FOR DYNAMICALLY CONTROLLED CACHING - Systems and methods for improving caching mechanisms in a storage system are disclosed. The method includes storing data associated with a write input/output (I/O) request at a cache; determining an amount of dirty data stored in the cache, where the dirty data is data in the cache that has not yet been written to a persistent storage location managed by a storage system; determining if the amount of dirty data exceeds a threshold value; determining a cache flush rate based on the amount of dirty data stored at the cache, when the amount of dirty data exceeds the threshold value; and writing data from the cache at the determined cache flush rate to the persistent storage location. | 03-24-2016 |
20160085677 | SYSTEM AND METHOD FOR REPURPOSING DEAD CACHE BLOCKS - A processing system having a multilevel cache hierarchy employs techniques for repurposing dead cache blocks so as to use otherwise wasted space in a cache hierarchy employing a write-back scheme. For a cache line containing invalid data with a valid tag, the valid tag is maintained for cache coherence purposes or otherwise, resulting in a valid tag for a dead cache block. A cache controller repurposes the dead cache block by storing any of a variety of new data at the dead cache block, while storing the new tag in a tag entry of a dead block tag way with an identifier indicating the location of the new data. | 03-24-2016 |
20160098347 | TEMPORAL CLONES TO IDENTIFY VALID ITEMS FROM A SET OF ITEMS - Techniques are provided for using bitmaps to indicate which items, in a set of items, are invalid. The bitmaps include an “active” bitmap and one or more “temporal clones”. The active bitmap indicates which items in the set are currently valid. The temporal clones are outdated versions of the active bitmap that indicate which items in the set were invalid at previously points in time. Temporal clones may not be very different from each other. Therefore, temporal clones may be efficiently compressed. For example, a bitmap may be selected as a “base bitmap”, and one or more other bitmaps are encoded using delta encoding. Run length encoding may then be applied to further compress the bitmap information. These bitmaps may then be used to determine which items are valid relative to past-version requests. | 04-07-2016 |
20160147660 | ACCESS EXTENT MONITORING FOR DATA TRANSFER REDUCTION - A data processor system includes a local memory, a processor core, and an extent monitor. The local memory stores a block of data at a task memory location that is exclusive to a particular task during a duration of time. The processor core accesses the task memory location of the local memory during the execution of the particular task, and modifies to the block of data stored in the task memory location. The extent monitor monitors a write operation the processor core to the local memory to determine a first most-extreme address of the task memory location modified by the execution of the particular task during the duration of time. The processor core also executes a write back instruction to write back to a shared memory location less than the entire block of data based upon the most-extreme address. | 05-26-2016 |
20160162407 | MULTICORE, MULTIBANK, FULLY CONCURRENT COHERENCE CONTROLLER - This invention optimizes non-shared accesses and avoids dependencies across coherent endpoints to ensure bandwidth across the system even when sharing. The coherence controller is distributed across all coherent endpoints. The coherence controller for each memory endpoint keeps a state around for each coherent access to ensure the proper ordering of events. The coherence controller of this invention uses First-In-First-Out allocation to ensure full utilization of the resources before stalling and simplicity of implementation. The coherence controller provides Snoop Command/Response ID Allocation per memory endpoint. | 06-09-2016 |
20160170877 | SYSTEM AND METHOD FOR MANAGING BANDWIDTH AND POWER CONSUMPTION THROUGH DATA FILTERING | 06-16-2016 |
20160170881 | VIRTUAL MACHINE BACKUP | 06-16-2016 |
20160179676 | CLEANING A WRITE-BACK CACHE | 06-23-2016 |
20160378653 | LOG-STRUCTURED B-TREE FOR HANDLING RANDOM WRITES - A sorted key-value store is implemented using a write-back cache maintained in memory, a B-tree data structured maintained in disk, and a logical and physical log for providing transactions. The logical log and write-back cache are used to answer client requests, while dirty blocks in the write-back cache are periodically flushed to disk using the physical log. | 12-29-2016 |
20160378656 | STORAGE DEVICE, CACHE-WRITE CONTROL METHOD, AND CACHE-WRITE CONTROL PROGRAM - When write data is written in part of a write unit area of a secondary cache, a condition determining unit determines whether the write unit area in the write destination extends across the management unit areas of the secondary cache and, if the write unit area in the write destination extends across the management unit areas, determines whether the already stored data in an unupdated area is to be retained based on the use condition of the management unit area that includes the unupdated area, in which the write data is not written, in the write unit area as the write destination. If the condition determining unit determines that the already stored data is to be retained, a secondary-cache reading/writing control unit writes the write data in the management unit area as the write destination while the already stored data is retained. | 12-29-2016 |