Class / Patent application number | Description | Number of patent applications / Date published |
710263000 | Interrupt queuing | 51 |
20080256280 | Splitting One Hardware Interrupt To Multiple Handlers - A method and apparatus are provided for reducing latency associated with processing events of a hardware interrupt. Send and receive events share the same hardware interrupt. A receive handler and a separate send handler are provided to simultaneously process completion of a send event and a receive event. In addition, separate queues are provided to communicate receipt of an event to the respective interrupt handler. | 10-16-2008 |
20080276027 | INTERRUPT CONTROL APPARATUS, BUS BRIDGE, BUS SWITCH, IMAGE PROCESSING APPARATUS, AND INTERRUPT CONTROL METHOD - An interrupt control apparatus that controls an interrupt process request caused by a predetermined interrupt factor is disclosed. The interrupt control apparatus includes: an obtaining unit configured to obtain an interrupt process request signal including an interrupt factor identifier associated with at least equal to or more than two interrupt factors; an interrupt process unit configured to execute an interrupt process requested by the interrupt process request signal; and a control unit configured to control the interrupt process unit so as not to execute interrupt processes caused by interrupt factors associated with the interrupt factor identifier until the interrupt process executed by the interrupt process unit ends. | 11-06-2008 |
20080320194 | MONITORED NOTIFICATION FACILITY FOR REDUCING INTER-PROCESS / INTER-PARTITION INTERRUPTS - Example operations related to deferring interrupts are herein disclosed. In one example embodiment, a method includes, but is not limited to, writing a message to a memory location shared between a sender and a receiver; and requesting that an interrupt be transmitted to the receiver after a specified latency has elapsed, wherein an interrupt that is pending is stored in a trigger memory. It can be appreciated by one of skill in the art that one or more various aspects of the disclosure may include but are not limited to circuitry and/or programming for effecting the herein-referenced aspects; the circuitry and/or programming can be virtually any combination of hardware, software, and/or firmware configured to effect the herein-referenced aspects depending upon the design choices of the system designer. In addition to the foregoing, other aspects are described in the claims, drawings, and text forming a part of the present application. | 12-25-2008 |
20090172230 | DISTRIBUTED REAL-TIME OPERATING SYSTEM - A distributed control system and methods of operating such a control system are disclosed. In one embodiment, the distributed control system is operated in a manner in which interrupts are at least temporarily inhibited from being processed to avoid excessive delays in the processing of non-interrupt tasks. In another embodiment, the distributed control system is operated in a manner in which tasks are queued based upon relative timing constraints that they have been assigned. In a further embodiment, application programs that are executed on the distributed control system are operated in accordance with high-level and/or low-level requirements allocated to resources of the distributed control system. | 07-02-2009 |
20100030939 | REQUEST CONTROLLER, PROCESSING UNIT, ARRANGEMENT, METHOD FOR CONTROLLING REQUESTS AND COMPUTER PROGRAM PRODUCT - An request controller for controlling requests of a processing unit. The request controller may include an request controller input for receiving an request and an request processing unit connected to the request controller input. The request may request to switch a context of said processing unit or to switch the processing unit from a current an operation to another operation. The request processing unit may decide on the request based on a decision criterion. An request controller output may be connected to the request processing unit, for outputting information about at least granted request request. The request processing unit may include a control logic unit including: a state input for receiving information about a current state of a system including the processing unit; and a request input for receiving information about a received request request. The control logic unit may be arranged to determine whether the received request belongs to the current state of the processor, to grant the request when the received request does belong to the current state and to reject the request in case the request does not belong to the current state. The control logic unit may further include a control logic output for outputting an request grant signal when the request is granted. | 02-04-2010 |
20100100656 | INTERRUPTION FACILITY FOR ADJUNCT PROCESSOR QUEUES - Interruption facility for adjunct processor queues. In response to a queue transitioning from a no replies pending state to a reply pending state, an interruption is initiated. This interruption signals to a processor that a reply to a request is waiting on the queue. In order for the queue to take advantage of the interruption capability, it is enabled for interruptions. | 04-22-2010 |
20100106877 | APPARATUS AND METHOD TO CONTROL ACCESS TO STORED INFORMATION - A method is disclosed to control access to stored information. The method supplies a control unit in communication with a computing device and in communication with stored information. If the computing device requests access to that stored information, the method determines if access to the stored information is available. When access to the stored information becomes available, then the method reserves a communication pathway interconnecting the control unit and the requesting computing device, thereby disallowing the sending of non-MPLF unsolicited status via that reserved communication pathway, and provides a message to the computing device, using that reserved communication pathway, granting access to the stored information. | 04-29-2010 |
20100169528 | Interrupt technicques - Techniques are described that can be used by a message engine to notify a core or hardware thread of activity. For example, an inter-processor interrupt can be used to notify the core or hardware thread. The message engine may generate notifications in response to one or more message received from a transmitting message engine. Message engines may communicate without sharing memory space. | 07-01-2010 |
20100217905 | Synchronization Optimized Queuing System - A synchronization optimized queuing method and device to minimize software/hardware interaction in network interface hardware during an end-of-initiative process, including network adapter queue implementations for network interface hardware for optimized communication in a computer system. An end-of-initiative procedure to ensure that the network interface hardware has received an interrupt enable and to recheck the interrupt queue is unnecessary in the present invention. | 08-26-2010 |
20100262740 | MULTIPLE COMMAND QUEUES HAVING SEPARATE INTERRUPTS - A host device may include a driver that is arranged and configured to communicate commands to a data storage device and multiple pairs of queues, where each of the pairs of queues may include a command queue that is populated with commands for retrieval by the data storage device and a response queue that is populated with responses by the data storage device for retrieval by the host device, where each response queue is associated with an interrupt and an interrupt handler. | 10-14-2010 |
20100262741 | COMPUTER SYSTEM, INTERRUPT RELAY CIRCUIT AND INTERRUPT RELAY METHOD - A method for making it possible for a virtualization software (VMM) to generally identify a PCI function of an interrupt requester presupposing the existing I/O devices based on the PCI express is provided. An interrupt relay circuit is provided between an I/O device based on the PCI express and a PCI express bridge. The interrupt relay circuit receives and relays an interrupt transaction issued by the I/O device, and records whether there is an interrupt request in an interrupt indicator in association with an interrupt identifier. A VMM | 10-14-2010 |
20100274938 | PERIPHERAL ADAPTER INTERRUPT FREQUENCY CONTROL BY ESTIMATING PROCESSOR LOAD AT THE PERIPHERAL ADAPTER - Interrupt frequency control by estimating processor load in the peripheral adapter provides adaptive interrupt latency to improve performance in a processing system. A mathematical function of the depth of one or more queues of the adapter is compared to its historical value in order to provide an estimate of processor load. The estimated processor load is then used to set a parameter that controls the frequency of an interrupt generator, which may be controlled by setting an interrupt queue depth threshold, packet frequency threshold or interrupt hold-off time value. The mathematical function may be the ratio of the transmit queue depth to the receive queue depth and the historical value may be predetermined, user-settable, obtained during a calibration interval or obtained by taking a long-term average of the mathematical function of the queue depths. | 10-28-2010 |
20110082959 | TIMEOUT PREVENTING DEVICE, A TIMEOUT PREVENTING METHOD AND A PROGRAM THEREOF - Preventing time out of an IO transaction during CPU re-initialization by controlling the IO transaction so that the time when the IO transaction is continuously stopped during the CPU re-initialization process is within a predetermined time that prevents complete time out of an interrupt of an IO transaction. In a case where the IO transaction would be continuously stopped for greater than the predetermined time during a CPU re-initialization the IO transaction is stopped and restarted within the predetermined time. The status of the interrupt during such stopping and starting is stored so as not to loose the interrupt status during the interval between such stopping and starting. | 04-07-2011 |
20110093637 | Interrupt Moderation - A technique for interrupt moderation allows coalescing interrupts from a device into groups to be processed as a batch by a host processor. Receive and send completions may be processed differently. When the host is interrupted for receive completions, it may check for send completions, reducing the need for interrupts related to send completions. Timers and a counter allow coalescing interrupts into a single interrupt that can be used to signal the host to process multiple completions. The technique is suitable for both dedicated interrupt line and message-signaled interrupts. | 04-21-2011 |
20110131357 | Interrupt Queuing in a Media Controller Architecture - Described embodiments provide a media controller for servicing contexts corresponding to data transfer requests from host devices. The media controller includes a context generator for generating contexts corresponding to the data transfer requests and a buffer for storing one or more context pointers, each pointer corresponding to a context and an action by a system module associated with the context. A context processor is configured to complete a context when the action by a media controller module associated with the context is complete, remove each pointer from the buffer associated with the completed context, and determine whether an interrupt corresponds to the completed context and removed pointer. If no interrupt corresponds to the completed context, the completed context is cleared. If an interrupt corresponds to the completed context, the interrupt is provided to a master processor and a completed context recycler for recycling the completed context pointer to the context generator. | 06-02-2011 |
20110289249 | INTERRUPTION FACILITY FOR ADJUNCT PROCESSOR QUEUES - Interruption facility for adjunct processor queues. In response to a queue transitioning from a no replies pending state to a reply pending state, an interruption is initiated. This interruption signals to a processor that a reply to a request is waiting on the queue. In order for the queue to take advantage of the interruption capability, it is enabled for interruptions. | 11-24-2011 |
20110320662 | IDENTIFICATION OF TYPES OF SOURCES OF ADAPTER INTERRUPTIONS - A source identification facility is provided that enables identification of the one or more types of adapters requesting an interrupt in order to facilitate processing of the interrupt. The adapter types are accessible to the operating system and are used to tailor processing by the operating system of the interrupt. | 12-29-2011 |
20120096206 | INTER-VIRTUAL MACHINE INTERRUPT COALESCING - Disclosed is a system with multiple virtual machines passing I/O requests via a shared memory space. A flag in shared memory is set to a first state in response to a first hypervisor I/O interrupt to indicate that an I/O processing routine is active (running). I/O requests are retrieved from an I/O queue in the shared memory by the I/O processing routine. Based on an indicator that there are no I/O requests remaining in said I/O queue, the shared flag is set to a second state to indicate that the I/O processing routine is deactivated (sleeping). In response to said shared flag being in the second state, when new I/O requests are going to be made, a second hypervisor I/O interrupt is generated. In response to said shared flag being in said first state, I/O requests are inserted into the I/O queue without generating a second hypervisor I/O interrupt. | 04-19-2012 |
20120151111 | APPARATUS AND METHOD OF PROCESSING INTERRUPT FOR IMPROVING USER INPUT PROCESSING PERFORMANCE IN MOBILE DEVICE VIRTUALIZATION ENVIRONMENT - Provided is an apparatus of processing an interrupt, the apparatus including: an interrupt queue storing the input device interrupt when a target virtual machine to process an input device interrupt generated by a user input device is not scheduled; and an interrupt inspector judging whether a processing time of the input device interrupt stored in the interrupt queue reaches a threshold and when the processing time of the input device interrupt reaches the threshold, granting a priority higher than an initial value to the virtual machine to process the corresponding interrupt. | 06-14-2012 |
20120179851 | Computer System Interrupt Handling - A system, method and article of manufacture for an accelerated processing device (APD) to request a central processing unit (CPU) to process a task, comprising enqueuing a plurality of tasks on a queue using the APD, generating a user-level interrupt and transmitting to the CPU the plurality of tasks in the queue using an interrupt handler associated with a CPU thread. | 07-12-2012 |
20120198112 | Adapting Legacy/Third Party IPs to Advanced Power Management Protocol - An apparatus adapts a pre-designed circuit module not supporting a power management protocol to a power management protocol. The apparatus disconnects a bus interface, disables interrupt and stops a clock to the pre-designed circuit module on a external idle request signal. | 08-02-2012 |
20120221756 | METHOD AND APPARATUS FOR ADJUSTING PERIOD OF CLOCK INTERRUPTION - The present application relates to a method and an apparatus for adjusting a period of clock interruption. The method comprises: determining a number of processes in a run-queue of a processor; and determining the period of clock interruption for use in a run state of the processor such that the period of clock interruption for use when the number of the processes is greater than a reference threshold is less than the period of clock interruption for use when the number of the processes is not greater than the reference threshold. The apparatus comprises a first determination block and a second determination block. With the method and apparatus according to the embodiment of the application, it is possible to dynamically adjust the period of clock interruption such that the period of clock interruption for use in the run state of the processor can be changed according to needs with flexibility. | 08-30-2012 |
20120260014 | DATA PROCESSOR AND CONTROL SYSTEM - Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests. | 10-11-2012 |
20120284444 | Interrupt Moderation - A technique for interrupt moderation allows coalescing interrupts from a device into groups to be processed as a batch by a host processor. Receive and send completions may be processed differently. When the host is interrupted for receive completions, it may check for send completions, reducing the need for interrupts related to send completions. Timers and a counter allow coalescing interrupts into a single interrupt that can be used to signal the host to process multiple completions. The technique is suitable for both dedicated interrupt line and message-signaled interrupts. | 11-08-2012 |
20130024589 | MULTI-CORE PROCESSOR SYSTEM, COMPUTER PRODUCT, AND CONTROL METHOD - A multi-core processor system includes a given configured to queue an interrupt process of a software interrupt request to the given core, and execute queued processes in the order of queuing at the given core; execute preferentially an interrupt process of a hardware interrupt request to the given core over a process under execution at the given core; determine whether the software interrupt request is a specific software interrupt request; and perform control to preferentially execute the interrupt process without queuing, upon determining that the software interrupt request is the specific software interrupt request. | 01-24-2013 |
20130054858 | METHOD AND SYSTEM FOR CONDITIONAL INTERRUPTS - A method for issuing interrupts includes a receiving communication adapter receiving a first remote directed memory access (RDMA) write with immediate, identifying a completion queue descriptor corresponding to the first RDMA write with immediate and to a receiving entity, incrementing an interrupt counter in response to the first RDMA write with immediate. The method further includes storing, by the receiving communication adapter, in response to determining that the interrupt counter value is less than the interrupt threshold value, data in the first RDMA write with immediate on the receiving device without triggering an interrupt to the receiving entity. The receiving communication adapter further receives a second RDMA write with immediate, and increments the interrupt counter value corresponding to the completion queue descriptor in response to the second RDMA write with immediate. The method further includes triggering the interrupt to the receiving entity in response to the interrupt counter value exceeding the interrupt threshold value. | 02-28-2013 |
20130086289 | INTERRUPTION FACILITY FOR ADJUNCT PROCESSOR QUEUES - Interruption facility for adjunct processor queues. In response to a queue transitioning from a no replies pending state to a reply pending state, an interruption is initiated. This interruption signals to a processor that a reply to a request is waiting on the queue. In order for the queue to take advantage of the interruption capability, it is enabled for interruptions. | 04-04-2013 |
20130151744 | Interrupt Moderation - A technique for interrupt moderation allows coalescing interrupts from a device into groups to be processed as a batch by a host processor. Receive and send completions may be processed differently. When the host is interrupted for receive completions, it may check for send completions, reducing the need for interrupts related to send completions. Timers and a counter allow coalescing interrupts into a single interrupt that can be used to signal the host to process multiple completions. The technique is suitable for both dedicated interrupt line and message-signaled interrupts. | 06-13-2013 |
20130275637 | MANAGING OVER-INITIATIVE THIN INTERRUPTS - A method, system, and computer program product identify extraneous input/output interrupts for a queued input/output device architecture. At least one interrupt is determined to have been generated for at least one queue in a plurality of queues of a queued input/output device architecture. An interrupt handler of an operating system determines at least one of if the queue is associated with at least one reply message waiting to be dequeued for a previously processed interrupt, and if the queue fails to include at least one pending reply for a previously received unprocessed interrupt. The interrupt is identified as an extraneous interrupt in response to the determining one of that the queue is associated with at least one reply message waiting to be dequeued for a previously processed interrupt, and that the queue fails to include at least one pending reply for a previously received unprocessed interrupt. | 10-17-2013 |
20140082242 | REDUCING LATENCY IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS LINK - A method and system are described for reducing latency in a peripheral component interconnect express (PCIe) link between a host and an endpoint. In the described embodiments, an interrupt is issued from the endpoint to the host using the PCIe link. Then, while the interrupt is pending at the host, the PCIe link is prevented from entering a power-saving mode with an exit latency greater than a predetermined time period. | 03-20-2014 |
20140143467 | System and Method for Reducing Communication Overhead Between Network Interface Controllers and Virtual Machines - Available buffers in the memory space of a guest operating system of a virtual machine are provided to a network interface controller (NIC) for use during direct memory access (DMA) and the guest operating system is notified accordingly when data is written into such available buffers. These capabilities obviate the requirement of using hypervisor memory as a staging area to determine which virtual machine to forward incoming data. | 05-22-2014 |
20140173149 | COMPLETION NOTIFICATION FOR A STORAGE DEVICE - A method for providing notification of completion of a computing task includes providing access to an information handling resource for a first information handling system, registering the first information handling system with a first completion queue, submitting commands from the first information handling system to a first submission queue, providing access to the information handling resource for second first information handling system, registering the second information handling system with the first completion queue, and submitting commands from the second information handling system to a second submission queue. Upon execution of commands in the first submission queue and the second submission queue, an entry in is created a first completion queue. Upon the creation of an entry in the first completion queue, an interrupt is selectively sent to the first information handling resource and to the second information handling resource. | 06-19-2014 |
20140195708 | DETERMINING WHEN TO THROTTLE INTERRUPTS TO LIMIT INTERRUPT PROCESSING TO AN INTERRUPT PROCESSING TIME PERIOD - Provided are a computer program product, system, and method for determining when to throttle interrupts to limit interrupt processing to an interrupt processing time. Upon receiving interrupts from the hardware device, a determination is made as to whether a number of received interrupts exceeds an interrupt threshold during a interrupt tracking time period. If so, an interrupt throttling state is set to a first value indicating to only process interrupts during an interrupt processing time period. Interrupts from the hardware device are processed during the interrupt time period when the interrupt throttling state is set to the first value. Interrupts received from the hardware are masked during a processing of a scan loop of operations while the interrupt throttling has the first value and the interrupt processing time period has expired, wherein the masked interrupts are not processed while processing the scan loop of operations. | 07-10-2014 |
20140223061 | SYSTEM AND DETERMINISTIC METHOD FOR SERVICING MSI INTERRUPTS USING DIRECT CACHE ACCESS - A system and method for creating a guaranteed MSI latency by coupling a coprocessor, which may be a dedicated agent, to the existing front side bus (“FSB”) in a processor (e.g., Intel® Atom™ processor) to handle deterministic interrupts. MSI interrupts may be automatically forwarded to the coprocessor using the existing Direct | 08-07-2014 |
20140281087 | MODERATED COMPLETION SIGNALING - The moderation of event notifications from a network interface card. The network interface card has multiple completion queues that queue of completed work. The moderation batches up this completed work such that potentially multiple work requests are aggregated into a single event notification. This moderation reduces processing overhead since it spreads the overhead associated with a single interrupt to multiple event notifications The decision on moderation may be performed per connection, or even per constituent queue of the connection. The principles herein allow moderation to reduce overhead without slowing network throughput. | 09-18-2014 |
20140325109 | METHOD OF INTERRUPT CONTROL AND ELECTRONIC SYSTEM USING THE SAME - A method of interrupt control for an electronic system, the electronic system including a host and an electronic device, includes receiving digital data generated by the electronic device; determining a value of the digital data and dividing a possible range of the value of the digital data into a plurality of regions; and sending an interrupt signal to the host when the value of the digital data changes from a first region among the plurality of regions to a second region among the plurality of regions and remains within the second region for a specific period of time. | 10-30-2014 |
20140359184 | METHOD AND APPARATUS FOR ALLOCATING INTERRUPTIONS - The present disclosure relates to a method and an apparatus for allocating interruptions in a multi-core system. A method for allocating interruptions in a multi-core system according to one embodiment of the present disclosure comprises: an interrupt load extraction step of extracting interrupt loads of each interruption type; a step of extracting task loads of each core; a weighting factor determination step of determining weighting factors using a difference between task loads of the cores; a step of reflecting weighting factors to extract a converted value of the interrupt load; and an interruption allocation step of allocating interruption types to the cores such that the sums of the converted values of the interrupt loads allocated to each core and the allocated task loads are uniform. According to one embodiment of the present disclosure, interruptions can be allocated such that both task processing and interruption processing can be performed in an efficient manner. | 12-04-2014 |
20150019780 | CONTROLLING OPERATIONS ACCORDING TO ANOTHER SYSTEM'S ARCHITECTURE - An I/O device operating according to a native computer architecture is accessed by a primary computer system operating according to a primary computer architecture. An application program of the primary computer system requests an I/O operation to access the I/O device. To facilitate this access, an application program interface formed of primary instructions for execution by the primary processor processes the I/O operation to provide an I/O request and to receive an interrupt in response to completion of the access. A thread is formed of primary instructions for execution by the primary processor for receiving the interrupt from the application program interface. A subsystem operates in response to the I/O request to access the I/O device and to provide the interrupt. | 01-15-2015 |
20150019781 | MANAGING OVER-INITIATIVE THIN INTERRUPTS - A method, system, and computer program product identify extraneous input/output interrupts for a queued input/output device architecture. At least one interrupt is determined to have been generated for at least one queue in a plurality of queues of a queued input/output device architecture. The interrupt is identified as an extraneous interrupt in response to the determining one of that the queue is associated with at least one reply message waiting to be dequeued for a previously processed interrupt, and that the queue fails to include at least one pending reply for a previously received unprocessed interrupt. | 01-15-2015 |
20150067217 | SELECTING I/O INTERRUPT TARGET FOR MULTI-CORE SERVER SYSTEMS - Implementations of the present disclosure involve a system and/or method for handling errors in a multi-node commercial computing system running a number of guest applications simultaneously. In particular, the system and/or method provides the ability to program on a per-error basis the destination within the system for an interrupt based on an I/O error, the ability to provision for multiple/redundant error reporting paths for a class of more severe errors and/or distributed set of error status and log registers to aid software in narrowing down the source of an error that triggered the interrupt. In addition, the system provides for dynamically altering the destination of the error handling in response to one or more operating conditions of the system. Such flexibility in the system provides for a more robust error handling without impacting the performance of the multi-node computing system. | 03-05-2015 |
20150081942 | MULTI-CORE PROCESSOR SYSTEM, COMPUTER PRODUCT, AND CONTROL METHOD - A multi-core processor system includes a given configured to queue an interrupt process of a software interrupt request to the given core, and execute queued processes in the order of queuing at the given core; execute preferentially an interrupt process of a hardware interrupt request to the given core over a process under execution at the given core; determine whether the software interrupt request is a specific software interrupt request; and perform control to preferentially execute the interrupt process without queuing, upon determining that the software interrupt request is the specific software interrupt request. | 03-19-2015 |
20150089103 | NON-VOLATILE MEMORY CONTROLLER PROCESSING NEW REQUEST BEFORE COMPLETING CURRENT OPERATION, SYSTEM INCLUDING SAME, AND METHOD - A non-volatile memory controller, system and method capable of processing a next request as an interrupt before completing a current operation are disclosed. The non-volatile memory system includes a first memory storing meta data loaded from a flash memory; a second memory storing the meta data copied from the first memory; and a flash memory controller copying the meta data from the first memory to the second memory, changing the meta data in the second memory, and then re-copying the changed meta data from the second memory to the first memory during a first-type operation that requires changes in the meta data. | 03-26-2015 |
20150127865 | METHOD AND APPARATUS USE WITH INTERRUPTS - A system is configured to capture a set of interrupts and output the interrupts serially onto an interconnect. The interrupts, which are routed to a destination, may first be packetized such that additional information is associated with the interrupt within the packet. | 05-07-2015 |
20150143011 | INTERRUPTION FACILITY FOR ADJUNCT PROCESSOR QUEUES - Interruption facility for adjunct processor queues. In response to a queue transitioning from a no replies pending state to a reply pending state, an interruption is initiated. This interruption signals to a processor that a reply to a request is waiting on the queue. In order for the queue to take advantage of the interruption capability, it is enabled for interruptions. | 05-21-2015 |
20150356036 | AGGREGATION OF INTERRUPTS USING EVENT QUEUES - Embodiments of input/output hub unit are disclosed for aggregating interrupts received from multiple endpoint devices. The input/output hub may include an interface unit and one or more communication units. Each communication unit may be configured to receive messages from a corresponding endpoint device. The interface unit may be configured to update a first pointer within a first data structure responsive to a request from a given one of the communication units. The interface unit may be further configured to stored data in a second data structure responsive to updating the first pointer, reading a second pointer and the first pointer, and sending an interrupt responsive to a determination that the first and second pointers are equal. | 12-10-2015 |
20150378792 | DEFERRAL INSTRUCTION FOR MANAGING TRANSACTIONAL ABORTS IN TRANSACTIONAL MEMORY COMPUTING ENVIRONMENTS - A deferral instruction associated with a transaction is executed in a transaction execution computing environment with transactional memory. Based on executing the deferral instruction, a processor sets a defer-state indicating that pending disruptive events such as interrupts or conflicting memory accesses are to be deferred. A pending disruptive event is deferred based on the set defer-state, and the transaction is completed based on the disruptive event being deferred. The progress of the transaction may be monitored during a deferral period. The length of such deferral period may be specified by the deferral instruction. Whether the deferral period has expired may be determined based on the monitored progress of the transaction. If the deferral period has expired, the transaction may be aborted and the disruptive event may be processed. | 12-31-2015 |
20160011647 | POWER CONTROL METHOD AND ELECTRONIC DEVICE SUPPORTING THE SAME | 01-14-2016 |
20160026587 | MULTICORE PROCESSOR SYSTEM, COMPUTER PRODUCT, ASSIGNING METHOD, AND CONTROL METHOD - A multicore processor system includes core configured to detect a process assignment instruction; acquire a remaining time obtained by subtracting a processing time of interrupt processing assigned to an arbitrary core of a multicore processor from a period that is from a calling time of the interrupt processing to an execution time limit of the interrupt processing, upon detecting the process assignment instruction; judge if the remaining time acquired at the acquiring is greater than or equal to a processing time of processing defined to limit an interrupt in the process; and assign the process to the arbitrary core, upon judging that the remaining time is greater than or equal to the processing time of the processing defined to limit an interrupt in the process. | 01-28-2016 |
20160124874 | METHOD AND APPARATUS FOR INTERRUPT COALESCING - Apparatus and methods implemented therein moderate the rate at which a peripheral device interrupts the operation of a host device. Moderation of interrupts is achieved by implementing interrupt coalescing schemes. In response to detecting an assertion of a first interrupt, a first time value from a free-running counter is read. A second time value is read from the free-running counter when an assertion of a second interrupt is detected. An identifier of the first interrupt is communicated to a host device when a sum of the first time value and an interrupt coalescing time period is equal to or greater than an instantaneous time read from the free-running counter. An identifier of the second interrupt is communicated to the host device when a sum of the second time value and an interrupt coalescing time period is equal to or greater than an instantaneous time read from the free-running counter. | 05-05-2016 |
20160124880 | METHODS AND SYSTEMS FOR ACCESSING STORAGE USING A NETWORK INTERFACE CARD - Methods and systems for efficiently processing input/output requests are provided. A network interface card (NIC) is coupled to a storage device via a peripheral link and accessible to a processor of a computing device executing instructions out of a memory device. The NIC is configured to receive a read/write request to read/write data; translate the read/write request to a storage device protocol used by the storage device coupled to the NIC; notify the storage device of the read/write request, without using the processor of the computing device, where the storage device reads/writes the data and notifies the NIC; and then the NIC prepares a response to the read/write request without having to use the processor of the computing device. | 05-05-2016 |
20160147680 | INTERRUPTION FACILITY FOR ADJUNCT PROCESSOR QUEUES - Interruption facility for adjunct processor queues. In response to a queue transitioning from a no replies pending state to a reply pending state, an interruption is initiated. This interruption signals to a processor that a reply to a request is waiting on the queue. In order for the queue to take advantage of the interruption capability, it is enabled for interruptions. | 05-26-2016 |