Class / Patent application number | Description | Number of patent applications / Date published |
710317000 | Crossbar | 76 |
20080215792 | Multiple processor system and method including multiple memory hub modules - A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory modules in the first rank. The data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules in the first rank that are used to access the memory module in the second set. Each of the memory modules includes several memory devices coupled to a memory hub. The memory hub includes a memory controller coupled to each memory device, a link interface coupled to a respective processor or memory module, and a cross bar switch coupling any of the memory controllers to any of the link interfaces. | 09-04-2008 |
20080222342 | Crossbar comparator - A device includes a first crossbar array having first input columns and first output rows, wherein a plurality of the rows of the first crossbar array are configured to store first stored data in the form of high or low resistance states, and a second crossbar array having second input columns and second output rows, wherein a plurality of the rows of the second crossbar array are configured to store second stored data in the form of high or low resistance states. The second stored data is a complement of the first stored data and the first output rows are electrically connected to the second output rows. The device provides for data storage and comparison for computer processing, audio/speech recognition, and robotics applications. | 09-11-2008 |
20080235431 | Method Using a Master Node to Control I/O Fabric Configuration in a Multi-Host Environment - A method is directed to use of a master root node, in a distributed computer system provided with multiple root nodes, to control the configuration of routings through an I/O switched-fabric. One of the root nodes is designated as the master root node or PCI Configuration Manager (PCM), and is operable to carry out the configuration while each of the other root nodes remains in a quiescent or inactive state. In one useful embodiment pertaining to a system of the above type, that includes multiple root nodes, PCI switches, and PCI adapters available for sharing by different root nodes, a method is provided wherein the master root node is operated to configure routings through the PCI switches. Respective routings are configured between respective root nodes and the PCI adapters, wherein each of the configured routings corresponds to only one of the root nodes. A particular root node is enabled to access each of the PCI adapters that are included in any configured routing that corresponds to the particular root node. At the same time, the master root node writes into a particular root node only the configured routings that correspond to the particular root node. Thus, the particular root node is prevented from accessing an adapter that is not included in its corresponding routings. | 09-25-2008 |
20080307150 | Optimized Switching Method - There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit. | 12-11-2008 |
20080307151 | Operational amplifier with resistance switch crossbar feedback - A control circuit includes an operational amplifier having an inverting input, a non-inverting input, and an output, an array of impedance elements including capacitors are connected to the output of the operational amplifier, and a resistance switch crossbar array configured to store data in the form of high or low resistance states, wherein the resistance switch crossbar array is electrically connected between the array of impedance elements and the inverting input of the operational amplifier. The crossbar control circuit may be implemented in a control system to provide for adjustment of the control system to changes in environmental conditions or to change the function of the control system. | 12-11-2008 |
20090037639 | JTAGCHAIN Bus Switching and Configuring Device - A JTAG bus cross point switching device that is commanded by the same bus which it configures. In a preferred embodiment a JTAG chain includes a cross point switching device that is capable of adding, omitting, or rearranging devices on a JTAG bus. The switching device itself is controlled by commands on the JTAG bus which it configures. | 02-05-2009 |
20090089478 | Crossbar channel router having a distributed arbitration scheme - A router is provided that includes a plurality of lanes to receive inbound data from a plurality of different input ports. The router may further include a shared crossbar channel coupled to each of the lanes and to a plurality of output ports, the crossbar channel to receive inbound data from the plurality of lanes and to provide outbound data to the plurality of output ports. Each lane may include a local lane arbiter, a global lane arbiter and a port arbiter associated with each port. | 04-02-2009 |
20090144480 | MULTI-PROCESSOR SYSTEM ON CHIP PLATFORM AND DVB-T BASEBAND RECEIVER USING THE SAME - A multi-processor system on chip (SoC) platform and a DVB-T baseband receiver using the same are disclosed. The multi-processor SoC platform includes a first processor, at least one second processor, at least one slave device communicating with the first processor and the second processor and a communication interface (CI) unit connecting the slave device to the first processor and the second processor according to a cross-bar switching method to allow the slave device to be communicated with the first processor and the second processor. Therefore, the multi-processor SoC platform having flexibility with being adapted for high speed calculation by using a cross-bar switch is provided. | 06-04-2009 |
20090172242 | SYSTEM AND METHOD FOR CONNECTING A MASTER DEVICE WITH MULTIPLE GROUPINGS OF SLAVE DEVICES VIA A LINBUS NETWORK - A LINBUS communication network comprises a microcontroller unit containing processing circuitry for performing predefined digital processing functions. LINBUS communication network hardware is located within the microcontroller unit for digitally communicating with an off-chip LINBUS device for transmitting data thereto and receiving data therefrom. A plurality of LINBUS communication network interfaces selectively connects one of a plurality of groups of slave devices to the LINBUS network communications hardware. | 07-02-2009 |
20090193172 | CROSS-BAR SWITCHING IN AN EMULATION ENVIRONMENT - A system and method are disclosed for crossbar switching in an emulation environment. The switch is designed to coordinate scheduling between different crossbars in the system and to be dynamically reconfigurable during operation. In one aspect, a crossbar switch includes a switching matrix and an array of control cells. The control cells use a high-frequency clock to perform high-speed switching and a low-frequency clock in order to initiate a switching sequence. The low-frequency clock initiates the sequence at a time coordinated with other crossbars in the system to optimize scheduling. In another aspect, the control cells include a memory containing control bits for the switching matrix. The memory may be reconfigured without stopping traffic management through the crossbar switch. In yet another aspect, the high-frequency sequence may provide for the ability to loop. In still another aspect, the crossbar switches may receive multiplexed input signals that can be routed to several crossbar outputs without the need for an internal demultiplexing stage. | 07-30-2009 |
20090198864 | NETWORK SWITCH AND METHOD OF SWITCHING IN NETWORK - A network switch with a plurality of crossbar switches that is available to suppress increase in the circuit scale is provided. The network switch has: the plurality of crossbar switches that transfer unit data in a specified format; a receiving side transfer unit that transfers data received from a network to the plurality of crossbar switches in the unit data basis; and a plurality of transmitting side transfer units that transmit data transferred from the plurality of crossbar switches to the network. The receiving side transfer sets a consecutive serial number to the unit data in transfer sequence, and distributes the unit data to the plurality of crossbar switches. Each of the plurality of transmitting side transfer units has a plurality of queues for the respective crossbar switches that stores the transferred unit data, and extracts the unit data with smallest serial number of the unit data stored in the queues when all of the queues store the unit data. | 08-06-2009 |
20090210610 | Computer system, data relay device and control method for computer system - A computer system includes a plurality of system boards each of which includes two systems arranged in a duplicated structure and a data relay device. The data relay device includes a degeneration determining unit that determines whether each of the systems is degenerated based on a signal that is transmitted from the each of the systems; a dummy-information creating unit that creates dummy information by adding dummy data to identification information and destination information, the identification information indicating a head of proper data that is transmitted from one of the systems constituting the duplicated structure with the other system that has been determined as being degenerated, and the destination information indicating destination of the data; and a data transmitting unit that transmits, as synchronized data, proper information that is transmitted from the one of the systems, and the dummy information. | 08-20-2009 |
20090240866 | Multi-port memory and computer system provided with the same - A multi-port memory, comprising: m (m≧2) input/output ports independent of one another; n (n≧2) memory banks independent of one another; and a route switching circuit capable of optionally setting signal routes of a command, an address, and input/output data between the m input/output ports and the n memory banks, wherein the route switching circuit allocates p (1≦p≦m) input/output ports optionally selected from the m input/output ports to a memory bank optionally selected from the n memory banks. | 09-24-2009 |
20090248948 | System and Method for A Distributed Crossbar Network Using a Plurality of Crossbars - A system and method for single hop, processor-to-processor communication in a multiprocessing system over a plurality of crossbars are disclosed. Briefly described, one embodiment is a multiprocessing system comprising a plurality of processors having a plurality of high-bandwidth point-to-point links; a plurality of processor clusters, each processor cluster having a predefined number of the processors residing therein; and a plurality of crossbars, one of the crossbars coupling each of the processors of one of the plurality of processor clusters to each of the processors of another of the plurality of processor clusters, such that all processors are coupled to each of the other processors, and such that the number of crossbars is equal to [X*(X−1)/2], wherein X equals the number of processor clusters. | 10-01-2009 |
20090282182 | MULTIPLE PROCESSOR SYSTEM AND METHOD INCLUDING MULTIPLE MEMORY HUB MODULES - A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory modules in the first rank. The data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules in the first rank that are used to access the memory module in the second set. Each of the memory modules includes several memory devices coupled to a memory hub. The memory hub includes a memory controller coupled to each memory device, a link interface coupled to a respective processor or memory module, and a cross bar switch coupling any of the memory controllers to any of the link interfaces. | 11-12-2009 |
20090307408 | Peer-to-Peer Embedded System Communication Method and Apparatus - According to one embodiment, an embedded system includes at least one processor, memory and peripheral subsystem. Each subsystem has a terminating node configured to issue and receive messages for the subsystem. A bus fabric interconnects the subsystems and includes a plurality of non-terminating nodes located at different points in the bus fabric and interconnected with the terminating nodes to form a peer-to-peer communication matrix between the subsystems. The non-terminating nodes route the messages over the peer-to-peer matrix so that instructions included in the messages are delivered to the terminating nodes identified in the messages for execution. Each node is assigned one or more unique object identifiers for identifying the nodes and the instructions included in the messages identify different control and data flow functions supported by different ones of the subsystems. | 12-10-2009 |
20090319717 | SCALABLE DISTRIBUTED MEMORY AND I/O MULTIPROCESSOR SYSTEMS AND ASSOCIATED METHODS - A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact. | 12-24-2009 |
20100077127 | Flexible Connection Scheme Between Multiple Masters and Slaves - The present invention describes a flexible routing scheme between masters and slaves in complex digital systems. The routing scheme is optimized for maximum versatility and configurability using switched resources in the form of configurable crossbar switches. | 03-25-2010 |
20100138586 | ADAPTIVE AND MODULAR UPS SYSTEM AND METHOD - An uninterruptible power supply (UPS) system that may incorporate a battery subsystem including at least one battery for generating electrical power, and a UPS subsystem including at least one power module. At least one first bus system may couple the battery subsystem to the UPS subsystem to supply electrical power to the UPS subsystem. An input and output (I/O) subsystem is in communication with an output of the UPS subsystem for generating an output signal. At least one second bus system may be used for coupling the output of the UPS subsystem to the I/O subsystem. At least one of the first and second bus systems may include a pair of parallel coupled, independent busses, and may further have a tie bar for enabling the pair of busses to be reconfigured as a single bus. | 06-03-2010 |
20100211718 | METHOD AND APPARATUS FOR CONGESTION-AWARE ROUTING IN A COMPUTER INTERCONNECTION NETWORK - The present disclosure relates to an example of a method for a first router to adaptively determine status within a network. The network may include the first router, a second router and a third router. The method for the first router may comprise determining status information regarding the second router located in the network, and transmitting the status information to the third router located in the network. The second router and the third router may be indirectly coupled to one another. | 08-19-2010 |
20100211719 | Crossbar circuitry and method of operation of such crossbar circuitry - Crossbar circuitry, and a method of operation of such crossbar circuitry, are provided. The crossbar circuitry has an array of data input paths and data output paths where the data output paths are transverse to the data input paths. At each intersection between a data input path and a data output path, a crossbar cell is provided that comprises a storage circuit programmable to store a routing value, and a transmission circuit. In a transmission mode of operation the transmission circuit is responsive to the routing value indicating that the data input path should be coupled to the data output path to detect the data input along the data input path, and to output an indication of that data on the data output path at the associated intersection. Control circuitry is used to issue control signals to the crossbar cells, and during a configuration mode of operation the control circuitry re-utilises at least one of the data output paths to program the storage circuitry of one or more of the crossbar cells. Such a construction of crossbar circuitry provides a very regular design, with uniform delay across all paths, and which requires significantly less control lines than typical prior art crossbar designs. Such crossbar circuitry is readily scalable to form large crossbars. | 08-19-2010 |
20100211720 | Crossbar circuitry and method of operation of such crossbar circuitry - Crossbar circuitry, and a method of operation of such crossbar circuitry, are provided. The crossbar circuitry has an array of data input paths and data output paths where the data output paths are transverse to the data input paths. At each intersection between a data input path and a data output path, a crossbar cell is provided that comprises a configuration storage circuit programmable to store a routing value, a transmission circuit, and an arbitration circuit. In a transmission mode of operation, the transmission circuit is responsive to the routing value being a first value, indicating that the data input path should be coupled to the data output path, to detect the data input along the data input path, and to output an indication of that data on the data output path at the associated intersection. In an arbitration mode of operation, the arbitration circuitry is operable in the presence of an asserted transmission request from the associated source circuit to operate in combination with the arbitration circuits of other crossbar cells associated with the same data output path to re-use the bit lines of the data output path to detect the presence of multiple asserted transmission requests for the same data output path. In the event of such multiple asserted transmission requests, the arbitration circuitry operates in combination with the other arbitration circuits to implement a predetermined priority scheme to cause the configuration storage circuit of only one crossbar cell associated with the same data output path to have its routing value programmed to the first value, thereby resolving conflict between the multiple asserted transmission requests according to the predetermined priority scheme. Such a construction of crossbar circuitry enables a very efficient resolution of conflicts to be performed, whilst providing a very regular design, with uniform delay across all paths, and which requires significantly less control lines that typical prior art crossbar designs. Such crossbar circuitry is readily scalable to form large crossbars. | 08-19-2010 |
20100274946 | INTEGRATED CIRCUIT AND INFORMATION PROCESSING DEVICE - In an LSI system using an on-chip bus, when a transfer on the bus is delayed due to a fully loaded buffer in a destination module, a source module cannot proceed to the next processing. Such an unwanted situation is eliminated by plural transferring buffers which are provided in an on-chip bus on the LSI for temporarily storing transfer data. With the transferring buffers, even if a buffer within a slave module, specified as the destination, is fully loaded and cannot accept any more transfer, a bus master can transfer data to a transferring buffer provided on the on-chip bus. Thus, the bus master is not kept waiting for execution of a transfer, irrespective of the state of the buffer within the slave. With the provision of plural transferring buffers, input/output operations can be performed in parallel. | 10-28-2010 |
20110016259 | Information processing device, data transfer circuit, and control method of information processing device - Cross bar control circuits are connected to each other by two buses, which are a broadcast bus for transmitting a broadcast packet from a system board to all system boards other than the system board and a point-to-point bus for transmitting a unicast packet from a system board to another system board. When unicast packets passing through the point-to-point bus are too many, the unicast packets are output by using the broadcast bus in addition to the point-to-point bus if the broadcast bus is not used. In this way, the unicast packets can be output quickly and efficiently, so that use efficiency of the broadcast bus and the point-to-point bus can be increased as a whole. | 01-20-2011 |
20110035529 | Partitioning a Crossbar Interconnect in a Multi-Channel Memory System - A method includes identifying a first set of masters and a second set of masters from a plurality of masters. The plurality of masters have access to a multi-channel memory via a crossbar interconnect. The method includes partitioning the crossbar interconnect into a plurality of partitions comprising at least a first partition corresponding to the first set of masters and a second partition corresponding to the second set of masters. The method also includes allocating a first set of buffer areas within the multi-channel memory. The first set of buffer areas correspond to the first set of masters. The method further includes allocating a second set of buffer areas within the multi-channel memory. The second set of buffers correspond to the second set of masters. | 02-10-2011 |
20110035530 | Network system, information processing apparatus, and control method for network system - A network system includes a crossbar switch, and a plurality of crossbar interfaces having ports connected to the crossbar switch. A bypass route directly connects crossbar interfaces forming a group in which a frequency of use of the ports is greater than or equal to a predetermined value amongst the plurality of crossbar interfaces. | 02-10-2011 |
20110055452 | METHOD AND PROGRAM FOR MEMORY RELOCATION CONTROL OF COMPUTER, AND COMPUTER SYSTEM - A computer system comprises a computer that includes a plurality of CPU sockets including one or more CPU cores, a crossbar switch, and a memory controller each, and memories connected under the respective plurality of CPU sockets, the plurality of CPU sockets being connected to each other. When all the CPU cores in a CPU socket enter a power saving state and a total amount of memory use falls below a predetermined threshold, the computer relocates contents of the memory connected under the CPU socket to a memory under another CPU socket, thereby eliminating an access to the memory connected under the CPU socket and bringing a whole of the CPU socket into the power saving state. | 03-03-2011 |
20110060860 | BACKPLANE NETWORK DISTRIBUTION - A backplane arrangement | 03-10-2011 |
20110138098 | Crossbar circuitry for applying an adaptive priority scheme and method of operation of such crossbar circuitry - Crossbar circuitry has an array of data input and output paths where the data output paths are transverse to the data input paths. At each intersection between a data input path and a data output path, a crossbar cell is provided which includes a configuration storage circuit programmable to store a routing value, a transmission circuit, and an arbitration circuit. In a transmission mode of operation, the transmission circuit is responsive to the routing value being a first value, indicating that the data input path should be coupled to the data output path, to detect the data input along the data input path, and to output an indication of that data on the data output path at the associated intersection. In an arbitration mode of operation, the arbitration circuitry is operable to selectively modify the voltage on said plurality of bit lines in order to apply an adaptive priority scheme. | 06-09-2011 |
20110138099 | Method for communicating between nodes and server apparatus - According to an aspect of the embodiment, an input/output device transmits a message to a first node controller of a parent node which is set in advance via a cross bar. At this point, the cross bar generates information based on node information of the input/output device, and adds the generated information to the message. The first node controller transmits, via the cross bar, the message to a second node controller of a parent node corresponding to an input/output device that is to receive the message. The second node controller transmits, via the cross bar, the message to an input/output device that is to receive the message. At this point, the cross bar transmits the message restored by deleting the generated information from the message to the input/output device which is set as a destination. | 06-09-2011 |
20110258361 | PETAFLOPS ROUTER - Disclosed is a method and system for performing operations on at least one input data vector in order to produce at least one output vector to permit easy, scalable and fast programming of a petascale equivalent supercomputer. A PetaFlops Router may comprise one or more PetaFlops Nodes, which may be connected to each other and/or external data provider/consumers via a programmable crossbar switch external to the PetaFlops Node. Each PetaFlops Node has a FPGA and a programmable intra-FPGA crossbar switch that permits input and output variables to be configurably connected to various physical operators contained in the FPGA as desired by a user. This allows a user to specify the instruction set of the system on a per-application basis. Further, the intra-FPGA crossbar switch permits the output of one operation to be delivered as an input to a second operation. By configuring the external crossbar switch, the output of a first operation on a first PetaFlops Node may be used as the input for a second operation on a second PetaFlops Node. An embodiment may provide an ability for the system to recognize and generate pipelined functions. Streaming operators may be connected together at run-time and appropriately staged to allow data to flow through a series of functions. This allows the system to provide high throughput and parallelism when possible. The PetaFlops Router may implement the user desired instructions by appropriately configuring the intra-FPGA crossbar switch on each PetaFlops Node and the external crossbar switch. | 10-20-2011 |
20110283038 | Information processing system, information processing device, control method for information processing device, and computer-readable recording medium - An information processing system including plural information processing devices multi-dimensionally connected with one another, where each of the information processing devices includes first and second receiving storage devices to store data allocated to first and second virtual channels in respective data transmitting and receiving directions, a virtual channel control unit to compare a position in a dimension of a destination information processing device with a position in the same dimension of an own information processing device, and if the comparison result indicates that the position of the own information processing device matches a position one information processing device before the position of the destination information processing device, change one of the first and the second virtual channels to the other one, and a data storage unit to store the allocated data in a corresponding one of the first and second storage devices. | 11-17-2011 |
20110320678 | CROSSPOINT SWITCH FOR USE IN VIDEO AND OTHER APPLICATIONS - A crosspoint selector switch for simultaneously supporting multiple data formats having different switch reconfiguration timing requirements, comprising; a configurable switch section for selectively connecting outputs thereof to receive data from respective inputs thereof in response to operational switch data; and a configuration section operatively connected to provide the operational switch data to the switch section, the configuration section storing switch configuration data supporting multiple different configurations of the switch section, the configuration section being operative to receive different operational update commands each associated with a different configuration for the switch section and update the operational switch data from the stored switch configuration data to reconfigure the switch section in dependence on which of the different operational update commands is received. | 12-29-2011 |
20120047310 | Crossbar circuitry for applying a pre-selection prior to arbitration between transmission requests and method of operation of such crossbar circuitry - Crossbar circuitry has data input and output paths, and at each intersection between a data input and output path, a crossbar cell is provided. A transmission circuit is responsive to a stored routing value to couple a data input path to a selected data output path. Pre-selection circuitry cooperates with the pre-selection circuits of other crossbar cells on the same data output path to use the bit lines of the data output path to compare quality-of-service values associated with multiple asserted transmission requests and to determine a subset thereof which have a highest value of the quality-of-service values. Arbitration circuitry implements a predetermined priority scheme to choose from that subset of requests and to cause the configuration storage circuit of only one crossbar cell associated with the same data output path to have its routing value programmed to the first value, thereby resolving conflict between multiple asserted transmission requests. | 02-23-2012 |
20120159037 | MEMORY INTERLEAVING DEVICE AND METHOD USING REORDER BUFFER - A memory interleaving device includes a slave interface, a master interface, and a crossbar switch. The slave interface is connected with a master intellectual property through an on-chip network. The master interface is connected with a slave intellectual property. The crossbar switch connects the slave interface with the master interface. The memory interleaving device transmits requests from the master intellectual property to the slave intellectual property, receives data or responses respectively corresponding to the requests from the slave intellectual property, and transmits the data or responses to the master intellectual property in an order in which the requests are received. | 06-21-2012 |
20120210040 | MICRO-CROSSBAR AND ON-DIE DATA NETWORK - An integrated circuit (IC) having an on-die data network is disclosed. The IC includes a first bus and second buses configured to convey signals in first and second directions, respectively, along a first axis. The second direction is opposite the first. The IC further includes third and fourth buses configured to convey signals in third and fourth directions, respectively, along a second axis perpendicular to the first axis. The fourth direction is opposite the third. Each bus is N-bits wide and unidirectional. Signal lines of two different buses having equal bit significance and opposite direction are arranged adjacent to one another. A crossbar unit having N crossbar switching circuits is configured to couple signal lines of a selected one of the buses to a corresponding signal line of another selected one of the buses. The signal lines of the buses are implemented on different metal layers than the crossbar switching circuits. | 08-16-2012 |
20120324140 | CODING FOR CROSSBAR ARCHITECTURE - A method for encoding bits to be stored within a crossbar memory architecture performed by a physical computing system includes designating, with the physical computing system, a subset of crosspoints within a crossbar matrix, the crossbar matrix comprising a number of disjointed intersecting wire segments, the subset corresponding to a predetermined path through the crossbar matrix; and encoding, with the physical computing system, a number of data bits to be placed along the predetermined path; in which the encoding causes bits pertaining to at least one of the wire segments to be subject to a constraint when the data bits are placed along the predetermined path. | 12-20-2012 |
20130007337 | SEGMENTATION AND REASSEMBLY OF DATA FRAMES - A system and method of transmitting data frames between a plurality of input ports to a plurality of output ports is described. The input ports segment portions of the received data frames to provide smaller data cells which are individually transmitted to an output port associated with a destination of the segmented data frame. Based upon information provided in the data cells received at the output port, the output port determines the ordinal positions of the received data cells within the segmented data frame and reassembles the data frame which was segmented at the input port. The output port then forwards the reassembled frame toward the associated destination. | 01-03-2013 |
20130046915 | Scalable and Configurable System on a Chip Interrupt Controller - Embodiments include a system and method for an interrupt controller that propagates interrupts to a subsystem in a system-on-a-chip (SOC). Interrupts are provided to an interrupt controller that controls access of interrupts to a particular subsystem in the SOC that includes multiple subsystems. Each subsystem in the SOC generates multiple interrupts to other subsystems in the SOC. The interrupt controller processes multiple interrupts and generates an interrupt output. The interrupt output is then transmitted to a particular subsystem. | 02-21-2013 |
20130046916 | FIBRE ADAPTER FOR A SMALL FORM-FACTOR PLUGGABLE UNIT - The disclosure is directed at a fibre adapter for use with small form factor pluggable (SFP) devices comprising a set of cages for receiving the SFP devices and a switch for interconnecting inputs and outputs of the set of cages. | 02-21-2013 |
20130159595 | Serial Interface for FPGA Prototyping - In aspects of serial interface for FPGA prototyping, an advanced crossbar interconnect (AXI) bridge structure enables serial data communication between field programmable gate arrays (FPGA) in a system-on-chip (SoC). The AXI bridge structure includes a parallel interface configured to receive AXI data signals from an AXI component implemented at a first FPGA. A transmit (TX) engine is configured to packetize the AXI data signals into an AXI data packet, and transmit the AXI data packet to a second FPGA via a serial link. The AXI bridge structure also includes a receive (RX) engine configured to receive an additional AXI data packet from the second FPGA via the serial link, and extract AXI data signals from the additional AXI data packet. The parallel interface is further configured to provide the additional AXI data signals to the AXI component. | 06-20-2013 |
20130173840 | COMMUNICATIONS CONTROL SYSTEM WITH A SERIAL COMMUNICATIONS INTERFACE AND A PARALLEL COMMUNICATIONS INTERFACE - A communications control system is disclosed that includes a serial communications interface and a parallel communications interface for coupling a plurality of input/output modules with a control module. The serial communications interface is configured for connecting the plurality of input/output modules to the control module in parallel to transmit information between the plurality of input/output modules and the control module, and the parallel communications interface is configured for separately connecting the plurality of input/output modules to the control module to transmit information between the plurality of input/output modules and the control module, and to transmit information between individual ones of the plurality of input/output modules. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch. | 07-04-2013 |
20130219103 | Configurable Mesh Data Bus In An Island-Based Network Flow Processor - An island-based network flow processor (IB-NFP) integrated circuit includes rectangular islands disposed in rows. A configurable mesh data bus includes a command mesh, a pull-id mesh, and two data meshes. The configurable mesh data bus extends through all the islands. For each mesh, each island includes a centrally located crossbar switch and eight half links. Two half links extend to ports on the top edge of the island, a half link extends to a port on a right edge of the island, two half links extend to ports on the bottom edge of the island, and a half link extents to a port on the left edge of the island. Two additional links extend to functional circuitry of the island. The configurable mesh data bus is configurable to form a command/push/pull data bus over which multiple transactions can occur simultaneously on different parts of the integrated circuit. | 08-22-2013 |
20130254453 | COMPUTER SYSTEM, AND SWITCH AND PACKET TRANSFER CONTROL METHOD USED THEREIN - A system and method are disclosed to prevent a reduction in the number of I/O devices which can be connected when building a PCIe topology by connecting I/O devices to a computer via a PCIe switch. A switch with which a computer and I/O devices are connected includes: a first PCI-PCI bridge which is positioned on the computer side; a second PCI-PCI bridge which is positioned on the I/O device side; trapper units which trap packet data which is inputted into the switch; a packet routing unit which transfers packet data to the I/O devices; and a management processor which is connected to the trapper units and provides the computer a virtual PCI-PCI bridge and a virtual link by execution of a program. The trapper units adjudicate the destination of the packet data which is transferred from the computer. | 09-26-2013 |
20130262735 | DATA PROCESSING APPARATUS, COMPUTATION DEVICE, CONTROL METHOD FOR DATA PROCESSING APPARATUS - A data processing apparatus includes a plurality of computation devices connected to each other by a communication path. Each of the computation devices includes: a switching section provided to each of terminals and switchable between an upper layer use state in which communication is performed by a communication section between a given terminal of a plurality of terminals and a corresponding internal path and there is no connection performed by a bypass section between a corresponding pair of the plurality of the terminals, and an upper layer non-use state in which communication is not performed by a communication section between the given terminal of the plurality of the terminals and the corresponding internal path and connection is performed by the bypass section between the corresponding pair of the plurality of the terminals. | 10-03-2013 |
20130311697 | SWITCHING DEVICE FOR ROUTING DATA, COMUTER INTERCONNECTION NETWORK AND ROUTING METHOD USING SUCH DEVICE - The invention is directed to a switching device (S | 11-21-2013 |
20140025862 | SERVER SYSTEM AND DYNAMIC MAINTENANCE METHOD FOR CROSSBAR BOARD - According to an aspect of an embodiment, a server system includes a service processor, a plurality of system boards and a plurality of crossbar boards connecting the system boards. The service processor includes a first notifier that notifies each of the crossbar boards of a crossbar board subjected to maintenance. The crossbar boards each include a first transmitter that, when notified by the service processor that the crossbar board subjected to maintenance is another crossbar board, generates a suspension packet for suspending packet transmission to the another crossbar board and transmits the suspension packet to each of the system boards. The system boards each include a suspender that, when receiving the suspension packet from the crossbar board, suspends packet transmission to the crossbar board subjected to maintenance. | 01-23-2014 |
20140032811 | MULTI-ROOT PERIPHERAL CONNECT INTERFACE MANAGER - Described herein is a detachable multi-host computing system ( | 01-30-2014 |
20140040528 | RECONFIGURABLE CROSSBAR NETWORKS - Reconfigurable crossbar networks, and devices, systems and methods, including hardware in the form of logic (e.g. application specific integrated circuits (ASICS)), and software in the form of machine readable instructions stored on machine readable media (e.g., flash, non-volatile memory, etc.), which implement the same, are provided. An example of a reconfigurable crossbar network includes a crossbar. A plurality of endpoints is coupled to the crossbar. The plurality of endpoints is grouped into regions at design time of the crossbar network. A plurality of regional interconnects are provided. Each regional interconnect connects a group of endpoints within a given region. | 02-06-2014 |
20140047157 | PARALLEL COMPUTER SYSTEM, CROSSBAR SWITCH, AND METHOD OF CONTROLLING PARALLEL COMPUTER SYSTEM - A parallel computer system includes a plurality of processors including a first processor and a plurality of second processors; and a crossbar switch provided with a plurality of ports; wherein the first processor transmits data to a first port among the plurality of ports, and transmits standby time information to the first port in the case where the plurality of second processors are unable to transmit data to the first port despite receiving a communication authorization notification from the first port, and the first port receives the standby time information, and after the standby time elapses, selects one of the plurality of second processors. | 02-13-2014 |
20140075085 | METHOD AND APPARATUS FOR TRANSFERRING PACKETS BETWEEN INTERFACE CONTROL MODULES OF LINE CARDS - An access system includes line cards. The line cards include first and second line cards. The first line card receives a first packet and includes a first interface control module that generates a first request signal to transfer the first packet. The first request signal includes an identifier of a second interface control module in the second line card. Crossbar modules are separate from the line cards and include first and second crossbar modules. The first crossbar module includes a first scheduler module. The second crossbar module transfers packets between a pair of the line cards. The packets include the first packet. The first scheduler module is separate from the line cards and, based on the first request signal, schedules the transfer of the packets from the first interface control module, through the second crossbar module, and to the second interface control module. | 03-13-2014 |
20140101358 | BYTE SELECTION AND STEERING LOGIC FOR COMBINED BYTE SHIFT AND BYTE PERMUTE VECTOR UNIT - Exemplary embodiments of the present invention disclose a method and system for executing data permute and data shift instructions. In a step, an exemplary embodiment encodes a control index value using the recoding logic into a 1-hot-of-n control for at least one of a plurality of datum positions in the one or more target registers. In another step, an exemplary embodiment conditions the 1-hot-of-n control by a gate-free logic configured for at least one of the plurality of datum positions in the one or more target registers for each of the data permute instructions and the at least one data shift instruction. In another step, an exemplary embodiment selects the 1-hot-of-n control or the conditioned 1-hot-of-n control based on a current instruction mode. In another step, an exemplary embodiment transforms the selected 1-hot-of-n control into a format applicable for the crossbar switch. | 04-10-2014 |
20140115224 | MEMORY INTERCONNECT NETWORK ARCHITECTURE FOR VECTOR PROCESSOR - The present disclosure provides a memory interconnection architecture for a processor, such as a vector processor, that performs parallel operations. An example processor may include a compute array that includes processing elements; a memory that includes memory banks; and a memory interconnect network architecture that interconnects the compute array to the memory. In an example, the memory interconnect network architecture includes a switch-based interconnect network and a non-switch based interconnect network. The processor is configured to synchronously load a first data operand to each of the processing elements via the switch-based interconnect network and a second data operand to each of the processing elements via the non-switch-based interconnect network. | 04-24-2014 |
20140122771 | WEIGHTAGE-BASED SCHEDULING FOR HIERARCHICAL SWITCHING FABRICS - Techniques are disclosed to implement a scheduling scheme for a crossbar scheduler that provides distributed request-grant-accept arbitration between input group arbiters and output group arbiters in a distributed switch. Input and output ports are grouped and assigned a respective arbiter. The input group arbiters communicate requests indicating a count of respective ports having data packets to be transmitted via one of the output ports. The output group arbiter attempts to accommodate the requests for each member of an input group before proceeding to a next input group. | 05-01-2014 |
20140136751 | MULTI-CHANNEL STORAGE SYSTEM SUPPORTING A MULTI-COMMAND PROTOCOL - Techniques are generally described related to a multi-channel storage system. One example multi-channel storage system may include a plurality of memory-controllers, each memory-controller configured to control one or more storage units. The multi-channel storage system may further include a multi-channel interface having a plurality of input-output (IO) channels; and a channel-controller switch configured to support data communications between any one of the plurality of IO channels and any one of the plurality of memory-controllers. Upon receiving a request instructing using at least two of the plurality of IO channels and at least two of the plurality of memory-controllers, the multi-channel interface of the multi-channel storage system is configured to utilize the channel-controller switch to concurrently transfer data via the at least two of the plurality of IO channels or the at least two of the plurality of memory-controllers. | 05-15-2014 |
20140164673 | MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME - A memory controller connected with a storage medium via a plurality of channels is provided which includes a signal processing block including a plurality of signal processing engines; and a decoding scheduler configured to control a data path such that at least one activated signal processing engine of the plurality of signal processing engines is connected with the plurality of channels, respectively. | 06-12-2014 |
20140181357 | CROSSTALK AWARE ENCODING FOR A DATA BUS - Techniques for encoding data are described herein. An example of a device in accordance with the present techniques includes a signaling module coupled to a plurality of digital inputs. The signaling module is to encode data received at the plurality of digital inputs to generate encoded data. Based on the encoded data, the signaling module can drive line voltages on a plurality of signal lines of a bus. Each one of the plurality of line voltages corresponds to a weighted sum of the data received at the plurality of digital inputs. | 06-26-2014 |
20140181358 | CROSSTALK AWARE DECODING FOR A DATA BUS - Techniques for decoding encoded data are described herein. An example of a device in accordance with the present techniques includes a signaling module with a receiver, quantizer, and arithmetic circuit. The receiver receives a plurality of encoded line voltages or currents on a plurality of signal lines. The quantizer determines signal levels of each of the plurality of signal lines at a unit interval. The arithmetic circuit provides a plurality of digital output bits of the decoder based on the signal levels. Each one of the digital output bits is a mathematical combination of all of the signal levels. | 06-26-2014 |
20140189190 | MECHANISM FOR FACILITATING DYNAMIC CANCELLATION OF SIGNAL CROSSTALK IN DIFFERENTIAL INPUT/OUTPUT CHANNELS - A mechanism is described for facilitating dynamic cancellation of signal crosstalk in input/output differential channels according to one embodiment. A method of embodiments may include detecting crosstalk between a first differential signal channel pair (“differential pair”) and a second differential pair of a plurality of differential pairs at a computing system, and switching polarity relating to the first transmission links of the first differential pair to cancel out the crosstalk with the second differential pair. | 07-03-2014 |
20140244890 | CABLE, USER APPARATUS CONNECTED WITH CABLE, AND OPERATING METHOD THEREOF - A method, electronic device apparatus and a cable apparatus for reducing crosstalk in a signal transmitted to an electronic device through the cable apparatus are disclosed. The cable apparatus has a plurality of signal lines. The device and method may determine a relevant communication scheme, activate the relevant communication scheme by electrically coupling at least one of the plurality of signal lines of the cable apparatus correlating to the activated relevant communication scheme. At least one of the plurality of signal lines of the cable apparatus not correlating to the activated relevant communication scheme is electrically grounded. | 08-28-2014 |
20140281112 | METHOD AND APPARATUS FOR DYNAMIC POWER SAVING WITH FLEXIBLE GATING IN A CROSS-BAR ARCHITECTURE - Various aspects of dynamic power reduction in a bus communication architecture are described herein as embodied in an XBAR architecture that provides flexible gating of multiple paths and repeater circuitry to allow any of a number of selected clients to communicate with any of the other interconnected clients while reducing dynamic power consumption by disabling unused repeater circuitry in the bus communication architecture. | 09-18-2014 |
20140281113 | HOST INTERFACE CROSSBAR FOR SENSOR HUB - A microcontroller for a peripheral hub includes a plurality of host bus interface microdrivers and a corresponding plurality of host transports. A first manager client, associated with a supported peripheral device, processes messages from a first host. A host manager module routes asynchronous communications, including but not limited to HID input reports, from a client to a host via one of a plurality of supported transports via a targeted transport indicated in the communication. The host manager modules routes synchronous communications from a host to a client via a targeted transport selected from a plurality of transports. | 09-18-2014 |
20140281114 | Memory Interface and Method of Interfacing Between Functional Entities - A data and signal interface for controlling the transfer of data and signals between a memory array and macro function such as that of a digital signal processor (DSP) core. In one embodiment, the interface comprises a plurality of memory ports which interface with X/Y memory banks, a plurality of function ports, each with a function controller, which interface with DSP functions, a crossbar connecting the memory and function ports, and an arbitration unit for arbitrating memory access by the function ports. The memory interface advantageously allows multiple simultaneous accesses of memory banks via a plurality of macro functions, each access under the control of a parent processor instruction. A standardized protocol used for memory read/write operations is also disclosed. | 09-18-2014 |
20140289445 | HARDWARE ACCELERATOR SYSTEM AND METHOD - There is provided a hardware accelerator system and method. The system and method relate to a low power scalable stream compute accelerator for general matrix multiply (GEMM). There is provided a systolic compute accelerator architecture for matrix operations. Further, the system may include an application specific engine. | 09-25-2014 |
20140344501 | NETWORK-ON-CHIP ARCHITECTURE FOR MULTI-PROCESSOR SOC DESIGNS - A system and method embodying some aspects for communicating between nodes in a network-on-chip are provided. The system comprises a microprocessing chip and a plurality of connection paths. The microprocessing chip comprises sixteen processing nodes disposed on the chip. The plurality of connection paths are configured such that each is at most three hops away front any other node. Each node also has connection paths to at most three other nodes. | 11-20-2014 |
20140359195 | CROSSBAR SWITCH, INFORMATION PROCESSING APPARATUS, AND INFORMATION PROCESSING APPARATUS CONTROL METHOD - A bus connecting ports of a crossbar switch in a ring form is provided, and the configuration information of registers in ports is transferred between ports via the bus and updated, and thus a wiring length of the bus connecting the registers is reduced. | 12-04-2014 |
20150019790 | COMMUNICATIONS CONTROL SYSTEM WITH A SERIAL COMMUNICATIONS INTERFACE AND A PARALLEL COMMUNICATIONS INTERFACE - A communications control system is disclosed that includes a serial communications interface and a parallel communications interface for coupling a plurality of input/output modules with a control module. The serial communications interface is configured for connecting the plurality of input/output modules to the control module in parallel to transmit information between the plurality of input/output modules and the control module, and the parallel communications interface is configured for separately connecting the plurality of input/output modules to the control module to transmit information between the plurality of input/output modules and the control module, and to transmit information between individual ones of the plurality of input/output modules. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch. | 01-15-2015 |
20150067229 | NUMA NODE PERIPHERAL SWITCH - Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address. The many-to-many and many-to-one peripheral switches forwards the transaction packets internally within the switch based on the destination address such that the packets are forwarded to a node via which the memory address can be accessed. The platform architectures may also be configured to support migration operations in response to failure or replacement of a node. | 03-05-2015 |
20150357010 | MEMORY DEVICE POWER MANAGERS AND METHODS - Memory devices and methods are described that include a stack of memory dies and an attached logic die. Method and devices described provide for power management of portions of a stack of memory dies. Additional devices, systems, and methods are disclosed. | 12-10-2015 |
20150370738 | Computer Processor Employing Split Crossbar Circuit For Operand Routing And Slot-Based Organization Of Functional Units - A computer processor including a plurality of functional units that performs operations that produce result operands at different characteristic latencies over multiple cycles. An interconnect network provides data paths for transfer of operand data between functional units. The interconnect network includes first and second crossbar parts. The first crossbar part is configured to route result operands produced with the lowest characteristic latency to any other functional unit. The second crossbar part is configured to route result operands with higher characteristic latency relative to the lowest characteristic latency to the first crossbar part where such result operands are in turn routed to any functional unit. In another aspect, the functional units can be organized as multiple slots where each slot can produce multiple result operands of different characteristic latencies in the same cycle, and wherein each slot employs separate result registers for each characteristic latency present on the slot. | 12-24-2015 |
20150370741 | Computing System Framework With Unified Storage, Processing, And Network Switching Fabrics Incorporating Network Switches And Method For Making And Using The Same - A system and method for making and using a computing system framework with unified storage, processing, and network switching fabrics are provided. Processing nodes, either physical or virtual, are associated with intra-module ports, inter-module ports, and local storage spaces. A plurality of processing nodes are linked through intra-module ports to form processing modules. A plurality of the processing modules are connected through inter-module ports to form the computing system. Network switch can be incorporated into intra-module or inter-module connections. Several inter-module connection schemes, which can be adapted to use with existing network packet routing algorithms, are disclosed. Each processing node needs only to keep track of the states of its directly connected neighbors, obviating the need for a high-speed connection to the rest processing nodes within the system. Dedicated network switching equipment can be flexibly employed and network capacity grows naturally as processing nodes are added. | 12-24-2015 |
20160004292 | MICROCONTROLLER WITH MULTIPLE POWER MODES - A microcontroller operable in a high power mode and a low power unit (LPU) run mode includes primary and LPU domains, primary and LPU mode controllers, and primary and LPU clock generator modules. The primary domain includes a first set of circuits and a first set of cores. The LPU domain includes second and third sets of circuits, a second set of cores, and a switching module. In the high power mode, the switching module connects the first and second sets of cores to at least one of the first, second and third sets of circuits, while in the LPU run mode, the switching module isolates the LPU domain from the primary domain and activates a small microcontroller system (SMS) that includes the LPU domain, the LPU mode controller and the LPU clock generator module. The SMS has further low power modes within the LPU run mode. | 01-07-2016 |
20160019172 | UTILIZATION OF SOLID STATE MEMORY DEVICES - Technologies are generally described for systems, devices and methods effective to utilize a solid state memory device. A memory device may include one or more input/output ports effective to receive data at, and facilitate transfer from, the memory device. The memory device may further include a memory controller. The memory controller may be effective to control access to data stored in the memory device. The memory device may further include two or more flash chips effective to store data in the memory device. The memory device may further include a crossbar switch. The crossbar switch may be coupled between the one or more input/output ports and the two or more flash chips. The crossbar switch may be effective to enable the one or more input/output ports to access the two or more flash chips through the memory controller. | 01-21-2016 |
20160085706 | Methods And Systems For Controlling Ordered Write Transactions To Multiple Devices Using Switch Point Networks - Ordered write transactions from requester devices to multiple target devices are controlled using switch point networks. The requester device and the multiple target devices for the write transactions are coupled to a network of interconnected switch points. Write requests are generated for a plurality of parcels associated with a block of data to be written. The write requests have a particular order associated with an order in which the parcels are to be written, and these write requests are provided to the switch point interconnection network in the particular order. At least one of the switch points is then used to control the flow of write requests to the multiple target devices such that the particular order is maintained. In one embodiment, the target devices are memory devices, and the particular order is based upon the AXI (Advanced eXtensible Interface) protocol. | 03-24-2016 |
20160170916 | COHERENT MEMORY INTERLEAVING WITH UNIFORM LATENCY | 06-16-2016 |
20160179728 | HIGH BANDWIDTH CORE TO NETWORK-ON-CHIP INTERFACE | 06-23-2016 |