Class / Patent application number | Description | Number of patent applications / Date published |
710309000 | Arbitration | 31 |
20080235428 | METHOD AND SYSTEM FOR DYNAMIC SWITCHING BETWEEN MULTIPLEXED INTERFACES - A bridge is disclosed. The bridge comprises a first interface having at least one multiplexed clock signal line. The multiplexed clock signal line outputs first and second control signals for respectively controlling the access to first and second devices coupled to the bridge. The bridge selectively outputs the first clock signal or the second clock signal to the multiplexed clock signal line to access the first device or the second device respectively. | 09-25-2008 |
20080244146 | AGGREGATION OF ERROR MESSAGING IN MULTIFUNCTION PCI EXPRESS DEVICES - A method of aggregating events in a PCIe (Peripheral Component Interconnect Express) multifunction device minimizes reported error messages, where several functions share a common PCIe interface logic. A predetermined number of function entities with logical gates, connected in daisy chain configuration, process incoming information, and a decision is made whether each function entity will generate a blocking control or a pass-through control. The error messages are aggregated across the function entities in a single clock cycle with the help of an error controller. The functions can be from IEEE 1394 interface, graphics display controller, sound card, PCIe switch, or PCIe to PCI bridge connection. Each function preferably has a different configuration and security level setting for error reporting and messaging. There may be a plurality of parallel daisy chains, and the PCIe device may include three layers namely, a physical layer, data link layer and transaction protocol layer (for error logging, reporting). | 10-02-2008 |
20090037635 | BUS ARBITRATION DEVICE - A bus arbitration device includes a top arbiter, and the hierarchical bus arbitration device also includes a first arbiter. The said first arbiter arbitrates the first kind of requests, wherein the first kind of requests relates to the first kind of master units. The said second arbiter arbitrates the second kind of requests different from the first kind of requests, wherein the second kind of requests relates to the second kind of master units different from the first kind of master units. Wherein the said first arbiter and the said second arbiter are downward respectively from the top arbiter to form the hierarchical bus arbitration structure. Bus arbitration efficiency increases by this bus arbitration device. | 02-05-2009 |
20090106474 | Multi-Host USB Device - A USB device may be simultaneously configured and accessed by two or more USB hosts. The USB device may include separate upstream ports and buffers for each host, and a multi-host capable device controller configured to respond to simultaneous USB requests received from more than one host. The USB device may maintain a dedicated address, configuration, and response information for each host. The USB device may include a shared USB function block, and a multi-host controller configured to establish concurrent respective USB connections between the shared USB function block and two or more USB hosts, to allow the two or more USB hosts to simultaneously configure the USB device for the shared USB function. The multi-host controller may be configured to receive and respond to simultaneous respective USB access requests for the shared USB function sent by the two or more USB hosts. | 04-23-2009 |
20090164691 | IO PROCESSOR - An IO processor includes an embedded central processing unit (CPU), a switch connected to the embedded CPU, an external CPU bus controller connected to the switch for optionally connecting to an external CPU, a first memory controller connected to the switch for connecting to a first memory, and a second memory controller connected to the switch for optionally connecting to a second memory. The IO processor may be connected to the external CPU, to the second memory, or be capable of connecting to external CPUs of different ranks, depending on the situation, so as to meet the cost considerations and the actual application requirements. | 06-25-2009 |
20090164692 | DATA TRANSFER APPARATUS WITH CONTROL OF BUSES TO OPTIMIZE DATA TRANSFER - A bus bridge is connected to a primary bus and a secondary bus, and relays data between a master and a target which are each connected to a different one of the primary and secondary buses. The bus bridge includes a primary bus interface, a secondary bus interface, a data FIFO, and a register block. The register block, which can be written by the master, includes two registers corresponding to the primary and secondary buses. Relay information showing the number of entries of data to be relayed from the target to the master is registered in a register corresponding to a bus to which the target is connected. In a read transaction, the primary bus interface or the secondary bus interface reads data from the target until data of the amount shown by the registered relay information is stored in the data FIFO. | 06-25-2009 |
20090216933 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR PIPELINE ARBITRATION - A method for pipeline arbitration including receiving a first request for a shared chip interface from a first pipeline, determining whether a response bus of the shared chip interface is needed by the first request, and if it is determined that the response bus is not needed by the first request, concluding that the first request needs just an address bus of the shared chip interface, arbitrating the first request with a second request for the shared chip interface received from a second pipeline for access to the address bus, sending the first request to the address bus if the first request wins the arbitration over the second request, and rejecting the first request if the second request wins the arbitration over the first request. A corresponding system and computer program product. | 08-27-2009 |
20090300257 | System and Method of Increasing Data Processing on a Diagnostic Tool - A method of processing J1850 requests using a scan tool having multiple processor systems is provided. The scan tool includes a first processor that processes data according to scan tool functions to assist with diagnosing and repairing a vehicle. A second processor receives data transmitted to the first processor and stores the data in a buffer. The second processor determines whether the data is complete to enable the first processor to make a determination regarding the data. | 12-03-2009 |
20090327569 | CONTROLLED FREQUENCY CORE PROCESSOR AND METHOD FOR STARTING-UP SAID CORE PROCESSOR IN A PROGRAMMED MANNER - Embodiments of the invention relate to a driven-frequency processor core. It comprises at least one processor, a non-volatile memory comprising a startup program, a bridge interconnecting buses linking the various components of said processor core, an interface component. The non-volatile memory comprises at least two frequency-related configurations each corresponding to an operating mode of the buses and/or of the components of said processor core. The non-volatile memory comprises an item of information which makes it possible to determine which operating mode should be used, said item of information being read by the interface component so as to determine the chosen mode. The interface component generates one or more clock signals, the frequency of said generated clock signals corresponding substantially to that described by the configuration of the chosen mode. The clock signals drive the buses and/or the components of said processor core. Embodiments of the invention also relate to a method for starting-up said processor core in a programmed mode. In particular, the invention is applied to processor cores embedded in aircraft. | 12-31-2009 |
20100005213 | Access Table Lookup for Bus Bridge - Cross-bar segment routing and access table address remapping functions are combined within a cross-bar of a system-on-a-chip. In this manner, address remapping may occur prior to segment routing. One or more access table caching registers may be included for each master port. The caching registers may allow for a rapid lookup of one or more access table entries associated with each master, as well as allow for the simultaneous lookup by multiple masters without adding ports to the access table. A segment identifier may be stored in the caching registers to indicate how to route a matching request to the appropriate slave segment. | 01-07-2010 |
20100115171 | MULTI-CHIP PROCESSOR - Provided is a multiprocessor configured by stacking a plurality of unit chips each having, at least, a processor core and a memory, and the unit chip has a configuration including: a plurality of processor cores; a plurality of memories; a construction controlling unit setting connection relations between the processor core and the memory and between the processor core and the outside of the chip; and a chip connecting unit transmitting transaction between the processor, the memory, or the construction controlling unit and another stacked unit chip to be connected. The chip connecting units are arranged so as to be rotationally symmetric to each other on side portions of the unit chip, so that any of the unit chips configured by stacking is rotationally connected. | 05-06-2010 |
20100306439 | DATA CHECK CIRCUIT - A data check circuit comprising: a request signal output circuit configured to output a request signal for requesting occupation of a bus to an arbitration circuit configured to arbitrate the occupation of the bus, when a CPU connected, as a bus master, with the bus for accessing a memory outputs an instruction signal for providing an instruction for starting detection of whether or not data stored in the memory is correct; a data acquisition circuit configured to acquire data stored in the memory through the bus, when the arbitration circuit outputs a permission signal for permitting the occupation of the bus based on the request signal; and a data processing circuit configured to perform processing for detecting whether or not the acquired data is correct, the acquired data acquired by the data acquisition circuit. | 12-02-2010 |
20110082961 | Sharing Data Crossbar for Reads and Writes in a Data Cache - The invention sets forth an L1 cache architecture that includes a crossbar unit configured to transmit data associated with both read data requests and write data requests. Data associated with read data requests is retrieved from a cache memory and transmitted to the client subsystems. Similarly, data associated with write data requests is transmitted from the client subsystems to the cache memory. To allow for the transmission of both read and write data on the crossbar unit, an arbiter is configured to schedule the crossbar unit transmissions as well and arbitrate between data requests received from the client subsystems. | 04-07-2011 |
20110179212 | Bus arbitration for sideband signals - Systems and methods of bus arbitration for sideband signals in a multichip system are disclosed. An exemplary method comprises packaging at least one sideband signal as a micropacket. The method also comprises holding the micropacket in an outgoing sideband register. The method also comprises monitoring a bus for a quiescent state, the bus having a plurality of links to other chips in the multichip system. The method also comprises issuing the micropacket from the outgoing sideband register if the bus is in a quiescent state. | 07-21-2011 |
20110185102 | BUS BRIDGE AND METHOD FOR INTERFACING OUT-OF-ORDER BUS AND MULTIPLE ORDERED BUSES - A method for interfacing an out-of-order bus and multiple ordered buses and a bus bridge. The bus bridge includes multiple ordered bus interfaces, where each ordered bus interface is coupled to an ordered bus. A flow control logic circuit is coupled to the out-of-order bus and to the multiple ordered bus interfaces. The flow control logic circuit controls a flow of transaction requests between the out-of-order bus and each of the ordered buses interfaces. The flow control logic circuit includes an updating circuit for updating dependency resolution attributes and data readiness attributes associated with transaction requests, and a shared memory unit for storing the dependency resolution attributes, the data readiness attributes and the transaction requests where the transaction requests are destined to the ordered buses. A managing circuit, coupled to the shared memory unit and to the multiple ordered bus interfaces, is used to determine a readiness of each transaction request based on a dependency resolution attribute and a data readiness attribute associated with the transaction request, and for managing a dequeueing of ready transaction requests to the ordered bus interfaces based on an availability of the ordered bus interfaces. | 07-28-2011 |
20110276739 | INTEGRATED MEMORY CONTROL APPARATUS - An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory. | 11-10-2011 |
20120079159 | Throttling Integrated Link - Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an Integrated Input/Output hub (e.g., integrated on the same die as a processor) causes throttling of a link coupled between the IIO and an Input/Output (IO) device. Other embodiments are also disclosed. | 03-29-2012 |
20120297106 | Method and System for Dynamically Managing a Bus of a Portable Computing Device - A method and system for dynamically managing a bus within a portable computing device (“PCD”) are described. The method and system include monitoring software requests with a bus manager. The bus manager determines if a software request needs to be converted into at least one of an instantaneous bandwidth value and an average bandwidth value. The bus manager then converts the software requests into these two types of values as needed. The bus manager calculates a sum of average bandwidth values across all software requests in the PCD. With these values, the bus manager may dynamically adjust settings of the bus based on instantaneous or near instantaneous demands from the master devices. This dynamic adjustment of the bus settings may afford more power savings for the PCD during low loads or during sleep states. | 11-22-2012 |
20130073773 | ACCESS CONTROL APPARATUS, IMAGE FORMING APPARATUS, AND ACCESS CONTROL METHOD - An access control apparatus includes an external bus control unit that controls an external bus for transmitting and receiving data to and from an external device. The external bus control unit includes: a plurality of storage units disposed corresponding to the external device for temporarily storing data from an internal bus; and an arbitration unit that selects a storage unit for transferring data to the external bus from the plurality of storage units in response to an access request from the internal bus and outputs the data stored in the selected storage unit to the external bus. | 03-21-2013 |
20130227191 | Image Forming Apparatus - An image forming apparatus according to the present disclosure includes: a first IC chip; a second IC chip connected to the first IC chip via a serial bus; and a memory that is either connected to or included in the first IC chip. The first IC chip includes: a first internal bus; a memory controller of the memory; a first processing circuit which outputs an access request to the memory; plural buffers corresponding to plural arbitration priority degrees of the first internal bus, and a request classifying circuit which identifies an arbitration priority degree of a requester of the access request received from the second IC chip and causes a buffer corresponding to the identified arbitration priority degree to buffer the access request. The first internal bus performs arbitration of access requests from the first processing circuit and the plural buffers in accordance with the arbitration priority degrees. | 08-29-2013 |
20130262733 | DISTRIBUTED REORDER BUFFERS - A Network-on-Chip (NoC) is provided that performs reordering of transaction responses such as those with requests that cross address mapping boundaries. Ordering is ensured by filtering logic in reorder buffers, some of which include storage to allow multiple simultaneously pending transactions. Transactions are transported by a packet-based transport protocol. The reorder buffering is done at packet level, within the transport topology. Reorder buffers are distributed physically throughout the floorplan of the chip, they have localized connectivity to initiators, and they operate in separate power and clock domains. | 10-03-2013 |
20130275647 | PCIE SMBUS SLAVE ADDRESS SELF-SELECTION - Embodiments of the invention describe an apparatus, system and method for slave devices to “self-select” their own Inter-Integrated Circuit/System Management Bus (I2C/SMBus) slave addresses upon initialization. Embodiments of the invention describe logic/modules to retrieve a first SMBus slave address included in non-volatile memory for a slave device, wherein said slave device is communicatively coupled to a host system via an SMBus. A first message (e.g., a ping) is transmitted to the first SMBus slave address via the SMBus. If a response to the first message is not received, the first SMBus slave address is selected for the slave device. If a response to the first message is received, the first SMBus slave address is changed by an offset value to determine a second SMBus slave address for transmitting a second message via the SMBus. | 10-17-2013 |
20140032808 | INTEGRATED CIRCUIT HAVING A BUS NETWORK, AND METHOD FOR THE INTEGRATED CIRCUIT - A bus network passes pending messages from bus interface to bus interface until they are downloaded at a target bus interface by a target device connected to the target bus interface. The messages are tagged with at least one download control bit. The download control bit has a priority state indicating that a message has already passed the target bus interface at least once without being downloaded. When controlling selection of messages for downloading by the target device, the target bus interface selects messages with the download control bit in the priority state with a greater probability than messages not having a download control bit in the priority state. | 01-30-2014 |
20140215116 | MULTI-BUS SYSTEM - A multi-bus system includes a first layer bus, a second layer bus connected to the first layer bus, at least one master device, and a decoder. The at least one master device is configured to be connected to the first layer bus via a first data path, and configured to be connected to the second layer bus via a second data path. The decoder is configured to directly connect the at least one master device to the first layer bus via the first data path, and directly connect the at least one master device to the second layer bus via the second data path. | 07-31-2014 |
20140310444 | DYNAMIC BALANCING OF BUS BANDWIDTH ACROSS MULTIPLE ROUTES - A method includes receiving feedback information indicative of an overload condition from an arbiter. The method further includes deprioritizing a routing bus based on the received feedback information and selecting a routing bus to use to send a transaction across a system-on-chip (SOC). | 10-16-2014 |
20150052283 | INTERFACE APPARATUS AND MEMORY BUS SYSTEM - An exemplary interface apparatus according to the present disclosure connects together an initiator and a packet exchange type bus network formed on the integrated circuit. In the bus network, if the initiator has submitted request data with a deadline time specified, the initiator receives, by the deadline time, response data to be issued by a node in response to the request data. The interface apparatus includes: a correcting circuit which corrects the deadline time of the request data according to the timing when the request data has been submitted, thereby generating corrected deadline time information; a header generator which generates a packet header that stores the corrected deadline time information; and a packetizing processor which generates a request packet based on the request data and the packet header. | 02-19-2015 |
20150067226 | BACKPLANE CONTROLLER TO ARBITRATE MULTIPLEXING OF COMMUNICATION - A backplane controller to couple to a carrier interface and a plurality of host controllers of different types. The backplane controller is to identify a host controller corresponding to a type of a storage device of a storage device carrier. The storage device carrier is to interface with the carrier interface. The backplane controller is to arbitrate multiplexing of communication between the carrier interface and the identified host controller. | 03-05-2015 |
20160055111 | USING A CREDITS AVAILABLE VALUE IN DETERMINING WHETHER TO ISSUE A PPI ALLOCATION REQUEST TO A PACKET ENGINE - In response to receiving a novel “Return Available PPI Credits” command from a credit-aware device, a packet engine sends a “Credit To Be Returned” (CTBR) value it maintains for that device back to the credit-aware device, and zeroes out its stored CTBR value. The credit-aware device adds the credits returned to a “Credits Available” value it maintains. The credit-aware device uses the “Credits Available” value to determine whether it can issue a PPI allocation request. The “Return Available PPI Credits” command does not result in any PPI allocation or de-allocation. In another novel aspect, the credit-aware device is permitted to issue one PPI allocation request to the packet engine when its recorded “Credits Available” value is zero or negative. If the PPI allocation request cannot be granted, then it is buffered in the packet engine, and is resubmitted within the packet engine, until the packet engine makes the PPI allocation. | 02-25-2016 |
20160077984 | MECHANISM FOR MANAGING ACCESS TO AT LEAST ONE SHARED INTEGRATED PERIPHERAL OF A PROCESSING UNIT AND A METHOD OF OPERATING THEREOF - The present application relates to a mechanism for managing access to at least one shared integrated peripheral of a processing unit and a method of operating thereof. The mechanism is operative in an available state and a locked state. The mechanism comprises at least one context register and a bus interface for receiving a request. A filtering unit obtains information relating to a context of the received request. If in the available state, a managing unit loads the context register with the obtained context information; and grants access in response to the received request. If in the locked state, the managing unit detects whether the obtained context information matches with the context information stored in the context register; and if the obtained and stored context information match, grants access in response to the received request. Otherwise, access is denied. | 03-17-2016 |
20160103772 | SIDE CHANNEL ACCESS THROUGH USB STREAMS - A system may provide side channel access of a Universal Serial Bus (USB) device using USB streams. The system may include a USB interface with a USB device controller, an internal bus, a logical unit number (LUN) arbiter coupled between the USB controller and the internal bus, and a secondary interface coupled with the LUN arbiter. The system may include a plurality of storage devices coupled to the internal bus. The system may provide access to the storage devices via both the USB device controller and the secondary interface. The LUN arbiter may accept a plurality of USB streams (e.g., storage device access requests) from the USB device controller and at least one additional USB stream (e.g., storage device access request) from the secondary interface. The LUN arbiter may determine a priority of access between USB streams originating from the USB device controller and the secondary interface. | 04-14-2016 |
20160140071 | Arbitrated Access To Resources Among Multiple Devices - An arbiter circuit manages and enforces arbitration and quality of service (QOS) among multiple devices accessing a resource, such as a memory. The arbiter circuit receives requests from a number of devices to use resources of a bridge connecting to a memory, and maintains a count of bridge resources available on a per-device and per-bus basis. The arbiter circuit operates to select a next one of the requests to grant a bridge resource based on the device originating the request, a count of the per-device resources available, and a count of the resources available to the bus connecting the device to the bridge. | 05-19-2016 |