Class / Patent application number | Description | Number of patent applications / Date published |
710111000 | Rotational prioritizing (i.e., round robin) | 12 |
20100082864 | SELECTION CIRCUIT AND PACKET PROCESSING APPARATUS - An aspect of the embodiment utilizes a selection circuit that includes a first storage circuit for storing information of m×n bits each corresponding to a choice. The storage circuit indicates whether the corresponding choice is in a selectable state or not. A first round robin circuit for executing a round robin process on the second storage circuit selects one of the bits contained in the corresponding bit string and indicates that a choice is in a selectable state. A second round robin circuit executes the round robin process on the bit string having the m-bit width to select one of the bits indicating that the corresponding choice, and a control circuit controls the first and the second round robin circuit. | 04-01-2010 |
20100146177 | NEGATION-BASED ROUND-ROBIN ARBITER - A device includes an M-bit input request for service bus, a MASKGEN component that generates a shifting mask, the MASK component that generates an 2*M-bit enabled request for service bus, a NEGATE component that may perform a negation operation on the MASK 2*M-bit enabled request for service output, and a COMBINE component which receives the MASK 2*M-bit enabled request for service output and 2*M-bit NEGATE output and combines them into M-bit 1-HOT grant output bus. The COMBINE output indicates which request for service is being granted by the device. | 06-10-2010 |
20110125946 | Arbitrated Access To Memory Shared By A Processor And A Data Flow - Memory access arbitration allowing a shared memory to be used both as a memory for a processor and as a buffer for data flows, including an arbiter unit that makes assignment for access requests to the memory sequentially and transfers blocks of data in one round-robin cycle according to bandwidths required for the data transfers, sets priorities for the transfer blocks so that the bandwidths required for the data transfers are met by alternate transfer of the transfer blocks, and executes an access from the processor with an upper limit set for the number of access times from the processor to the memory in one round-robin cycle so that the access from the processor with the highest priority and with a predetermined transfer length exerts less effect on bandwidths for data flow transfers in predetermined intervals between the transfer blocks. | 05-26-2011 |
20110320659 | DYNAMIC MULTI-LEVEL CACHE INCLUDING RESOURCE ACCESS FAIRNESS SCHEME - An apparatus for controlling access to a resource includes a shared pipeline configured to communicate with the resource, a plurality of command queues configured to form instructions for the shared pipeline and an arbiter coupled between the shared pipeline and the plurality of command queues configured to grant access to the shared pipeline to a one of the plurality of command queues based on a first priority scheme in a first operating mode. The apparatus also includes interface logic coupled to the arbiter and configured to determine that contention for access to the resource exists among the plurality of command queues and to cause the arbiter to grant access to the shared pipeline based on a second priority scheme in second operating mode. | 12-29-2011 |
20120173781 | ROUND ROBIN ARBITER WITH MASK AND RESET MASK - In order to provide a solution for performing priority arbitration, a mask and reset-mask are generated in concert with a priority arbitration scheme. A plurality of requestors may issue requests for a shared resource. The priority arbitration scheme may grant access to a single requestor for a single priority assignment period. The mask may assist the priority arbitration scheme to assign priority to the plurality of requestors by temporarily removing a subset of the plurality of requestors for a particular priority assignment period. If the mask allows for no allowable requestors during the priority assignment period, a reset-mask scheme is implemented to reset the mask to permit an increased number of requestors access to the priority arbitration scheme. | 07-05-2012 |
20120203946 | LIVELOCK PREVENTION MECHANISM IN A RING SHAPED INTERCONNECT UTILIZING ROUND ROBIN SAMPLING - A novel and useful cost effective mechanism for detecting the livelock/starvation of transactions in a ring shaped interconnect that utilizes minimal logic resources. Rather than monitor all transactions concurrently in the ring, the mechanism monitors only a single transaction in the ring. A sampling point is located at a point in the ring which contains a set of N latches. If the monitored transaction is not being starved, it is released and the detection logic moves on the next candidate transaction in round robin fashion. If the monitored transaction passes the sampling point a threshold number of times, it is deemed to be starved and a starvation prevention handling procedure is activated. By traversing the entire ring a single transaction at a time, all starving transactions will eventually be detected with an upper limit on the detection time of O(N | 08-09-2012 |
20130124767 | INTEGRATED CIRCUIT HAVING A BUS NETWORK, AND METHOD FOR THE INTEGRATED CIRCUIT - A bus network passes pending messages from bus interface to bus interface until they are downloaded at a target bus interface by a target device connected to the target bus interface. The messages are tagged with at least one download control bit. The download control bit has a priority state indicating that a message has already passed the target bus interface at least once without being downloaded. When controlling selection of messages for downloading by the target device, the target bus interface selects messages with the download control bit in the priority state with a greater probability than messages not having a download control bit in the priority state. | 05-16-2013 |
20140129749 | DYNAMIC SHARED READ BUFFER MANAGEMENT - A structure and method of allocating read buffers among multiple bus agents requesting read access in a multi-processor computer system. The number of outstanding reads a requestor may have based on the current function it is executing is dynamically limited, instead of based on local buffer space available or a fixed allocation, which improves the overall bandwidth of the requestors sharing the buffers. A requesting bus agent may control when read data may be returned from shared buffers to minimize the amount of local buffer space allocated for each requesting agent, while maintaining high bandwidth output for local buffers. Requests can be made for virtual buffers by oversubscribing the physical buffers and controlling the return of read data to the buffers. | 05-08-2014 |
20140372648 | MULTI MASTER ARBITRATION SCHEME IN A SYSTEM ON CHIP - A multi master system on chip (SoC) includes a plurality of masters comprising a first master and a second master, each configured to generate a request. A next state generator in the multi master SoC is configured to generate a next state of a round robin pointer in response to the request and a current state of the round robin pointer. The round robin pointer is configured to generate an enable signal to enable a priority encoder for the first master in response to the current state of the round robin pointer. Further, the next state of the round robin pointer is generated such that a priority is maintained for the first master until there is a request from the second master. | 12-18-2014 |
20150127863 | MAINTAINING I/O PRIORITY AND I/O SORTING - Multiple variants of a data processing system, which maintains I/O priority from the time a process makes an I/O request until the hardware services that request, will be described. In one embodiment, a data processing system has one or more processors having one or more processor cores, which execute an operating system and one or more applications of the data processing system. The data processing system also can have one or more non-volatile memory device coupled to the one or more processors to store data of the data processing system, and one or more non-volatile memory controller coupled to the one or more processors. The one or more non-volatile memory controller enables a transfer of data to at least one non-volatile memory device, and the priority level assigned by the operating system is maintained throughout the logical data path of the data processing system. | 05-07-2015 |
20160103777 | MEMORY AGGREGATION DEVICE - The invention relates to a memory aggregation device for storing a set of input data streams and retrieving data to a set of output data streams, the memory aggregation device comprising: a set of first-in first-out (FIFO) memories each comprising an input and an output; an input interconnector configured to interconnect each one of the set of input data streams to each input of the set of FIFO memories according to an input interconnection matrix; an output interconnector configured to interconnect each output of the set of FIFO memories to each one of the set of output data streams according to an output interconnection matrix; an input selector; an output selector; and a memory controller. | 04-14-2016 |
20160162425 | ASSOCIATING PROCESS PRIORITY WITH I/O QUEUING - Described herein is a system and method for associating process priority with I/O queuing. The system can receive a first I/O request from a first process; store the first I/O request in an I/O queue; receive a second I/O request from a second process; store the second I/O request in the I/O queue; and sort the I/O queue based, at least in part, on a first priority of the first process and a second priority of the second process. | 06-09-2016 |