# Division

## Subclass of:

## 708 - Electrical computers: arithmetic processing and calculating

## 708100000 - ELECTRICAL DIGITAL CALCULATING COMPUTER

## 708200000 - Particular function performed

## 708490000 - Arithmetical operation

### Patent class list (only not empty are listed)

#### Deeper subclasses:

Class / Patent application number | Description | Number of patent applications / Date published |
---|---|---|

708650000 | Division | 31 |

20100332578 | Method and apparatus for performing efficient side-channel attack resistant reduction - A time-invariant method and apparatus for performing modular reduction that is protected against cache-based and branch-based attacks is provided. The modular reduction technique adds no performance penalty and is side-channel resistant. The side-channel resistance is provided through the use of lazy evaluation of carry bits, elimination of data-dependent branches and use of even cache accesses for all memory references. | 12-30-2010 |

20120066283 | DIVIDER AND METHOD OF OPERATING THE SAME - Provided are a divider having a small area and an improved operation speed and a method of operating the same. The divider includes a memory, a controller, and a multiplier. The memory is configured to store table values included in a predetermined range. The controller is configured to receive a divisor, generate an address expressed in a plurality of bits according to the bits except the most significant bit of the divisor, and receive the table value corresponding to the address from the memory. The multiplier is configured to receive a dividend and calculate an initial value by multiplying the dividend and the table value corresponding to the address. Herein, the controller determines an exponent of the divisor and right-shifts the initial value by the exponent of the divisor. | 03-15-2012 |

20110060786 | DEVICE FOR COMPUTING QUOTIENTS, FOR EXAMPLE FOR CONVERTING LOGICAL ADDRESSES INTO PHYSICAL ADDRESSES - A device for calculating the quotient q and remainder r of the division (y·k | 03-10-2011 |

20090248780 | Polynomial data processing operation - A data processing system | 10-01-2009 |

20100185716 | EIGENVALUE DECOMPOSITION APPARATUS AND EIGENVALUE DECOMPOSITION METHOD - The present invention provides an eigenvalue decomposition apparatus that can perform processing in parallel at high speed and high accuracy. The eigenvalue decomposition apparatus comprises a matrix dividing portion | 07-22-2010 |

20120131082 | COMPUTATION OF A REMAINDER BY DIVISION USING PSEUDO-REMAINDERS - Methods, computer systems, and computer program products for calculating a remainder by division of a sequence of bytes interpreted as a first number by a second number is provided. A pseudo-remainder by division associated with a first subsequence of the sequence of bytes is calculated. A property of this pseudo-remainder is that the first subsequence of the sequence of bytes, interpreted as a third number, and the pseudo-remainder by division have the same remainder by division when divided by the second number. A second subsequence of the sequence of bytes interpreted as the first number is appended to the pseudo-remainder, interpreted as a sequence of bytes, so as to create a sequence of bytes interpreted as a fourth number. The first number and the fourth number have the same remainder by division when divided by the second number. | 05-24-2012 |

20120166512 | High speed design for division & modulo operations - Techniques for efficiently performing division and modulo operations in a programmable logic device. In one set of embodiments, the division and modulo operations are synthesized as one or more alternative arithmetic operations, such as multiplication and/or subtraction operations. The alternative arithmetic operations are then implemented using dedicated digital signal processing (DSP) resources, rather than non-dedicated logic resources, resident on a programmable logic device. In one embodiment, the programmable logic device is a field-programmable gate array (FPGA), and the dedicated DSP resources are pre-fabricated on the FPGA. Embodiments of the present invention may be used in Ethernet-based network devices to support the high-speed packet processing necessary for 100G Ethernet, 32-port (or greater) trunking, 32-port/path (or greater) load balancing (such as 32-path ECMP), and the like. | 06-28-2012 |

20140222884 | OPTIMIZING FIXED POINT DIVIDE - Systems, apparatus and methods are described related to optimizing fixed point divide. | 08-07-2014 |

20130103733 | METHOD AND APPARATUS FOR USE IN THE DESIGN AND MANUFACTURE OF INTEGRATED CIRCUITS - A method and apparatus are provided for manufacturing integrated circuits performing invariant integer division x/d. A desired rounding mode is provided and an integer triple (a,b,k) for this rounding mode is derived. Furthermore, a set of conditions for the rounding mode is derived. An RTL representation is then derived using the integer triple. From this a hardware layout can be derived and an integrated circuit manufactured with the derived hardware layout. When the integer triple is derived a minimum value of k for the desired rounding mode and set of conditions is also derived. | 04-25-2013 |

20130173683 | Range Check Based Lookup Tables - Mechanisms for utilizing a reduced lookup table circuit to perform an operation in a data processing device are provided. A first input value is input for selecting a subset of values from the reduced lookup table circuit. The reduced lookup table circuit stores only boundary cell values from a fully filled lookup table corresponding to the reduced lookup table circuit. The subset of values comprises only a subset of boundary cell values corresponding to the first input value. A second value is input and a comparison, by the reduced lookup table circuit, of the second value to each of the boundary cell values in the subset of boundary cell values is performed. The reduced lookup table circuit outputs an output value based on results of the comparison of the second value to each of the boundary cell values in the subset of boundary cell values. | 07-04-2013 |

20110295921 | Hybrid Greatest Common Divisor Calculator for Polynomials - A hybrid greatest common divisor (GCD) calculator analyzes characteristics of polynomials and selects a particular GCD algorithm from multiple available GCD algorithms based on a combination of characteristics of the polynomials. The selected GCD algorithm is then applied to calculate the GCD of the polynomials. | 12-01-2011 |

20120254276 | COMPLEX DIVIDER AND ASSOCIATED METHOD - A complex divider utilized for dividing a first complex number by a second complex number to generate a computing result includes a computing unit and a dividing unit. The computing unit is utilized for receiving the first complex value and the second complex value, generating a third complex value according to the first complex value and the second complex value, and generating a real number according to the second complex value. The dividing unit is coupled to the computing unit, and is utilized for receiving the third complex value and the real number and dividing the third complex value by the real number to obtain the computing result. | 10-04-2012 |

20140059106 | ARITHMETIC CIRCUIT FOR PERFORMING DIVISION BASED ON RESTORING DIVISION - An arithmetic circuit for performing division based on restoring division includes an intermediate remainder register configured to store an intermediate remainder, a quotient prediction circuit configured to perform, based on information about two most significant digits of the intermediate remainder and a most significant digit of a divisor, quotient prediction having lower precision than a highest precision obtainable from the information, thereby generating a prediction result, a fixed-value multiplication circuit configured to output one or more N-th (N: integer) multiples of the divisor selected in response to the prediction result, one or more subtracters configured to subtract, from the intermediate remainder, the one or more N-th multiples of the divisor output from the fixed-value multiplication circuit, and a partial quotient calculating circuit configured to obtain a partial quotient in response to one or more carry-out bits of one or more subtractions performed by the one or more subtracters. | 02-27-2014 |

20120259907 | PIPELINED DIVIDE CIRCUIT FOR SMALL OPERAND SIZES - A pipelined circuit for performing a divide operation on small operand sizes. The circuit includes a plurality of stages connected together in a series to perform a subtractive divide algorithm based on iterative subtractions and shifts. Each stage computes two quotient bits and outputs a partial remainder value to the next stage in the series. The first and last stages utilize a radix-4 serial architecture with edge modifications to increase efficiency. The intermediate stages utilize a radix-4 parallel architecture. The divide architecture is pipelined such that input operands can be applied to the divider on each clock cycle. | 10-11-2012 |

20140089372 | Divider Logic Circuit and Implement Method Therefor - A divider logic circuit for obtaining a quotient S of a dividend M divided by a divisor N, includes a first constant value input terminal, a first adder, a second constant value input terminal, a base number input terminal, at least one integer power device, at least one right shift register, a second adder, and a multiplier; wherein the integer power device determines a first constant value that the base number is N | 03-27-2014 |

20080222230 | Multiplier-divider having error offset function - A multiplier-divider capable of offsetting errors includes a plurality of multiplication and division units to perform processes and arrangements so that errors generated by signals passing through the multiplier-divider are offset. As a result impact of the errors is reduced. More than one processing signal can be obtained from the same power supply to reduce loss of external sampling. | 09-11-2008 |

20080208947 | METHOD AND APPRATUS FOR EVALUATING VISITORS TO A WEB SERVER - Different web pages on a web server are associated with different qualification profiles, each of which is assigned a value by the web-site proprietor. Traffic data hits at the web-site are analyzed to determine which web pages the visitor viewed on the web server. Each qualifying visitor is thereafter associated with a qualification profile and a corresponding value. In another aspect of the invention, visitors arriving as a result of an advertisement on a remote web-site are tracked. The web-site proprietor is consequently able to determine a return on advertising investment based on the value of visitors brought to the site by the tracked advertisement. | 08-28-2008 |

20090216825 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR DETECTING ERRORS IN FIXED POINT DIVISION OPERATION RESULTS - A method, computer program product and a system for detecting errors in a result of a fixed-point division operation are provided. The method includes: receiving a result of a fixed-point division operation for a dividend and a divisor; performing a first comparison of the divisor and a remainder of the result; performing a second comparison of a sign of the dividend and a sign of the remainder; and determining whether the result is correct based on the first comparison and the second comparison. | 08-27-2009 |

20160147503 | DATA PROCESSING APPARATUS HAVING COMBINED DIVIDE-SQUARE ROOT CIRCUITRY - A processing apparatus has combined divide-square root circuitry for performing a radix-N SRT divide algorithm and a radix-N SRT square root algorithm, where N is an integer power-of-2. The combined circuitry has shared remainder updating circuitry which performs remainder updates for a greater number of iterations per cycle for the SRT divide algorithm than for the SRT square root algorithm. This allows reduced circuit area while avoiding the SRT square root algorithm compromising the performance of the SRT divide algorithm. | 05-26-2016 |

708651000 | Decimal | 1 |

20090193066 | COMMUNICATION APPARATUS, METHOD OF CHECKING RECEIVED DATA SIZE, MULTIPLE DETERMINING CIRCUIT, AND MULTIPLE DETERMINATION METHOD - A dividing unit sets an actual packet length transferred from a packet receiving section to a variable U, and then sets 2 | 07-30-2009 |

708653000 | Binary | 11 |

20140195581 | FIXED POINT DIVISION CIRCUIT UTILIZING FLOATING POINT ARCHITECTURE - A system, method, and computer program product for dividing two binary numbers. The divider implements a fixed point division function using a floating point normalization architecture to yield the closest initial quotient approximation. The divider normalizes the input dividend and divisor to a range of [0.5, 1.0) by scaling each by necessary factors of two. The normalized inputs are submitted to a divider core that may be optimized for dividing inputs of such limited ranges. The divider core output is then rescaled by an appropriate factor of two, appropriately signed, and loaded into saturating registers for output in various formats. The divider core progressively outputs quotient bits in decreasing order of significance until a predetermined level of precision is reached, typically fewer bits than in a complete quotient, for faster output. One embodiment generates the six most significant quotient bits in one clock cycle. | 07-10-2014 |

20130275484 | DIVISION CIRCUIT AND MEMORY CONTROLLER - A separation circuit separates a 32-bit dividend, (e.g., 1695) into 4-bit segments and outputs 9 separated dividends. The position of each dividend counted from the dividend having the lowest bit is i. A first output circuit concatenates at the end of a dividend, 0s of number equal to an integer multiple of 4 bits. Each calculation circuit outputs an 8-bit quotient, a numerical value created by the first output circuit divided by 3(=2 | 10-17-2013 |

20120158812 | PARALLEL COMPUTATION OF A REMAINDER BY DIVISION OF A SEQUENCE OF BYTES - Methods, computer systems, and computer program products for calculating a remainder by division of a sequence of bytes interpreted as a first number by a second number are provided. A first remainder by division associated with a first subset of the sequence of bytes is calculated with a first processor. A second remainder by division associated with a second subset of the sequence of bytes is calculated with a second processor. The calculating of the second remainder by division may occur at least partially during the calculating of the first remainder by division. A third remainder by division is calculated based on the calculating of the first remainder by division and the calculating of the second remainder by division. | 06-21-2012 |

20130124594 | DIVIDER CIRCUITRY WITH QUOTIENT PREDICTION BASED ON ESTIMATED PARTIAL REMAINDER - An integrated circuit comprises divider circuitry configured to perform a division operation. The divider circuitry may be part of an arithmetic logic unit or other computational unit of a microprocessor, digital signal processor, or other type of processor. The divider circuitry iteratively determines bits of a quotient over multiple stages of computation. In determining the quotient in one embodiment, the divider circuitry is configured to estimate a partial remainder for a given one of the stages and to predict one or more of the quotient bits for one or more subsequent stages based on the estimated partial remainder so as to allow one or more computations to be skipped for said one or more subsequent stages, thereby reducing power consumption. The integrated circuit may be incorporated in a computer, a mobile telephone, a storage device or other type of processing device. | 05-16-2013 |

20150363170 | CALCULATION OF A NUMBER OF ITERATIONS - Performing an arithmetic operation in a data processing unit, including calculating a number of iterations for performing the arithmetic operation with a given number of bits per iteration. The number of bits per iteration is a positive natural number. A number of consecutive digit positions of a digit in a sequence of bits represented in the data processing unit is counted. The length of the sequence is a multiple of the number of bits per iteration. A quotient of the number of consecutive digit positions divided by the number of bits per iteration is calculated, as well as a remainder of the division. | 12-17-2015 |

20120271873 | PARALLEL COMPUTATION OF A REMAINDER BY DIVISION OF A SEQUENCE OF BYTES - A remainder by division of a sequence of bytes interpreted as a first number by a second number is calculated. A first remainder by division associated with a first subset of the sequence of bytes is calculated with a first processor. A second remainder by division associated with a second subset of the sequence of bytes is calculated with a second processor. The calculating of the second remainder by division may occur at least partially during the calculating of the first remainder by division. A third remainder by division is calculated based on the calculating of the first remainder by division and the calculating of the second remainder by division. | 10-25-2012 |

20140122556 | INTEGER DIVIDER MODULE - A method includes receiving a dividend and a divisor for performing a division operation. Numbers p and n are found, for which the divisor equals 2 | 05-01-2014 |

20090157791 | FLEXIBLE ACCUMULATOR FOR RATIONAL DIVISION - A system and method are provided for rational division. The method accepts accepting a binary numerator and a binary denominator. A binary first sum is created of the numerator and a binary first count from a previous cycle. A binary first difference is created between the first sum and the denominator. In response to comparing the first sum with the denominator, and first carry bit is generated and added to a first binary sequence. The first binary sequence is used to generate a k-bit quotient. Typically, the denominator value is larger than the numerator value. In one aspect, the numerator and denominator form a rational number. Alternately, the numerator may be an n-bit bit value formed as either a repeating or non-repeating sequence, and the denominator is an (n+1)-bit number with a decimal value of 2 | 06-18-2009 |

20090172069 | METHOD AND APPARATUS FOR INTEGER DIVISION - The invention provides a method, arithmetic divider unit, and system for dividing a dividend D | 07-02-2009 |

708654000 | Multiplication by reciprocal | 1 |

20110099217 | Method and System for Determining a Quotient Value - A method for determining a quotient value from a dividend value and a divisor value in a digital processing circuit is provided. The method includes computing a reciprocal value of the divisor value and multiplying the reciprocal value by the dividend value to obtain a reciprocal product, the reciprocal product having an integer part. The method also includes computing an intermediate remainder value by computing a product of the integer part and the divisor value, and subtracting the resulting product from the dividend value and determining the quotient value based upon the intermediate remainder value. | 04-28-2011 |

708655000 | Repeated subtraction | 1 |

708656000 | Multiples of divisor | 1 |

20080307032 | Divider Circuit - A divider circuit for dividing a dividend by a divisor, includes: a multiplicative divisor generating circuit configured to generate 2 | 12-11-2008 |