Class / Patent application number | Description | Number of patent applications / Date published |
708517000 | Logarithmic format | 10 |
20080208946 | Method Of Data Analysis - A method of analysis of incomplete data sets to detect fraudulent data is disclosed. The method comprises computing constant values for various leading digit sequence lengths, computing artificial Benford frequencies for the digit sequence lengths, computing a standard deviation for each of the sequence lengths, and flagging any digit sequences in the data set that deviate more than an upper bound number of standard deviations from the artificial Benford frequencies, the upper bound used to determine if the observed data deviates enough to be considered anomalous and potentially indicative of fraud or abuse. | 08-28-2008 |
20090164545 | Electronic Circuitry and Method for Determination of Amplitudes of Received Signals - A method and a calculating circuit for generating an output signal representing an actual amplitude of a received digitized signal having a magnitude of the actual amplitude equal or greater than a value of a saturation level of a dynamic range of a receiver. For the determination of the actual amplitude, firstly, a predetermined time interval is selected. Then, a total number of samples of the received digitized signal within the predetermined time interval is calculated. Further, a number of samples of the received digitized signal within the predetermined time interval with the amplitude equal to the saturation level is calculated. Thereafter, a ratio between the number of the samples with the amplitude value equal to the saturation level and the total number of the samples is calculated. For calculation of the magnitude of the actual amplitude a predetermined relationship between the magnitude of the amplitude and the ratio is applied and the output signal representing the actual amplitude is provided. | 06-25-2009 |
20120011186 | METHOD FOR QUANTIFYING AND ANALYZING INTRINSIC PARALLELISM OF AN ALGORITHM - A method for quantifying and analyzing intrinsic parallelism of an algorithm is adapted to be implemented by a computer, and includes the steps of: configuring the computer to represent the algorithm by means of a plurality of operation sets; configuring the computer to obtain a Laplacian matrix according to the operation sets; configuring the computer to compute eigenvalues and eigenvectors of the Laplacian matrix; and configuring the computer to obtain a set of information related to intrinsic parallelism of the algorithm according to the eigenvalues and the eigenvectors of the Laplacian matrix. | 01-12-2012 |
20120203814 | COMPUTER FOR AMDAHL-COMPLIANT ALGORITHMS LIKE MATRIX INVERSION - A family of computers is disclosed and claimed that supports simultaneous processes from the single core up to multi-chip Program Execution Systems (PES). The instruction processing of the instructed resources is local, dispensing with the need for large VLIW memories. The cores through the PES have maximum performance for Amdahl-compliant algorithms like matrix inversion, because the multiplications do not stall and the other circuitry keeps up. Cores with log based multiplication generators improve this performance by a factor of two for sine and cosine calculations in single precision floating point and have even greater performance for log | 08-09-2012 |
20130054665 | METHODS AND SYSTEMS FOR PERFORMING EXPONENTIATION IN A PARALLEL PROCESSING ENVIRONMENT - An automated method of performing exponentiation is disclosed. A plurality of tables holding factors for obtaining results of Exponentiations are provided. The plurality of tables are loaded into computer memory. Each factor is the result of a second exponentiation of a constant and an exponent. The exponent is related to a memory address corresponding to the factor. A plurality of memory addresses are identified for performing the first exponentiation by breaking up the first exponentiation into equations, the results of which are factors of the first Exponentiation. The exponents of the equations are related to the memory addresses corresponding to the factors held in the tables. A plurality of lookups into the computer memory are performed to retrieve the factors held in the tables corresponding to the respective memory addresses. The retrieved factors are multiplied together to obtain the result of the first exponentiation. | 02-28-2013 |
20130080494 | ARITHMETIC DEVICE AND DATABASE - An arithmetic device includes a database that stores a first indicator representing a base unit included in a unit system being assigned with a prime number other than a prime factor of a prefix, and a second indicator derived by combining the base units, in a form of a simple fraction; a conversion section that obtains a plurality of physical quantities each including a quantity, a prefix, and possibly a unit, to derive a third indicator by converting the unit into the first indicator and multiplying the converted first indicator by the prefix, or when the unit belongs to the derived unit, by converting the unit into the second indicator and multiplying the converted second indicator by the prefix; and an arithmetic section that performs calculation between the quantities of the plurality of physical quantities and between the third indicators. | 03-28-2013 |
20130110899 | DISTRIBUTED PROCESSING SYSTEM AND METHOD FOR DISCRETE LOGARITHM CALCULATION | 05-02-2013 |
20140006468 | Method and system for forensic data analysis in fraud detection employing a digital pattern more prevalent than Benford's Law | 01-02-2014 |
20140297708 | Fast Quantum and Classical Phase Estimation - A quantum phase estimator may include at least one phase gate, at least one controlled unitary gate, and at least one measurement device. The quantum phase estimator receives at least one ancillary qubit and a calculational state comprised of multiple qubits. The phase gate may apply random phases to the ancillary qubit, which is used as a control to the controlled unitary gate. The controlled unitary gate applies a second random phase to the calculational state. The measurement device may measure a state of the ancillary qubit from which a phase of the calculational state may be determined. | 10-02-2014 |
20150106417 | PARALLEL COMPUTATION OF A REMAINDER BY DIVISION OF A SEQUENCE OF BYTES - Methods, computer systems, and computer program products for calculating a remainder by division of a sequence of bytes interpreted as a first number by a second number are provided. A first subset of bytes is read, and an associated first remainder by division is calculated and stored in the memory location from which the subset was read. A second subset of bytes is read, and an associated second remainder by division is calculated with a second processor. The calculating of the second remainder by division may occur at least partially during the calculating of the first remainder by division. A third and fourth subset of bytes is read and associated remainders are calculated. | 04-16-2015 |