# Scaling

## Subclass of:

## 708 - Electrical computers: arithmetic processing and calculating

## 708100000 - ELECTRICAL DIGITAL CALCULATING COMPUTER

## 708200000 - Particular function performed

### Patent class list (only not empty are listed)

#### Deeper subclasses:

Class / Patent application number | Description | Number of patent applications / Date published |
---|---|---|

708208000 | Scaling | 19 |

20100250636 | APPARATUS AND METHODS FOR DYNAMIC DATA-BASED SCALING OF DATA - Disclosed are apparatus and methods for dynamic data-based scaling of data. The disclosed methods and apparatus involve storing one or more input data samples, which are to be scaled and input to a processing function such as a Fast Fourier Transform. A scaling value operable for scaling the one or more data samples is determined based on the one or more input data samples, and then the stored data samples are scaled based on the computed scaling value when read out of storage prior to the processing function. The scaling of data based on the input data allows the data to be scaled dynamically, not statically, and ensures that the data fits within a desired bit width constraint of the processing function thereby economizing processing resources. | 09-30-2010 |

20120246208 | FIR Filter with Reduced Element Count - A finite impulse response (FIR) filter having a differential output and capable of having negative coefficients, and a method of designing the filter, is disclosed. In contrast to the prior art, in which two output signals requires the use of two identical sets of impedance devices corresponding to the Fourier coefficients that create the desired response of the filter, the described method and system uses only a single set of impedance devices, and thus approximately one-half of the number of impedance devices used in the prior art. This is accomplished by appropriately selecting which resistors contribute to which output, so that a differential output may be obtained that is substantially the same as if impedance devices corresponding to all of the coefficients were used for each signal. | 09-27-2012 |

20150333734 | Low Delay Modulated Filter Bank - The document relates to modulated sub-sampled digital filter banks, as well as to methods and systems for the design of such filter banks. In particular, the present document proposes a method and apparatus for the improvement of low delay modulated digital filter banks. The method employs modulation of an asymmetric low-pass prototype filter and a new method for optimizing the coefficients of this filter. Further, a specific design for a 64 channel filter bank using a prototype filter length of 640 coefficients and a system delay of 319 samples is given. The method substantially reduces artifacts due to aliasing emerging from independent modifications of subband signals, for example when using a filter bank as a spectral equalizer. The method is preferably implemented in software, running on a standard PC or a digital signal processor (DSP), but can also be hardcoded on a custom chip. The method offers improvements for various types of digital equalizers, adaptive filters, multiband companders and spectral envelope adjusting filter banks used in high frequency reconstruction (HFR) or parametric stereo systems. | 11-19-2015 |

20130066933 | METHOD AND APPARATUS FOR DERIVING COMPOSITE TIE METRIC FOR EDGE BETWEEN NODES OF A TELECOMMUNICATION CALL GRAPH - A method for deriving a composite tie metric for an edge between nodes of a telecommunication call graph includes receiving descriptive data with original values for descriptive attributes associated with a telecommunication call graph formed by edges between nodes. Each edge relates to two nodes. Each original value relates to an edge and a descriptive attribute forming an edge-attribute pair for the corresponding original value. The descriptive data is stored in a local storage device. Scaling factors for each descriptive attribute are determined taking into account a distribution of the original values for the corresponding descriptive attribute and a common base for the descriptive attributes. Weighting factors are determined for each descriptive attribute. The composite tie metric is computed for an edge based on the original value, scaling factor, and weighting factor for the descriptive attributes. | 03-14-2013 |

20150058388 | FRACTIONAL SCALING DIGITAL FILTERS AND THE GENERATION OF STANDARDIZED NOISE AND SYNTHETIC DATA SERIES - Generation of standardized noise signals that provide mathematically correct noise with no errors and no loss of data, and can generate the noise of specific environments based on the transfer function of that environment are discussed. Various embodiments can generate synthetic data sets based on natural data sets that have similar scaling behavior. Fractional scaling digital filters, containing the fractional scaling characteristics of one or more of the eleven fundamental forms of basic building block transfer functions which incorporate the scaling exponent, can be encoded on FPGA devices or DSP chips for use in digital signal processing. Fractional Scaling Digital Filters allow fractional calculus, and thus fractional filtering (e.g., fractional scaling, fractional phase shifting, fractional integration, or fractional differentiation), to be performed on any signal, represent exact filtering solutions rather than approximations, and demonstrably are extremely accurate, highly efficient, and exhibit a higher level of performance than traditional DSP filters. | 02-26-2015 |

20140214911 | Software Tool for Implementing Modified QR Decomposition in Hardware - System and method for developing a circuit for QR decomposition with auxiliary functionality. A first function is included in a first program. The first function is configurable to specify an auxiliary function to be performed by a modified QR decomposition circuit in addition to QR decomposition of a matrix A into two matrices Q and R using a Modified Gram Schmidt process. A second program is automatically generated based on configuration of the QR decomposition and the first function. The second program includes program code implementing the QR decomposition and the auxiliary function for the first function in the first program. A hardware configuration program (HCP) may be automatically generated based on the first program, including the second program, where the HCP is deployable to hardware, e.g., a programmable hardware element, thereby implementing the modified QR decomposition circuit, including the QR decomposition of the matrix A and the auxiliary function. | 07-31-2014 |

20140214910 | Implementing Modified QR Decomposition in Hardware - System and method for computing QR matrix decomposition and inverse matrix R | 07-31-2014 |

20150088946 | FLOATING POINT SCALING PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS - A method of an aspect includes receiving a floating point scaling instruction. The floating point scaling instruction indicates a first source including one or more floating point data elements, a second source including one or more corresponding floating point data elements, and a destination. A result is stored in the destination in response to the floating point scaling instruction. The result includes one or more corresponding result floating point data elements each including a corresponding floating point data element of the second source multiplied by a base of the one or more floating point data elements of the first source raised to a power of an integer representative of the corresponding floating point data element of the first source. Other methods, apparatus, systems, and instructions are disclosed. | 03-26-2015 |

20130318138 | APPARATUS AND METHOD FOR PERFORMING DECIMAL DIVISION - A method for performing decimal division comprises: scaling a unsigned divisor D to a range; calculating multiplies of the scaled unsigned divisor D; storing multiples of the scaled unsigned divisor in a register; predicting a next single-bit quotient using a remainder R | 11-28-2013 |

20140074900 | ARCHITECTURE GUIDED OPTIMAL SYSTEM PRECISION DEFINITION ALGORITHM FOR CUSTOM INTEGRATED CIRCUIT - Systems and methods are disclosed to automatically determine an optimal number format representation for a model or code to be implemented in a custom integrated circuit (IC) by determining a ratio of dynamic range to static range in the model or code, and selecting a floating point or a fixed point number representation based on the ratio; determining the optimal number representation format based on a cost function that includes hardware area and power cost associated with a predetermined bit precision arithmetic; automatically generating a processor architecture customized to the optimal number representation format; and synthesizing the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication. | 03-13-2014 |

20090265404 | FAST SINGULAR VALUE DECOMPOSITION FOR EXPEDITING COMPUTER ANALYSIS SYSTEM AND APPLICATION THEREOF - The present invention uses a computer analysis system of a fast singular value decomposition to overcome the bottleneck of a traditional singular value decomposition that takes much computing time for decomposing a huge number of objects, and the invention can also process a matrix in any form without being limited to symmetric matrixes only. The decomposition and subgroup concept of the fast singular value decomposition works together with the decomposition of a variance matrix and the adjustment of an average vector of a column vector are used for optimizing the singular value decomposition to improve the overall computing speed of the computer analysis system. | 10-22-2009 |

20150019604 | FUNCTION ACCELERATOR - A circuit and method for accelerating function evaluation. In one embodiment, a processor includes a function accelerator unit configured to evaluate a mathematical function. The function accelerator unit includes a coefficient generator and a polynomial evaluator. The coefficient generator is configured to generate coefficients for a polynomial evaluated to produce a solution to the function. The coefficient generator varies values of the coefficients based on an input value at which the function is to be evaluated. The polynomial evaluator configured to apply the coefficients provided by the coefficient generator to evaluate the polynomial at the input value. | 01-15-2015 |

20150088947 | MULTIPLY ADD FUNCTIONAL UNIT CAPABLE OF EXECUTING SCALE, ROUND, GETEXP, ROUND, GETMANT, REDUCE, RANGE AND CLASS INSTRUCTIONS - A method is described that involves executing a first instruction with a functional unit. The first instruction is a multiply-add instruction. The method further includes executing a second instruction with the functional unit. The second instruction is a round instruction. | 03-26-2015 |

20140046991 | ARITHMETIC LOGIC UNIT FOR USE WITHIN A FLIGHT CONTROL SYSTEM - An arithmetic logic unit (ALU) for use within a flight control system is provided. The ALU comprises a first register configured to receive a first operand, a second register configured to receive a second operand, and an adder coupled to the first register and the second register. The adder is configured to generate a sum of the first operand and the second operand and to generate intermediate sums that are used to determine a product of the first operand and the second operand. | 02-13-2014 |

20110302231 | METHOD AND APPARATUS FOR PERFORMING NUMERICAL CALCULATIONS - There is provided a method of processing an iterative computation on a computing device comprising at least one processor. Embodiments of the method comprises performing, on a processor, an iterative calculation on data in a fixed point numerical format having a scaling factor, wherein the scaling factor is selectively variable for different steps of said calculation in order to prevent overflow and to minimise underflow. By providing such a method, the reliability, precision and flexibility of floating point operations can be achieved whilst using fixed point processing logic. The errors which fixed-point units are usually prone to generate if the range limits are exceeded can be mitigated, whilst still providing the advantage of a significantly reduced logic area to perform the calculations in fixed point. | 12-08-2011 |

20130218937 | ARITHMETIC APPARATUS, ELLIPTIC SCALAR MULTIPLICATION METHOD OF ARITHMETIC APPARATUS, ELLIPTIC SCALAR MULTIPLICATION PROGRAM, RESIDUE OPERATION METHOD OF ARITHMETIC APPARATUS, AND RESIDUE OPERATION PROGRAM - A scalar multiplication unit references a t-bit sequence representing a random number k one bit at a time from the most significant bit, and upon each referencing, sets in a work variable R[0] a value obtained by doubling a specific point G on an elliptic curve set in a scalar multiplication variable R, and sets in a work variable R[1] a value obtained by adding the specific point G to the work variable R[0]. The scalar multiplication unit | 08-22-2013 |

20110173243 | SCALED EXPONENTIAL SMOOTHING - A method and system for scaled exponential smoothing are provided. Multiple exponentially smoothed values are maintained for items and events occur on one or more of the items. The method maintains a gradually inflated representation of the smoothed values of items, such that the representation at a given time for an item where no event has occurred is not altered. Using a scaling technique enables the smoothed values for the objects on which an event has not occurred to remain the same. This reduces the number of calculations required significantly, enabling the use of the smoothing technique in a wide range of applications. | 07-14-2011 |

20140108476 | DETERMINATION OF THE TRANSFER FUNCTION OF A SIGNAL-PROCESSING SYSTEM WITHOUT A KNOWN INPUT SIGNAL - Methods for determining the transfer function of a signal-processing system that do not require a known input signal. The methods are based on two representations 1(x) and I | 04-17-2014 |

20080208939 | Decoder device and decoding method - A decoder having an element decoding unit generating external information for input data, including an exponent position determining unit, when the external information output from the element decoding unit is input, of information excluding a sign bit from the external information, specifying an exponent that is a bit position where a value different from a sign bit first appears, a mantissa obtaining unit obtaining information of 1-bit or a plurality of bits in a position next to the exponent as a mantissa out of the external information, a storage unit storing the exponent and the mantissa and a restoring unit restoring the external information by reading the exponent and the mantissa stored in the storage unit, wherein the element decoding unit performs iteration decoding based on the restored external information is utilized. | 08-28-2008 |