Entries |
Document | Title | Date |
20080201128 | Method and System for Performing Ternary Verification - A method and system for performing ternary verification is disclosed. Initially, a ternary model is generated from a binary model of a logic circuit design. The pairings used to encode the ternary model are then recorded. Next, the number of the recorded gate pairings is reduced by removing all invalid gate pairings. A ternary verification is performed on the ternary model having a reduced number of gate pairings. | 08-21-2008 |
20080208555 | SIMULATION METHOD AND SIMULATION APPARATUS - A simulation method and apparatus including a restore point setting unit setting restore points in core models for executing threads using parallel processing. The method also includes storing information for reproducing a state the core models at the restore points. | 08-28-2008 |
20080208556 | Accurate pin-based memory power model using arc-based characterization - A pin-based memory power modeling method using arc-based characterization includes steps as follows. All power arcs of a memory model are identified and characterized. A power arc is selected from the identified and characterized power arcs. Output bus switching power is computed by removing overlapping power using the selected power arc, and a temporary value for various input ramp times and output loads is derived. Output pin power for the selected power arc is calculated using the temporary value and a ratio of a number of output bits switching over an entire bus width. Switching power for the selected power arc is calculated by a power estimation tool based on port activity and an input intrinsic power value. | 08-28-2008 |
20080215305 | Emulated Memory Management - A first software program executing on a computing device emulates a second computing device executing a software program using emulated memory. The first software program permits the second software program to perform an operation on a contiguous portion of the emulated memory only when a pointer and a table entry both contain the same identifier, thus protecting against common types of memory usage errors in the second software program. The pointer has an address to the contiguous portion. The table entry maps to the contiguous portion. A plurality of table entries map to a respective plurality of contiguous portion of the emulated memory. A plurality of the pointers each contain the address to a respective contiguous portion of the emulated memory as well as containing an identifier corresponding to the respective contiguous portion of the emulated memory. The second computing device can be high or low in resources. | 09-04-2008 |
20080243462 | INSTRUCTION ENCODING IN A HARDWARE SIMULATION ACCELERATOR - A hardware simulation accelerator to simulate logic designs, a method to encode instructions for use in the hardware simulation accelerator, and a computer program product having code of the method by which the hardware simulation accelerator can read encoded instructions to simulate the logic design, and computer program product of the encoded instructions to simulate a logic design in a hardware accelerator. Each instruction has one of a plurality of opcodes, the opcodes select which of the hardware resources of the hardware simulation accelerator will implement and use the values set forth in other programmable bits of the encoded instruction. The encoded instruction may be a routing and/or a gate evaluation instruction. | 10-02-2008 |
20080255821 | CONTROLLING OPERATION OF A DIGITAL SYSTEM UTILIZING REGISTER ENTITIES - In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains first and second latches each having a respective plurality of different possible latch values. With one or more statements, a first Dial instance is associated with the first latch and a second Dial instance is associated with the second latch. A setting of the first Dial instance thus controls which of the plurality of different possible values is loaded in the first latch, and a setting of the second Dial instance controls which of the plurality of different possible values is loaded in the second latch. With a statement, a Register instance is concurrently associated with both the first and the second latches, such that a setting of the Register instance controls the latch values loaded in both the first and second latches. | 10-16-2008 |
20080281571 | METHOD, SYSTEM AND PROGRAM PRODUCT SUPPORTING SEQUENTIAL LOGIC IN SIMULATION INSTRUMENTATION OF AN ELECTRONIC SYSTEM - According to a method of simulation processing, a collection of files including one or more HDL source files describing design entities collectively representing a digital design to be simulated is received. The HDL source file(s) include a statement specifying inclusion of an instrumentation entity not forming a portion of the digital design but enabling observation of its operation during simulation. The instrumentation entity includes sequential logic containing at least one storage element, where the instrumentation entity has an output signal indicative of occurrence of a simulation event. The collection of files is processed to obtain an instrumented simulation executable model. The processing includes instantiating at least one instance of each of the plurality of design entities and instantiating the instrumentation entity. The processing further includes instantiating external instrumentation logic, logically coupled to each instance of the instrumentation entity, to record occurrences of the event. | 11-13-2008 |
20080288231 | Apparatus and method for cooperation verification - A cooperation verifying apparatus includes a storage unit and a processing unit. The processing unit simulates a software-based portion and a hardware-based portion in a target system, issues instruction signals from the software-based portion to the hardware-based portion in order during the simulation, stores a data of a progress state of the simulation of the software-based portion in the storage unit, stores the instruction signals in an order of reception as an input history in the storage unit and associates the input history with the progress state data. | 11-20-2008 |
20080294411 | Systems and Methods for Logic Verification - Methods and systems for simulating logic may translate logic design into executable code for a multi-processor based parallel logic simulation device. A system may implement one or more parallel execution methods, which may include IPMD, MPMD, and/or DDMT. | 11-27-2008 |
20080294412 | DESIGN STRUCTURE FOR PERFORMING CACHELINE POLLING UTILIZING STORE WITH RESERVE AND LOAD WHEN RESERVATION LOST INSTRUCTIONS - A design structure for performing cacheline polling utilizing store and reserve and load when reservation lost instructions is disclosed. In one embodiment a method is provided which comprises storing a buffer flag busy indicator data value within a first cacheable memory location and setting a load/store operation reservation on said first cacheable memory location via a store and reserve instruction. In the described embodiment, a data value stored within the first cacheable memory location is accessed via a conditional load instruction in response to a determination that the load/store operation reservation on the first cacheable memory location has been reset. Conversely, execution of the conditional load instruction is stalled in response to a determination that the load/store operation reservation on the first cacheable memory location has not been reset. | 11-27-2008 |
20080300849 | Design Structure for Improved Logic Simulation Using a Negative Unknown Boolean State - A system and method for simulating a circuit design using both an unknown Boolean state and a negative unknown Boolean state is provided. When the circuit is simulated, one or more initial simulated logic elements are initialized to the unknown Boolean state. The initialized unknown Boolean states are then fed to one or more simulated logic elements and the simulator simulates the handling of the unknown Boolean state by the simulated logic elements. Examples of simulated logic elements include gates and latches, such as flip-flops, inverters, and basic logic gates. The processing results in at least one negative unknown Boolean state. An example of when a negative unknown Boolean state would result would be when the unknown Boolean state is inverted by an inverter. The resulting negative unknown Boolean state is then fed to other simulated logic elements that generate further simulation results based on processing the negative unknown Boolean state. | 12-04-2008 |
20080306722 | Logic verification system - There is provided a logic verification system having improved development time and design quality, in which all pins of an FPGA module are wired in direct between the FPGA module and a bridge circuit used in the verification processes of a logic simulator accelerator and a logic emulator, a cutting end of the verification object logic is assigned to an external interface connector of the FPGA module when the logic simulation is accelerated, and the correspondence between each pin of external interface connector of the FPGA module and logic signal is performed on the logic simulator on the general purpose processor. | 12-11-2008 |
20090006066 | Method and System for Automatic Selection of Test Cases - A system for selecting a test case. A test case with a high score is selected. A simulation job is run on a device under test on a plurality of processors using the selected test case. Simulation performance and coverage data is collected for the selected test case and the collected simulation performance and coverage data is stored in a database. | 01-01-2009 |
20090063121 | OPTIMIZATION OF DISPLAYED RF COVERAGE - A method for optimizing RF coverage includes dividing a floor plan according to a plurality of grids. Radio frequency coverage for each of the plurality of grids is calculated to render a plurality of coverages. First data representative of the plurality of coverage grids is provided to a client. Second data representative of an incremental change in radio frequency coverage for a first grid of the plurality of grids is provided to the client. | 03-05-2009 |
20090106010 | TECHNIQUE FOR DIGITAL CIRCUIT FUNCTIONALITY RECOGNITION FOR CIRCUIT CHARACTERIZATION - A method and system of digital circuit functionality recognition for circuit characterization is disclosed. In one embodiment, a method for determining the valid arcs includes receiving a truth table including state information associated with input pins and their associated output pins in the digital circuit. Valid arcs are then determined based on whether a change in each of the input pins causes a change in associated one of the output pins using the received truth table. A first arc table is then formed using state information associated with substantially the determined valid arcs. Redundant arcs are then identified in the first arc table using the associated state information. A second arc table is then formed by removing the state information associated with the redundant arcs from the first arc table. | 04-23-2009 |
20090112557 | System and Method of Automating the Addition of RTL Based Critical Timing Path Counters to Verify Critical Path Coverage of Post-Silicon Software Validation Tools - A system and method for modifying a simulation model and optimizing an application program to produce valid hardware-identified operating conditions that are matched with simulator-identified operating conditions in order to modify a simulator accordingly is presented. A critical path coverage analyzer includes critical path measurement logic into a simulation model that injects errors into the critical path and provides visibility into the number of times that an application program exercises the critical path. The critical path coverage analyzer uses the critical path measurement logic to optimize an application program to adequately exercise and test the critical paths. Once optimized, the critical path coverage analyzer runs the optimized application program on a hardware device to produce hardware-identified operating conditions. The hardware-identified operating conditions are matched against simulator-identified operating conditions. When discrepancies exist, the simulator is modified accordingly to match the hardware-identified operating conditions. | 04-30-2009 |
20090132221 | Verification of Highly Optimized Synchronous Pipelines via Random Simulation Driven by Critical Resource Scheduling System and Program Product - Testing a model of a logic circuit model. The testing includes generating valid random input stimulus sequences for a logic circuit model. Enumerating critical resource requirements, enumerating critical resource availabilities does this, and selecting of stimulus sequences and determining legal times for execution of said stimulus sequences based on resource availability. This includes generating a plurality of possible combinations of input stimulus sequences and generating an array representation of critical resource requirements. These are used to generate an array representation of critical resources availabilities. | 05-21-2009 |
20090144044 | Logic simulator and logic simulation method - A logic simulator includes a storage device and a simulator part. The storage device stores a signal duration delay file which associates first signal duration information indicating duration of an input signal supplied to a logic gate of a logic circuit with first element delay value information indicating a first element delay value. The simulator part extracts first element delay value information associated with the first signal duration information corresponding to second signal duration information indicating duration of an input signal supplied to the logic gate when a logic simulation is performed by referring the signal duration delay file, and performs the logic simulation of the logic circuit based on the extracted first element delay value information. By setting element delay value taking duration of an input signal into account, highly accurate logic simulation can be achieved. | 06-04-2009 |
20090164197 | METHOD FOR TRANSFORMING OVERLAPPING PATHS IN A LOGICAL MODEL TO THEIR PHYSICAL EQUIVALENT BASED ON TRANSFORMATION RULES AND LIMITED TRACEABILITY - A method for transforming paths in a logical model to their physical equivalent in a physical model is provided. A logical model is retrieved. All entities in the logical model are mapped. All paths connecting the entities of the logical model are mapped. Tables are created that correspond to the entities in the logical model for traceability. Columns are created that correspond to attributes of the paths in the logical model for traceability. A reduced logical model is created by reducing overlapping paths in the logical model. Virtual logic paths are created where an entity is rolled up, is rolled down, or participates in a many-to-many relationship in the reduced logical model. The reduced logical model is transformed into a physical model. | 06-25-2009 |
20090171645 | LOGIC SIMULATOR AND LOGIC SIMULATION METHOD - According to one embodiment, a logical circuit to be simulated includes a timing network and a specific logical device. The timing network transmits a logical value change of an input signal in correspondence with an elapse of time or clock number increments. The specific logical device receives a timing network output signal that appears at an exit node of the timing network, and a logical value change or a logical value after change of the clock. When predetermined constraint information represents a constraint that a time period or the demanded number of clock cycles needed for a transition of a signal level change to pass through a signal path in the timing network is equal to or smaller than a predetermined numerical value (or equal to or larger than a predetermined numerical value), it is checked if the signal input to the specific logical device violates the predetermined constraint information. | 07-02-2009 |
20090222252 | DATA DRIVEN LOGIC SIMULATION CHIP AND TOOLCHAIN - An apparatus and method may be used for compiling a hardware logic design into data-driven logic programs to be executed on a data-driven chip. The apparatus may include storage with a library for defining a net-list synthesized by a synthesis tool. The apparatus may also include a data-driven logic verification chip comprising a plurality of logic processors. The apparatus may further include a code generator for adopting heuristics to convert the net-list into data driven logic programs and for allocating hardware resources to balance computing and storage loads across the plurality of logic processors of the verification chip. | 09-03-2009 |
20090240483 | SYSTEM AND COMPUTER PROGRAM PRODUCT FOR AUTOMATIC LOGIC MODEL BUILD PROCESS WITH AUTONOMOUS QUALITY CHECKING - A computer program product stored including machine executable instructions stored on machine readable media, the instructions configured for performing automatic logic build processes and implementing autonomic quality checking, by implementing a method including: providing a model repository for holding at least one component; updating the model repository with at least one component; creating a tag for each sub-component of a selected component of the model repository; associating each tag with a latest version of each respective sub-component; and issuing a component submit notice to identify at least one of a dependency and a priority between selected components. A system is also provided. | 09-24-2009 |
20090248386 | DESCRIPTION PROCESSING DEVICE, DESCRIPTION PROCESSING METHOD, AND RECORDING MEDIUM - A description processing device has: a receiving unit which receives a behavior level description; a label-name generating unit which generates a label name; a label disposing unit which disposes a top label statement; an extracting unit which extracts an extracted label statement, a variable-name generating unit which generates a variable name; a replacing unit which replaces a statement immediately below the top label statement to the extracted label statement by a column of a conditional executable statement and an operation/assignment statement and replaces a jump statement for jumping the extracted label statement by a column of an operation/assignment statement and a jump statement for jumping to the top label; a control unit which repeats the extraction, the generation of a new variable name, and the replacement; an inserting unit which inserts an operation/assignment statement; and an output unit which outputs the behavior level description. | 10-01-2009 |
20090254331 | COMPACT CIRCUIT-SIMULATION OUTPUT - Embodiments of a computer system for simulating a circuit are described. During a first mode of the simulation, the computer system stores primary signals and circuit relationships between primary signals and secondary signals associated with a portion of the circuit in a file, where the primary signals are independent of gate outputs in the portion of the circuit, and the secondary signals are driven by gates in the portion of the circuit. Moreover, during a second mode of the simulation, the computer system stores dynamic changes in additional relationships between signals to the file, where the signals can include primary signals, secondary signals, or both. | 10-08-2009 |
20090259453 | Method of modeling SRAM cell - A method of modeling an SRAM cell is provided. Initially, transistor models are provided based on transistor devices, and an SRAM cell model is provided including the transistor models. The present methodology streamlines the modeling process by modeling in order the pull up, pass gate and pull down transistors so as to minimize the number of transistor modeling iterations needed, and by focusing on the specific areas of transistor operation to achieve the desired level of operational accuracy. Variations to the model are provided, mimicking variations in data from actual devices, and yield based on failure estimation is measured using the model and its variations. | 10-15-2009 |
20090313001 | SIMULATION APPARATUS, SIMULATION METHOD AND COMPUTER-READABLE RECORDING MEDIUM ON OR IN WHICH SIMULATION PROGRAM IS RECORDED - The present invention relates to a technique for executing performance evaluation simulation of a system to be implemented by software or hardware. A simulation apparatus includes a first acquisition section for executing existing tentative software to acquire a first execution log, a division section for dividing the first execution log into a plurality of basic processing units, a basic processing execution log production section for modifying some of the plural basic processing units to produce a basic processing execution log to be used for simulation, and a simulation execution section for inputting the basic processing execution log to a hardware model to execute the simulation to acquire information required for the performance evaluation. | 12-17-2009 |
20100017187 | RANDOM INITIALIZATION OF LATCHES IN AN INTEGRATED CIRCUIT DESIGN FOR SIMULATION - Latches in a net of a simulated integrated circuit design are initialized to known logical states prior to application of a reset signal at the beginning of the simulation. The logical states may be set by generating a list of the latches, sorting them in random order, and then dividing them into two groups based on the random order with high and low logical states respectively assigned to the two groups. In a specific implementation the latch states are set using an HDL force command prior to applying the reset signal, and the force command is removed after applying the reset signal using an HDL release command. If the circuit description is a gate-level netlist, then logical states of gates within the storage elements are also set. | 01-21-2010 |
20100076742 | SIMULATION MODEL FOR TRANSISTORS - Various embodiments include methods and apparatus for simulating a transistor using a simulation model that includes a transistor simulation model coupled to diode simulation model. | 03-25-2010 |
20100094610 | Circuit simulation model generation apparatus, circuit simulation model generation method and circuit simulation apparatus - A circuit simulation model generation apparatus includes: a power supply wiring model generation section that generates a power supply wiring model which is a model of the power supply wiring; a logic circuit model generation section that generates a logic circuit model which is a model of the logic circuit; and a link section that adds, to the logic circuit model and the power supply wiring model, a voltage controller that acquires a potential value of a logic circuit connecting terminal and gives the acquired potential value to a power supply wiring connecting terminal and a current controller that acquires a current value of the power supply wiring connecting terminal and gives the acquired current value to the logic circuit connecting terminal in the simulation, and links the logic circuit model and the power supply wiring model to generate a simulation model. | 04-15-2010 |
20100106477 | MEDIUM STORING LOGIC SIMULATION PROGRAM, LOGIC SIMULATION APPARATUS, AND LOGIC SIMULATION METHOD - A logic simulation apparatus includes: a jitter detector generation section | 04-29-2010 |
20100174521 | DATA PROCESSING WITH CIRCUIT MODELING - Various aspects of the present invention are directed to design modeling and/or processing of streaming data. According to an example embodiment, a system to model a hardware specification includes a platform ( | 07-08-2010 |
20100250224 | POWER SOURCE NOISE ANALYSIS DEVICE AND ANALYSIS METHOD - A power source noise analysis device includes an analysis portion. The analysis portion estimates an internal impedance of a semiconductor chip being an object to be analyzed based on a power current waveform, which is obtained by simulation of the semiconductor chip based on design data of the semiconductor chip. The analysis portion carries out a noise analysis of a power system including a board having the semiconductor chip mounted thereon based on the internal impedance. | 09-30-2010 |
20100286976 | Systems and Methods for Logic Verification - Methods and systems for simulating logic may translate logic design into executable code for a multi-processor based parallel logic simulation device. A system may implement one or more parallel execution methods, which may include IPMD, MPMD, and/or DDMT. | 11-11-2010 |
20100305933 | Method and Apparatus for Verifying Logic Circuits Using Vector Emulation with Vector Substitution - A method for verifying a logic circuit in a prototyping system includes (a) configuring programmable logic circuits of the prototyping system to implement the logic circuit and to implement probe circuits for accessing internal nodes of the logic circuit; (b) preparing emulation vectors for use in a vector emulation of the logic circuit in the prototyping system; (c) setting one or more vector substitution points; (d) preparing one or more packet vectors at each vector substitution point for replacing emulation vectors in the vector emulation; (e) performing the vector emulation using the emulation vectors until one of the vector substitution points is reached; and (f) substituting packet vectors for the corresponding emulation vectors at vector substitution point and continuing the vector emulation. | 12-02-2010 |
20100305934 | LOGICAL SIMULATION SYSTEM, LOGICAL SIMULATION METHOD, AND LOGICAL SIMULATION PROGRAM - A program that simulates a netlist data including a plurality of basic elements using a computer includes a logic operation section configured to stipulate a logic operation of at least one of the plurality of the basic elements, a change detection section configured to detect changes in signal levels at an input-and-output end of the at least one of the plurality of the basic elements, and a data storage section configured to store a position data corresponding to the changes of the signal levels. | 12-02-2010 |
20100324881 | SATISFIABILITY (SAT) BASED BOUNDED MODEL CHECKERS - A method uses a SAT solver operating to cycle k to find bugs in a model having finite computation paths therein, wherein said bugs are on computation paths of less than length k. Another method includes adding an additional state variable to a model to be checked, where a governing state machine of the additional variable has a “sink” state. The method includes having a translation using the additional variable whenever a state indicates a bad state and performing satisfiability solving with the model and the translation. | 12-23-2010 |
20110054876 | PHYSICAL REALIZATIONS OF A UNIVERSAL ADIABATIC QUANTUM COMPUTER - Devices, methods and articles advantageously allow communications between qubits to provide an architecture for universal adiabatic quantum computation. The architecture includes a first coupled basis A | 03-03-2011 |
20110161066 | DELTA RETIMING IN LOGIC SIMULATION - Aspects of the present invention are directed to improving the speed of event-driven simulation by manipulating delta delays in a system model to reduce delta cycle executions. The manipulation is performed in a manner that preserves delta cycle accurate timing on selected signals of the system, which may be of interest to a designer. Methods and systems are provided for identifying the signals of interest, and for determining portions of the design that may have delta delays retimed. Preserving the timing on the signals of interest ensures that race conditions and glitches present in the design on the signals of interest are still viewable by the designer. To reduce simulation time, delta delays may be moved from high activity signals to low activity signals, the total number of delta delays may be reduced, or a number of processes executed may be reduced. | 06-30-2011 |
20110213605 | Satisfiability (SAT) Based Bounded Model Checkers - Systems and methods that use a solver to find bugs in a target model of a computing system having one or more finite computation paths are provided. The bugs on computation paths of less than a predetermined length are detected by translating the target model to include a state variable AF for one or more states of the target model, wherein AF(S) represents value of the state variable AF at state S; and solving the translated version of the target model that satisfies predetermined constrains. | 09-01-2011 |
20110238400 | DEVICE FOR A METHOD OF MODELLING A PHYSICAL STRUCTURE | 09-29-2011 |
20110257955 | Gate-Level Logic Simulator Using Multiple Processor Architectures - Techniques for simulating operation of a connectivity level description of an integrated circuit design are provided, for example, to simulate logic elements expressed through a netlist description. The techniques utilize a host processor selectively partitioning and optimizing the descriptions of the integrated circuit design for efficient simulation on a parallel processor, more particularly a SIMD processor. The description may be segmented into cluster groups, for example macro-gates, formed of logic elements, where the cluster groups are sized for parallel simulation on the parallel processor. Simulation may occur in an oblivious as well as event-driven manner, depending on the implementation. | 10-20-2011 |
20110270599 | METHOD FOR TESTING INTEGRATED CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE - A method for testing an integrated circuit includes simulating the integrated circuit and generating waveforms of signals at a plurality of nodes of the integrated circuit, generating a text file representing the signal waveforms by detecting a waveform change of the signals, and analyzing the text file. | 11-03-2011 |
20110295584 | VERIFICATION SUPPORT PROGRAM, LOGIC VERIFICATION DEVICE, AND VERIFICATION SUPPORT METHOD - A computer-readable recording medium configured to store a verification support program, the program causing a computer to execute logic verification operations for a system including a plurality of control circuits, and a plurality of hardware units that correspond to the control circuits. The logic verification operations are executed using a verification model of the system. The verification model includes a control circuit model which has a function of the control circuit, and a plurality of hardware models which have functions of the plurality of hardware units. The logic verification operations include accepting instructions from the plurality of hardware models by the control circuit model; selecting an instruction to be processed by one of the plurality of hardware models from the accepted instructions by the control circuit model; and reporting a processing request of the selected instruction to the plurality of hardware models by the control circuit model. | 12-01-2011 |
20120046931 | MULTIPLE POWER-SUPPLY SIMULATION RESULT ANALYZER AND METHOD OF ANALYZING THE SAME - In a method of displaying a waveform of a simulation result, a waveform file extractor which extracts information of voltage values in addition to simulation times, values, and signal names input as waveform information, and a waveform display unit which enables a display of the wave information with the voltage values added are included. Thus, when a waveform of a multiple power-supply simulation is displayed on a display, voltage information is displayed together with the waveform, thereby allowing the voltage information to be analyzed together with a change in value at each simulation time. Thus, efficient analysis is achieved. | 02-23-2012 |
20120136642 | INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD - An information processing apparatus connected to an emulator to arrange a verification model and a verification target includes a compile unit configured to create a first data transfer unit arranged in a computer to transfer data from the computer to the emulator based on a description of a file function of a verification program and a generation unit configured to generate a second data transfer unit that receives the data from the first data transfer unit and transfers the received data to the verification target based on the description of the file function. | 05-31-2012 |
20120265515 | METHOD AND SYSTEM AND COMPUTER PROGRAM PRODUCT FOR ACCELERATING SIMULATIONS - Method, system, and computer program product. The method may include: receiving a model of a circuit that includes logic that is designed to receive sequence information and/or constants from input modules of the circuit. Updating the model or generating a new model that includes an interface and an initialization module. The initialization module may provide, to a hardware accelerator and during an initialization of a simulation of the circuit, the constants and/or the sequence information. The interface may interface between a simulator and a hardware accelerator that includes one or more FPGAs. Generating FPGA code of an amended logic that includes the logic and a programmable module; wherein the programmable module may receive, during the initialization of the simulation, the constants and/or the sequence information, and to provide during the simulation and to the logic, at least one out of the constants and a sequence represented by the sequence information. | 10-18-2012 |
20120278057 | PHYSICAL REALIZATIONS OF A UNIVERSAL ADIABATIC QUANTUM COMPUTER - Devices, methods and articles advantageously allow communications between qubits to provide an architecture for universal adiabatic quantum computation. The architecture includes a first coupled basis A | 11-01-2012 |
20120290282 | REACHABILITY ANALYSIS BY LOGICAL CIRCUIT SIMULATION FOR PROVIDING OUTPUT SETS CONTAINING SYMBOLIC VALUES - A logic simulation program, method and system for obtaining a set of reachable states for a logic design that can be used to provide input to other algorithms that simplify the netlist describing the logic design or perform other types of processing, provides an efficient, compact behavior when simulating large designs. Rather than simulating using ternary input and state value representations that are restricted to true, false and unknown, the techniques of the present invention use input symbolic values that are retained in the set of reachable states retained as the output. Behaviors such as oscillators, transient values, identical signals, dependent logical states and chicken-switch determined states can be detected in the simulation results and the netlist simplified using the results of the detection. | 11-15-2012 |
20120296623 | MACHINE TRANSPORT AND EXECUTION OF LOGIC SIMULATION - A processing architecture and methods are disclosed in which a simulation state vector can be contained in a common memory, formatted in a known form, distributed in a deterministic bus to a sea of logic processors, and returned to the common memory through the deterministic bus. | 11-22-2012 |
20130282352 | REAL TIME LOGIC SIMULATION WITHIN A MIXED MODE SIMULATION NETWORK - Technologies relating to real time logic simulation within a mixed mode simulation network are described. Mixed mode simulation networks may comprise Boolean Processing Units (BPUs) and Real Time Processing Units (RTPUs). Mixed mode simulation networks may send an input simulation state vector to the processing units, and the processing units may process portions thereof to calculate portions of an output simulation state vector. BPUs may be adapted to calculate portions of the output simulation state vector without accounting for delay times attributable to operation of a simulated system, while RTPUs may be adapted to calculate portions of the output simulation state vector with accounting for delay times attributable to operation of the simulated system. The calculated portions of the output simulation state vector may be combined in a computational memory, and the resulting output simulation state vector may be used as an input simulation state vector in a next simulation calculation cycle. | 10-24-2013 |
20140149100 | METHOD FOR CHARACTERIZING THE SENSITIVITY OF AN ELECTRONIC COMPONENT FOR A METHOD FOR DESIGNING ELECTRONIC EQUIPMENT - A method for designing electronic equipment comprising at least one electronic component. The component executes a dynamic application and is subjected to disruptions. The software application utilizes internal elements of the component. The method comprises a stage for characterizing a sensitivity parameter of the component to the disruptions. The stage comprises the step of executing the software application on a device configured to reproduce the operation of the component, and performance related signals are monitored, during the execution of the software application, to access the predetermined component elements. A dwell time of the software application in the component elements are deduced from the monitoring of the performance related signals. | 05-29-2014 |
20140236563 | INTEGRATED CIRCUIT SIMULATION METHOD AND SYSTEM - Provided is an integrated circuit simulation method. The simulation time points of the entire circuit are divided into a plurality of independent simulation time windows, and according to a logic simulation result, the simulation initial data of the simulation window starting point of each simulation time window is determined, and as an overlapping time region is present at the head-tail connection between adjacent simulation time windows, the circuit simulation calculation of the current simulation time window can be ended at the overlapping time region, so as to implement independent parallel simulation calculation for each simulation time window. Therefore, the time required for the simulation of the entire circuit is approximately the maximum value of the circuit simulation time required for each simulation time window, thereby greatly increasing the efficiency of circuit simulation and effectively shortening the design period of the integrated circuit. | 08-21-2014 |
20140278329 | Modeling Content-Addressable Memory For Emulation - Aspects of the invention relate to techniques for modeling content-addressable memory for emulation. An emulation device according to various embodiments of the invention comprises one or more memory modeling blocks reconfigurable to emulate a content-addressable memory or a random-access memory. The emulation device may be processor-based or FPGA-based. Each of the one or more memory modeling blocks comprises memory circuitry and a dedicated comparison unit configured to compare a search word or a portion of a search word received by the each of the one or more memory modeling blocks with data stored in the memory circuitry. The comparison unit may comprise a comparator and a register coupled to the comparator and configured to store matching data. The matching data may be unencoded matching data. A plurality of the memory modeling blocks may be programmable to emulate a single content-addressable memory. | 09-18-2014 |
20150356220 | AUTOMATED INPUT SIMULATION FOR SIMULATED PROGRAMMABLE LOGIC CONTROLLER - Input simulation is provided ( | 12-10-2015 |
20160019326 | DESIGN SIMULATION USING PARALLEL PROCESSORS - A method for design simulation includes partitioning a verification task of a design ( | 01-21-2016 |
20160063158 | METHOD AND DEVICE FOR SIMULATING A CIRCUIT DESIGN - The present invention discloses a method and device for simulating a circuit design. The method includes identifying at least one Sequential-cell-To-Sequential-cell (S2S) block in the circuit design, wherein the S2S block includes at least one input sequential cell, at least one output sequential cell, and an intermediate portion between the input sequential cell and the output sequential cell, wherein the intermediate portion includes at least one combinational cell; determining logic characteristics and timing characteristics of the intermediate portion; and replacing the intermediate portion with a functional module having the logic characteristics and the timing characteristics to generate a simplified circuit design to be used in simulation. With the technical solution according to embodiments of the invention, time needed in simulation is shortened. | 03-03-2016 |
20160098505 | EFFICIENT EMULATION AND LOGIC ANALYSIS - An emulation environment includes a host system and an emulator. The host system configures the emulator to load a design under test (DUT) and the emulator emulates the DUT. The emulator includes one or more design field-programmable gate arrays (FPGAs) that emulate the DUT. In addition, the emulator includes at least one system FPGA with a logic analyzer and multiple virtual FPGA. The virtual FPGAs emulate sections of the DUT. By the virtual FPGAs emulating sections of the DUT, the logic analyzer is able to obtain for performing logic analysis certain signals from the virtual FPGAs, rather than from the design FPGAs. | 04-07-2016 |