Class / Patent application number | Description | Number of patent applications / Date published |
505170000 | Information processing (e.g., logic circuits, computer, etc.) or information storage or retrieval system, device, or component (i.e., both dynamic and static) | 22 |
20090075825 | SYSTEMS, METHODS, AND APPARATUS FOR CONTROLLING THE ELEMENTS OF SUPERCONDUCTING PROCESSORS - A computer system employs a network that between a data programming system and one or more superconducting programmable devices of a superconducting processor chip. Routers on the network, such as first-, second- and third-stage routers direct communications with the superconducting programmable devices. A superconducting memory register may load data signals received from a first-stage router into corresponding superconducting programmable devices. The system may employ additional superconducting chips, first-, second- or third-stage routers. | 03-19-2009 |
20090192041 | SYSTEMS, DEVICES, AND METHODS FOR CONTROLLABLY COUPLING QUBITS - A transverse coupling system may include a first qubit, a second qubit, a first conductive path capacitively connecting the first qubit and the second qubit, a second conductive path connecting the first qubit and the second qubit, and a dc SQUID connecting the first and the second conductive paths wherein the compound junction loop is threaded by an amount of magnetic flux. | 07-30-2009 |
20110065586 | SYSTEMS, METHODS AND APPARATUS FOR SUPERCONDUCTING DEMULTIPLEXER CIRCUITS - A switching cell for a demultiplexer circuit includes a superconducting input signal path, at least two superconducting output signal paths, and transformers located between an intersection node and respective ends of the output signal paths. Flux applied via the transformers can influence which direction a signal propagates. The switching cell may also include power input nodes. Switching cells may be arranged in various configurations, for example a binary tree or H-tree. A superconducting inductor ladder circuit can perform a digital-to-analog conversion. Flux storage structures may be used with individual switching cells. Latching qubits may be employed. Buffer rows of switching cells may be used to reduce or eliminate cascade error. | 03-17-2011 |
20120094838 | SYSTEMS, METHODS AND APPARATUS FOR DIGITAL-TO-ANALOG CONVERSION OF SUPERCONDUCTING MAGNETIC FLUX SIGNALS - A superconducting flux digital-to-analog converter includes a superconducting inductor ladder circuit. The ladder circuit includes a plurality of closed superconducting current paths that each includes at least two superconducting inductors coupled in series to form a respective superconducting loop, successively adjacent or neighboring superconducting loops are connected in parallel with each other and share at least one of the superconducting inductors to form a flux divider network. A data signal input structure provides a respective bit of a multiple bit signal to each of the superconducting loops. The data signal input structure may include a set of superconducting quantum interference devices (SQUIDs). The data signal input structure may include a superconducting shift register, for example a single-flux quantum (SFQ) shift register or a flux-based superconducting shift register comprising a number of latching qubits. | 04-19-2012 |
20130005580 | SYSTEMS, DEVICES, AND METHODS FOR ANALOG PROCESSING - A system may include first and second qubits that cross one another and a first coupler having a perimeter that encompasses at least a part of the portions of the first and second qubits, the first coupler being operable to ferromagnetically or anti-ferromagnetically couple the first and the second qubits together. A multi-layered computer chip may include a first plurality N of qubits laid out in a first metal layer, a second plurality M of qubits laid out at least partially in a second metal layer that cross each of the qubits of the first plurality of qubits, and a first plurality N times M of coupling devices that at least partially encompasses an area where a respective pair of the qubits from the first and the second plurality of qubits cross each other. | 01-03-2013 |
20130017955 | Energy Efficient Data CenterAANM Hennessy; Michael J.AACI Ballston LakeAAST NYAACO USAAGP Hennessy; Michael J. Ballston Lake NY USAANM Mueller; Eduard K.AACI Ballston LakeAAST NYAACO USAAGP Mueller; Eduard K. Ballston Lake NY USAANM Mueller; Otward M.AACI Ballston LakeAAST NYAACO USAAGP Mueller; Otward M. Ballston Lake NY US - An energy efficient data center incorporating superconducting power transmission cables coupled with cryogenically cooled semiconductor inverters and converters, used to supply power to cryogenically operated or room-temperature computers and servers. Other options and features include a lighting system whose performance is enhanced by the cold temperatures, fiber optic connections operated at cryogenic temperatures, integrated renewable energy power sources, advanced energy storage technologies, cryogenically operated computers, and a number of other cryogenic hardware. The operating temperature of the cryogenic components can be anywhere in the range between 0 K and 200 K, with other components operating above 200 K. | 01-17-2013 |
20130190185 | SYSTEMS, METHODS AND APPARATUS FOR PLANAR EXPULSION SHIELDS - A superconducting magnetic shielding system includes first and second planar superconducting shields respectively positioned above and below an environment to be shielded. The shields are each thermally coupled to a cold source at a respective thermalizing point. When the shields are cooled into the superconducting regime, they passively block magnetic fields via the Meissner Effect. Each shield may also be shaped to produce a smooth temperature gradient extending away from its thermalizing point; thus, as the shields are cooled, magnetic fields may be expelled away from the thermalizing point and, consequently, away from the environment to be shielded. A heater may also be provided opposite the thermalizing points to improve control of the temperature gradient. | 07-25-2013 |
20130196855 | SUPERCONDUCTING QUANTUM CIRCUIT HAVING A RESONANT CAVITY THERMALIZED WITH METAL COMPONENTS - A quantum electronic circuit device includes a housing having an internal resonant cavity, a qubit disposed within a volume of the internal resonant cavity and a non-superconducting metallic material mechanically and thermally coupled to the qubit within the internal resonant cavity and contiguously extending to the exterior of the housing. | 08-01-2013 |
20130303379 | HYBRID SUPERCONDUCTING-MAGNETIC MEMORY CELL AND ARRAY - In one embodiment, the invention is a hybrid superconducting-magnetic memory cell and array. One embodiment of a memory cell includes a magnetoresistive element and at least one superconducting element wired in parallel with the magnetoresistive element. In a further embodiment, memory cells of the disclosed configuration are arranged to form a memory array. | 11-14-2013 |
20140187427 | QUANTUM PROCESSOR BASED SYSTEMS AND METHODS THAT MINIMIZE AN OBJECTIVE FUNCTION - Quantum processor based techniques minimize an objective function for example by operating the quantum processor as a sample generator providing low-energy samples from a probability distribution with high probability. The probability distribution is shaped to assign relative probabilities to samples based on their corresponding objective function values until the samples converge on a minimum for the objective function. Problems having a number of variables and/or a connectivity between variables that does not match that of the quantum processor may be solved. Interaction with the quantum processor may be via a digital computer. The digital computer stores a hierarchical stack of software modules to facilitate interacting with the quantum processor via various levels of programming environment, from a machine language level up to an end-use applications level. | 07-03-2014 |
20140235450 | MULTI-TUNABLE SUPERCONDUCTING CIRCUITS - A method of characterizing a tunable superconducting circuit, includes selecting an operating direct current (DC) flux for a first charge island from a plurality of coupled charge islands residing in the tunable superconducting circuit coupled to a first resonator and a second resonator, tuning operating DC flux values for at least two charge islands from the plurality of coupled charge islands, measuring coupling energies of the first resonator and the second resonator and measuring frequencies from each of the plurality of coupled charge islands. | 08-21-2014 |
20140274725 | CHIP MODE ISOLATION AND CROSS-TALK REDUCTION THROUGH BURIED METAL LAYERS AND THROUGH-VIAS - A method for fabricating a chip surface base includes preparing a first substrate, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias, preparing a second substrate, bonding the first and second substrates and exposing the metal fillings. A method for fabricating a chip surface base includes preparing a first and second substrate, depositing a metal on at least one of the first and second substrates, bonding the first and second substrates, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias and exposing the metal fillings. A chip surface base device includes a first substrate, a second substrate, a metal layer disposed between the first and second substrates and a plurality vias disposed on the first substrate. | 09-18-2014 |
20140357493 | QUANTUM BITS AND METHODS OF FORMING THE SAME - A Josephson junction (JJ) quantum bit (qubits) arranged on a substrate is provided. In one embodiment, each qubit comprises a dielectric layer, a superconductor base layer portion underlying the dielectric layer and a first dielectric diffused region adjacent a dielectric layer/superconductor base layer portion junction. The qubit further comprise a superconductor mesa layer portion overlying the dielectric layer and having a second dielectric diffused region adjacent a dielectric layer/superconductor mesa layer portion junction, the first and second dielectric diffused regions mitigating further diffusion from other semiconductor processes on the plurality of qubits. | 12-04-2014 |
20150111754 | UNIVERSAL ADIABATIC QUANTUM COMPUTING WITH SUPERCONDUCTING QUBITS - A quantum processor is operable as a universal adiabatic quantum computing system. The quantum processor includes physical qubits, with at least a first and second communicative coupling available between pairs of qubits via an in-situ tunable superconducting capacitive coupler and an in-situ tunable superconducting inductive coupler, respectively. Tunable couplers provide diagonal and off-diagonal coupling. Compound Josephson junctions (CJJs) of the tunable couplers are responsive to a flux bias to tune a sign and magnitude of a sum of a capacitance of a fixed capacitor and a tunable capacitance which is mediated across a pair of coupling capacitors. The qubits may be hybrid qubits, operable in a flux regime or a charge regime. Qubits may include a pair of CJJs that interrupt a loop of material and which are separated by an island of superconducting material which is voltage biased with respect to a qubit body. | 04-23-2015 |
20150119252 | SYSTEMS AND METHODS FOR FABRICATION OF SUPERCONDUCTING INTEGRATED CIRCUITS - Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer. | 04-30-2015 |
20160019468 | SYSTEMS, DEVICES, AND METHODS FOR ANALOG PROCESSING - A system may include first and second qubits that cross one another and a first coupler having a perimeter that encompasses at least a part of the portions of the first and second qubits, the first coupler being operable to ferromagnetically or anti-ferromagnetically couple the first and the second qubits together. A multi-layered computer chip may include a first plurality N of qubits laid out in a first metal layer, a second plurality M of qubits laid out at least partially in a second metal layer that cross each of the qubits of the first plurality of qubits, and a first plurality N times M of coupling devices that at least partially encompasses an area where a respective pair of the qubits from the first and the second plurality of qubits cross each other. | 01-21-2016 |
20160071903 | GROUND GRID FOR SUPERCONDUCTING CIRCUITS - One example includes a superconducting circuit. The circuit includes a plurality of layers comprising a first conductor layer and a second conductor layer overlying the first conductor layer, each of the first and second conductor layers comprising at least one signal element. The circuit also includes a ground grid that is conductively coupled to ground and comprises a first plurality of parallel ground lines that occupy the first conductor layer and extend in a first direction and a second plurality of parallel ground lines that occupy the second conductor layer and extend in a second direction that is orthogonal with respect to the first direction. | 03-10-2016 |
20160254434 | Systems and Methods for Suppressing Magnetically Active Surface Defects in Superconducting Circuits | 09-01-2016 |
505171000 | Recording by magnetism, magnetic record carriers, or recording head arrangements | 4 |
20120108434 | HYBRID SUPERCONDUCTING-MAGNETIC MEMORY CELL AND ARRAY - In one embodiment, the invention is a hybrid superconducting-magnetic memory cell and array. One embodiment of a memory cell includes a magnetoresistive element and at least one superconducting element wired in parallel with the magnetoresistive element. In a further embodiment, memory cells of the disclosed configuration are arranged to form a memory array. | 05-03-2012 |
20120184445 | Superconducting Devices with Ferromagnetic Barrier Junctions - A superconducting memory cell includes a magnetic Josephson junction (MJJ) with a ferromagnetic material, having at least two switchable states of magnetization. The binary state of the MJJ manifests itself as a pulse appearing, or not appearing, on the output. A superconducting memory includes an array of memory cells. Each memory cell includes a comparator with at least one MJJ. Selected X and Y-directional write lines in their combination are capable of switching the magnetization of the MJJ. A superconducting device includes a first and a second junction in a stacked configuration. The first junction has an insulating layer barrier, and the second junction has an insulating layer sandwiched in-between two ferromagnetic layers as barrier. An electrical signal inputted across the first junction is amplified across the second junction. | 07-19-2012 |
20140296076 | MAGNETIC MEMORY SYSTEM AND METHODS IN VARIOUS MODES OF OPERATION - A magnetic memory system includes a superconductor circuit and one or more magnetic memory elements to store data. To write data, a driver circuit in the superconductor circuit generates a magnetic signal for transmission over a superconductor link extending between the superconductor circuit and the magnetic memory element. To read data, a sensing circuit in the superconductor circuit monitors a superconductor link extending from sensing circuit to the magnetic memory element. The magnetic memory element can be a spin-transfer type magnetic memory element. | 10-02-2014 |
20150094207 | PHASE HYSTERETIC MAGNETIC JOSEPHSON JUNCTION MEMORY CELL - One embodiment describes a memory cell. The memory cell includes a phase hysteretic magnetic Josephson junction (PHMJJ) that is configured to store one of a first binary logic state corresponding to a binary logic-1 state and a second binary logic state corresponding to a binary logic-0 state in response to a write current and to generate a superconducting phase based on the stored digital state. The memory cell also includes at least one Josephson junction having a critical current that is based on the superconducting phase of the PHMJJ and being configured to provide an output corresponding to the stored digital state in response to a read current. | 04-02-2015 |