Class / Patent application number | Description | Number of patent applications / Date published |
438713000 | Forming tapered profile (e.g., tapered etching, etc.) | 7 |
20080286978 | ETCHING AND PASSIVATING FOR HIGH ASPECT RATIO FEATURES - An etch method includes etching a masked substrate to form a recess with a first sidewall in the substrate. A thin surface layer of the substrate on the first sidewall is then converted into a passivation layer. The masked substrate is etched again to deepen the recess in the substrate. A surface layer of the substrate on the second sidewall of the recess is then converted into a passivation layer. In one embodiment, upon removal of the passivation layers from both sidewalls, the first and second sidewalls of the high aspect ratio recess are aligned to within 10 Å of each other to provide a high aspect ratio recess having a vertical profile. | 11-20-2008 |
20090197420 | METHOD FOR ETCHING A SILICON-CONTAINING ARC LAYER TO REDUCE ROUGHNESS AND CD - A method of dry developing a multi-layer mask having a silicon-containing anti-reflective coating (ARC) layer on a substrate is described. The method comprises forming the multi-layer mask on the substrate, wherein the multi-layer mask comprises a lithographic layer overlying the silicon-containing ARC layer. A feature pattern is then formed in the lithographic layer using a lithographic process, wherein the feature pattern comprises a first critical dimension (CD). Thereafter, the feature pattern is transferred from the lithographic layer to the silicon-containing ARC layer using a dry plasma etching process, wherein the first CD in the lithographic layer is reduced to a second CD in the silicon-containing layer and a first edge roughness is reduced to a second edge roughness in the silicon-containing ARC layer. | 08-06-2009 |
20110275219 | HIGH PRESSURE BEVEL ETCH PROCESS - A method of bevel edge processing a semiconductor in a bevel plasma processing chamber in which the semiconductor substrate is supported on a semiconductor substrate support is provided. The method comprises evacuating the bevel etcher to a pressure of 3 to 100 Torr and maintaining RF voltage under a threshold value; flowing a process gas into the bevel plasma processing chamber; energizing the process gas into a plasma at a periphery of the semiconductor substrate; and bevel processing the semiconductor substrate with the plasma. | 11-10-2011 |
20120083129 | APPARATUS AND METHODS FOR FOCUSING PLASMA - Apparatus and methods for plasma etching are disclosed. In one embodiment, a method for etching a plurality of features on a wafer includes positioning the wafer within a chamber of a plasma etcher, generating plasma ions using a radio frequency power source and a plasma source gas, directing the plasma ions toward the wafer using an electric field, and focusing the plasma ions using a plasma focusing ring. The plasma focusing ring is configured to increase a flux of plasma ions arriving at a surface of the wafer to control the formation of the plurality of features and structures associated therewith. | 04-05-2012 |
20140051255 | COPPER DISCOLORATION PREVENTION FOLLOWING BEVEL ETCH PROCESS - A method of bevel edge etching a semiconductor substrate having exposed copper surfaces with a fluorine-containing plasma in a bevel etcher in which the semiconductor substrate is supported on a semiconductor substrate support comprises bevel edge etching the semiconductor substrate with the fluorine-containing plasma in the bevel etcher; evacuating the bevel etcher after the bevel edge etching is completed; flowing defluorinating gas into the bevel etcher; energizing the defluorinating gas into a defluorination plasma at a periphery of the semiconductor substrate; and processing the semiconductor substrate with the defluorination plasma under conditions to prevent discoloration of the exposed copper surfaces of the semiconductor substrate upon exposure, the discoloration occurring upon prolonged exposure to air. | 02-20-2014 |
20140357086 | Methods of Forming a Substrate Opening - A method of forming a substrate opening includes forming a plurality of side-by-side openings in a substrate. At least some of immediately adjacent side-by-side openings are formed in the substrate to different depths relative one another. Walls that are laterally between the side-by-side openings are removed to form a larger opening having a non-vertical sidewall surface where the walls were removed in at least one straight-line vertical cross-section that passes through the sidewall surface orthogonally to the removed walls. | 12-04-2014 |
20150318150 | REAL-TIME EDGE ENCROACHMENT CONTROL FOR WAFER BEVEL - A plasma processing system includes a bottom electrode disposed in a chamber. A lower extended electrode is disposed around the bottom electrode. An upper ceramic plate is disposed above the bottom electrode in an opposing relationship. An upper extended electrode is disposed around the upper ceramic plate. A lower process exclusion zone (PEZ) ring is situated between the lower extended electrode and the bottom electrode. An upper PEZ ring is situated between the upper extended electrode and the upper ceramic plate, with the upper PEZ ring having an RF electrode ring embedded therein. The system also includes a first RF generator for generating RF power for the bottom electrode, a second RF generator for generating RF power for the RF electrode ring embedded in the upper PEZ ring, and a controller for transmitting processing instructions. The processing instructions include power settings for the first and second RF generators. | 11-05-2015 |