Entries |
Document | Title | Date |
20080318410 | METHOD OF FORMING METAL ELECTRODE OF SYSTEM IN PACKAGE - A method for forming a metal electrode of a system in package of a system in package including a multilayer semiconductor device having semiconductor devices stacked in a plurality of layers. The method may include forming a through hole extending through the plurality of layers, forming a combustible material layer having high viscosity at a lower portion of the through hole in order to seal the lower portion thereof, and forming a through electrode by filling copper in the through hole. There is an effect of efficiently forming a through electrode having a large depth corresponding to the height of stacked semiconductor devices in the system in package. Filling copper in a through hole having a large depth-to-width ratio may be efficiently done by OSP coating, electrolysis copper plating, and electro Cu plating processes. | 12-25-2008 |
20090149018 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING AN INTERCONNECT STRUCTURE THAT INCREASES IN IMPURITY CONCENTRATION AS WIDTH INCREASES - The present invention provides a semiconductor device capable of suppressing an increase in electrical resistance of a narrow interconnect, while keeping reliability of a wide interconnect from being degraded. A semiconductor device comprises a plurality of interconnect layers, and an interconnect in at least one interconnect layer among the plurality of interconnect layers contains an impurity, and the wider the interconnect in the at least one interconnect layer is, the higher concentration of the impurity the interconnect contains. | 06-11-2009 |
20090305497 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device, includes: forming a first film pattern above a substrate; forming a plurality of second film patterns like sandwiching the first film pattern from both sides; forming a third film in such a way that an upper surface of the first film pattern and an upper surface and an exposed side surface of each of the plurality of second film patterns are coated with the third film; removing a portion of the third film until the upper surface of the first film pattern is exposed; removing, by a wet process, the first film pattern exposed after the portion of the third film is removed; and removing a remainder of the third film by a dry process after the first film pattern is removed. | 12-10-2009 |
20100184286 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device comprises forming a metal wiring on a semiconductor substrate, forming an insulating film over the semiconductor substrate with the metal wiring, forming a through hole in the insulating film, performing sputter-etching to enlarge an cross section of the through hole, and forming a stacked film. In forming the stacked film, there are formed a first titanium film, a titanium nitride film, and a second titanium film in this order over the insulating film including an inner surface of the through hole at a temperature within a range from 20 to 40° C., and a first Al layer, a second Al layer, and a third Al layer in this order over the second titanium film. | 07-22-2010 |
20130237052 | METHOD OF FABRICATING ARRAY SUBSTRATE FOR IN-PLANE SWITCHING MODE LIQUID CRYSTAL DISPLAY DEVICE - A method of fabricating an array substrate for an in-plane switching (IPS)-mode liquid crystal display (LCD) device, which includes a common electrode and a pixel electrode with a fine line width, are provided. The formation of the pixel electrode and the common electrode of the array substrate includes depositing two different metal layers and patterning the two different metal layers using a selective etching process. Thus, the pixel electrode and a central common electrode may be formed to have a fine line width so that the IPS-mode LCD device can have an improved aperture ratio. | 09-12-2013 |
20190148223 | CONTACT METALLIZATION PROCESS | 05-16-2019 |
20220139775 | INTEGRATED CIRCUIT INTERCONNECT STRUCTURES WITH ULTRA-THIN METAL CHALCOGENIDE BARRIER MATERIALS - Integrated circuit interconnect structures including an interconnect metallization feature with a barrier material comprising a metal and a chalcogen. Introduction of the chalcogen may improve diffusion barrier properties at a given barrier material layer thickness with increasing the barrier layer thickness. A barrier material, such as TaN, may be deposited at minimal thickness, and doped with a chalcogen before or after one or more fill materials are deposited over the barrier material. During thermal processing mobile chalcogen impurities may collect within regions within the barrier material to high enough concentrations for at least a portion of the barrier material to be converted into a metal chalcogenide layer. The metal chalcogenide layer may have greater crystallinity than a remainder of the barrier layer. | 05-05-2022 |