Entries |
Document | Title | Date |
20080206974 | FABRICATION OF SEMICONDUCTOR DEVICE HAVING COMPOSITE CONTACT - A method of fabricating a semiconductor device with a composite contact is provided. The fabrication includes forming the composite contact to a semiconductor layer in a semiconductor structure. The composite contact is formed by forming a DC conducting electrode attached to a semiconductor layer in a semiconductor structure and forming a capacitive electrode that is partially over the DC conducting electrode and extends beyond the DC conducting electrode. The composite contact provides a combined resistive-capacitive coupling to the semiconductor layer. As a result, a contact impedance is reduced when the corresponding semiconductor device is operated at high frequencies. | 08-28-2008 |
20080233727 | Method of manufacturing semiconductor device - Disclosed is a method for manufacturing a semiconductor device. More specifically, in the invention, a gate pattern is formed and then an interlayer insulating pattern burying the space between the gate patterns is formed to ensure the region into which a landing plug contact hole has to be opened, thereby avoiding a problem in that the landing plug contact hole is not opened when forming the landing plug contact hole in a subsequent process. As a result, a failure that may occur in a subsequent test process can be avoided and further a current drivability of a gate, a tWR feature and a timing margin are ensured and thereby improve the device features. | 09-25-2008 |
20080293228 | CMOS Compatible Method of Forming Source/Drain Contacts for Self-Aligned Nanotube Devices - A method is provided for forming metal contacts to nanotube devices in a standard CMOS process flow. In accordance with one feature, a method for forming source/drain contacts to nanotube devices acting as FETs is provided while minimizing metal contamination to the complementary metal oxide semiconductor (CMOS) circuitry in a standard CMOS process flow. The method includes forming nanotube devices on a semiconductor substrate during a front end process of a CMOS process flow, while forming metallic contacts for the nanotube devices during a back end process of the CMOS process flow. This enables the formation of nanotube devices to be integrated within a standard CMOS process flow, thereby opening avenues to commercializing new generation of RFCMOS technology where superior RF/analog circuitry based on nanotube devices can be combined with digital circuitry based on standard silicon CMOS. | 11-27-2008 |
20090011583 | Method of manufacturing a semiconductor device - A gate structure is formed on a substrate. An insulating interlayer is formed covering the gate structure. The substrate is heat treated while exposing a surface of the insulating interlayer to a hydrogen gas atmosphere. A silicon nitride layer is formed directly on the interlayer insulating layer after the heat treatment and a metal wiring is formed on the insulating interlayer. The metal wiring may include copper. Heat treating the substrate while exposing a surface of the interlayer insulating layer to a hydrogen gas atmosphere may be preceded by forming a plug through the first insulating interlayer that contacts the substrate, and the metal wiring may be electrically connected to the plug. The plug may include tungsten. | 01-08-2009 |
20090075465 | METHODS OF FORMING A CONDUCTIVE INTERCONNECT IN A PIXEL OF AN IMAGER AND IN OTHER INTEGRATED CIRCUITRY - A method of forming conductive interconnects includes forming a node of a circuit component on a substrate. A conductive metal line is formed at a first metal routing level that is elevationally outward of the circuit component. Insulative material is deposited above the first metal routing level over the conductive metal line and the circuit component. In a common masking step, a first opening is etched through the insulative material to the conductive metal line and a second opening is etched through the insulative material to the node of the circuit component that is received elevationally inward of the conductive metal line. Conductive material is concurrently deposited to within the first and second openings in respective conductive connection with the conductive metal line and the node of the circuit component. A first metal line at a second metal routing level that is above the first metal routing level is formed in conductive connection with the conductive material in the first opening. A second metal line at the second metal routing level is formed in conductive connection with the conductive material in the second opening. | 03-19-2009 |
20090117724 | MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device includes the steps of forming an insulating film having a prescribed repetition pattern on one surface of a semiconductor substrate and then depositing semiconductor layers on the one surface of the semiconductor substrate; forming trenches from the other surface of the semiconductor substrate in such a manner that the trenches come into contact with the semiconductor layer, that plural trenches are formed for each semiconductor chip to be formed on the semiconductor substrate, and that at least one pattern of the insulating film is exposed through the bottom of each trench; and covering the inside surfaces of the trenches and the other surface of the semiconductor substrate with a metal electrode. | 05-07-2009 |
20090137107 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device according to an embodiment of the invention includes forming patterns on a substrate, depositing a light absorption layer on the patterns, processing the light absorption layer to form a first region which includes a first type of pattern included in the patterns and is coated with the light absorption layer having a first thickness, a second region which includes a second type of pattern included in the patterns and is coated with the light absorption layer having a second thickness thinner than the first thickness, and a third region which includes a third type of pattern included in the patterns and is coated with the light absorption layer having a third thickness thinner than the second thickness, and annealing the substrate by radiating light on the substrate. | 05-28-2009 |
20090163008 | Lithographically Space-Defined Charge Storage Regions In Non-Volatile Memory - Lithographically-defined spacing is used to define feature sizes during fabrication of semiconductor-based memory devices. Sacrificial features are formed over a substrate at a specified pitch having a line size and a space size defined by a photolithography pattern. Charge storage regions for storage elements are formed in the spaces between adjacent sacrificial features using the lithographically-defined spacing to fix a gate length or dimension of the charge storage regions in a column direction. Unequal line and space sizes at the specified pitch can be used to form feature sizes at less than the minimally resolvable feature size associated with the photolithography process. Larger line sizes can improve line-edge roughness while decreasing the dimension of the charge storage regions in the column direction. Additional charge storage regions for the storage elements can be formed over the charge storage regions so defined, such as by depositing and etching a second charge storage layer to form second charge storage regions having a dimension in the column direction that is less than the gate length of the first charge storage regions. | 06-25-2009 |
20090176357 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor device comprises a conductive pad formed in a semiconductor substrate. The semiconductor device further includes a conductive pattern overlying a peripheral region of the conductive pad. The conductive pattern has an opening to expose another region of the conductive pad. The semiconductor device also includes a conductive contact extending through the opening. The conductive contact is electrically connected to the conductive pad. As a result, manufacturing cost for the semiconductor device may be reduced while manufacturing throughput may be improved. | 07-09-2009 |
20090181529 | Method of forming a contact hole and method of manufacturing a semiconductor device having the same - In a method of forming a contact hole and a method of manufacturing a semiconductor device having the same, a first insulation interlayer is formed on a substrate. A dummy pattern is formed on the first insulation interlayer. A second insulation interlayer is formed to cover the dummy pattern. A photoresist pattern is formed on the second insulation interlayer. The photoresist pattern has an exposed portion. The dummy pattern under the photoresist pattern is arranged to cross over the exposed portion of the photoresist pattern. The first and second insulation interlayers are etched using the photoresist pattern and the dummy pattern as an etching mask, to form a plurality of contact holes on both sides of the dummy pattern. Accordingly, the contact holes may be formed to have a smaller width. | 07-16-2009 |
20090186473 | Methods of Forming a Conductive Interconnect in a Pixel of an Imager and in Other Integrated Circuitry - A method of forming conductive interconnects includes forming a node of a circuit component on a substrate. A conductive metal line is formed at a first metal routing level that is elevationally outward of the circuit component. Insulative material is deposited above the first metal routing level over the conductive metal line and the circuit component. In a common masking step, a first opening is etched through the insulative material to the conductive metal line and a second opening is etched through the insulative material to the node of the circuit component that is received elevationally inward of the conductive metal line. Conductive material is concurrently deposited to within the first and second openings in respective conductive connection with the conductive metal line and the node of the circuit component. A first metal line at a second metal routing level that is above the first metal routing level is formed in conductive connection with the conductive material in the first opening. A second metal line at the second metal routing level is formed in conductive connection with the conductive material in the second opening. | 07-23-2009 |
20090191698 | TFT ARRAY PANEL AND FABRICATING METHOD THEREOF - Disclosed is display part such as a TFT array panel comprising an aluminum layer, and a molybdenum layer formed on the aluminum layer. The thickness of the molybdenum layer may be about 10% to about 40% the thickness of the aluminum layer. As a result, a top surface of the aluminum layer may have a width about equal to a bottom surface of the molybdenum layer. | 07-30-2009 |
20090203203 | METHOD FOR THE FABRICATION OF A TRANSISTOR GATE THAT INCLUDES THE BREAKDOWN OF A PRECURSOR MATERIAL INTO AT LEAST ONE METALLIC MATERIAL, USING AT LEAST ONE - A microelectronic method for the fabrication of a transistor gate using a precursor material that is suitable for being broken down into at least one metallic material after having been exposed to an electron beam. The invention applies in particular to the fabrication of multi-channel transistors, of the FinFET, suspended-channel, ITS or GAA type. | 08-13-2009 |
20090209096 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING DECREASED CONTACT RESISTANCE - A method for manufacturing a semiconductor device includes the steps of forming an insulation layer having a contact hole, on a semiconductor substrate, forming a Co layer on the insulation layer including a surface of the contact hole, conducting primary annealing to allow the Co layer and a portion of the semiconductor substrate to react with each other such that a CoSi layer is formed at an interface therebetween. The resultant semiconductor substrate is cleaned to remove a portion of the Co layer not having reacted in the primary annealing. A barrier layer is formed on the insulation layer, the CoSi layer, and the surface of the contact hole. A secondary annealing is conducted to convert the CoSi layer into a CoSi | 08-20-2009 |
20090258483 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - Embodiments relate to a method of manufacturing a semiconductor device that may simplify a manufacturing process and may reduce process costs. According to embodiments, the method may include simultaneously forming a first gate of a first device area and a second gate of a second device area, patterning a PMD layer to form a first contact hole exposing the first gate, depositing and planarizing a high dielectric constant material and first and second metallic materials on the semiconductor substrate to expose PMD layer, forming an insulating layer, a metal layer and a third gate in the first contact hole, patterning the PMD layer to form a second contact hole exposing the second gate, and depositing a third metallic material on the semiconductor substrate and planarizing it such that the PMD layer is exposed, thereby forming a contact in the second contact hole. | 10-15-2009 |
20090269915 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE PREVENTING LOSS OF JUNCTION REGION - A method for manufacturing a semiconductor device includes forming an insulation layer having a contact hole on a semiconductor substrate. A metal silicide layer is deposited on a surface of the contact hole and the insulation layer to have a concentration gradient that changes from a silicon-rich composition to a metal-rich composition, with the lower portion of the metal silicide layer having the silicon-rich composition and the upper portion of the metal silicide layer having the metal-rich composition. The metal silicide layer is then annealed so that the compositions of metal and silicon in the metal silicide layer become uniform. | 10-29-2009 |
20090286386 | WIRE STRUCTURE, METHOD OF FORMING WIRE, THIN FILM TRANSISTOR SUBSTRATE, AND METHOD OF MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE - Provided are a wire structure, a method of forming a wire, a thin film transistor (TFT) substrate, and a method of manufacturing the TFT substrate. The wire structure includes a barrier layer disposed on a lower structure, a copper conductive layer comprising copper or copper alloy disposed on the barrier layer, an intermediate layer comprising copper nitride disposed on the copper conductive layer, and a capping layer disposed on the intermediate layer. | 11-19-2009 |
20090298271 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device prevents failure of self-aligned contacts to improve the yield of the semiconductor device. A height of a device isolating film is larger than a height of an active region. A recess region of the device isolating film is planarized by a wet etching process to remove a hard mask layer when a recess gate is etched. A contact plug is then formed in the recess region between adjacent recess gates. | 12-03-2009 |
20090317966 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method has forming a metal film containing platinum by depositing a metal on a source/drain diffusion layer primarily made of silicon formed on a semiconductor substrate and on a device isolation insulating film; forming a silicide film by silicidation of an upper part of the source/drain diffusion layer by causing a reaction between silicon in the source/drain diffusion layer and the metal on the source/drain diffusion layer by a first heating processing; forming a metal oxide film by a oxidation processing to oxidize selectively at least a surface of the metal film on the device isolation insulating film; increasing the concentration of silicon in the silicide film by a second heating processing; and selectively removing the metal oxide film and an unreacted part of the metal film on the device isolation insulating film. | 12-24-2009 |
20100015789 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A semiconductor device | 01-21-2010 |
20100022079 | SYSTEMS AND METHODS FOR REDUCING CONTACT TO GATE SHORTS - A method for reducing contact to gate shorts in a semiconductor device and the resulting semiconductor device are described. In one embodiment, a gate is formed on a substrate, a contact is formed on the gate and the substrate, and an insulator is formed between the gate and the contact. The insulator may be formed by oxidizing the gate to form a dielectric between the contact and the gate after the contact is formed on the gate. | 01-28-2010 |
20100029072 | Methods of Forming Electrical Interconnects Using Thin Electrically Insulating Liners in Contact Holes - Methods of forming integrated circuit devices include forming an electrically insulating layer having a contact hole therein, on a substrate, and then depositing an electrically insulating liner onto a sidewall of the contact hole using an atomic layer deposition (ALD) technique. This electrically insulating liner, which may include gelatinous silica or silicon dioxide, for example, may be deposited to a thickness in a range from 40 Å to 100 Å. A portion of the electrically insulating liner is then removed from a bottom of the contact hole and a barrier metal layer is then formed on the electrically insulating liner and on a bottom of the contact hole. The step of forming the barrier metal layer may be followed by filling the contact hole with a metal interconnect. | 02-04-2010 |
20100075491 | DRY ETCHING METHOD OF SILICON COMPOUND FILM - A silicon compound film is dry etched by parallel-plate type dry etching using an etching gas including at least COF | 03-25-2010 |
20100081265 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a first film on a target film; forming resist patterns on the first film; processing the first film with the resist patterns to form first patterns including: periodic patterns; and aperiodic patterns; removing the resist patterns; forming a second film over the target film; processing the second film to form second side wall patterns on side walls of the first patterns; removing the periodic patterns; and processing the target film with the aperiodic patterns and the second side wall patterns, thereby forming a target patterns including: periodic target patterns; aperiodic target patterns; and dummy patterns arranged between the periodic target patterns and the aperiodic patterns and arranged periodically with the periodic target patterns. | 04-01-2010 |
20100105198 | Gate Electrode of semiconductor device and method of forming the same - A method of forming a gate electrode of a semiconductor device includes forming a first polysilicon layer in a peripheral circuit region of a substrate, forming a barrier layer on the first polysilicon layer, the barrier layer providing an ohmic contact, forming a stack structure including a tunneling insulation layer, an electric charge storing layer, and a blocking insulation layer in a memory cell region of the substrate, forming a second polysilicon layer on the barrier layer and the blocking insulation layer, and siliciding the second polysilicon layer and forming a silicide gate electrode. | 04-29-2010 |
20100120238 | SEMICONDUCTOR MANUFACTURING APPARATUS AND METHOD - A first aspect of the present invention provides a semiconductor manufacturing apparatus including: a load lock chamber; a transfer chamber; and a treatment chamber | 05-13-2010 |
20100124816 | Reticles and methods of forming semiconductor devices - A reticle may include a transparent substrate, a first phase pattern having a first thickness disposed on the transparent substrate, a chrome pattern disposed on the first phase pattern, and a second phase pattern having a second thickness disposed on the transparent substrate. The first phase pattern and the chrome pattern may be disposed to overlap with each other. A method of forming a semiconductor device may include forming a gate insulating layer and a gate electrode on a semiconductor substrate, forming a spacer on a sidewall of the gate electrode, forming an interlayer insulating layer over an exposed surface of the semiconductor substrate, and forming a common contact hole. The contact hole may include a first portion exposing the gate electrode, a second portion exposing the semiconductor substrate, and a third portion connecting the first and second portions, by patterning the interlayer insulating layer. | 05-20-2010 |
20100124817 | METHOD OF FABRICATING SELF-ALIGNED CONTACT PAD USING CHEMICAL MECHANICAL POLISHING PROCESS - A method of fabricating a self-aligned contact pad (SAC) includes forming stacks of a conductive line and a capping layer on a semiconductor substrate, spacers covering sidewalls of the stacks, and an insulation layer filling gaps between the stacks and exposing the top of the capping layer, etching the capping layer to form damascene grooves, forming a plurality of first etching masks with a material different from that of the capping layer to fill the damascene grooves without covering the top of the insulation layer, and forming a second etching mask having an opening region that exposes some of the first etching masks and a portion of the insulation layer located between the first etching masks. The method further includes etching the portion of the insulation layer exposed by the opening region using the first and second etching masks to form a plurality of opening holes, removing the second etching mask, forming a conductive layer filling the opening holes to cover the remaining first etching masks and performing a chemical mechanical polishing (CMP) process on the conductive layer using the capping layer as a polishing end point to remove the first etching masks such that a plurality of SAC pads separated from each other are formed that fill the opening holes. | 05-20-2010 |
20100144133 | METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - A method for manufacturing a semiconductor memory device, includes: forming a stacked unit above a semiconductor substrate, the stacked unit including a plurality of insulating layers alternately stacked with a plurality of electrode layers, the electrode layers being formed of a semiconductor; making a hole in the stacked unit to pass through the electrode layers and the insulating layers; forming an insulating film on a side wall of the hole, the insulating film including a charge storage layer; forming a semiconductor layer in an interior of the hole to align in a stacking direction of the electrode layers and the insulating layers to form a memory string by multiply connecting memory cells in the stacking direction, the memory cell including the electrode layer, the charge storage layer opposing the electrode layer, and the semiconductor layer opposing the charge storage layer; making a trench in a portion of the stacked unit proximal to the memory string to pass through the electrode layers and the insulating layers; forming a metal film on a side wall of the trench; forming a cap film to cover the metal film and fill into the trench; performing heat treatment in the state where the cap film is filled into the trench to cause the metal film to react with the semiconductor of the electrode layers and form a compound between the semiconductor and the metal film at portions of the electrode layers contacting the metal film; removing the cap film and an unreacted excess portion of the metal film; and providing a dielectric substance in the trench after the cap film and the unreacted excess portion are removed. | 06-10-2010 |
20100167513 | DUAL ALIGNMENT STRATEGY FOR OPTIMIZING CONTACT LAYER ALIGNMENT - An improved method for optimizing layer registration during lithography in the fabrication of a semiconductor device is disclosed. In one example, the method comprises optimizing contact layer registration of an SRAM device having a plurality of transistors having active and gate region features extending generally along a channel length (X) direction and a channel width (Y) direction, respectively. The method comprises aligning a contact layer to a gate layer in the channel length direction (X), using gate layer overlay marks to control the alignment of the contact layer in the channel length direction (X) of the semiconductor device. The method further includes aligning the contact layer to an active layer in the channel width direction (Y), using active layer overlay marks to control the alignment of the contact layer in the channel width direction (Y) of the semiconductor device. | 07-01-2010 |
20100173485 | Method of manufacturing a non-volatile memory device - A method of manufacturing a non-volatile memory device providing a semiconductor layer in which a cell region and a peripheral region are defined, sequentially forming a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer on the cell region and the peripheral region, forming a trench for exposing a portion of the first conductive layer of the peripheral region, wherein the trench is formed by removing portions of the second conductive layer and the second insulating layer in the peripheral region, performing a trimming operation for removing portions of the second conductive layer and the second insulating layer of the cell region, forming a spacer on a side surface of the trench, and forming a silicide layer that is electrically connected to the first conductive layer, wherein the silicide layer is formed by performing a silicidation process on the spacer. | 07-08-2010 |
20100184280 | METHOD OF FORMING METAL ION TRANSISTOR - A method of forming a metal ion transistor comprises forming a first electrode in a first isolation layer; forming a second isolation layer over the first isolation layer; forming a first cell region of a low dielectric constant (low-k) dielectric over the first electrode in the second isolation layer, the first cell region isolated from the second isolation layer; forming a cap layer over the second isolation layer and the first cell region, at least thinning the cap layer over the first cell region; depositing a layer of the low-k dielectric over the second isolation layer and the first cell region; forming metal ions in the low-k dielectric layer; patterning the low-k dielectric layer to form a second cell region; sealing the second cell region using a liner; and forming a second electrode contacting the second cell region and a third electrode contacting the second cell region. | 07-22-2010 |
20100190326 | Method for Fabricating Semiconductor Memory Device - A method for fabricating a semiconductor memory device includes: forming a lower conductive layer over a semiconductor substrate; forming an insulation layer over the lower conductive layer; etching the insulation layer to form a contact hole that exposes a portion of the lower conductive layer; forming a contact plug in the contact hole; doping the contact plug by performing a plasma doping process while varying a temperature of regions the semiconductor substrate; and forming an upper conductive layer connected with the lower conductive layer through the contact plug. | 07-29-2010 |
20100190327 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND DESIGN SUPPORT APPARATUS - A semiconductor device manufacturing method includes: forming a conductive film over a substrate; forming an assist pattern on the conductive film; forming a metal film to cover the conductive film and the assist pattern; etching back the metal film to form at least one side wall film on a side surface of the assist pattern; removing the assist pattern; forming at least one resist pattern to selectively expose a portion of the conductive film and a portion of the side wall film; performing etching using the resist pattern as a mask to remove the exposed portion of the side wall film; and etching the conductive film using the side wall film as a mask to form a gate electrode and a contact region electrically connected to the gate electrode. | 07-29-2010 |
20100190328 | Self Aligned Silicided Contacts - Structures and methods of forming self aligned silicided contacts are disclosed. The structure includes a gate electrode disposed over an active area, a liner disposed over the gate electrode and at least a portion of the active area, an insulating layer disposed over the liner. A first contact plug is disposed in the insulating layer and the liner, the first contact plug disposed above and in contact with a portion of the active area, the first contact plug including a first conductive material. A second contact plug is disposed in the insulating layer and the liner, the second contact plug disposed above and in contact with a portion of the gate electrode, the second contact plug includes the first conductive material. A contact material layer is disposed in the active region, the contact material layer disposed under the first contact plug and includes the first conductive material. | 07-29-2010 |
20100203714 | SEMICONDUCTOR STORAGE DEVICE - It is intended to provide a semiconductor device having a reduced thickness of a silicon nitride film on an outer periphery of a gate electrode of an SGT. A semiconductor device of the present invention is constructed using a MOS transistor which has a structure where a drain, a gate and a source are arranged in a vertical direction with respect to a substrate, and the gate is formed to surround a pillar-shaped semiconductor layer. The semiconductor device comprises: a silicide layer formed in an upper surface of each of upper and lower diffusion layers formed in upper and underneath portions of the pillar-shaped semiconductor layer, in a self-alignment manner, wherein the silicide layer is formed after forming a first dielectric film on a sidewall of the pillar-shaped semiconductor layer to protect the sidewall of the pillar-shaped semiconductor layer during formation of the silicide layer; and a second dielectric film formed, after forming the silicide layer and then removing the first dielectric film, in such a manner as to cover a source/drain region formed in the underneath portion of the pillar-shaped semiconductor layer, the gate electrode formed on the sidewall of the pillar-shaped semiconductor layer, and a source/drain region formed on the upper portion of the pillar-shaped semiconductor layer. | 08-12-2010 |
20100210098 | SELF-ALIGNED CONTACT - A method of forming contacts for semiconductor devices, the method including depositing an inter-level dielectric (ILD) over a plurality of gate stacks, in which the divots within the inter-level dielectric layer are defined by the spaces between the gate stacks, filling the divots with an initial fill material, depositing a masking material on the dielectric over the gate stacks, and selectively etching the fill material to form contact vias. The fill material may be a self-assembly material such as a multi-block copolymer in which the blocks self organize vertically within the divots, so that a selective etch of the block material will remove the vertically organized blocks from the divot, but leave at least one block over the gate regions. In another embodiment, the fill material may be a metal, and the masking material may be a parylene based polymer. | 08-19-2010 |
20100210099 | METHODS OF FORMING A METAL SILICIDE LAYER FOR SEMICONDUCTOR DEVICES - Methods of forming a metal silicide layer are provided that include exposing polysilicon through just dry etching (JDE) and recessesing an oxide layer through chemical dry etching (CDE). In particular, dry etching is primarily performed to an extent to expose the polysilicon. Then, CDE is secondarily performed to expose the polysilicon. The CDE process includes selecting an etchant source among combinations of NF | 08-19-2010 |
20100221904 | Process for Manufacturing a Non-Volatile Memory Electronic Device Integrated on a Semiconductor Substrate and Corresponding Device - A non-volatile memory electronic device integrated on a semiconductor substrate includes non-volatile memory cells organized in a matrix, and circuitry associated therewith. Each memory cell includes a gate electrode projecting from the semiconductor substrate. Source and drain regions are formed in the semiconductor substrate and aligned with the gate electrodes. At least one portion of the gate electrodes are insulated from each other by air-gaps which are closed on top by a third non-conforming dielectric layer. | 09-02-2010 |
20100227460 | METHOD OF MANUFACTURING NOR FLASH MEMORY - In a method of manufacturing a NOR flash memory, when the memory device dimensions are further reduced, the forming of spacers at two lateral sides of the gate structures is omitted, and a space between two gate structures can be directly filled up with a dielectric spacer or a shallow trench isolation (STI) layer. Therefore, it is possible to avoid the problem of increased difficulty in manufacturing memory device caused by forming spacers in an extremely small space between the gate structures. The method also enables omission of the self-alignment step needed to form the salicide layer. Therefore, the difficulty in self-alignment due to the extremely small space between the gate structures can also be avoided. | 09-09-2010 |
20100227461 | METHOD FOR THE FABRICATION OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In fabrication processes of semiconductor integrated circuit devices, a technique for improving the carrier mobility has been frequently employed. This technique utilizes strain caused by the stress typically of a silicon nitride film. With this, a batchwise wet processing with hot phosphoric acid should be performed so as to highly selectively remove the silicon nitride film over a complicated device structure on a front side of a wafer. This processing removes also a silicon nitride film on the back side of the wafer, and after a series of strain-imparting processes, a polysilicon member is exposed from the back side surface of the wafer. However, common techniques for cleaning typically of back sides of wafers may not sufficiently effectively clean the back side containing a polysilicon as a main component, because these techniques are designed to be adopted to a back side containing, for example, a silicon nitride film, but the polysilicon and the silicon nitride film differ from each other in properties. To void the problem, a wet cleaning process is performed before a lithography process. The wet cleaning process includes two steps, in which FPM cleaning and SPM cleaning are performed in this order. | 09-09-2010 |
20100227462 | PAD STRUCTURE FOR LIQUID CRYSTAL DISPLAY AND METHOD OF MANUFACTURING THEREOF - A liquid crystal display has a pad structure. The pad structure includes at least one pad formed on a substrate, an insulating film formed on the pad, and at least one conductive layer connected to the pad through contact holes defined through the insulating film. The insulating film covers side surfaces of the pad and a portion of the substrate adjacent to the side surfaces of the pad. | 09-09-2010 |
20100227463 | Methods of Forming Pad Structures and Related Methods of Manufacturing Recessed Channel Transistors that Include Such Pad Structures - Methods of forming pad structures are provided in which a first contact region and second contact regions are formed in an active region of a substrate. An insulating interlayer is formed on the substrate. The insulating interlayer has a first opening that exposes the first contact region and the second contact regions. First conductive pads are formed in the first opening. Each first conductive pad is in electrical contact with a respective one of the second contact regions. Spacers are formed, where each spacer is on a sidewall of a respective one of the first conductive pads. Finally, a second conductive pad is formed between the first conductive pads and in electrical contact with the first contact region to complete the pad structure. | 09-09-2010 |
20100285658 | INTEGRATING A FIRST CONTACT STRUCTURE IN A GATE LAST PROCESS - A method is provided that includes providing a substrate; forming a transistor in the substrate, the transistor having a dummy gate; forming a dielectric layer over the substrate and transistor; forming a contact feature in the dielectric layer; and after forming the contact feature, replacing the dummy gate of the transistor with a metal gate. An exemplary contact feature is a dual contact. | 11-11-2010 |
20100330791 | Method for Fabricating Contacts in Semiconductor Device - Disclosed is a method for fabricating a contact in a semiconductor device, including: obtaining a pattern layout including bit lines arranged across a cell matrix region of a semiconductor substrate, cell storage node contacts arranged to pass through a portion of a first interlayer insulation layer between the bit lines, and dummy storage node contacts additionally arranged in an end of the arrangement of the cell storage node contacts; and forming the cell storage node contacts and the dummy storage node contacts using the pattern layout. | 12-30-2010 |
20100330792 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes the steps of forming conductive patterns on a substrate; forming an interlayer dielectric between the conductive patterns; defining contact holes in the interlayer dielectric to expose portions of the substrate between the conductive patterns; forming a first conductive layer on a surface including the contact holes; forming contact plugs in such a way as to be isolated in the respective contact holes, by etching a surface of the first conductive layer to expose upper end surfaces of the conductive patterns; etching a partial thickness of the conductive patterns so that the upper end surfaces of the conductive patterns are lower than an upper end surface of the interlayer dielectric; and forming an insulation layer on the resultant structure. | 12-30-2010 |
20100330793 | METHOD FOR FORMING SEMICONDUCTOR DEVICE - A method for forming a highly integrated semiconductor device having multiplayer conductive lines is presented. The method includes the operations of forming, etching, burying and forming. The first forming operation includes forming a line-type conductive layer on a semiconductor substrate including a buried gate to expose the gate. The etching operation includes etching the conductive layer to expose at least a region between one side of an active area defined in the semiconductor substrate and an opposite side of the neighboring active area, both the active areas being arranged next to each other in a major axis direction of the gate. The burying operation includes burying a first insulating film in the etched line-type conductive layer. The second forming operation includes forming a bit line passing through the center of the active area in a direction perpendicular to the major axis direction of the gate. | 12-30-2010 |
20110034016 | METHOD OF MANUFACTURING A CMOS DEVICE WITH ZERO SOFT ERROR RATE - A CMOS device and method of manufacture is provided for producing an integrated circuit that is not susceptible to various soft errors such as single-event upsets, multi-bit upsets or single-event latchup. The CMOS device and method utilizes a new and novel well architecture in conjunction with metal source/drain electrodes to eliminate soft errors. In one embodiment, the CMOS device uses a first metal source/drain material for the NMOS device and a second metal source/drain material for the PMOS device. The CMOS device further uses a multi-layered well-structure with a shallow N-well and a buried P-well for the PMOS device and a shallow P-well and a buried N-well for the NMOS device. | 02-10-2011 |
20110053365 | METHOD OF MANUFACTURING GATE STRUCTURE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING THE SAME - In a method for manufacturing a semiconductor device, a silicon oxide layer is formed on a substrate. The silicon oxide layer is treated with a solution comprising ozone. Then, a conductive layer is formed on the silicon oxide layer treated with the solution. | 03-03-2011 |
20110053366 | METHODS OF FABRICATING MEMORY DEVICES - Methods of fabricating a memory device can include forming a plurality of wordlines on a semiconductor substrate. A ground select line can be formed on a first side of the wordlines. A string select line can be formed on a second side of the wordlines. The wordlines can extend between the ground select line and the string select line. First spacers may be formed between the wordlines, between the ground select line and an adjacent one of the wordlines and between the string select line and an adjacent one of the wordlines. Second spacers can be formed on sidewalls of the ground select line and the string select line displaced from the first spacers. The second spacers can be formed from a different material than the first spacers. | 03-03-2011 |
20110086503 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH BURIED GATES - A method for fabricating a semiconductor device includes providing a substrate including cell regions and peripheral regions; selectively forming a gate conductive layer over the substrate in the peripheral regions, forming a sealing layer over the substrate with the gate conductive layer formed thereon, forming an insulation layer over the sealing layer to cover the substrate with the gate conductive layer formed on the substrate, planarizing the insulation layer to expose the sealing layer formed over the gate conductive layer, and forming a plurality of plugs in the cell regions, the plurality of the plugs penetrating the insulation layer and the sealing layer. | 04-14-2011 |
20110092060 | METHODS OF FORMING WIRING STRUCTURES - A semiconductor memory wiring method includes: receiving a substrate having a cell array region and a peripheral circuit region; depositing a first insulating layer on the substrate; forming a first contact plug in the cell array region, the first contact plug having a first conductive material extending through the first insulating layer; forming a first elongated conductive line at substantially the same time as forming the first contact plug, the first elongated conductive line having the first conductive material directly covering and integrated with the first contact plug; forming a second contact plug in the peripheral circuit region at substantially the same time as forming the first contact plug, the second contact plug having the first conductive material extending through the first insulating layer; and forming a second elongated conductive line at substantially the same time as forming the second contact plug, the second elongated conductive line having the first conductive material directly covering and integrated with the second contact plug. | 04-21-2011 |
20110097884 | METHOD TO ATTAIN LOW DEFECTIVITY FULLY SILICIDED GATES - A method of forming fully silicided (FUSI) gates in MOS transistors which is compatible with wet etch processes used in source/drain silicide formation is disclosed. The gate silicide formation step produces a top layer of metal rich silicide which is resistant to removal in wet etch processes. A blocking layer over active areas prevents source/drain silicide formation during gate silicide formation. Wet etches during removal of the blocking layer and source/drain metal strip do not remove the metal rich gate silicide layer. Anneal of the gate silicide to produce a FUSI gate with a desired stoichiometry is delayed until after formation of the source/drain silicide. The disclosed method is compatible with nickel and nickel-platinum silicide processes. | 04-28-2011 |
20110159677 | METHOD OF FABRICATING LANDING PLUG CONTACT IN SEMICONDUCTOR MEMORY DEVICE - A landing plug contact in a semiconductor memory device is fabricated by: forming gate spacer layers at sides of the gate stacks to define a first contact hole and a second contact hole, where a landing plug contact will be formed between the gate spacer layers of the first contact hole and no landing plug contact is formed in the second contact hole; forming a conductive layer to fill at least the first and second contact holes; forming a hard mask pattern over the conductive layer to expose the conductive layer filling the second contact hole; removing the conductive layer filling the second contact hole by an etching process; forming an insulation layer to fill at least the second contact hole where the conductive layer is removed; and forming a landing plug contact within the contact hole by performing a planarization process on the insulation layer and the conductive layer. | 06-30-2011 |
20110165767 | SELECTIVE IMPLEMENTATION OF BARRIER LAYERS TO ACHIEVE THRESHOLD VOLTAGE CONTROL IN CMOS DEVICE FABRICATION WITH HIGH-k DIELECTRICS - The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric. | 07-07-2011 |
20110171818 | METHODS OF FORMING A GATE STRUCTURE - A method of forming a gate structure can be provided by forming a tunnel insulation layer on a substrate and forming a floating gate on the tunnel insulation layer. A dielectric layer pattern can be on the floating gate and a control gate can be formed on the dielectric layer pattern, which can be provided by forming a first conductive layer pattern on the dielectric layer pattern. A metal ohmic layer pattern can be formed on the first conductive layer pattern. A diffusion preventing layer pattern can be formed on the metal ohmic layer pattern. An amorphous layer pattern can be formed on the diffusion preventing layer pattern forming a second conductive layer pattern on the amorphous layer pattern. The floating gate can be further formed by forming an additional first conductive layer pattern on the tunnel insulation layer. An additional metal ohmic layer pattern can be formed on the additional first conductive layer pattern. An additional diffusion preventing layer can be formed pattern on the additional metal ohmic layer pattern. An additional amorphous layer pattern can be formed on the additional diffusion preventing layer pattern and an additional second conductive layer pattern can be formed on the additional amorphous layer pattern. | 07-14-2011 |
20110183505 | METHODS OF FORMING FINE PATTERNS IN INTEGRATED CIRCUIT DEVICES AND METHODS OF MANUFACTURING INTEGRATED CIRCUIT DEVICES INCLUDING THE SAME - A method of fabricating an integrated circuit device includes forming first and second preliminary mask structures on a hard mask layer in respective first and second regions of the substrate. Spacers are formed on opposing sidewalls of the first and second preliminary mask structures, and the first preliminary mask structure is selectively removed from between the spacers in the first region. The hard mask layer is etched using the spacers and the second preliminary mask structure as a mask to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region and a second mask pattern including the opposing sidewall spacers and the second preliminary mask structure therebetween in the second region. An insulation layer is patterned using the first and second mask patterns as respective masks to define a first trench in the first region and a second trench in the second region having a greater width than the first trench, and first and second conductive patterns are formed in the first and second trenches. | 07-28-2011 |
20110195565 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion thereof. A trench is disposed in the workpiece extending at least through the buried layer. At least one sinker contact is disposed in the top portion of the workpiece. The at least one sinker contact is proximate sidewalls of at least a portion of the trench and is adjacent the buried layer. An insulating material is disposed on the sidewalls of the trench. A conductive material is disposed within the trench and is coupled to a lower portion of the workpiece. | 08-11-2011 |
20110207313 | Semiconductor Devices and Methods of Fabricating the Same - Semiconductor devices and a methods of fabricating the semiconductor devices are provided. The methods may include forming a pattern on a substrate, forming a capping dielectric layer on the pattern, and thermally processing the substrate. After thermally processing the substrate, the methods may further include forming a diffusion barrier layer by a nitride process that may include supplying nitrogen to the capping dielectric layer. The methods may also include forming an etching stop layer on the diffusion barrier layer, forming an inter-layer dielectric layer on the etching stop layer, and planarizing the inter-layer dielectric layer. | 08-25-2011 |
20110250744 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes a first block having first memory cells and first select transistors, a second block having second memory cells and second select transistors, and arranged adjacent to the first block in a first direction, the second select transistor being arranged to face the first select transistor and commonly having a diffusion region with the first select transistor, a first interconnection layer provided on the diffusion region between the first and second blocks and extending in a second direction, and a second interconnection layer having a first portion provided in contact with an upper portion of the first interconnection layer and extending to a portion outside the first interconnection layer, and a second portion extending in the second direction and connected to the first portion in a portion outside a portion on the first interconnection layer. | 10-13-2011 |
20110256701 | METHOD FOR TUNING THE WORK FUNCTION OF A METAL GATE OF THE PMOS DEVICE - The present application discloses a method for tuning the work function of a metal gate of the PMOS device, comprising the steps of depositing a layer of metal nitride or a metal on a layer of high-k gate dielectric by physical vapor deposition (PVD), as a metal gate; doping the metal gate with dopants such as Al, Pt, Ru, Ga, Ir by ion implantation; and driving the doped metal ions to the interface between the high-k gate dielectric and interfacial SiO | 10-20-2011 |
20110256702 | THIN FILM TRANSISTOR AND DISPLAY DEVICE, AND METHOD FOR MANUFACTURING THEREOF - The present invention discloses a display device and a manufacturing method thereof by which a manufacturing process can be simplified. Further, the present invention discloses technique for manufacturing a pattern such as a wiring into a desired shape with good controllability. A method for forming a pattern for constituting the display device according to the present invention comprises the steps of forming a first region and a second region; discharging a composition containing a pattern formation material to a region across the second region and the first region; and flowing a part of the composition discharged to the first region into the second region; wherein wettability with respect to the composition of the first region is lower than that of the second composition. | 10-20-2011 |
20110256703 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to one embodiment includes: a substrate having an element region where a semiconductor element is formed; a via hole formed in a portion of the substrate adjacent to the element region; a conducting portion provided in the via hole via an insulating layer; and a buffer layer provided between the substrate and the insulating layer, wherein the buffer layer is made of a material in which a difference in thermal expansion coefficient between the substrate and the buffer layer is smaller than that between the substrate and the insulating layer. | 10-20-2011 |
20110269303 | Reduced Defectivity in Contacts of a Semiconductor Device Comprising Replacement Gate Electrode Structures by Using an Intermediate Cap Layer - Superior contact elements may be formed in semiconductor devices in which sophisticated replacement gate approaches may be applied. To this end, a dielectric cap layer is provided prior to patterning the interlayer dielectric material so that any previously created cracks may be reliably sealed prior to the deposition of the contact material, while the removal of any excess portion thereof may be performed without an undue interaction with the electrode metal of the gate electrode structures. Consequently, a significantly reduced defect rate may be achieved. | 11-03-2011 |
20110281426 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device and a method of forming the semiconductor device includes: forming gate electrodes on a semiconductor substrate and forming spacers on both side surfaces of the gate electrodes; forming capping patterns on the gate electrodes; and forming a metal contact between the gate electrodes. Each of the capping patterns is formed to have a width greater than a width of each of the gate electrodes. | 11-17-2011 |
20110300699 | FABRICATION OF A MEMORY WITH TWO SELF-ALIGNED INDEPENDENT GATES - A method for making a micro-electronic non-volatile memory device provided with transistors having gates placed side by side, the method comprising the steps of:
| 12-08-2011 |
20110312170 | SEMICONDUCTOR DEVICE AND FABRICATION MEHTOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device and a fabrication method of the semiconductor device, the semiconductor device including: a gate electrode, a source electrode, and a drain electrode which are placed on a first surface of a substrate, and have a plurality of fingers; a gate terminal electrode, a source terminal electrode, and the drain terminal electrode which governed and formed a plurality of fingers for every the gate electrode, the source electrode, and the drain electrode; an active area placed on an underneath part of the gate electrode, the source electrode, and the drain electrode, on the substrate between the gate electrode and source electrode, and on the substrate between the gate electrode and the drain electrode; a sealing layer which is placed on the active area, the gate electrode, the source electrode, and the drain electrode through a cavity part, and performs a hermetic seal of the active area, the gate electrode, the source electrode, and the drain electrode. Accordingly, the semiconductor element itself can have air-tightness, it is not necessary to cover the gate electrode surface with a damp-proof protective film, gate capacitance of the semiconductor element is reduced, and high frequency characteristics and gain of the semiconductor element improve. | 12-22-2011 |
20120021595 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes providing a substrate having junction regions and contact plugs formed thereon. A second insulating layer is formed over a first insulating layer and includes first and second pad holes extending in different directions and exposing the contact plugs. First and second conductive pads are formed in the first and second pad holes, respectively. A third insulating layer is formed and includes dual damascene patterns and pad contact holes. The dual damascene pattern exposes the first conductive pad, and each pad contact hole exposes a second conductive pad. First pad contact plugs and a first bit line are formed in the dual damascene pattern and a second pad contract plug is formed in each pad contact hole. A fourth insulating layer including trenches is formed. Each trench exposes a second pad contact plug. A second bit line is formed in each trench. | 01-26-2012 |
20120034771 | BOND PAD FOR LOW K DIELECTRIC MATERIALS AND METHOD FOR MANUFACTURE FOR SEMICONDUCTOR DEVICES - A method for manufacturing a semiconductor device having improved contact structure includes providing a semiconductor substrate, forming a plurality of gate structures formed on a portion of the substrate, forming an interlayer dielectric layer overlying the gate structures, and forming a first copper interconnect layer overlying the substantially flat surface region of the interlayer dielectric layer. The method further includes forming a dielectric layer overlying the first copper interconnect layer, forming a second copper interconnect layer overlying the dielectric layer, and providing a copper ring structure enclosing an entirety of an inner region of the dielectric layer, the copper ring structure being provided between the first copper interconnect layer and the second copper interconnect layer to maintain the inner region of the dielectric layer. In addition, the method includes forming a bonding pad structure overlying a region within the inner region of the dielectric layer. | 02-09-2012 |
20120045889 | INTEGRATING A FIRST CONTACT STRUCTURE IN A GATE LAST PROCESS - A method is provided that includes providing a substrate; forming a transistor in the substrate, the transistor having a dummy gate; forming a dielectric layer over the substrate and transistor; forming a contact feature in the dielectric layer; and after forming the contact feature, replacing the dummy gate of the transistor with a metal gate. An exemplary contact feature is a dual contact. | 02-23-2012 |
20120058633 | Methods Of Forming Features Of Integrated Circuitry - Methods of forming features such as word lines of memory circuitry are disclosed. One such method includes forming an initial pitch multiplied feature pattern extending from a target area into only one of a first or second periphery area received on opposing sides of the target area. Thereafter, a subsequent feature pattern is formed which extends from the target array area into the other of the first or second periphery area. The initial and subsequent feature patterns may be used in forming features in an underlying material which extend from the target area to the first and second periphery areas. Other embodiments are disclosed. | 03-08-2012 |
20120083108 | Transistor Level Routing - A system and a method for transistor level routing are disclosed. The method comprises forming a high-k dielectric layer over a substrate, forming a metal layer directly over the high-k dielectric layer, and selectively disposing a semiconductive layer over the metal layer. The method further comprises forming a first transistor in a first region and a second transistor in a second region spaced from the first region, the first and second transistor having gate stacks comprising a high-k dielectric layer, a metal layer and a semiconductive layer, and forming an electrical connection between the first transistor and the second transistor comprising the high-k dielectric layer and the metal layer but not the semiconductive layer. | 04-05-2012 |
20120083109 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a bit line that is provided in a semiconductor substrate, a silicide layer that has side faces and a bottom face surrounded by the bit line and is provided within the bit line, an ONO film that is provided on the semiconductor substrate, and sidewalls that are in contact with the side faces of a trapping layer in the ONO film over the portions of the bit line located on both sides of the silicide layer, the sidewalls being formed with silicon oxide films including phosphorus. | 04-05-2012 |
20120100705 | METHOD FOR FORMING MEMORY CELL TRANSISTOR - A method for forming a memory cell transistor is disclosed which includes providing a substrate, forming a trench structure in the substrate, depositing a conductive substance on the surface of the substrate to form a conductive member inside the trench structure, forming one or more dielectric layers on the surface of the substrate, forming one or more first conductive layers on top of the dielectric layers, and etching the first conductive layers and the dielectric layers to form a hole structure extending through the first conductive and the dielectric layers, reaching to the substrate surface. One or more second conductive layers may be formed on top of the first conductive layers, with the second conductive layer material filling the hole structure. | 04-26-2012 |
20120108047 | Methods Of Forming Conductive Contacts In The Fabrication Of Integrated Circuitry - A method of forming a conductive contact includes forming a structure comprising an upper surface joining with a sidewall surface. The sidewall surface contains elemental-form silicon. Silicon is epitaxially grown from the sidewall surface. Dielectric material is formed over the upper surface and the epitaxially-grown silicon. A conductive contact is formed through the dielectric material to conductively connect with the upper surface. | 05-03-2012 |
20120108048 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A method of fabricating a three-dimensional semiconductor memory device includes providing a substrate which includes a cell array region and a peripheral region. The method further includes a peripheral structure on the peripheral region of the substrate, where the peripheral structure includes peripheral circuits and is configured to expose the cell array region of the substrate. The method further includes forming a lower cell structure on the cell array region of the substrate, forming an insulating layer to cover the peripheral structure and the lower cell structure on the substrate, planarizing the insulating layer using top surfaces of the peripheral structure and the lower cell structure as a planarization stop layer, and forming an upper cell structure on the lower cell structure. | 05-03-2012 |
20120115320 | SEMICONDUCTOR DEVICE HAVING DECREASED CONTACT RESISTANCE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first plug formed on a semiconductor substrate and exposed on side and upper surfaces of an upper part thereof and a second plug formed on the first plug to contact the exposed side and upper surfaces of the upper part of the first plug. | 05-10-2012 |
20120135592 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is disclosed, which reduces a step difference between a peripheral region and a cell region. In the semiconductor device, a metal contact of the peripheral region is configured in a multi-layered structure. Prior to forming a bit line and a storage node contact in the cell region, a contact and a line are formed in the peripheral region, such that a step difference between the cell region and the peripheral region is reduced, resulting in a reduction in parasitic capacitance between lines. | 05-31-2012 |
20120142179 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a lower film including a cell region and a peripheral circuit region, forming a first sacrificial film on the lower film, the first sacrificial film having trenches in the cell region, forming a second sacrificial pattern on the first sacrificial film, the second sacrificial pattern having line-shaped patterns spaced apart from each other and crossing the trenches in the cell region, and the second sacrificial pattern covering a top surface of the first sacrificial film in the peripheral circuit region, and patterning the first sacrificial film to form upper holes in portions of the trenches exposed by the second sacrificial pattern. | 06-07-2012 |
20120149184 | METHODS OF MANUFACTURING SELF ALIGNED BURIED CONTACT ELECTRODES FOR VERTICAL CHANNEL TRANSISTORS - A semiconductor device including vertical field effect transistors may comprise a buried insulating film stacked on a semiconductor substrate and spaced apart first and second active regions vertically penetrating the buried insulating film. The active regions and the buried insulating film are covered with an interlayer insulating film. An upper interconnection is disposed in the interlayer insulating film. A gate electrode extends from a part of the upper interconnection into the buried insulating film between the first and second active regions. A protective film pattern is disposed to cover a top surface of the upper interconnection. First and second buried contact electrodes penetrating the interlayer insulating film to be in contact with top surfaces of the first and second active regions are provided. Related manufacturing methods are also described. | 06-14-2012 |
20120156867 | METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a gate structure through a first insulating interlayer on a substrate such that the gate structure includes a spacer on a sidewall thereof, forming a first hard mask on the gate structure, partially removing the first insulating interlayer using the first hard mask as an etching mask to form a first contact hole such that the first contact hole exposes a top surface of the substrate, forming a metal silicide pattern on the top surface of the substrate exposed by the first contact hole, and forming a plug electrically connected to the metal silicide pattern. | 06-21-2012 |
20120178250 | TESTING WIRING STRUCTURE AND METHOD FOR FORMING THE SAME - The invention provides a method for forming a testing wiring structure of a thin film transistor (TFT) motherboard for applying signals to a plurality of signal lines in a pixel region on the motherboard and a method for forming the same. The formed testing wiring structure comprises a gate layer metallic testing wiring and a drain layer metallic testing wiring that is over and intersects the gate layer metallic testing wiring. A pixel electrode layer testing wiring is further provided over the drain layer metallic testing wiring in an intersecting region where the drain layer metallic testing wiring intersects the gate layer metallic testing wiring. The pixel electrode layer testing wiring is electrically connected to the drain layer metallic testing wiring to be a redundant testing wiring of the drain layer metallic testing wiring. | 07-12-2012 |
20120184094 | METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide substrate having a substrate surface is prepared. An insulating film is formed to cover a part of the substrate surface. A contact electrode is formed on the substrate surface, so as to be in contact with the insulating film. The contact electrode contains Al, Ti, and Si atoms. The contact electrode includes an alloy film made of an alloy containing Al atoms and at least any of Si atoms and Ti atoms. The contact electrode is annealed such that the silicon carbide substrate and the contact electrode establish ohmic connection with each other. Thus, in a case where a contact electrode having Al atoms is employed, insulation reliability of the insulating film can be improved. | 07-19-2012 |
20120196432 | Method for Manufacturing Contact Holes in CMOS Device Using Gate-Last Process - The present invention provides a method for manufacturing contact holes in a CMOS device by using a gate-last process, comprising: forming high-K dielectrics/metal gates (HKMG) of a first type MOS; forming and metalizing lower contact holes of the source/drain of a first type MOS and a second type MOS as well as forming HKMG of a second type MOS simultaneously, wherein the lower contact holes of the source/drain are filled with the same material as that used by the metal gate of the second type MOS; forming and metalizing contact holes of metal gates of a first type MOS and a second type MOS as well as upper contact holes of the source/drain, wherein the upper contact holes of the source/drain are aligned with the lower contact holes of the source/drain. The method reduces the difficulty of contact hole etching and metal deposition, simplifies the process steps, and increases the reliability of the device. | 08-02-2012 |
20120202342 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor device includes depositing a wiring metal layer on a photoresist layer and a portion of a first layer of a gate lead-out electrode which is exposed via an opening, lifting-off a wiring metal layer formed on the photoresist layer forming an interlayer insulation film over the entire surface including the first layer and the wiring metal layer, selectively removing the interlayer insulation film thereby forming a contact via reaching a source region formed in a cell region, and forming a source electrode on the interlayer insulation film and electrically connecting a source electrode with the source region. | 08-09-2012 |
20120214297 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE INCLUDING BURIED CHANNEL ARRAY TRANSISTOR - A method of fabricating a semiconductor device includes partially removing an active region and an isolation region to form a gate buried trench, forming a gate insulating layer on an inner wall of the gate buried trench, forming a gate conductive pattern on the gate insulating layer to fill the gate buried trench, and a height of an uppermost surface of the gate conductive pattern is lower than a height of an uppermost surface of the substrate. The method also includes forming an interlayer insulating layer on the substrate and on the gate conductive pattern, the interlayer insulating layer includes an upper insulating region and a lower insulating region, the lower insulating region fills the gate buried trench, the upper insulating region is formed over the substrate, and forming a bit contact plug connected to the active region through the interlayer. | 08-23-2012 |
20120220114 | TENSILE STRESS ENHANCEMENT OF NITRIDE FILM FOR STRESSED CHANNEL FIELD EFFECT TRANSISTOR FABRICATION - A method for inducing a tensile stress in a channel of a field effect transistor (FET) includes forming a nitride film over the FET; forming a contact hole to the FET through the nitride film; and performing ultraviolet (UV) curing of the nitride film after forming the contact hole to the FET through the nitride film, wherein the UV cured nitride film induces the tensile stress in the channel of the FET. | 08-30-2012 |
20120231619 | METHOD OF FABRICATING AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME - A method of fabricating a semiconductor memory device includes preparing a semiconductor substrate which is divided into a cell array region and a core and peripheral region adjacent to the cell array region. Signal lines may be formed in a lower layer in a cell region. An insulation layer may be formed on the lower layer. Signal lines connected to cell region signal lines may be formed on an insulation layer of the peripheral region. A capping layer may be formed on the insulation layer and the core and peripheral signal lines. The capping layer may be etched to expose the lower layer of the cell array region and an etch stop may be formed on the lower layer and the core and peripheral region. | 09-13-2012 |
20120231620 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: diffusion layers formed at the front surface of a substrate; low-resistance parts formed at the front surfaces of the diffusion layers so as to have resistance lower than the diffusion layer; and rear contact electrodes passing through the substrate from the rear surface of the substrate to be connected to the low-resistance parts through the diffusion layers. | 09-13-2012 |
20120238085 | SEMICONDUCTOR ELEMENT, SEMICONDUCTOR DEVICE AND METHODS FOR MANUFACTURING THEREOF - The present invention provides a method of manufacturing a semiconductor element having a miniaturized structure and a semiconductor device in which the semiconductor element having a miniaturized structure is integrated highly, by overcoming reduction of the yield caused by alignment accuracy, accuracy of a processing technique by reduced projection exposure, a finished dimension of a resist mask, an etching technique and the like. An insulating film covering a gate electrode is formed, and a source region and a drain region are exposed, a conductive film is formed thereover, a resist having a different film thickness is formed by applying the resist over the conductive film, the entire surface of the resist is exposed to light and developed, or the entire surface of the resist is etched to form a resist mask, and the conductive film is etched by using the resist mask to form a source and drain electrode. | 09-20-2012 |
20120264280 | Methods of Fabricating Semiconductor Devices Having Buried Word Line Interconnects - A semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein. A buried word line is disposed in the substrate in the cell region and has a top surface lower than top surfaces of cell active regions in the cell region. A gate line is disposed on the substrate in the peripheral circuit region. A word line interconnect is disposed in the substrate in the peripheral circuit region, the word line interconnect including a first portion contacting the buried word line and having a top surface lower than a top surfaces of the cell active regions and a second portion that is overlapped by and in contact with the gate line. | 10-18-2012 |
20120270386 | METHOD FOR PREPARING CONTACT PLUG STRUCTURE - In a further embodiment of the present invention, a method for preparing a contact structure includes the steps of forming a conductive stack on the semiconductor substrate; forming a patterned mask on the conductive stack; forming a depression in an upper portion of the conductive stack; forming a spacer layer on the surface of the depression and the patterned mask; forming a mask block filling the depression; removing a portion of the spacer layer not covered by the mask block; and removing a portion of the conductive stack by using the mask block and the patterned mask to form the contact structure including at least one tall contact plug under the patterned mask and at least one the short contact plug under the mask block. | 10-25-2012 |
20120276728 | TRENCH TYPE SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - The trench type semiconductor device includes a gate insulating film placed on the bottom surface and the sidewall surface of the trench formed from the surface of a first base layer; a gate electrode placed on the gate insulating film and fills up into a trench; an interlayer insulating film covering the gate electrode; a second base layer placed on the surface of the first base layer, and is formed more shallowly than the bottom surface of the trench; a source layer placed on the surface of the second base layer; a source electrode connected to the second base layer in the bottom surface of a self-aligned contact trench formed in the second base layer by applying the interlayer insulating film as a mask, and is connected to the source layer in the sidewall surface; a drain layer placed at the back side of the first base layer; and a drain electrode placed at the drain layer, for achieving the minute structure by the self-alignment, reducing the on resistance, and improving the breakdown capability, and providing a fabrication method for the same. | 11-01-2012 |
20120276729 | NON-VOLATILE MEMORY DEVICES INCLUDING SHARED BIT LINES AND METHODS OF FABRICATING THE SAME - Provided are non-volatile memory devices and methods of fabricating the same, including improved bit line and contact formation that may reduce resistance and parasitic capacitance, thereby reducing manufacturing costs and improving device performance. The non-volatile memory devices may include a substrate; a plurality of field regions formed on the substrate, each of the field regions including a homogeneous first field and a second field that is divided into two sub regions via a bridge region; an active region formed on the substrate and defined as having a string structure by the field regions, where at least two strings may be connected via one of the bridge regions; and a plurality of shared bit lines may be formed on the field regions and connected to the active region via bit line contacts, where the bit line contacts may be direct contacts. | 11-01-2012 |
20120282765 | Method of Forming Metal Gates and Metal Contacts in a Common Fill Process - The method described herein involves a method of forming metal gates and metal contacts in a common fill process. The method may involve forming a gate structure comprising a sacrificial gate electrode material, forming at least one conductive contact opening in a layer of insulating material positioned adjacent the gate structure, removing the sacrificial gate electrode material to thereby define a gate electrode opening, and performing a common deposition process to fill the conductive contact opening and the gate electrode opening with a conductive fill material. | 11-08-2012 |
20120289038 | SEMICONDUCTOR DEVICE HAVING CONTROLLABLE TRANSISTOR THRESHOLD VOLTAGE - In an embodiment, a semiconductor device includes a single-layer gate nonvolatile memory in which a floating gate is formed on a semiconductor substrate. The floating gate is formed above a diffusion layer serving as a control gate of the nonvolatile memory. The diffusion layer may be insulated from the semiconductor substrate by an insulating film such as a silicon oxide film. A pair of diffusion layers may be formed in surface regions of the semiconductor substrate on the two sides of the floating gate extending on a tunnel oxide film in an embodiment. The configuration described herein may realize a reliable semiconductor device in a low-cost process, may have a control gate which may withstand a high voltage applied when data is erased or written, and may prevent an operation error by minimizing variations in the threshold value, in some embodiments. | 11-15-2012 |
20120302052 | Methods of Forming Electrical Contacts - Some embodiments include methods of forming contacts. A row of projections may be formed over a semiconductor substrate. The projections may include a plurality of repeating components of an array, and a terminal projection. The terminal projection may have a sacrificial material spaced from semiconductor material of the substrate by a dielectric structure. An electrically conductive line may be formed along the row. The line may wrap around an end of the terminal projection and bifurcate into two branches that are along opposing sides of the repeating components. The individual branches may have regions spaced from the sacrificial material by segments of gate dielectric. The sacrificial material may be removed, together with the segments of gate dielectric, to form a contact opening. An electrically conductive contact may be formed within the contact opening and directly against the regions of the branches. | 11-29-2012 |
20120322251 | Borderless Contacts For Semiconductor Devices - In one exemplary embodiment of the invention, a method (e.g., to fabricate a semiconductor device having a borderless contact) including: forming a first gate structure on a substrate; depositing an interlevel dielectric over the first gate structure; planarizing the interlevel dielectric to expose a top surface of the first gate structure; removing at least a portion of the first gate structure; forming a second gate structure in place of the first gate structure; forming a contact area for the borderless contact by removing a portion of the interlevel dielectric; and forming the borderless contact by filling the contact area with a metal-containing material. | 12-20-2012 |
20120329259 | METHOD FOR FABRICATING METAL-OXIDE- SEMICONDUCTOR FIELD-EFFECT TRANSISTOR - A method for fabricating a metal-oxide-semiconductor field-effect transistor includes the following steps. Firstly, a substrate is provided. A gate structure, a first spacer, a second spacer and a source/drain structure are formed over the substrate. The second spacer includes an inner layer and an outer layer. Then, a thinning process is performed to reduce the thickness of the second spacer, thereby retaining the inner layer of the second spacer. After a stress film is formed on the inner layer of the second spacer and the source/drain structure, an annealing process is performed. Afterwards, the stress film is removed. | 12-27-2012 |
20120329260 | GRAPHENE TRANSISTOR WITH A SELF-ALIGNED GATE - A method of forming a transistor structure is provided. The method includes forming a graphene layer on an insulating layer; forming a stack of a first metal portion and a second metal portion over the graphene layer, wherein sidewalls of the first metal portion are vertically coincident with sidewalls of the second metal portion; and laterally offsetting the sidewalls of the first metal portion relative to the sidewalls of the second metal portion by a lateral distance. | 12-27-2012 |
20130012010 | SEMICONDUCTOR DEVICE EXHIBITING REDUCED PARASITICS AND METHOD FOR MAKING SAME - A semiconductor device includes a substrate and a gate stack disposed on the substrate. An upper layer of the gate stack is a metal gate conductor and a lower layer of the gate stack is a gate dielectric. A gate contact is in direct contact with the metal gate conductor. | 01-10-2013 |
20130012011 | INTERCONNECTION STRUCTURE FOR N/P METAL GATES - This description relates to a method for fabricating an interconnection structure in a complementary metal-oxide-semiconductor (CMOS). The method includes forming a first opening in a dielectric layer over a substrate and partially filling the first opening with a second work-function metal layer, wherein a top surface of the second work-function metal layer is below a top surface of the first opening. The method further includes forming a second opening adjoining the first opening in the dielectric layer over the substrate and depositing a first work-function metal layer in the first and second openings, whereby the first work-function metal layer is over the second work-function metal layer in the first opening. The method further includes depositing a signal metal layer over the first work-function metal layer in the first and second openings and planarizing the signal metal layer. | 01-10-2013 |
20130017677 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a MOSFET includes the steps of: forming a gate oxide film on an active layer, forming a gate electrode on the gate oxide film, forming a source contact electrode in ohmic contact with the active layer, and forming an interlayer insulating film made of silicon dioxide so as to cover the gate electrode after the source contact electrode is formed. The step of forming a source contact electrode includes the steps of forming a metal layer including aluminum so as to be in contact with the active layer, and alloying the metal layer. | 01-17-2013 |
20130023115 | Borderless Contacts in Semiconductor Devices - A method includes depositing a dummy fill material over exposed portions of a substrate and a gate stack disposed on the substrate, removing portions of the dummy fill material to expose portions of the substrate, forming a layer of spacer material over the exposed portions of the substrate, the dummy fill material and the gate stack, removing portions of the layer of spacer material to expose portions of the substrate and the dummy fill material, depositing a dielectric layer over the exposed portions of the spacer material, the substrate, and the gate stack, removing portions of the dielectric layer to expose portions of the spacer material, removing exposed portions of the spacer material to expose portions of the substrate and define at least one cavity in the dielectric layer, and depositing a conductive material in the at least one cavity. | 01-24-2013 |
20130040449 | ULTRAVIOLET ENERGY SHIELD FOR NON-VOLATILE CHARGE STORAGE MEMORY - An integrated circuit with non-volatile memory cells shielded from ultraviolet light by a shielding structure compatible with chemical-mechanical processing. The disclosed shielding structure includes a roof structure with sides; along each side are spaced-apart contact posts, each with a width on the order of the wavelength of ultraviolet light to be shielded, and spaced apart by a distance that is also on the order of the wavelength of ultraviolet light to be shielded. The contact posts may be provided in multiple rows, and extending to a diffused region or to a polysilicon ring or both. The multiple rows may be aligned with one another or staggered relative to one another. | 02-14-2013 |
20130059434 | METHOD FOR MANUFACTURING ELECTRODES AND WIRES IN GATE LAST PROCESS - The present invention provides a method for manufacturing a gate electrode and a contact wire simultaneously in a gate last process, comprising the steps of: forming a gate trench in an inter layer dielectric layer on a substrate; forming a filling layer in the gate trench and on the inter layer dielectric layer; etching the filling layer and the inter layer dielectric layer to expose the substrate, to thereby form a source/drain contact hole; removing the filling layer to expose the gate trench and the source/drain contact hole; forming metal silicide in the source/drain contact hole; depositing a gate dielectric layer and a metal gate in the gate trench; filling metal in the gate trench and the source/drain contact hole; and planarizing the filled metal. In accordance with the manufacturing method of the present invention, the gate electrode wire will be made of the same metal material as the contact hole such that the two can be manufactured by one CMP process. Such a design has the advantages of simplifying complexity of process integration on one hand and greatly strengthening control of defects by CMP process on the other hand, thereby avoiding the defects like erosion and dishing that may be produced between different metal materials. | 03-07-2013 |
20130078791 | SEMICONDUCTOR DEVICE FABRICATION METHODS WITH ENHANCED CONTROL IN RECESSING PROCESSES - Semiconductor device fabrication methods having enhanced control in recessing processes are provided. In a method for fabricating a semiconductor device or plurality of them, a structure is formed. The method includes preparing a limited amount of the structure having a depth of less than ten atomic layers for removal. Further, the method includes performing a removal process to remove the limited amount of the structure. The method repeats preparation of successive limited amounts of the structure for removal, and performance of the removal process to form a recess at an upper portion of the structure. | 03-28-2013 |
20130102140 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. In one aspect, the device has a first and second active layer on a substrate, the second active layer having a higher bandgap than the first active layer, being substantially Ga-free and including at least Al. The device has a gate insulating layer on a part of the second active layer formed by thermal oxidation of a part of the second active layer. The device has a gate electrode on at least a part of the gate insulating layer and a source electrode and drain electrode on the second active layer. The device has, when in operation and when the gate and source electrode are at the same voltage, a two-dimensional electron gas layer between the first and second active layer only outside the location of the gate electrode and not at the location of the gate electrode. | 04-25-2013 |
20130137257 | Method of Forming a Semiconductor Device by Using Sacrificial Gate Electrodes and Sacrificial Self-Aligned Contact Structures - Disclosed herein are various methods of forming a semiconductor device using sacrificial gate electrodes and sacrificial self-aligned contacts. In one example, the method includes forming two spaced-apart sacrificial gate electrodes comprised of a first material, forming a sacrificial contact structure comprised of a second material, wherein the second material is selectively etchable with respect to said first material, and performing an etching process on the two spaced-apart sacrificial gate electrodes and the sacrificial contact structure to selectively remove the two spaced-apart sacrificial gate electrode structures selectively relative to the sacrificial contact structure. | 05-30-2013 |
20130149853 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes the steps of: preparing a substrate; forming a gate insulating film; forming a gate electrode; forming an interlayer insulating film to surround the gate electrode; forming a contact hole extending through the interlayer insulating film to expose a main surface of the substrate; and forming a first metal film on and in contact with a side wall surface of the contact hole, the first metal film containing at least one of Ti and Si and containing no Al; forming a second metal film containing Ti, Al, and Si on and in contact with the first metal film; and forming a source electrode containing Ti, Al, and Si by heating the first and second metal films. | 06-13-2013 |
20130157450 | Methods of Forming Metal Silicide Regions on Semiconductor Devices - Disclosed herein are various methods of forming metal silicide regions on semiconductor devices. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, performing a selective metal silicide formation process to form metal silicide regions in source/drain regions formed in or above the substrate, after forming the metal silicide regions, removing the sacrificial gate structure to define a gate opening and forming a replacement gate structure in the gate opening, the replacement gate structure comprised of at least one metal layer. | 06-20-2013 |
20130164924 | Structure and Method for Fabricating Fin Devices - A structure and method of forming a semiconductor device with a fin is provided. In an embodiment a hard mask is utilized to pattern a gate electrode layer and is then removed. After the hard mask has been removed, the gate electrode layer may be separated into individual gate electrodes. | 06-27-2013 |
20130178052 | METHOD FOR FABRICATING SILICON-ON-INSULATOR TRANSISTOR WITH SELF-ALIGNED BORDERLESS SOURCE/DRAIN CONTACTS - A method is provided for fabricating a transistor. A replacement gate stack is formed on a semiconductor layer, a gate spacer is formed, and a dielectric layer is formed. The dummy gate stack is removed to form a cavity. A gate dielectric and a work function metal layer are formed in the cavity. The cavity is filled with a gate conductor. One and only one of the gate conductor and the work function metal layer are selectively recessed. An oxide film is formed in the recess such that its upper surface is co-planar with the upper surface of the dielectric layer. The oxide film is used to selectively grow an oxide cap. An interlayer dielectric is formed and etched to form a cavity for a source/drain contact. A source/drain contact is formed in the contact cavity, with a portion of the source/drain contact being located directly on the oxide cap. | 07-11-2013 |
20130178053 | SELF-ALIGNED CONTACT EMPLOYING A DIELECTRIC METAL OXIDE SPACER - A dielectric liner is formed on sidewalls of a gate stack and a lower contact-level dielectric material layer is deposited on the dielectric liner and planarized. The dielectric liner is recessed relative to the top surface of the lower contact-level dielectric material layer and the top surface of the gate stack. A dielectric metal oxide layer is deposited and planarized to form a dielectric metal oxide spacer that surrounds an upper portion of the gate stack. The dielectric metal oxide layer has a top surface that is coplanar with a top surface of the planarized lower contact-level dielectric material layer. Optionally, the conductive material in the gate stack may be replaced. After deposition of at least one upper contact-level dielectric material layer, at least one via hole extending to a semiconductor substrate is formed employing the dielectric metal oxide spacer as a self-aligning structure. | 07-11-2013 |
20130189833 | Method of Forming Self-Aligned Contacts for a Semiconductor Device - Disclosed herein is a method of forming self-aligned contacts for a semiconductor device. In one example, the method includes forming a plurality of spaced-apart sacrificial gate electrodes above a semiconducting substrate, wherein each of the gate electrodes has a gate cap layer positioned on the gate electrode, and performing at least one etching process to define a self-aligned contact opening between the plurality of spaced-apart sacrificial gate electrodes. The method further includes removing the gate cap layers to thereby expose an upper surface of each of the sacrificial gate electrodes, depositing at least one layer of conductive material in said self-aligned contact opening and removing portions of the at least one layer of conductive material that are positioned outside of the self-aligned contact opening to thereby define at least a portion of a self-aligned contact positioned in the self-aligned contact opening. | 07-25-2013 |
20130189834 | SELF-ALIGNED CONTACTS FOR HIGH k/METAL GATE PROCESS FLOW - A semiconductor structure is provided that includes a semiconductor substrate having a plurality of gate stacks located thereon. Each gate stack includes a high k gate dielectric layer, a work function metal layer and a conductive metal. A spacer is located on sidewalls of each gate stack and a self-aligned dielectric liner is present on an upper surface of each spacer. A bottom surface of each self-aligned dielectric liner is present on an upper surface of a semiconductor metal alloy. A contact metal is located between neighboring gate stacks and is separated from each gate stack by the self-aligned dielectric liner. The structure also includes another contact metal having a portion that is located on and in direct contact with an upper surface of the contact metal and another portion that is located on and in direct contact with the conductive metal of one of the gate stacks. | 07-25-2013 |
20130196496 | Integrating a First Contact Structure in a Gate Last Process - A method is provided that includes providing a substrate; forming a transistor in the substrate, the transistor having a dummy gate; forming a dielectric layer over the substrate and transistor; forming a contact feature in the dielectric layer; and after forming the contact feature, replacing the dummy gate of the transistor with a metal gate. An exemplary contact feature is a dual contact. | 08-01-2013 |
20130224941 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - A silicon carbide semiconductor device is provided that includes a semiconductor layer made of silicon carbide and having a surface with a trench having a sidewall formed of a crystal plane tilted at an angle in a range of not less than 50° and not more than 65° relative to the {0001} plane, and an insulating film formed to contact the sidewall of the trench. A maximum value of the nitrogen concentration in a region within 10 nm from the interface between the sidewall of the trench and the insulating film is not less than 1×10 | 08-29-2013 |
20130230978 | SELF-ALIGNED CONTACTS - A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer. | 09-05-2013 |
20130252410 | SELECTIVE LOW-TEMPERATURE OHMIC CONTACT FORMATION METHOD FOR GROUP III-NITRIDE HETEROJUNCTION STRUCTURED DEVICE - A method for forming a selective ohmic contact for a Group III-nitride heterojunction structured device may include forming a conductive layer and a capping layer on an epitaxial substrate including at least one Group III-nitride heterojunction layer and having a defined ohmic contact region, the capping layer being formed on the conductive layer or between the conductive layer and the Group III-nitride heterojunction layer in one of the ohmic contact region and non-ohmic contact region, and applying at least one of a laser annealing process and an induction annealing process on the substrate at a temperature of less than or equal to about 750° C. to complete the selective ohmic contact in the ohmic contact region. | 09-26-2013 |
20130252411 | MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE - According one embodiment, a method for manufacturing a semiconductor device is provided, which includes forming a pair of element isolation insulation films on a semiconductor substrate, forming a gate electrode structure on sides of the gate electrode structure, selectively removing oxide films that are formed on a top surface of the diffusion layer and a top surface of the gate electrode by placing the substrate in a gas atmosphere selected from the group consisting of F, Cl, Br, I, H, O, Ar, or N; and irradiating the semiconductor substrate with microwave radiation. The method also includes depositing a metal film on a top surface of the diffusion layer and a top surface of the gate electrode, and a silicide film is formed by heating the substrate. | 09-26-2013 |
20130252412 | PROCESS FOR PRODUCING AN INTEGRATED CIRCUIT - A process for producing an integrated circuit on the surface of a substrate, the process including: producing a first layer, including active zones and insulating zones, on the surface of the substrate; producing gate zones on the surface of the first layer, the gate zones each being surrounded by insulating spacers; producing source/drain electrodes; producing a dielectric layer between the insulating spacers, the dielectric layer having an upper surface level with the upper surfaces of the gate zones; partially etching each gate zone so as to lower the upper surface of a first part of each gate zone; and depositing an insulating dielectric layer on the first parts of the gate zones. | 09-26-2013 |
20130252413 | SURROUND GATE CMOS SEMICONDUCTOR DEVICE - The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer. | 09-26-2013 |
20130273726 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE INCLUDING PROCESS MONITORING PATTERN HAVING OVERLAPPING INPUT/OUTPUT PAD ARRAY AREA - The semiconductor device includes a process monitoring pattern and an input/output (I/O) pad array area, the process monitoring pattern including a lower layer having a peripheral area surrounding a first internal area, the first internal area exposed by an internal open area, an external structure on the peripheral area of the lower layer, and a first dam disposed in the peripheral area spaced apart from the external structure by an external open area, the first dam defining the first internal area. The peripheral area overlaps the input/output (I/O) pad array area of the semiconductor device. | 10-17-2013 |
20130280899 | SILICIDE FORMATION AND ASSOCIATED DEVICES - Improved silicide formation and associated devices are disclosed. An exemplary method includes providing a semiconductor material having spaced source and drain regions therein, forming a gate structure interposed between the source and drain regions, performing a gate replacement process on the gate structure to form a metal gate electrode therein, forming a hard mask layer over the metal gate electrode, forming silicide layers on the respective source and drain regions in the semiconductor material, removing the hard mask layer to expose the metal gate electrode, and forming source and drain contacts, each source and drain contact being conductively coupled to a respective one of the silicide layers. | 10-24-2013 |
20130288471 | METHODS OF FORMING SELF-ALIGNED CONTACTS FOR A SEMICONDUCTOR DEVICE - One illustrative method disclosed herein involves forming gate structures for first and second spaced-apart transistors above a semiconducting substrate, forming an etch stop layer above the substrate and the gate structures, performing at least one angled ion implant process to implant at least one etch-inhibiting species into less than an entirety of the etch stop layer, after performing at least one angled ion implant process, forming a layer of insulating material above the etch stop layer, performing at least one first etching process to define an opening in the layer of insulating material and thereby expose a portion of the etch stop layer, performing at least one etching process on the exposed portion of the etch stop layer to define a contact opening therethrough that exposes a doped region formed in the substrate, and forming a conductive contact in the opening that is conductively coupled to the doped region. | 10-31-2013 |
20130295755 | METHODS FOR FORMING TRENCHES - Methods for making a semiconductor device are disclosed. The method includes forming a plurality of gate stacks on a substrate, forming an etch buffer layer on the substrate, forming a dielectric material layer on the etch buffer layer, forming a hard mask layer on the substrate, wherein the hard mask layer includes one opening, and etching the dielectric material layer to form a plurality of trenches using the hard mask layer and the etch buffer layer as an etch mask. | 11-07-2013 |
20130295756 | METHODS OF FORMING CONTACTS FOR SEMICONDUCTOR DEVICES USING A LOCAL INTERCONNECT PROCESSING SCHEME - One method disclosed herein includes forming a plurality of source/drain contacts that are conductively coupled to a source/drain region of a plurality of transistor devices, wherein at least one of the source/drain contacts is a local interconnect structure that spans the isolation region and is conductively coupled to a first source/drain region in a first active region and to a second source/drain region in a second active region, and forming a patterned mask layer that covers the first and second active regions and exposes at least a portion of the local interconnect structure positioned above an isolation region that separates the first and second active regions. The method further includes performing an etching process through the patterned mask layer to remove a portion of the local interconnect structure, thereby defining a recess positioned above a remaining portion of the local interconnect structure, and forming an insulating material in the recess. | 11-07-2013 |
20130295757 | SHORT GATE-LENGTH HIGH ELECTRON-MOBILITY TRANSISTORS WITH ASYMMETRIC RECESS AND SELF-ALIGNED OHMIC ELECTRODES - A method for fabricating InP-based high electron-mobility transistors (HEMTs) and GaAs-based metamorphic electron-mobility transistors (MHEMTs) by utilizing asymmetrically recessed Γ-gates and self-aligned ohmic electrodes is disclosed. The fabrication starts with mesa isolation, followed by gate recess and gate metal deposition, in which the gate foot is placed asymmetrically in the recess groove, with the offset towards the source. It is important to use Γ-gates as the shadow mask for ohmic metal deposition, because it allows a source-gate spacing as small as 0.1 micron, greatly reducing the critical source resistance, and it retains a relatively large gate-drain spacing, enabling a decent breakdown voltage when coupled with the asymmetric gate recess. It is also critical to maintain a large stem height of the Γ-gates to assure a sufficient gap between the top of the gates and the ohmic metal after its deposition to reduce the parasitic capacitance. The uniqueness of this technology would best fit the applications that require low voltage and/or low DC power consumption. | 11-07-2013 |
20130323919 | METHODS TO STOP CONTACT METAL FROM EXTRUDING INTO REPLACEMENT GATES - A method of preventing contact metal from protruding into neighboring gate devices to affect work functions of the neighboring gate devices is provided includes forming a gate structure. Forming the gate structure includes forming a work function layer, and forming a gate metal layer having a void, wherein the work function layer surrounds the gate metal layer. The method further includes forming a contact plug having a contact metal directly on the gate metal layer of the first gate stack, wherein the contact metal protrudes into the void, and the work function layer prevents the contact metal from protruding into a second gate stack. | 12-05-2013 |
20130323920 | Method of fabricating a gate-all-around word line for a vertical channel dram - A method of fabricating a self-aligned buried wordline in a structure which contains a self-aligned buried bit line, where the overall structure which makes up a portion of a vertical channel DRAM. The materials and processes used enable self-alignment of elements of the buried wordline during the fabrication process. In addition, the materials and processes used enable for formation of individual DRAM cells which have a buried bit line width which is 16 nm or less and a perpendicular buried wordline width which is 24 nm or less. | 12-05-2013 |
20130344691 | Methods of Forming Electrical Contacts - Some embodiments include methods of forming contacts. A row of projections may be formed over a semiconductor substrate. The projections may include a plurality of repeating components of an array, and a terminal projection. The terminal projection may have a sacrificial material spaced from semiconductor material of the substrate by a dielectric structure. An electrically conductive line may be formed along the row. The line may wrap around an end of the terminal projection and bifurcate into two branches that are along opposing sides of the repeating components. The individual branches may have regions spaced from the sacrificial material by segments of gate dielectric. The sacrificial material may be removed, together with the segments of gate dielectric, to form a contact opening. An electrically conductive contact may be formed within the contact opening and directly against the regions of the branches. | 12-26-2013 |
20140004690 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | 01-02-2014 |
20140017885 | METHOD OF MANUFACTURING FIELD EFFECT TYPE COMPOUND SEMICONDUCTOR DEVICE - Disclosed is a method of manufacturing a field effect type compound semiconductor device in which leakage current of a device is decreased and breakdown voltage is enhanced. The method of manufacturing a field effect type compound semiconductor device includes: stacking an active layer and an ohmic layer on a substrate and forming a first oxide layer on the ohmic layer; forming a mesa region in predetermined regions of the first oxide layer, the ohmic layer, and the active layer; planarizing the mesa region after forming a nitride layer by evaporating a nitride on the mesa region; forming an ohmic electrode on the first oxide layer; forming a minute gate resist pattern after forming a second oxide layer on a semiconductor substrate in which the ohmic electrode is formed and forming a minute gate pattern having a under-cut shaped profile by dry-etching the first oxide layer, the nitride layer, and the second oxide layer; forming a gate recess region by forming a head pattern of a gamma gate electrode on the semiconductor substrate; and forming the gamma gate electrode by evaporating refractory metal on the semiconductor substrate in which the gate recess region is formed. | 01-16-2014 |
20140030880 | Method of Semiconductor Integrated Circuit Fabrication - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device. The method also includes forming a step-forming-hard-mask (SFHM) on the MG stack in a predetermined area on the semiconductor substrate, performing MG recessing, depositing a MG hard mask over the semiconductor substrate and recessing the MG hard mask to fully remove the MG hard mask from the MG stack in the predetermined area. | 01-30-2014 |
20140030881 | PHOTORESIST COMPOSITION, THIN FILM TRANSISTOR ARRAY PANEL, AND METHOD OF MANUFACTURING THE SAME - A positive photoresist composition including a novolac resin, a photo active compound (PAC), a melamine crosslinking agent, and a solvent. | 01-30-2014 |
20140038400 | 3D SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING SAME - A three dimensional (3D) semiconductor device includes; a vertical channel extending from a lower end proximate a substrate to an upper end and connecting a plurality of memory cells, and a cell array comprising the plurality of cells, wherein the cell array is arranged in a gate stack of layers having a stair-stepped structure disposed on the substrate. The gate stack includes a lower layer including a lower select line coupled to a lower non-memory transistor proximate the lower end, upper layers including conductive lines respectively coupled to an upper non-memory transistor proximate the upper end and connected as a single conductive piece to form an upper select line, and intermediate layers respectively including a word line and coupled to a cell transistor, wherein the intermediate layers are disposed between the lower select line and the upper select line. | 02-06-2014 |
20140038401 | RUTHENIUM FOR A DIELECTRIC CONTAINING A LANTHANIDE - A gate containing ruthenium for a dielectric having an oxide containing a lanthanide and a method of fabricating such a combination gate and dielectric produce a reliable structure for use in a variety of electronic devices. A ruthenium or a conductive ruthenium oxide gate may be formed on a lanthanide oxide. A ruthenium-based gate on a lanthanide oxide provides a gate structure that can effectively prevent a reaction between the gate and the lanthanide oxide. | 02-06-2014 |
20140051239 | DISPOSABLE CARBON-BASED TEMPLATE LAYER FOR FORMATION OF BORDERLESS CONTACT STRUCTURES - After formation of gate stacks, a carbon-based template layer is deposited over the gate stacks, and is optionally planarized to provide a planar top surface. A hard mask layer and a photoresist layer are subsequently formed above the carbon-based template layer. A pattern including openings is formed within the photoresist layer. The pattern is subsequently transferred through the hard mask layer and the carbon-based template layer with high selectivity to gate spacers to form self-aligned cavities within the carbon-based template layer. Contact structures are formed within the carbon-based template layer by a damascene method. The hard mask layer and the carbon-based template layer are subsequently removed selective to the contact structures. The contact structures can be formed as contact bar structures or contact via structures. Optionally, a contact-level dielectric layer can be subsequently deposited. | 02-20-2014 |
20140065809 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method of fabricating a semiconductor device includes forming a first gate pattern and a dummy gate pattern on a first active area and a second active area of a substrate, respectively, the first gate pattern including a first gate insulating layer and a silicon gate electrode, removing the dummy gate pattern to expose a surface of the substrate in the second active area, forming a second gate pattern including a second gate insulating layer and a metal gate electrode on the exposed surface of the substrate, the first gate insulating layer having a thickness larger than a thickness of the second gate insulating layer, and forming a gate silicide on the silicon gate electrode after forming the second gate pattern. | 03-06-2014 |
20140073123 | Method for Producing a Controllable Semiconductor Component - Disclosed is a method for producing a controllable semiconductor component. In a semiconductor body with a top side and a bottom side, a first trench protruding from the top side into the semiconductor body and a second trench protruding from the top side into the semiconductor body are formed in a common etching process. The first trench has a first width and the second trench has a second width greater than the first width. Then, in a common process, an oxide layer is formed in the first trench and in the second trench such that the oxide layer fills the first trench and electrically insulates a surface of the second trench. Subsequently, the oxide layer is removed from the first trench completely or at least partly such that the semiconductor body comprises an exposed first surface area arranged in the first trench. | 03-13-2014 |
20140094026 | METHOD FOR PROVIDING ELECTRICAL CONNECTIONS TO SPACED CONDUCTIVE LINES - An integrated circuit and a method of formation provide a contact area formed at an angled end of at least one linearly extending conductive line. In an embodiment, conductive lines with contact landing pads are formed by patterning lines in a mask material, cutting at least one of the material lines to form an angle relative to the extending direction of the material lines, forming extensions from the angled end faces of the mask material, and patterning an underlying conductor by etching using said material lines and extension as a mask. In another embodiment, at least one conductive line is cut at an angle relative to the extending direction of the conductive line to produce an angled end face, and an electrical contact landing pad is formed in contact with the angled end face. | 04-03-2014 |
20140113441 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a first interconnection and a second interconnection above a semiconductor substrate, forming a first sidewall insulating film on a side wall of the first interconnection, and a second sidewall insulating film on a side wall of the second interconnection, forming a conductive film above the semiconductor substrate with the first interconnection, the first sidewall insulating film, the second interconnection and the second sidewall insulating film formed on, and selectively removing the conductive film above the first interconnection and the second interconnection to form in a region between the first interconnection and the second interconnection a third interconnection formed of the conductive film and spaced from the first interconnection and the second interconnection by the first sidewall insulating film and the second sidewall insulating film. | 04-24-2014 |
20140127891 | METHOD FOR MANUFACTURING PIXEL STRUCTURE - A method for manufacturing pixel structure is provided. A patterned conductor layer including a gate, a scan line and a conductor pattern is formed on a substrate. A gate insulating layer, a metal oxide material layer and an etching stop material layer are formed on the substrate. Using the patterned conductor layer as mask, a patterned photoresist layer is formed on the etching stop material layer through a back exposure process. Using the patterned photoresist layer as mask, a metal oxide channel layer and an etching stop layer are formed above the gate. A source and a drain are formed on the etching stop layer. A passivation layer is formed on the substrate. A halftone mask is used to form a photosensitive layer on the passivation layer. The metal oxide material layer and the etching stop material layer on the scan line and the conductor pattern are removed. | 05-08-2014 |
20140134836 | DIELECTRIC CAP LAYER FOR REPLACEMENT GATE WITH SELF-ALIGNED CONTACT - Embodiments of the present invention provide a method of forming borderless contact for transistors. The method includes forming a sacrificial gate structure embedded in a first dielectric layer, the sacrificial gate structure including a sacrificial gate and a second dielectric layer surrounding a top and sidewalls of the sacrificial gate; removing a portion of the second dielectric layer that is above a top level of the sacrificial gate to create a first opening surrounded directly by the first dielectric layer; removing the sacrificial gate exposed by the removing of the portion of the second dielectric layer to create a second opening surrounded by a remaining portion of the second dielectric layer; filling the second opening with one or more conductive materials to form a gate of a transistor; and filling the first opening with a layer of dielectric material to form a dielectric cap of the gate of the transistor. | 05-15-2014 |
20140154877 | METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING LOW RESISTANCE METAL GATE STRUCTURES - Methods for fabricating integrated circuits having low resistance metal gate structures are provided. One method includes forming a metal gate stack in a FET trench formed in a FET region. The metal gate stack is etched to form a recessed metal gate stack and a recess. The recess is defined by sidewalls in the FET region and is disposed above the recessed metal gate stack. A liner is formed overlying the sidewalls and the recessed metal gate stack and defines an inner cavity in the recess. A copper layer is formed overlying the liner and at least partially fills the inner cavity. The copper layer is etched to expose an upper portion of the liner while leaving a copper portion disposed in a bottom portion of the inner cavity. Copper is electrolessly deposited on the copper portion to fill a remaining portion of the inner cavity. | 06-05-2014 |
20140162447 | FINFET HYBRID FULL METAL GATE WITH BORDERLESS CONTACTS - A method for fabricating a field effect transistor device includes patterning a fin on substrate, patterning a gate stack over a portion of the fin and a portion of an insulator layer arranged on the substrate, forming a protective barrier over the gate stack, a portion of the fin and a portion of the insulator layer, the protective barrier enveloping the gate stack, depositing a second insulator layer over portions of the fin and the protective barrier, performing a first etching process to selectively remove portions of the second insulator layer to define cavities that expose portions of source and drain regions of the fin without appreciably removing the protective barrier, and depositing a conductive material in the cavities. | 06-12-2014 |
20140170843 | Charge Trapping Split Gate Device and Method of Fabricating Same - Embodiments provide a split gate device, methods for fabricating a split gate device, and integrated methods for fabricating a split gate device and a periphery device. In an embodiment, the split gate device is a charge trapping split gate device, which includes a charge trapping layer. In another embodiment, the split gate device is a non-volatile memory cell, which can be formed according to embodiments as standalone or embedded with a periphery device. | 06-19-2014 |
20140179092 | METHOD FOR FORMING VOID-FREE POLYSILICON AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME - A method for fabricating a semiconductor device includes forming a buried gate electrode in a semiconductor substrate. An insulating layer is formed over the buried gate electrode and is etched to form a contact hole exposing the semiconductor substrate. A sacrificial spacer is formed on sidewalls of the insulating layer defining the contact hole. A polysilicon layer pattern is formed in the contact hole. The sacrificial spacer is removed to form an air gap around the polysilicon layer pattern. A thermal process is performed to remove a seam existing in the polysilicon layer pattern. | 06-26-2014 |
20140187029 | VERTICAL TYPE MEMORY DEVICE - A method of fabricating a semiconductor device, comprising: forming a plurality of memory cell strings; coupling an interconnection to at least two of the memory cell strings; and coupling a bitline to the interconnection. The interconnection includes a body extending along a first direction and a protrusion protruding from the body along a second direction. | 07-03-2014 |
20140220769 | INTEGRATED CIRCUITS INCLUDING ILD STRUCTURE, SYSTEMS, AND FABRICATION METHODS THEREOF - A method of forming an integrated circuit comprises forming a gate of a transistor over a substrate. The method further comprises forming a connecting line over the substrate, the connecting line being coupled with an active area of the transistor. The method also comprises forming a dielectric layer surrounding the gate and the connecting line. The method additionally comprises forming an etch stop layer over the dielectric layer and covering a portion of a top surface of the connecting line. The method further comprises forming a via structure comprising a via in physical contact with a top surface of the gate and another portion of the top surface of the connecting line. The method also comprises forming a metallic line structure being coupled with the via structure. | 08-07-2014 |
20140248761 | SEMICONDUCTOR DEVICE HAVING DUAL METAL SILICIDE LAYERS AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is manufactured using dual metal silicide layers. The semiconductor device includes a substrate having first and second regions, a first metal gate electrode on the substrate in the first region, a second metal gate electrode on the substrate in the second region, a first epitaxial layer on and in the substrate at both sides of the first metal gate electrode, a second epitaxial layer on and in the substrate at both sides of the second metal gate electrode, a first metal silicide layer on the first epitaxial layer, a second metal silicide layer on the second epitaxial layer, an interlayer dielectric layer on the first and second metal silicide layers, contact plugs passing through the interlayer dielectric layer and electrically connected to the first and second metal silicide layers. | 09-04-2014 |
20140248762 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device comprises the following steps. First, a substrate is provided, at least one fin structure is formed on the substrate, and a metal layer is then deposited on the fin structure to form a salicide layer. After depositing the metal layer, the metal layer is removed but no RTP is performed before the metal layer is removed. Then a RTP is performed after the metal layer is removed. | 09-04-2014 |
20140273424 | Method of Conducting a Direction-Specific Trimming Process for Contact Patterning - The present disclosure discloses a method of fabricating a semiconductor device. A first layer is formed over a substrate. A patterned second layer is then formed over the first layer. The patterned second layer includes an opening. A spacer material is then deposited in the opening, thereby reducing the opening in a plurality of directions. A direction-specific trimming process is performed to the spacer material and the second layer. Thereafter, the first layer is patterned with the second layer. | 09-18-2014 |
20140287574 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING FIELD PLATE ELECTRODE - According to one embodiment, in a method of a semiconductor device, a trench is formed in the direction of a lower surface from an upper surface of a semiconductor layer. A first insulating film is formed to cover an inner surface of the trench. An electrode material is formed to fill the trench and cover the upper surface of the semiconductor layer. The electrode material is selectively removed except a portion of the electrode material to fill the trench and a portion of the electrode material to cover an opening of the trench. The first insulating film to cover an upper portion of the trench is removed. The portions of the electrode material to fill the trench and cover the opening of the trench are etched back to form a first electrode at a lower portion of the trench. | 09-25-2014 |
20140287575 | SPATIAL ORIENTATION OF THE CARBON NANOTUBES IN ELECTROPHORETIC DEPOSITION PROCESS - A new method of electrophoretic nanotube deposition is proposed wherein individual nanotubes are placed on metal electrodes which have their length significantly exceeding their width, while the nanotube length is chosen to be close to that of the metal electrode. Due to electrostatic attraction of individual nanotube to the elongated electrode, every nanotube approaching the electrode is deposited along the electrode, since such an orientation is energetically favorable. This method offers opportunity to produce oriented arrays of individual nanotubes, which opens up a new technique for fabrication and mass production of nanotube-based devices and circuits. Several such devices are considered. These are MESFET- and MOSFET-like transistors and CMOS-like voltage inverter. | 09-25-2014 |
20140295657 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING MULTI-LAYERED INTERCONNECT STRUCTURE - Disclosed is a semiconductor device provided with an active element in a multilayer interconnect layer and decreased in a chip area. A second interconnect layer is provided over a first interconnect layer. A first interlayer insulating layer is provided in the first interconnect layer. A semiconductor layer is provided in a second interconnect layer and in contact with the first interlayer insulating layer. A gate insulating film is provided over the semiconductor layer. A gate electrode is provided over the gate insulating film. At least two first vias are provided in the first interconnect layer and in contact by way of upper ends thereof with the semiconductor layer. | 10-02-2014 |
20140329379 | PATTERNING METHOD FOR FORMING STAIRCASE STRUCTURE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME - A patterning method includes forming a photoresist layer on a processing layer and exposing the photoresist layer using a standing wave/defocusing exposure to produce a photoresist layer having a staircase pattern. | 11-06-2014 |
20140342540 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a buried gate is provided. The semiconductor device is formed in a structure in which a plurality of contacts having small step differences are stacked without forming a metal contact applying an operation voltage to the buried gate in a single contact and a contact pad is formed between the contacts so that failure due to misalignment can be prevented without a separate additional process for forming the contacts. | 11-20-2014 |
20140363961 | THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF - Provided is a thin film transistor array panel. The thin film transistor array panel includes: an insulation substrate including a display area with a plurality of pixels and a peripheral area around the display area; a gate line and a data line positioned in the display area of the insulation substrate; a first driving signal transfer line and a second driving signal transfer line positioned in the peripheral area of the insulation substrate; a first insulating layer positioned on the gate line and the data line; and a first photosensitive film positioned on the first driving signal transfer line and the second driving signal transfer line, in which the first photosensitive film is disposed only in the peripheral area. | 12-11-2014 |
20140377943 | FOUR TERMINAL TRANSISTOR FABRICATION - Producing a transistor includes providing a substrate including in order a first electrically conductive material layer positioned on the substrate and a first electrically insulating material layer positioned on the first electrically conductive material layer. A gate including a reentrant profile is formed from an electrically conductive material layer stack provided on the first electrically insulating material layer in which a first portion of the gate is sized and positioned to extend beyond a second portion of the gate. The gate including the reentrant profile and at least a portion of the first electrically insulating material layer are conformally coated with a second electrically insulating material layer. The second electrically insulating material layer is conformally coated the with a semiconductor material layer. A source and drain electrodes are formed simultaneously by directionally depositing a second electrically conductive material layer on portions of the semiconductor material layer. | 12-25-2014 |
20150017795 | Non-Volatile Memory With Silicided Bit Line Contacts - An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes. | 01-15-2015 |
20150024583 | METHOD OF MANUFACTURING LIQUID CRYSTAL DISPLAY - A method of manufacturing a liquid crystal display includes disposing a gate electrode and a light blocking member on a substrate, disposing a source electrode and a drain electrode on the gate electrode to form a thin film transistor, disposing a data line on the light blocking member, disposing an organic layer on the thin film transistor and the data line, exposing a first convex part of the organic layer to light in a first area corresponding to the thin film transistor during an exposure process, and exposing a second convex part of the organic layer to the light in a second area corresponding to the data line during the exposure process using a mask. The mask includes a first transflective part aligned with the first area and a second transflective part aligned with the second area during the exposure process. | 01-22-2015 |
20150031194 | METHOD FOR DESIGNING ANTENNA CELL THAT PREVENTS PLASMA INDUCED GATE DIELECTRIC DAMAGE IN SEMICONDUCTOR INTEGRATED CIRCUITS - An antenna cell for preventing plasma enhanced gate dielectric failures, is provided. The antenna cell design utilizes a polysilicon lead as a gate for a dummy transistor. The polysilicon lead may be one of a group of parallel, nested polysilicon lead. The dummy transistor includes the gate coupled to a substrate maintained at V | 01-29-2015 |
20150064892 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE - Semiconductor devices with reduced substrate defects and methods of manufacture are disclosed. The method includes forming at least one gate structure over a plurality of fin structures. The method further includes removing dielectric material adjacent to the at least one gate structure using a maskless process, thereby exposing an underlying epitaxial layer formed adjacent to the at least one gate structure. The method further includes depositing metal material on the exposed underlying epitaxial layer to form contact metal in electrical contact with source and drain regions, adjacent to the at least one gate structure. The method further includes forming active areas and device isolation after the formation of the contact metal, including the at least one gate structure. The active areas and the contact metal are self-aligned with each other in a direction parallel to the at least one gate structure. | 03-05-2015 |
20150064893 | METHOD FOR FORMING TRENCH MOS STRUCTURE - A method for forming a trench MOS structure. First, a substrate, an epitaxial layer, a doping region and a doping well are provided. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The doping well has a second conductivity type and is disposed on the epitaxial layer. The doping region has the first conductivity type and is disposed on the doping well. A gate trench penetrates the doping region and the doping well. The doping well is partially removed to form a bottom section of the gate trench. A gate isolation is formed to cover the inner wall of the bottom section and a top section of the gate trench. The gate trench is filled with a conductive material to form a trench gate. | 03-05-2015 |
20150064894 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - The semiconductor device includes a semiconductor substrate having a first active area defined by a first isolation layer; a gate insulating layer formed on the semiconductor substrate; a first conductive layer formed on the gate insulating layer; a dielectric layer formed on the first conductive layer; at least one first contact hole passing through the dielectric layer; a second conductive layer, formed on the dielectric layer, the second conductive layer filling the at least one first contact hole to contact the first conductive layer; and at least one first contact plug connected to the second conductive layer in the first active area, wherein the at least one first contact plug is offset from the at least one first contact hole to overlap the dielectric layer. | 03-05-2015 |
20150072511 | Oxidation and Etching Post Metal Gate CMP - A method includes forming a dummy gate of a transistor at a surface of a wafer, removing the dummy gate, and filling a metallic material into a trench left by the removed dummy gate. A Chemical Mechanical Polish (CMP) is then performed on the metallic material, wherein a remaining portion of the metallic material forms a metal gate of the transistor. After the CMP, a treatment is performed on an exposed top surface of the metal gate using an oxidation-and-etching agent comprising chlorine and oxygen. | 03-12-2015 |
20150079774 | Self-Alignment for using Two or More Layers and Methods of Forming Same - Embodiments of the present disclosure include self-alignment of two or more layers and methods of forming the same. An embodiment is a method for forming a semiconductor device including forming at least two gates over a substrate, forming at least two alignment structures over the at least two gates, forming spacers on the at least two alignment structures, and forming a first opening between a pair of the at least two alignment structures, the first opening extending a first distance from a top surface of the substrate. The method further includes filling the first opening with a first conductive material, forming a second opening between the spacers of at least one of the at least two alignment structures, the second opening extending a second distance from the top surface of the substrate, and filling the second opening with a second conductive material. | 03-19-2015 |
20150087142 | HIGH ELECTRON MOBILITY TRANSISTOR AND MANUFACTURING METHOD THEREOF - Disclosed is a manufacturing method of a high electron mobility transistor. The method includes: forming a source electrode and a drain electrode on a substrate; forming a first insulating film having a first opening on an entire surface of the substrate, the first opening exposing a part of the substrate; forming a second insulating film having a second opening within the first opening, the second opening exposing a part of the substrate; forming a third insulating film having a third opening within the second opening, the third opening exposing a part of the substrate; etching a part of the first insulating film, the second insulating film and the third insulating film so as to expose the source electrode and the drain electrode; and forming a T-gate electrode on a support structure including the first insulating film, the second insulating film and the third insulating film. | 03-26-2015 |
20150087143 | Jog Design in Integrated Circuits - A device includes an active region in a semiconductor substrate, a gate strip over and crossing the active region, and a jog over the active region and connected to the gate strip to form a continuous region. The jog is on a side of the gate strip. A first contact plug is at a same level as the gate strip, wherein the first contact plug is on the side of the gate strip. A second contact plug is over the jog and the first contact plug. The second contact plug electrically interconnects the first contact plug and the jog. | 03-26-2015 |
20150111373 | REDUCING GATE HEIGHT VARIATION IN RMG PROCESS - A method of forming transistors is provided. The method includes forming a plurality of transistor structures to have a plurality of dummy gates on a substrate. Each dummy gate is surrounded by sidewall spacers of a height, which is less than the dummy gate and is different for different transistor structures resulting in divots of different depths above the sidewall spacers. The method then deposits a conformal dielectric layer on top of the dummy gates and inside the divots of the plurality of transistor structures with the conformal dielectric layer having a thickness of at least half of a width of the divots, removes only a portion of the conformal dielectric layer that is on top of the dummy gates to expose the dummy gates; and replaces the dummy gates with a plurality of high-k metal gates. | 04-23-2015 |
20150111374 | SURFACE TREATMENT IN A DEP-ETCH-DEP PROCESS - Embodiments of present invention provide a method of forming semiconductor devices. The method includes creating an opening in a semiconductor structure; depositing a first layer of metal inside the opening with the first layer of metal partially filling up the opening; modifying a top surface of the first layer of metal in an etching process; passivating the modified top surface of the first layer of metal to form a passivation layer; and depositing a second layer of metal directly on top of the passivation layer. | 04-23-2015 |
20150118835 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes following steps. A substrate having at least a transistor embedded in an insulating material formed thereon is provided. The transistor includes a metal gate. Next, an etching process is performed to remove a portion of the metal gate to form a recess and to remove a portion of the insulating material to form a tapered part. After forming the recess and the tapered part of the insulating material, a hard mask layer is formed on the substrate to fill up the recess. Subsequently, the hard mask layer is planarized. | 04-30-2015 |
20150118836 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device is disclosed. Provided is a substrate having a dummy gate formed thereon, a spacer on a sidewall of the dummy gate and a first dielectric layer surrounding the spacer. The dummy gate is removed to form a gate trench. A gate dielectric layer and at least one work function layer is formed in the gate trench. The work function layer and the gate dielectric layer are pulled down, and a portion of the spacer is laterally removed at the same time to widen a top portion of the gate trench. A low-resistivity metal layer is formed in a bottom portion of the gate trench. A hard mask layer is formed in the widened top portion of the gate trench. | 04-30-2015 |
20150118837 | Method Of Semiconductor Integrated Circuit Fabrication - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings. | 04-30-2015 |
20150118838 | NOR STRUCTURE FLASH MEMORY AND MANUFACTURING METHOD THEREOF - A NOR flash memory and its manufacturing method are provided in the present disclosure, they are in the field of flash memory. In the manufacturing method, a mask dielectric layer is formed on a second polysilicon layer of a gate stack structure. In addition, part of the mask dielectric layer is etched patternedly to expose part of the second polysilicon layer which is close to a source. Furthermore, the exposed second polysilicon layer is self aligned to form a metal silicide layer. Thus in the NOR flash memory, an unetched mask dielectric layer is substantially located between a metal silicide layer and a drain contacting hole of the NOR flash memory. A drain current between the gate electrode and the drain electrode is small, the above manufacturing method is not complex, a process window is large, a side effect is small, which are advantageous to large scale production. | 04-30-2015 |
20150132933 | III-Nitride Semiconductor Device Fabrication - A III-nitride semiconductor device which includes a barrier body between the gate electrode and the gate dielectric thereof. | 05-14-2015 |
20150132934 | Methods of Forming Electrically Conductive Lines Devices - A method of forming an electrically conductive buried line and an electrical contact thereto includes forming of a longitudinally elongated conductive line within a trench in substrate material. A longitudinal end part thereof within the trench is of spoon-like shape having a receptacle. The receptacle is filled with conductive material. Insulative material is formed over the conductive material that is within the receptacle. A contact opening is formed over the conductive material that is within the receptacle. Conductor material is formed in the contact opening in electrical connection with the second conductive material that is within the receptacle. Other method and device implementations are disclosed. | 05-14-2015 |
20150132935 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate having an active region defined by an isolation layer, a gate line defining a bit line contact region in the active region and extending in one direction, and a dielectric layer covering the semiconductor substrate and the gate line formed in the semiconductor substrate. The semiconductor device is provided with a bit line contact hole formed in the dielectric layer and exposing the bit line contact region. In order to alleviate a self-aligned contact (SAC) fails caused by a conductive material remaining in a contact hole, the semiconductor device contains a bit line contact spaced apart from a sidewall of the bit line contact hole and formed in the bit line contact hole. | 05-14-2015 |
20150295063 | MECHANISM FOR FORMING METAL GATE STRUCTURE - A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate and forming a metal gate stack including a metal gate electrode over the semiconductor substrate. The method also includes applying an oxidizing solution containing an oxidizing agent over the metal gate electrode to oxidize the metal gate electrode to form a metal oxide layer on the metal gate electrode. | 10-15-2015 |
20150303201 | SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - Semiconductor devices, and methods for forming the same, include forming a first wiring film and an etching buffer film in a cell array region and a peripheral circuit region of a substrate, and forming a contact hole by selectively etching the etching buffer film and the first wiring film so as to expose an active region of the cell array region and at least a part of a field isolation region adjacent thereto. A bit line contact is formed in the contact hole to be in contact with the active region, and a second wiring film is formed over the substrate. By patterning the second wiring film, the bit line contact, the etching buffer film, and the first wiring film, a bit line is formed in the cell array region and a peripheral gate is formed in the peripheral circuit region. | 10-22-2015 |
20150325471 | Device And Methods For Small Trench Patterning - A semiconductor device and methods for small trench patterning are disclosed. The device includes a plurality of gate structures, and an etch buffer layer. The etch buffer layer includes an overhang component disposed on the upper portion of the gate structures with an edge that extends laterally. The width between the edges of adjacent overhang components is narrower than the width between adjacent gate structures. | 11-12-2015 |
20150325472 | ALIGNMENT TO MULTIPLE LAYERS - A method of aligning a new pattern to more than one previously defined pattern during the manufacture of an integrated circuit. A method of aligning a photolighography pattern reticle to a first previously defined pattern in a first direction and also aligning the photolithography pattern reticle to a second previously defined pattern in a second direction. A method of aligning a photolighography pattern reticle to two previously defined patterns in the same direction. | 11-12-2015 |
20150333135 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A compound semiconductor device includes: a compound semiconductor layer; a protective insulating film that covers a top of the compound semiconductor layer; and a gate electrode formed on the protective insulating film, wherein the protective insulating film has a first trench and a second trench which is formed side by side with the first trench and in which the protective insulating film remains with only a predetermined thickness on the compound semiconductor layer, and wherein the gate electrode fills the first trench, and one end of the gate electrode is away from the first trench and located at least in the second trench. | 11-19-2015 |
20150372099 | CONTACT SILICIDE FORMATION USING A SPIKE ANNEALING PROCESS - A substrate is provided. The substrate has a source/drain region formed therein and a dielectric layer formed thereover. A contact hole is etched in the dielectric layer to expose a portion of the source/drain region. A metal material is formed on the source/drain region exposed by the opening. A first annealing process is performed to facilitate a reaction between the metal material and the portion of the source/drain region disposed therebelow, thereby forming a metal silicide in the substrate. The first annealing process is a spike annealing process. A remaining portion of the metal material is removed after the performing of the first annealing process. Thereafter, a second annealing process is performed. Thereafter, a contact is formed in the contact hole, the contact being formed on the metal silicide. | 12-24-2015 |
20160005743 | SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a first conductive structure including a first conductive pattern that is formed over a substrate, a second conductive structure formed adjacent to a sidewall of the first conductive structure, and an insulation structure including an air gap that is formed between the first conductive structure and the second conductive structure, wherein the second conductive structure includes a second conductive pattern, an ohmic contact layer that is to formed over the second conductive pattern, and a third conductive pattern that is formed over the ohmic contact layer and is separated from the first conductive pattern through the air gap. | 01-07-2016 |
20160027692 | Method of Semiconductor Integrated Circuit Fabrication - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings. | 01-28-2016 |
20160035617 | OVERLAY MARKS, METHODS OF FORMING THE SAME, AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES USING THE SAME - In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed. | 02-04-2016 |
20160042992 | Method for Forming Interconnect Structure - A method comprises forming a plurality of interconnect components over a gate structure, wherein a bottom metal line of the interconnect components is connected to the gate structure through a gate plug, depositing a dielectric layer over a top metal line of the interconnect components, forming an opening in the dielectric layer, depositing a first barrier layer on a bottom and sidewalls of the opening using a non-plasma based deposition process, depositing a second barrier layer over the first barrier layer using a plasma based deposition process and forming a pad in the opening. | 02-11-2016 |
20160056042 | METHOD OF FORMING A METAL PATTERN AND METHOD OF MANUFACTURING A DISPLAY SUBSTRATE - A method of forming a metal pattern is disclosed. According to the method, a gate electrode and a pixel electrode are formed on a substrate. A metal layer is formed covering the gate electrode and the pixel electrode. A photo pattern is formed wherein a thickness of an area of the photo pattern that overlaps the gate electrode is smaller than a thickness of other areas of the photo pattern. The photo pattern is soft-baked. The photo pattern is exposed to light. The photo pattern is developed to expose a portion of the metal layer that overlaps the gate electrode. The exposed portion of the metal layer is removed to form a source electrode and a drain electrode, the source electrode and the drain electrode being spaced apart from each other with respect to the gate electrode. | 02-25-2016 |
20160056158 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer. | 02-25-2016 |
20160056170 | METHOD OF FABRICATING FLASH MEMORY DEVICE - A method of fabricating a flash memory device includes sequentially forming an etching object layer and a lower sacrificial layer on a substrate, and forming an upper sacrificial pattern structure on the lower sacrificial layer. The upper sacrificial pattern structure includes an upper sacrificial pad portion and an upper sacrificial line portion on the lower sacrificial layer. An upper spacer is formed by covering a side wall of the upper sacrificial pattern structure. A lower sacrificial pattern structure including a lower sacrificial pad portion and a lower sacrificial line portion is formed by etching the lower sacrificial layer, by using the upper sacrificial pad portion and the upper spacer as an etch mask. A lower spacer layer is formed by covering the lower sacrificial pattern structure. Finally, a lower mask pattern including at least one line mask, at least one bridge mask, and at least one pad mask, is formed by etching the lower spacer layer and the lower sacrificial pattern structure. | 02-25-2016 |
20160064517 | Copper Contact Plugs with Barrier Layers - A device includes a conductive layer including a bottom portion, and a sidewall portion over the bottom portion, wherein the sidewall portion is connected to an end of the bottom portion. An aluminum-containing layer overlaps the bottom portion of the conductive layer, wherein a top surface of the aluminum-containing layer is substantially level with a top edge of the sidewall portion of the conductive layer. An aluminum oxide layer is overlying the aluminum-containing layer. A copper-containing region is over the aluminum oxide layer, and is spaced apart from the aluminum-containing layer by the aluminum oxide layer. The copper-containing region is electrically coupled to the aluminum-containing layer through the top edge of the sidewall portion of the conductive layer. | 03-03-2016 |
20160064518 | Oxidation and Etching Post Metal Gate CMP - A method includes forming a dummy gate of a transistor at a surface of a wafer, removing the dummy gate, and filling a metallic material into a trench left by the removed dummy gate. A Chemical Mechanical Polish (CMP) is then performed on the metallic material, wherein a remaining portion of the metallic material forms a metal gate of the transistor. After the CMP, a treatment is performed on an exposed top surface of the metal gate using an oxidation-and-etching agent comprising chlorine and oxygen. | 03-03-2016 |
20160071953 | SACRIFICIAL PRE-METAL DIELECTRIC FOR SELF-ALIGNED CONTACT SCHEME - Various embodiments herein relate to formation of contact etch stop layers in the context of forming gates and contacts. In certain embodiments, a novel process flow is used, which may involve the deposition and removal of a sacrificial pre-metal dielectric material before a particular contact etch stop layer is formed. An auxiliary contact etch stop layer may be used in addition to a primary etch stop layer that is deposited previously. In certain cases the contact etch stop layer is a metal-containing material such as a nitride or an oxide. The contact etch stop layer may be deposited through a cyclic vapor deposition in some embodiments. The process flows disclosed herein provide improved protection against over-etching gate stacks, thereby minimizing gate-to-contact leakage. Further, the disclosed process flows result in wider flexibility in terms of materials and deposition conditions used for forming various dielectric materials, thereby minimizing parasitic capacitance. | 03-10-2016 |
20160079071 | Manufacturing Method of Metal Oxide Semiconductor Transistor - A manufacturing method of MOS transistor, the MOS transistor includes a substrate, a gate oxide, a gate, a source/drain region and a silicide layer. The gate oxide is disposed on the substrate and the gate is disposed on the gate oxide. The source/drain region is disposed in the substrate at two sides of the gate. The silicide layer is disposed on the source/drain region, wherein the silicide layer includes a curved bottom surface and a curved top surface, both the curved top surface and the curved bottom surface bend toward the substrate and the curved top surface is sunken from two sides thereof, two ends of the silicide layer point tips raised up over the source/drain region and the silicide layer in the middle is thicker than the silicide layer in the peripheral, thereby forming a crescent structure. The present invention further provides a manufacturing method of the MOS transistor. | 03-17-2016 |
20160079260 | Methods of Fabricating Semiconductor Devices - A method of fabricating a semiconductor device includes providing a substrate having a cell region and a peripheral circuit region. A plurality of bit line structures are formed on the substrate in the cell region, and a gate structure having the same structure as each of the bit line structures is formed on the substrate in the peripheral circuit region. A spacer is formed on sidewalls of the bit line structures and the gate structure. The bit line structures extend in a first direction and are spaced apart from each other in a second direction that is perpendicular to the first direction by first grooves that extend in the first direction. A sacrificial layer is formed to fill the first grooves and to cover top surfaces of the bit line structures and the gate structure. The sacrificial layer is planarized until the top surfaces of the bit line structures and the gate structure are exposed. | 03-17-2016 |
20160099264 | SYSTEM AND METHOD OF MANUFACTURING A THIN FILM TRANSISTOR SUBSTRATE - In a method of manufacturing a thin film transistor substrate, a first metal layer is formed on a first surface of a base substrate. The base substrate is cooled by contacting the first metal layer with a first cooling plate and by contacting a second surface of the base substrate with a second cooling plate. The first and second surfaces of the base substrate face opposite directions. A gate electrode is formed by patterning the first metal layer. A source electrode and a drain electrode are formed. The source electrode is spaced apart from the drain electrode. The source and drain electrodes partially overlap the gate electrode. A pixel electrode electrically connected to the drain electrode is formed. | 04-07-2016 |
20160104788 | Methods of Fabricating Semiconductor Devices - Semiconductor devices and methods of fabricating semiconductor devices are provided. The methods may include forming an interlayer insulation layer on a substrate. The interlayer insulation layer may surround a dummy silicon gate and may expose a top surface of the dummy silicon gate. The methods may also include recessing a portion of the interlayer insulation layer such that a portion of the dummy silicon gate protrudes above a top surface of the recessed interlayer insulation layer and forming an etch stop layer on the recessed interlayer insulation layer. A top surface of the etch stop layer may be coplanarly positioned with the top surface of the dummy silicon gate. The methods may further include forming a trench exposing the substrate by removing the dummy silicon gate using the etch stop layer as a mask. | 04-14-2016 |
20160118298 | OXIDE MEDIATED EPITAXIAL NICKEL DISILICIDE ALLOY CONTACT FORMATION - Contact openings are formed into a dielectric material exposing a surface portion of a semiconductor substrate. An interfacial oxide layer is then formed in each contact opening and on an exposed surface portion of the interfacial oxide layer. A NiPt alloy layer is formed within each opening and on the exposed surface portion of each interfacial oxide layer. An anneal is then performed that forms a contact structure of, from bottom to top, a nickel disilicide alloy body having an inverted pyramidal shape, a Pt rich silicide cap region and an oxygen rich region. A metal contact is then formed within each contact opening and atop the oxygen rich region of each contact structure. | 04-28-2016 |
20160118421 | METHOD FOR MANUFACTURING ARRAY SUBSTRATE - The present invention provides a method for manufacturing an array substrate, wherein each data line in a plurality of data line groups forms an integral structure with a first shorting bar, and after etching a source-drain component to form a source electrode and a drain electrode, the data line groups which do not correspond to the first shorting bar is disconnected from the first shorting bar. By adopting the method provided by the present invention, electrostatic breakdown in the manufacturing process of the array substrate can be reduced. | 04-28-2016 |
20160126101 | METHOD FOR FORMING A VARIABLE THICKNESS DIELECTRIC STACK - Producing a variable thickness dielectric stack includes providing a substrate with a first patterned conductive layer thereon. A first dielectric thin film is deposited using ALD and a first patterned deposition inhibitor layer, which is subsequently removed, to form a first patterned conformal dielectric layer having a first pattern. A second dielectric thin film is deposited using ALD and a second patterned deposition inhibitor layer to form a second patterned conformal dielectric layer having a second pattern. A second patterned conductive layer is formed with at least a portion of the first and second patterned conductive layers overlapping each other forming an overlap region. A portion of the first or second pattern extends into the overlap region such that one portion of the overlap region includes the first and second dielectric thin films, and another portion of the overlap region includes only the first or second dielectric thin film. | 05-05-2016 |
20160126319 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device having a MOS gate structure includes forming a device structure on a semiconductor substrate; forming an interlayer dielectric to cover the device structure; forming a contact hole through the interlayer dielectric; forming a transition metal film (e.g., Ni) on a portion of the semiconductor substrate exposed by the contact hole; (e) forming a metal film (e.g., Ti) on the entire surface of the semiconductor substrate; forming an oxide film in the surface of the metal film; selectively removing the metal film in which the oxide film has been formed, to thereby expose the transition metal film; and (h) exposing, to a hydrogen plasma atmosphere, the semiconductor substrate in which the transition metal film and the oxide film have been exposed, to thereby cause the transition metal film to generate heat and react with the semiconductor substrate and form an ohmic contact there between. | 05-05-2016 |
20160141212 | TECHNIQUES AND CONFIGURATIONS TO REDUCE TRANSISTOR GATE SHORT DEFECTS - Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed. | 05-19-2016 |
20160163594 | METHOD FOR FORMING VOID-FREE POLYSILICON AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME - A method for fabricating a semiconductor device includes forming a buried gate electrode in a semiconductor substrate. An insulating layer is formed over the buried gate electrode and is etched to form a contact hole exposing the semiconductor substrate. A sacrificial spacer is formed on sidewalls of the insulating layer defining the contact hole. A polysilicon layer pattern is formed in the contact hole. The sacrificial spacer is removed to form an air gap around the polysilicon layer pattern. A thermal process is performed to remove a seam existing in the polysilicon layer pattern. | 06-09-2016 |
20160172186 | Method For Metal Gate Surface Clean | 06-16-2016 |
20160172364 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME | 06-16-2016 |
20160181143 | SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR FABRICATING THE SAME | 06-23-2016 |
20160189967 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes providing a semiconductor substrate having a front surface and a back surface; forming a transition metal layer in a surface of the semiconductor substrate; and exposing the semiconductor substrate having the transition metal layer formed thereon to a hydrogen plasma atmosphere formed by microwaves, to cause the transition metal layer to generate heat, Thus, during the exposure of the semiconductor substrate, a portion of the semiconductor substrate contacting the transition metal layer is heated by a transfer of heat from the transition metal layer and, at an interface of the transition metal layer and the semiconductor substrate, an ohmic contact is formed by reaction of the transition metal layer and the semiconductor substrate, such as to form a transition metal silicide when the semiconductor substrate is silicon carbide. The ohmic contact provides a lower contact resistivity and device properties can be prevented from degrading. | 06-30-2016 |
20160189968 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device that reduces degradation of device properties includes forming an impurity region in a surface layer of a semiconductor substrate by ion injection; forming a transition metal layer in a surface of the impurity region; and exposing the semiconductor substrate with the transition metal layer formed thereon to a hydrogen plasma atmosphere formed by microwaves. The transition metal layer is heated and the heat is transferred from the transition metal layer to the impurity region to form an ohmic contact at the interface of the transition metal layer and the impurity region by reaction of the transition metal layer and the impurity region, and the impurity region is activated. When the substrate is a silicon carbide substrate, the ohmic contact is composed of a transition metal silicide and the impurity region, which is an ion injection layer, is activated. | 06-30-2016 |
20160189969 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a device structure in a surface of a semiconductor substrate, forming, in a face of the semiconductor substrate, a transition metal layer that contacts the semiconductor substrate, and exposing the semiconductor substrate having the transition metal layer formed thereon to a hydrogen plasma atmosphere formed by microwaves to cause the transition metal layer to generate heat. During exposure of the semiconductor substrate to the hydrogen plasma atmosphere, a portion of the semiconductor substrate contacting the transition metal layer is heated by a transfer of the heat from the transition metal layer, and an ohmic contact is formed at an interface of the transition metal layer and the semiconductor substrate by reaction of the transition metal layer and the semiconductor substrate. When the semiconductor substrate is silicon carbide, the ohmic contact is composed of a silicide, such as a transition metal silicide. | 06-30-2016 |
20160204030 | METHODS OF FORMING SEMICONDUCTOR DEVICE | 07-14-2016 |
20160380060 | SEMICONDUCTOR DEVICE HAVING AIR GAP AND METHOD FOR MANUFACTURING THE SAME, MEMORY CELL HAVING THE SAME AND ELECTRONIC DEVICE HAVING THE SAME - A method for fabricating a semiconductor device may include: forming a plurality of first isolation trenches and a plurality of line-shaped active regions by etching a semiconductor substrate; forming a line-shaped device isolation region in each of the plurality of first isolation trenches; forming a plurality of second isolation trenches extending in a second direction by etching the plurality of line-shaped active regions and the plurality of line-shaped device isolation regions; forming a connection trench to connect the plurality of second isolation trenches to each other; forming a shielding line in each of the plurality of second isolation trenches; and forming a shielding line interconnection in the connection trench. | 12-29-2016 |
20170236918 | REPLACEMENT METAL GATE STRUCTURES | 08-17-2017 |
20170236919 | ELECTRONIC DEVICE INCLUDING TRANSISTOR AND METHOD FOR FABRICATING THE SAME | 08-17-2017 |
20190148554 | REPLACEMENT METAL GATE STRUCTURES | 05-16-2019 |