Class / Patent application number | Description | Number of patent applications / Date published |
438353000 | Including isolation structure | 12 |
20090246928 | Semiconductor device with bipolar transistor and method of fabricating the same - Disclosed is a semiconductor device with a bipolar transistor and method of fabricating the same. The device may include a collector region in a semiconductor substrate. A base pattern may be disposed on the collector region. A hard mask pattern may be disposed on the base pattern. The hard mask pattern may include a buffering insulation pattern and a flatness stopping pattern stacked in sequence. An emitter electrode may be disposed in a hole that locally exposes the base pattern, penetrating the hard mask pattern. A base electrode may contact an outer sidewall of the hard mask pattern and may be disposed on the base pattern. The flatness stopping pattern may contain an insulative material with etching selectivity to the buffering insulation pattern, the emitter electrode, and the base electrode. | 10-01-2009 |
20110312147 | TRANSISTOR STRUCTURE WITH A SIDEWALL-DEFINED INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION AND METHOD OF FORMING THE TRANSISTOR - Disclosed are embodiments of a bipolar or heterojunction bipolar transistor and a method of forming the transistor. The transistor can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance C | 12-22-2011 |
20130065374 | Fluorine Implant Under Isolation Dielectric Structures to Improve Bipolar Transistor Performance and Matching - A method of fabricating an integrated circuit including bipolar transistors that reduces the effects of transistor performance degradation and transistor mismatch caused by charging during plasma etch, and the integrated circuit so formed. A fluorine implant is performed at those locations at which isolation dielectric structures between base and emitter are to be formed, prior to formation of the isolation dielectric. The isolation dielectric structures may be formed by either shallow trench isolation, in which the fluorine implant is performed after trench etch, or LOCOS oxidation, in which the fluorine implant is performed prior to thermal oxidation. The fluorine implant may be normal to the device surface or at an angle from the normal. Completion of the integrated circuit is then carried out, including the use of relatively thick copper metallization requiring plasma etch. | 03-14-2013 |
20140187014 | METHODS FOR FORMING BIPOLAR TRANSISTORS - Methods are provided for forming a device that includes merged vertical and lateral transistors with collector regions of a first conductivity type between upper and lower base regions of opposite conductivity type that are Ohmically coupled via intermediate regions of the same conductivity type and to the base contact. The emitter is provided in the upper base region and the collector contact is provided in outlying sinker regions extending to the thin collector regions and an underlying buried layer. As the collector voltage increases part of the thin collector regions become depleted of carriers from the top by the upper and from the bottom by the lower base regions. This clamps the collector regions' voltage well below the breakdown voltage of the PN junction formed between the buried layer and the lower base region. The gain and Early Voltage are increased and decoupled and a higher breakdown voltage is obtained. | 07-03-2014 |
438359000 | Dielectric isolation formed by grooving and refilling with dielectrical material | 7 |
20100055860 | Semiconductor Process and Integrated Circuit - In the fabrication of an integrated circuit, a shallow trench for isolation of a vertical bipolar transistor comprised in the circuit is fabricated by providing a semiconductor substrate of a first doping type. A buried collector region of a second doping type for the bipolar transistor is formed in the substrate. A silicon layer is epitaxially grown on top of the substrate. An active region of the second doping type for the bipolar transistor is formed in the epitaxially grown silicon layer, the active region being located above the buried collector region. A first trench is formed in the epitaxially grown silicon layer and the silicon substrate, the first trench surrounding, in a horizontal plane, the active region and extending vertically a distance into the substrate. An electrically insulating material is formed in the first trench. | 03-04-2010 |
20100323488 | Semiconductor device and method of manufacturing the same - Provided is a semiconductor device including: a silicon substrate; at least two trenches spaced apart from each other, being in parallel with each other, and being formed by vertically etching the silicon substrate from a surface thereof; an electrically insulating film for burying therein at least bottom surfaces of the trenches; a base region formed in a region of the silicon substrate located between the two trenches; and an emitter region and a collector region formed on portions of side surfaces of the trenches, respectively, the portions of the sides located above the insulating film and formed in the base region. | 12-23-2010 |
20110159659 | Novel Manufacturing Approach for Collector and N Type Buried Layer Of Bipolar Transistor - This invention disclosed a novel manufacturing approach of collector and buried layer of a bipolar transistor. One aspect of the invention is that an oxide-nitride-oxide (ONO) sandwich structure is employed instead of oxide-nitride dual layer structure before trench etching. Another aspect is, through the formation of silicon oxide spacer in trench sidewall and silicon oxide remaining in trench bottom in the deposition and etch back process, the new structure hard mask can effectively protect active region from impurity implanted in ion implantation process. | 06-30-2011 |
20130149832 | TRANSISTOR STRUCTURE WITH A SIDEWALL-DEFINED INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION AND METHOD OF FORMING THE TRANSISTOR - Disclosed are embodiments of a bipolar or heterojunction bipolar transistor and a method of forming the transistor. The transistor can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance C | 06-13-2013 |
438360000 | With epitaxial semiconductor formation in groove | 2 |
20090280616 | INTEGRATED TRANSISTOR, PARTICULARLY FOR VOLTAGES AND METHOD FOR THE PRODUCTION THEREOF - Integrated transistor and method for the production is disclosed. An explanation is given of, inter alia, a transistor having an electrically insulating isolating trench extending from a main area in the direction of a connection region remote from the main area. Moreover, the transistor contains an auxiliary trench extending from the main area as far as the connection region remote from the main area. The transistor requires a small chip area and has outstanding electrical properties. | 11-12-2009 |
20100330765 | INTEGRATED TRANSISTOR, PARTICULARLY FOR VOLTAGES AND METHOD FOR THE PRODUCTION THEREOF - Integrated transistor and method for the production is disclosed. An explanation is given of, inter alia, a transistor having an electrically insulating isolating trench extending from a main area in the direction of a connection region remote from the main area. Moreover, the transistor contains an auxiliary trench extending from the main area as far as the connection region remote from the main area. The transistor requires a small chip area and has outstanding electrical properties. | 12-30-2010 |
438361000 | Including deposition of polysilicon or noninsulative material into groove | 1 |
20130122677 | Methods of Forming Electrostatic Discharge Devices - Electrostatic discharge devices and methods of forming thereof are disclosed. In one embodiment, a semiconductor device includes an electrostatic discharge (ESD) device region disposed within a semiconductor body. A first ESD device is disposed in a first region of the ESD device region, and a second ESD device disposed in a second region of the ESD device region. The second region is separated from the first region by a first trench. | 05-16-2013 |
438362000 | Recessed oxide by localized oxidation (i.e., LOCOS) | 1 |
438363000 | With epitaxial semiconductor layer formation | 1 |
20100279482 | Semiconductor Device and Method of Manufacturing the Same - In a semiconductor device according to the present invention, two epitaxial layers are formed on a P type substrate. In the substrate and the epitaxial layers, isolation regions are formed to divide the substrate and the epitaxial layers into a plurality of islands. Each of the isolation regions is formed by connecting first and second P type buried layers with a P type diffusion layer. By disposing the second P type buried layer between the first P type buried layer and the P type diffusion layer, a lateral diffusion width of the first P type buried layer is reduced. By use of this structure, a formation region of the isolation region is reduced in size. | 11-04-2010 |