Class / Patent application number | Description | Number of patent applications / Date published |
438312000 | Having heterojunction | 27 |
20080305602 | Transistor Manufacture - An oxide layer is formed on material defining and surrounding an emitter window. The technique comprises depositing a non-conformal oxide layer on the surrounding material and in the emitter window, whereby the thickness of at least a portion of the oxide layer in the emitter window is smaller than the thickness of the oxide layer on the surrounding material outside the emitter window; and removing at least a portion of the oxide layer in the emitter window so as to reveal at least a portion of the bottom of the emitter window whilst permitting at least a portion of the oxide layer to remain on the surrounding material. The technique can be used in the manufacture of a self-aligned epitaxial base BJT (bipolar junction transistor) or SiGe HBT (hetero junction bipolar transistor). | 12-11-2008 |
20090029517 | Method of Making a Semiconductor Device - A method of making a semiconductor device, comprising: forming a first material and a second material; forming a first oxide on the first material and a second oxide on the second material; and etching second material so as to remove at least a portion of the second material. | 01-29-2009 |
20090053872 | METHOD OF MANUFACTURING A BIPOLAR TRANSISTOR - The invention relates to a method of manufacturing a bipolar transistor on a semiconductor substrate ( | 02-26-2009 |
20090221125 | Bipolar Junction Transistor and Manufacturing Method Thereof - An improved bipolar junction transistor and a method for manufacturing the same are provided. The bipolar junction transistor includes: a buried layer and a high concentration N-type collector region in a P-type semiconductor substrate; a low concentration P-type base region in the semiconductor substrate above the buried layer; a first high concentration P-type base region along an edge of the low concentration P-type base region; a second high concentration P-type base region at a center of the low concentration P-type base region; a high concentration N-type emitter region between the first and second high concentration base regions; and insulating layer spacers between the high concentration base regions and the high concentration emitter regions. In the bipolar junction transistor, the emitter-base distance can be reduced using a trench and an insulating layer spacer. This may improve base voltage and high-speed response characteristics. | 09-03-2009 |
20100047986 | GROUP III-V COMPOUND SEMICONDUCTOR BASED HETEROJUNCTION BIPOLAR TRANSISTORS WITH VARIOUS COLLECTOR PROFILES ON A COMMON WAFER - A wafer comprising at least one high F | 02-25-2010 |
20100062578 | Bipolar Transistor and Method for Making Same - One or more embodiments of the invention relate to a method of making a heterojunction bipolar transistor, including: forming a collector layer; forming a stack of at least a second dielectric layer overlying a first dielectric layer, the stack formed over the collector layer; removing a portion of each of the dielectric layers to form an opening through the stack; and forming a base layer within the opening. | 03-11-2010 |
20100068863 | Method of Manufacturing a Bipolar Transistor and Bipolar Transistor Obtained Therewith - The invention relates to a method of manufacturing a semiconductor device ( | 03-18-2010 |
20100159664 | SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR STRUCTURE AND METHOD - Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology. | 06-24-2010 |
20110230031 | BIPOLAR JUNCTION TRANSISTOR HAVING A HIGH GERMANIUM CONCENTRATION IN A SILICON-GERMANIUM LAYER AND A METHOD FOR FORMING THE BIPOLAR JUNCTION TRANSISTOR - A method for forming a germanium-enriched region in a heterojunction bipolar transistor and a heterojunction bipolar transistor comprising a germanium-enriched region. A base having a silicon-germanium portion is formed over a collector. Thermal oxidation of the base causes a germanium-enriched region to form on a surface of the silicon-germanium portion subjected to the thermal oxidation. An emitter is formed overlying the germanium-enriched portion region. The germanium-enriched region imparts advantageous operating properties to the heterojunction bipolar transistor, including improved high-frequency/high-speed operation. | 09-22-2011 |
20120064688 | METHOD FOR MANUFACTURING SILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR - A manufacturing method of a SiGe HBT is disclosed. Alter an emitter region is formed, an ion implantation is performed with a tilt angle to a base region by using an extrinsic base ion implantation process; boron ions are implanted during the extrinsic base ion implantation with an implantation dose from 1e15 to 1e16 cm | 03-15-2012 |
20130005108 | SILICON GERMANIUM (SiGe) HETEROJUNCTION BIPOLAR TRANSISTOR (HBT) - A heterojunction bipolar transistor (HBT), an integrated circuit (IC) chip including at least one HBT and a method of forming the IC. The HBT includes an extrinsic base with one or more buried interstitial barrier layer. The extrinsic base may be heavily doped with boron and each buried interstitial barrier layer is doped with a dopant containing carbon, e.g., carbon or SiGe:C. The surface of the extrinsic base may be silicided. | 01-03-2013 |
20150093872 | LATERAL HETEROJUNCTION BIPOLAR TRANSISTOR WITH LOW TEMPERATURE RECESSED CONTACTS - A method of forming the heterojunction bipolar transistor that includes providing a stack of a base layer, an extrinsic base layer, a first metal containing layer, and a dielectric cap layer. The dielectric cap layer and the first metal containing layer may be etched to provide a base contact and a dielectric cap. Exposed portions of the base layer may be etched selectively to the dielectric cap. A remaining portion of the base layer provides the base region. A hydrogenated silicon containing layer may be deposited with a low temperature deposition method. At least a portion of the hydrogenated silicon containing layer is formed on at least sidewalls of the base region. A second metal containing layer may be formed on the hydrogenated silicon containing layer. The second metal containing and the hydrogenated silicon containing layer may be etched to provide an emitter region and a collector region. | 04-02-2015 |
20160049493 | EMITTER CONTACT EPITAXIAL STRUCTURE AND OHMIC CONTACT FORMATION FOR HETEROJUNCTION BIPOLAR TRANSISTOR - Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device. The IC device includes a diffusion control layer as part of an emitter epitaxial structure. The IC device may utilize a common metallization scheme to simultaneously form an emitter contact and a base contact. Other embodiments may also be described and/or claimed. | 02-18-2016 |
438314000 | And additional electrical device | 4 |
20100240187 | INTEGRATED SEMICONDUCTOR STRUCTURE INCLUDING A HETEROJUNCTION BIPOLAR TRANSISTOR AND A SCHOTTKY DIODE - An integrated semiconductor structure includes a heterojunction bipolar transistor and a Schottky diode. The structure has a substrate, the heterojunction bipolar transistor overlying and contacting the substrate, wherein the heterojunction bipolar transistor includes a transistor collector layer, and a Schottky diode overlying the substrate and overlying the transistor collector layer. The Schottky diode includes a Schottky diode barrier layer structure that desirably is not of the same material, doping, and thickness as the transistor collector layer. | 09-23-2010 |
20110269289 | TRANSISTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A method of manufacturing a transistor device ( | 11-03-2011 |
20140154857 | Memory Device And Method For Making Same - Embodiments relate to a method of forming a memory array,comprising: forming a collector layer; forming a plurality of collector regions in the collector layer; forming a plurality of base regions over the collector region; forming a plurality of emitter regions over the base regions; forming a plurality of memory elements over the emitter regions, wherein the collector regions, base regions and emitter regions form heterojunction bipolar transistors. | 06-05-2014 |
20160005836 | HETEROJUNCTION BIPOLAR TRANSISTOR - The present disclosure is directed to a method that includes exposing a surface of a silicon substrate in a first region between first and second isolation trenches, etching the silicon substrate in the first region to form a recess between the first and second isolation trenches, and forming a base of a heterojunction bipolar transistor by selective epitaxial growth of a film comprising SiGe in the recess. | 01-07-2016 |
438318000 | Including isolation structure | 8 |
20080268604 | METHODS OF BASE FORMATION IN A BiCMOS PROCESS - Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer. | 10-30-2008 |
20100047987 | METHOD OF FABRICATING A BIPOLAR TRANSISTOR - The invention provides a method for fabricating a bipolar transistor applying a standard shallow trench isolation fabrication method to simultaneously form a vertical bipolar transistor ( | 02-25-2010 |
20130095631 | BIPOLAR TRANSISTOR WITH LOW RESISTANCE BASE CONTACT AND METHOD OF MAKING THE SAME - Embodiments of the present invention provide a bipolar transistor with low resistance base contact and method of manufacturing the same. The bipolar transistor includes an emitter, a collector, and an intrinsic base between the emitter and the collector. The intrinsic base extends laterally to an extrinsic base. The extrinsic base further includes a first semiconductor material with a first bandgap and a second semiconductor material with a second bandgap that is smaller than the first bandgap. | 04-18-2013 |
20130178037 | METHOD OF MANUFACTURING HETEROJUNCTION BIPOLAR TRANSISTOR AND HETEROJUNCTION BIPOLAR TRANSISTOR - A method of forming a heterojunction bipolar transistor by depositing a first stack comprising an polysilicon layer and a sacrificial layer on a mono-crystalline silicon substrate surface; patterning that stack to form a trench extending to the substrate; depositing a silicon layer over the resultant structure; depositing a silicon-germanium-carbon layer over the resultant structure; selectively removing the silicon-germanium-carbon layer from the sidewalls of the trench; depositing a boron-doped silicon-germanium-carbon layer over the resultant structure; depositing a further silicon-germanium-carbon layer over the resultant structure; | 07-11-2013 |
20150056777 | DEVICE ISOLATION WITH IMPROVED THERMAL CONDUCTIVITY - A method of making a semiconductor structure includes forming a trench through a shallow trench isolation (STI) structure and into a substrate, and forming a liner including an electrical insulator material on sidewalls of the trench. The method also includes forming a core including a high thermal conductivity material in the trench and on the liner, and forming a cap in the trench and on the core. | 02-26-2015 |
20150303275 | BASE PROFILE OF SELF-ALIGNED BIPOLAR TRANSISTORS FOR POWER AMPLIFIER APPLICATIONS - According to a bipolar transistor structure having a transistor top and a transistor bottom herein, a silicon substrate located at the transistor bottom has a collector region of a first conductivity type. An epitaxial base layer of a second conductivity type overlies, relative to the transistor top and bottom, a portion of the collector region. The epitaxial base layer has a bottom surface on the silicon substrate and a top surface opposite the bottom surface. A top region, relative to the transistor top and bottom, of the epitaxial base layer comprises a concentration of germanium having atomic compositions sufficient to avoid impacting transistor parameters, and sufficient to be resistant to selective chemical etching. A silicon emitter layer of the first conductivity type overlies, relative to the transistor top and bottom, a portion of the epitaxial base layer adjacent to the top surface of the epitaxial base layer. | 10-22-2015 |
20160190277 | BIPOLAR TRANSISTOR STRUCTURE AND A METHOD OF MANUFACTURING A BIPOLAR TRANSISTOR STRUCTURE - According to various embodiments, a bipolar transistor structure may include: a substrate; a collector region in the substrate; a base region disposed over the collector region, an emitter region disposed over the base region; a base terminal laterally electrically contacting the base region, wherein the base terminal includes polysilicon. | 06-30-2016 |
438319000 | Air isolation (e.g., mesa, etc.) | 1 |
20160380088 | BIPOLAR JUNCTION TRANSISTORS WITH A BURIED DIELECTRIC REGION IN THE ACTIVE DEVICE REGION - Device structure and fabrication methods for a bipolar junction transistor. A trench isolation region is formed that bounds an active device region along a sidewall. A dielectric region is formed that extends laterally from the sidewall of the active device region into the active device region. The dielectric region is located beneath a top surface of the active device region such that a section of the active device region is located between the top surface and the dielectric region. | 12-29-2016 |
438320000 | Self-aligned | 2 |
20090075446 | METHOD OF FABRICATING A HETEROJUNCTION BIPOLAR TRANSISTOR - The invention provides a method for fabricating a heterojunction bipolar transistor with a base connecting region ( | 03-19-2009 |
20150140771 | METHOD FOR FABRICATING A BIPOLAR TRANSISTOR HAVING SELF-ALIGNED EMITTER CONTACT - A method of producing a semiconductor device, comprising a substrate layer made of a semiconductor material of a first conductivity type and having a first insulation region, and a vertical bipolar transistor having a first vertical portion of a collector made of monocrystalline semiconductor material of a second conductivity type and disposed in an opening of the first insulation region, a second insulation region lying partly on the first vertical portion of the collector and partly on the first insulation region and having an opening in the region of the collector, in which opening a second vertical portion of the collector made of monocrystalline material is disposed, the portion including an inner region of the second conductivity type, a base made of monocrystalline semiconductor material of the first conductivity type, a base connection region surrounding the base in the lateral direction, a T-shaped emitter made of semiconductor material of the second conductivity type and overlapping the base connection region, wherein the base connection region, aside from a seeding layer adjacent the substrate or a metallization layer adjacent a base contact, consists of a semiconductor material which differs in its chemical composition from the semiconductor material of the collector, the base and the emitter and in which the majority charge carriers of the first conductivity type have greater mobility compared thereto. | 05-21-2015 |