Class / Patent application number | Description | Number of patent applications / Date published |
438241000 | And additional field effect transistor (e.g., sense or access transistor, etc.) | 13 |
20080261363 | DUAL GATED FINFET GAIN CELL - A memory gain cell for a memory circuit, a memory circuit formed from multiple memory gain cells, and methods of fabricating such memory gain cells and memory circuits. The memory gain cell includes a storage device capable of holding a stored electrical charge, a write device, and a read device. The read device includes a fin of semiconducting material, electrically-isolated first and second gate electrodes flanking the fin, and a source and drain formed in the fin adjacent to the first and the second gate electrodes. The first gate electrode is electrically coupled with the storage device. The first and second gate electrodes are operative for gating a region of the fin defined between the source and the drain to thereby regulate a current flowing from the source to the drain. When gated, the magnitude of the current is dependent upon the electrical charge stored by the storage device. | 10-23-2008 |
20100120213 | Embedded DRAM with multiple gate oxide thicknesses - A method of forming an embedded DRAM cell having multiple-thickness gate dielectrics. An oxidation-enhancing dopant is selectively implanted into a well region in an area that is exposed by a first mask. A thermal oxidation step simultaneously produces the field dielectric for two distinct devices each having a different oxide thickness. The method is applicable to quad-density DRAM cells using fewer oxidation steps. The method is also applicable to planar DRAM cells, and does not require increasing the number of masks during the fabrication of planar DRAM cells. | 05-13-2010 |
20100136759 | METHOD OF FABRICATING A DYNAMIC RANDOM ACCESS MEMORY - A method of fabricating a dynamic random access memory is provided. First, a substrate at least having a memory device area and a peripheral device area is provided, wherein an isolation structure and a capacitor are formed in the substrate of the memory device area, and an isolation structure and a well are formed in the substrate of the peripheral device area. A first oxide layer is formed on the substrate of the peripheral device area, and a passing gate isolation structure is formed on the substrate of the memory device area at the same time. A second oxide layer is formed on the substrate of the memory device area. And a first transistor is formed on the substrate of the memory device area, a passing gate is formed on the passing gate isolation structure, and a second transistor is formed on the substrate of the peripheral device area. | 06-03-2010 |
20100267210 | Semiconductor device and method of fabricating the same - A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cell active region. One of the at least two cell epitaxial layers may extend to one end of the cell gate capping layer and another one of the at least two cell epitaxial layers may extend to an opposite end of the cell gate capping layer. Cell impurity regions may be disposed in the cell active region. The cell impurity regions may correspond to a respective one of the at least two cell epitaxial layers. | 10-21-2010 |
20110165744 | MEMORY ARRAY WITH ULTRA-THIN ETCHED PILLAR SURROUND GATE ACCESS TRANSISTORS AND BURIED DATA/BIT LINES - A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally upward and aligned generally atop a corresponding data/bit line. The access transistors have a pillar extending generally upward with a source region formed so as to be in electrical communication with the corresponding data/bit line and a drain region formed generally at an upper portion of the pillar and a surround gate structure substantially completely encompassing the pillar in lateral directions and extending substantially the entire vertical extent of the pillar and word lines extending generally in a second direction and in electrical contact with a corresponding surround gate structure at least a first surface thereof such that bias voltage applied to a given word line is communicated substantially uniformly in a laterally symmetric extent about the corresponding pillar via the surround gate structure. | 07-07-2011 |
20130267071 | SELF-ALIGNED STRAP FOR EMBEDDED CAPACITOR AND REPLACEMENT GATE DEVICES - After forming a planarization dielectric layer in a replacement gate integration scheme, disposable gate structures are removed and a stack of a gate dielectric layer and a gate electrode layer is formed within recessed gate regions. Each gate electrode structure is then recessed below a topmost surface of the gate dielectric layer. A dielectric metal oxide portion is formed above each gate electrode by planarization. The dielectric metal oxide portions and gate spacers are employed as a self-aligning etch mask in combination with a patterned photoresist to expose and metalize semiconductor surfaces of a source region and an inner electrode in each embedded memory cell structure. The metalized semiconductor portions form metal semiconductor alloy straps that provide a conductive path between the inner electrode of a capacitor and the source of an access transistor. | 10-10-2013 |
20130330891 | DRAM WITH A NANOWIRE ACCESS TRANSISTOR - A semiconductor nanowire is formed integrally with a wraparound semiconductor portion that contacts sidewalls of a conductive cap structure located at an upper portion of a deep trench and contacting an inner electrode of a deep trench capacitor. The semiconductor nanowire is suspended from above a buried insulator layer. A gate dielectric layer is formed on the surfaces of the patterned semiconductor material structure including the semiconductor nanowire and the wraparound semiconductor portion. A wraparound gate electrode portion is formed around a center portion of the semiconductor nanowire and gate spacers are formed. Physically exposed portions of the patterned semiconductor material structure are removed, and selective epitaxy and metallization are performed to connect a source-side end of the semiconductor nanowire to the conductive cap structure. | 12-12-2013 |
20140024183 | METHOD OF FORMING SEMICONDUCTOR STRUCTURE - A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. An oxide material layer and a first conductive material layer are sequentially formed on the substrate in the cell and periphery areas. A patterning step is performed to form first and second stacked structures on the substrate respectively in the cell and periphery areas. First and second spacers are formed respectively on sidewalls of the first and second stacked structures. At least two first doped regions are formed in the substrate beside the first stacked structure, and two second doped regions are formed in the substrate beside the second stacked structure. A dielectric layer and a second conductive layer are formed at least on the first stacked structure. The first stacked structure, the dielectric layer, and the second conductive layer in the cell area constitute a charge storage structure. | 01-23-2014 |
20150050789 | Meander Line Resistor Structure - A method comprises implanting ions in a substrate to form a first active region and a second active region, depositing a first dielectric layer over the substrate, forming a first via and a second via in the first dielectric layer, wherein the first via is over the first active region and the second via is over the second active region, depositing a second dielectric layer over the first dielectric layer, forming a third via and a fourth via in the second dielectric layer, wherein the third via is over the first via and the fourth via is over the second via and forming a connector in a metallization layer over the second dielectric layer, wherein the connector is electrically connected to the third via and the fourth via. | 02-19-2015 |
20160064402 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In method for manufacturing a semiconductor device including a nonvolatile memory, a new method for manufacturing a capacitor element is provided. After working a control gate electrode, a gate insulation film including an electric charge accumulation section, and a memory gate electrode of a memory cell, in order to protect the memory cell, a p-type well of a MISFET is formed in a state the control gate electrode, the gate insulation film, and the memory gate electrode are covered by an insulation film. Also, this insulation film is used as a capacitor insulation film of a laminated type capacitor element. | 03-03-2016 |
20160126245 | EMBEDDED DRAM IN REPLACEMENT METAL GATE TECHNOLOGY - Methods for forming an eDRAM with replacement metal gate technology and the resulting device are disclosed. Embodiments include forming first and second dummy electrodes on a substrate, each dummy electrode having spacers at opposite sides and being surrounded by an ILD; removing the first and second dummy electrodes, forming first and second cavities, respectively; forming a hardmask over the substrate, exposing the first cavity; forming a deep trench in the substrate through the first cavity; removing the hardmask; and forming a capacitor in the first cavity and deep trench and concurrently forming an access transistor in the second cavity. | 05-05-2016 |
438242000 | Including transistor formed on trench sidewalls | 2 |
20090176339 | Method of multi-port memory fabrication with parallel connected trench capacitors in a cell - A method is provided for fabricating a multi-port memory in which a plurality of parallel connected capacitors are in a cell. A plurality of trench capacitors are formed which have capacitor dielectric layers extending along walls of the plurality of trenches, the plurality of trench capacitors having first capacitor plates and second capacitor plates opposite the capacitor dielectric layers from the first capacitor plates. The first capacitor plates are conductively tied together and the second capacitor plates are conductively tied together. In this way, the first capacitor plates are adapted to receive a same variable voltage and the second capacitor plates are adapted to receive a same fixed voltage. | 07-09-2009 |
20130171783 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE WITH VERTICAL CHANNEL TRANSISTOR - A semiconductor memory device includes a semiconductor substrate, a semiconductor pillar extending from the semiconductor substrate, the semiconductor pillar comprising a first region, a second region, and a third region, the second region positioned between the first region and the third region, the third region positioned between the second region and the semiconductor substrate, immediately adjacent regions having different conductivity types, a first gate pattern disposed on the second region with a first insulating layer therebetween, and a second gate pattern disposed on the third region, wherein the second region is ohmically connected to the substrate by the second gate pattern. | 07-04-2013 |