Entries |
Document | Title | Date |
20080242009 | SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - A method is provided for fabricating a memory device. A semiconductor substrate is provided which includes a first well region having a first conductivity type, a second well region having the first conductivity type, a first gate structure overlying the first well region and the second gate structure overlying the second well region. An insulating material layer is conformally deposited overlying exposed portions of the semiconductor substrate. Photosensitive material is provided over a portion of the insulating material layer which overlies a portion of the second well region. The photosensitive material exposes portions of the insulating material layer. The exposed portions of the insulating material layer are anisotropically etched to provide a sidewall spacer adjacent a first sidewall of the second gate structure, and an insulating spacer block formed overlying a portion of the second gate structure and adjacent a second sidewall of the second gate structure. A drain region and a source/base region are formed in the semiconductor substrate adjacent the first gate structure and a cathode region is formed in the semiconductor substrate adjacent the second gate structure. The drain region, the source/base region, and the cathode region have a second conductivity type. An anode region of the first conductivity type is formed adjacent the second gate structure in a portion of the source/base region. | 10-02-2008 |
20090298238 | METHODS FOR FABRICATING MEMORY CELLS AND MEMORY DEVICES INCORPORATING THE SAME - A method for fabricating a memory device is provided. A semiconductor layer is provided that includes first, second, third and fourth well regions of a first conductivity type in the semiconductor layer. A first gate structure overlies the first well region, a second gate structure overlies the second well region, a third gate structure overlies the third well region and is integral with the second gate structure, and a fourth gate structure overlies the fourth well region. Sidewall spacers are formed adjacent a first sidewall of the first gate structure and sidewalls of the second through fourth gate structures. In addition, an insulating spacer block is formed overlying a portion of the first well region and a portion of the first gate structure. The insulating spacer block is adjacent a second sidewall of the first gate structure. A first source region is formed adjacent the first gate structure, a common drain/cathode region is formed between the first and second gate structures, a second source region is formed adjacent the third gate structure, a common drain/source region is formed between the third and fourth gate structures, and a drain region is formed adjacent the fourth gate structure. A first base region is formed that extends into the first well region under the insulating spacer block adjacent the first gate structure, and an anode region is formed in the first well region that extends into the first well region adjacent the first base region. | 12-03-2009 |
20090317949 | ESD Protecting Circuit and Manufacturing Method Thereof - An ESD protecting circuit and a manufacturing method thereof are provided. The ESD protecting circuit includes a device isolation layer, first and second high-concentration impurity regions, a third high-concentration impurity region of a complementary type, first and second conductive wells, and a fourth conductive impurity region. The ESD protecting circuit is configured as a field transistor without a gate electrode, and the high breakdown voltage characteristics of the field transistor are lowered by implanting impurity ions, providing an ESD protecting circuit with a low breakdown voltage and low leakage current. Because the leakage current is reduced, the ESD protecting circuit can be used for an analog I/O device that is sensitive to current fluxes. Also, an N-type well may protect a junction of the field transistor. | 12-24-2009 |
20100062573 | METHOD FOR PRODUCING AN ELECTRONIC COMPONENT, METHOD FOR PRODUCING A THYRISTOR, METHOD FOR PRODUCING A DRAIN-EXTENDED MOS FILED-EFFECT TRANSISTOR, ELECTRONIC COMPONENT, DRAIN-EXTENDED MOS FIELD-EFFECT TRANSISTOR, ELECTRONIC COMPONENT ARRANGEMENT - In a method for producing an electronic component, a first doped connection region and a second doped connection region are formed on or above a substrate; a body region is formed between the first doped connection region and the second doped connection region; at least two gate regions separate from one another are formed on or above the body region; at least one partial region of the body region is doped by means of introducing dopant atoms, wherein the dopant atoms are introduced into the at least one partial region of the body region through at least one intermediate region formed between the at least two separate gate regions. | 03-11-2010 |
20100093136 | PROCESS FOR MANUFACTURING A CHARGE-BALANCE POWER DIODE AND AN EDGE-TERMINATION STRUCTURE FOR A CHARGE-BALANCE SEMICONDUCTOR POWER DEVICE - An embodiment of a process for manufacturing a semiconductor power device envisages the steps of: providing a body made of semiconductor material having a first top surface; forming an active region with a first type of conductivity in the proximity of the first top surface and inside an active portion of the body; and forming an edge-termination structure. The edge-termination structure is formed by: a ring region having the first type of conductivity and a first doping level, set within a peripheral edge portion of the body and electrically connected to the active region; and a guard region, having the first type of conductivity and a second doping level, higher than the first doping level, set in the proximity of the first top surface and connecting the active region to the ring region. The process further envisages the steps of: forming a surface layer having the first type of conductivity on the first top surface, also at the peripheral edge portion, in contact with the guard region; and etching the surface layer in order to remove it above the edge portion in such a manner that the etch terminates inside the guard region. | 04-15-2010 |
20110081751 | LATERAL INSULATED GATE BIPOLAR TRANSISTOR HAVING A RETROGRADE DOPING PROFILE IN BASE REGION AND METHOD OF MANUFACTURE THEREOF - In a semiconductor device of the present invention, a first base region | 04-07-2011 |
20110086471 | METHOD OF PRODUCING A SEMICONDUCTOR DEVICE WITH AN ALUMINUM OR ALUMINUM ALLOY ELECTRODE - A method of producing a semiconductor device that has a silicon substrate including a first major surface and a second major surface thereof, a front surface device structure being formed in a region of the first major surface, the method has a step of forming a rear electrode in a region of the second major surface, which includes evaporating or sputtering aluminum-silicon onto the second major surface to form an aluminum silicon film as a first layer of the rear electrode, the aluminum silicon film having a silicon concentration of at least 2 percent by weight when the thickness thereof is less than 0.3 μm. | 04-14-2011 |
20110129967 | THREE-TERMINAL POWER DEVICE WITH HIGH SWITCHING SPEED AND MANUFACTURING PROCESS - An embodiment of a power device having a first current-conduction terminal, a second current-conduction terminal, a control terminal receiving, in use, a control voltage of the power device, and a thyristor device and a first insulated-gate switch device connected in series between the first and the second conduction terminals; the first insulated-gate switch device has a gate terminal connected to the control terminal, and the thyristor device has a base terminal. The power device is further provided with: a second insulated-gate switch device, connected between the first current-conduction terminal and the base terminal of the thyristor device, and having a respective gate terminal connected to the control terminal; and a Zener diode, connected between the base terminal of the thyristor device and the second current-conduction terminal so as to enable extraction of current from the base terminal in a given operating condition. | 06-02-2011 |
20110136300 | METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE USING LASER ANNEALING FOR SELECTIVELY ACTIVATING IMPLANTED DOPANTS - A method for producing a semiconductor device such as a RC-IGBT or a BIGT having a patterned surface wherein partial regions doped with dopants of a first conductivity type and regions doped with dopants of a second conductivity type are on a same side of a semiconductor substrate is proposed. An exemplary method includes: (a) implanting dopants of the first conductivity type and implanting dopants of the second conductivity type into the surface to be patterned; (b) locally activating dopants of the first conductivity type by locally heating the partial region of the surface to be patterned to a first temperature (e.g., between 900 and 1000° C.) using a laser beam similar to those used in laser annealing; and (c) activating the dopants of the second conductivity type by heating the substrate to a second temperature lower than the first temperature (e.g., to a temperature below 600° C.). Boron is an exemplary dopant of the first conductivity type, and phosphorous is an exemplary dopant of the second conductivity type. Boron can be activated in the regions irradiated only with the laser beam, whereas phosphorus may be activated in a low temperature sintering step on the entire surface. | 06-09-2011 |
20110207267 | REVERSE BLOCK-TYPE INSULATED GATE BIPOLAR TRANSISTOR MANUFACTURING METHOD - A reverse block-type insulated gate bipolar transistor (IGBT) manufacturing method that, when manufacturing a reverse block-type IGBT having a separation layer formed along tapered surfaces of a V-shaped groove formed using anisotropic etching, can secure a highly reliable reverse pressure resistance, and suppress a leakage current when reverse biasing. When irradiating with a flash lamp for flash lamp annealing after implantation of ions into a second conductivity type separation layer and second conductivity type collector layer to form the second conductivity type collector layer and second conductivity type separation layer, the strongest portion of radiation energy is focused on a depth position from the upper portion to the central portion of a tapered side edge surface. | 08-25-2011 |
20110230016 | THIN-FILM SEMICONDUCTOR DEVICE, LATERAL BIPOLAR THIN-FILM TRANSISTOR, HYBRID THIN-FILM TRANSISTOR, MOS THIN-FILM TRANSISTOR, AND METHOD OF FABRICATING THIN-FILM TRANSISTOR - In a lateral bipolar transistor including an emitter, a base and a collector which are formed in a semiconductor thin film formed on an insulating substrate, the semiconductor thin film is a semiconductor thin film which is crystallized in a predetermined direction. In addition, in a MOS-bipolar hybrid transistor formed in a semiconductor thin film formed on an insulating substrate, the semiconductor thin film is a semiconductor thin film which is crystallized in a predetermined direction. | 09-22-2011 |
20120009740 | METHOD FOR FABRICATING SOI HIGH VOLTAGE POWER CHIP WITH TRENCHES - A method of manufacturing a SOI high voltage power chip with trenches is disclosed. The method comprises: forming a cave and trenches at a SOI substrate; filling oxide in the cave; oxidizing the trenches, forming oxide isolation regions for separating low voltage devices at the same time; filling oxide in the oxidized trenches; and then forming drain regions, source regions and gate regions for a high voltage power device and low voltage devices. The process involves depositing an oxide layer overlapping the cave of the SOI substrate. A SOI high voltage power chip thus made will withstand at least above 700V voltage. | 01-12-2012 |
20120021569 | MANUFACTURING METHOD OF SOI HIGH-VOLTAGE POWER DEVICE - The present invention relates to a manufacturing method of SOI devices, and in particular, to a manufacturing method of SOI high-voltage power devices. The method comprises steps of: forming a first oxide layer in a section on the surface of the SOI substrate; removing the first oxide layer to form a depressed area in the corresponding section of the upper surface of the SOI substrate; forming a second oxide layer, the upper surface of which is as high as the that of the SOI substrate, in the depressed area formed in step (B); performing photoetching and doping processes to form a P-type region, an N-type region and a gate region on the thus-formed structure where the second oxide layer is formed; forming a third oxide layer by deposition on the drift region of the structure after P-type and N-type regions are formed; wherein the total thickness of the third oxide layer and the second oxide layer approximates to the thickness of the buried oxide layer in the SOI substrate; and forming metal sub-regions, which are respectively in contact with the P-type region, the N-type region and the gate region, on the structure where the third oxide layer is formed, thereby forming a high-voltage power device. | 01-26-2012 |
20120115282 | INTEGRATED ELECTROSTATIC DISCHARGE (ESD) DEVICE - A method for making a semiconductor device includes providing a substrate of a first conductivity type and having a surface region, forming a well region of a second conductivity type and having a first depth in the substrate, adding a gate dielectric layer overlying the surface region, adding a gate layer overlying the gate dielectric layer, forming a first LDD region of the first conductivity type and having a second depth within the well region, forming an emitter region of the second conductivity type within the first LDD region, and forming a second LDD region of the first conductivity type with the well region, a channel region separates the first and second LDD regions. The method further includes forming a source region being of the first conductivity type within the second LDD region and adding an output pad coupled to both the drain and emitter regions. | 05-10-2012 |
20120252172 | Method for producing a thyristor - In a method for producing a thyristor, first and second connection regions are formed on or above a substrate; the first connection region is doped with dopant atoms of a first conductivity type and the second connection region is doped with dopant atoms of a second conductivity type; first and second body regions are formed between the connection regions, wherein the first body region is formed between the first connection region and second body region, and the second body region is formed between the first body region and second connection region; the first body region is doped with dopant atoms of the second conductivity type and the second body region is doped with dopant atoms of the first conductivity type, wherein the dopant atoms are in each case introduced into the respective body region using a Vt implantation method; a gate region is formed on or above the body regions. | 10-04-2012 |
20120329216 | WET CHEMISTRY PROCESSES FOR FABRICATING A SEMICONDUCTOR DEVICE WITH INCREASED CHANNEL MOBILITY - Embodiments of a semiconductor device having increased channel mobility and methods of manufacturing thereof are disclosed. In one embodiment, the semiconductor device includes a substrate including a channel region and a gate stack on the substrate over the channel region. The gate stack includes an alkaline earth metal. In one embodiment, the alkaline earth metal is Barium (Ba). In another embodiment, the alkaline earth metal is Strontium (Sr). The alkaline earth metal results in a substantial improvement of the channel mobility of the semiconductor device. | 12-27-2012 |
20130005093 | METHOD OF MANUFACTURING A REVERSE BLOCKING INSULATED GATE BIPOLAR TRANSISTOR - A method of manufacturing a reverse blocking insulated gate bipolar transistor to form an isolation layer for bending and extending a pn junction, which exhibits a high reverse withstand voltage, to the front surface side. This ensures a high withstand voltage in the reversed direction and reduces leakage current in the reversely biased condition. Formation of a tapered groove by an anisotropic alkali etching process is conducted, resulting in a semiconductor substrate left with a thickness of at least 60 μm between one principal surface and the bottom surface of the tapered groove formed from the other principal surface. | 01-03-2013 |
20130029461 | METHODS FOR FABRICATING ANODE SHORTED FIELD STOP INSULATED GATE BIPOLAR TRANSISTOR - A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer. | 01-31-2013 |
20130078771 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A collector layer having p type is formed on a silicon carbide substrate having n type. A drift layer having n type is formed on a top surface side of the collector layer. A body region provided on the drift layer and having p type, and an emitter region provided on the body region to be separated from the drift layer by the body region and having n type are formed. A bottom surface side of the collector layer is exposed by removing the silicon carbide substrate. | 03-28-2013 |
20130171778 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - On a single-crystal substrate, a drift layer is formed. The drift layer has a first surface facing the single-crystal substrate, and a second surface opposite to the first surface, is made of silicon carbide, and has first conductivity type. On the second surface of the drift layer, a collector layer made of silicon carbide and having second conductivity type is formed. By removing the single-crystal substrate, the first surface of the drift layer is exposed. A body region and an emitter region are formed. The body region is disposed in the first surface of the drift layer, and has the second conductivity type different from the first conductivity type. The emitter region is disposed on the body region, is separated from the drift layer by the body region, and has first conductivity type. | 07-04-2013 |
20130260515 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing an RC-IGBT provided with an IGBT and an FWD on the same substrate is provided. First, top surface device structures of an IGBT and an FWD are formed on the top surface of a semiconductor substrate. Then, with the side of an IGBT region on the top surface of the semiconductor substrate shielded by a first shielding mask, only an FWD region is irradiated with light ions. Next, with the side of the FWD region on the bottom surface of the semiconductor substrate shielded by a second shielding mask, only the IGBT region is irradiated with light ions. With this, a first lifetime control region | 10-03-2013 |
20130295728 | Semiconductor Structure and Manufacturing Method for the Same - A semiconductor structure and a manufacturing method for the same are provided. The semiconductor structure includes a first doped well, a first doped electrode, a second doped electrode, doped strips and a doped top region. The doped strips are on the first doped well between the first doped electrode and the second doped electrode. The doped strips are separated from each other. The doped top region is on the doped strips and extended on the first doped well between the doped strips. The first doped well and the doped top region have a first conductivity type. The doped strips have a second conductivity type opposite to the first conductivity type. | 11-07-2013 |
20130295729 | METHOD FOR MANUFACTURING REVERSE-BLOCKING SEMICONDUCTOR ELEMENT - In a method of manufacturing a reverse-blocking semiconductor element, a tapered groove is formed and ions are implanted into a rear surface and the tapered groove. Then, a furnace annealing process and a laser annealing process are performed to form a rear collector layer and a separation layer on the side surface of the tapered groove. In this way, it is possible to ensure a reverse breakdown voltage and reduce a leakage current when a reverse bias applied, even in a manufacturing method including a process of manufacturing a diffusion layer formed by forming a tapered groove and performing ion implantation and an annealing process for the side surface of the tapered groove as the separation layer for bending the termination of a reverse breakdown voltage pn junction to extend to the surface. | 11-07-2013 |
20130323887 | Thyristor-Based Memory Cells, Devices and Systems Including the Same and Methods for Forming the Same - Semiconductor devices including a plurality of thyristor-based memory cells, each having a cell size of 4F | 12-05-2013 |
20130344663 | REVERSE BLOCK-TYPE INSULATED GATE BIPOLAR TRANSISTOR MANUFACTURING METHOD - A reverse block-type insulated gate bipolar transistor (IGBT) manufacturing method that, when manufacturing a reverse block-type IGBT having a separation layer formed along tapered surfaces of a V-shaped groove formed using anisotropic etching, can secure a highly reliable reverse pressure resistance, and suppress a leakage current when reverse biasing. When irradiating with a flash lamp for flash lamp annealing after implantation of ions into a second conductivity type separation layer and second conductivity type collector layer to form the second conductivity type collector layer and second conductivity type separation layer, the strongest portion of radiation energy is focused on a depth position from the upper portion to the central portion of a tapered side edge surface. | 12-26-2013 |
20140162413 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method includes forming on a first main surface of a semiconductor wafer of a first conduction type, a gate electrode of a semiconductor element, an edge termination region for forming a breakdown voltage of the semiconductor element, and a first semiconductor region of a second conduction type which surrounds the semiconductor element and the edge termination region. A groove may be formed to reach the first semiconductor region from a second main surface of the semiconductor wafer. The groove is formed so that a portion of the semiconductor wafer, that forms an outer circumferential end of the semiconductor wafer, remains and the groove is further towards a center of the semiconductor wafer than the outer circumferential end. A third semiconductor region of the second conduction type is on a side wall of the groove and electrically connects the first semiconductor region and a second semiconductor region. | 06-12-2014 |
20140220746 | Fully Isolated LIGBT and Methods for Forming the Same - A method includes growing an epitaxy semiconductor layer over a semiconductor substrate. The epitaxy semiconductor layer is of a first conductivity type. A Lateral Insulated Gate Bipolar Transistor (LIGBT) is formed at a front surface of the epitaxy semiconductor layer. After the LIGBT is formed, a backside thinning is performed to remove the semiconductor substrate. An implantation is performed from a backside of the epitaxy semiconductor layer to form a heavily doped semiconductor layer. The heavily doped semiconductor layer is of a second conductivity type opposite the first conductivity type. | 08-07-2014 |
20140235020 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - Techniques capable of improving the yield of IGBTs capable of reducing steady loss, turn-off time, and turn-off loss are provided. Upon formation of openings in an interlayer insulting film formed on a main surface of a substrate, etching of a laminated insulating film of a PSG film and an SOG film and a silicon oxide film is once stopped at a silicon nitride film. Then, the silicon nitride film and the silicon oxide film are sequentially etched to form the openings. As a result, the openings are prevented from penetrating through an n-type source layer and a p | 08-21-2014 |
20140322871 | PARTIAL SOI ON POWER DEVICE FOR BREAKDOWN VOLTAGE IMPROVEMENT - Some embodiments of the present disclosure relate to a method to increase breakdown voltage of a power device. A power device is formed on a silicon-on-insulator (SOI) wafer made up of a device wafer, a handle wafer, and an intermediate oxide layer. A recess is formed in a lower surface of the handle wafer to define a recessed region of the handle wafer. The recessed region of the handle wafer has a first handle wafer thickness, which is greater than zero. An un-recessed region of the handle wafer has a second handle wafer thickness, which is greater than the first handle wafer thickness. The first handle wafer thickness of the recessed region provides a breakdown voltage improvement for the power device. | 10-30-2014 |
20140342511 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a first doped region, a second doped region, a doped strip and a top doped region. The first doped region has a first type conductivity. The second doped region is formed in the first doped region and has a second type conductivity opposite to the first type conductivity. The doped strip is formed in the first doped region and has the second type conductivity. The top doped region is formed in the doped strip and has the first type conductivity. The top doped region has a first sidewall and a second sidewall opposite to the first sidewall. The doped strip is extended beyond the first sidewall or the second sidewall. | 11-20-2014 |
20140357026 | PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes an implantation step of performing proton implantation from a rear surface of a semiconductor substrate of a first conductivity type and a formation step of performing an annealing process for the semiconductor substrate in an annealing furnace to form a first semiconductor region of the first conductivity type which has a higher impurity concentration than the semiconductor substrate after the implantation step. In the formation step, the furnace is in a hydrogen atmosphere and the volume concentration of hydrogen is in the range of 6% to 30%. Therefore, it is possible to reduce crystal defects in the generation of donors by proton implantation. In addition, it is possible to improve the rate of change into a donor. | 12-04-2014 |
20140363931 | INSULATED GATE BIPOLAR TRANSISTORS INCLUDING CURRENT SUPPRESSING LAYERS - An insulated gate bipolar transistor (IGBT) includes a first conductivity type substrate and a second conductivity type drift layer on the substrate. The second conductivity type is opposite the first conductivity type. The IGBT further includes a current suppressing layer on the drift layer. The current suppressing layer has the second conductivity type and has a doping concentration that is larger than a doping concentration of the drift layer. A first conductivity type well region is in the current suppressing layer. The well region has a junction depth that is less than a thickness of the current suppressing layer, and the current suppressing layer extends laterally beneath the well region. A second conductivity type emitter region is in the well region. | 12-11-2014 |
20140370665 | POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SUCH A POWER SEMICONDUCTOR DEVICE - A method for manufacturing a power semiconductor device is disclosed which can include: providing a wafer of a first conductivity type; and applying on a second main side of the wafer at least one of a dopant of the first conductivity type for forming a layer of the first conductivity type and a dopant of a second conductivity type for forming a layer of the second conductivity type. A Titanium layer with a metal having a melting point above 1300° C. is then deposited on the second main side. The Titanium deposition layer is annealed so that simultaneously an intermetal compound layer is formed at the interface between the Titanium deposition layer and the wafer and the dopant is diffused into the wafer. A first metal electrode layer is created on the second main side. | 12-18-2014 |
20150031174 | Method for Manufacturing Insulated Gate Bipolar Transistor IGBT - A method for manufacturing an IGBT includes: forming oxide layers on the surfaces of the front and the back of an N-type substrate; forming a buffer layer in the surface of the back of the N-type substrate; forming protection layers on the surfaces of the oxide layers; removing the protection layer and the oxide layer overlying the front of the N-type substrate while reserving the oxide layer and the protection layer on the back of the N-type substrate for protection of the back of the N-type substrate; forming a front IGBT structure and applying a protection film on the surface of the front IGBT structure for protection of the front IGBT structure; removing the protection layer and the oxide layer overlying the back of the N-type substrate; forming a back IGBT structure and a back metal layer; and removing the protection film overlying the surface of the front IGBT structure. | 01-29-2015 |
20150111347 | ELECTRONIC DEVICE STRUCTURE WITH A SEMICONDUCTOR LEDGE LAYER FOR SURFACE PASSIVATION - Electronic device structures including semiconductor ledge layers for surface passivation and methods of manufacturing the same are disclosed. In one embodiment, the electronic device includes a number of semiconductor layers of a desired semiconductor material having alternating doping types. The semiconductor layers include a base layer of a first doping type that includes a highly doped well forming a first contact region of the electronic device and one or more contact layers of a second doping type on the base layer that have been etched to form a second contact region of the electronic device. The etching of the one or more contact layers causes substantial crystalline damage, and thus interface charge, on the surface of the base layer. In order to passivate the surface of the base layer, a semiconductor ledge layer of the semiconductor material is epitaxially grown on at least the surface of the base layer. | 04-23-2015 |
20150140741 | Fully Isolated LIGBT and Methods for Forming the Same - A device includes a dielectric layer, and a heavily doped semiconductor layer over the dielectric layer. The heavily doped semiconductor layer is of a first conductivity type. A semiconductor region is over the heavily doped semiconductor layer, wherein the semiconductor region is of a second conductivity type opposite the first conductivity type. A Lateral Insulated Gate Bipolar Transistor (LIGBT) is disposed at a surface of the semiconductor region. | 05-21-2015 |
20150140742 | Methods of Forming Gated Devices - Some embodiments include methods of forming gated devices. An upper region of a semiconductor material is patterned into a plurality of walls that extend primarily along a first direction. The walls are spaced from one another by trenches that extend primarily along the first direction. Steps are formed along bottoms of the trenches. Gatelines are formed on the steps and along lower regions of the walls. After the gatelines are formed, the walls are patterned into spaced-apart pillars that have bottom regions below the gatelines. In some embodiments the gated devices may be transistors or thyristors. | 05-21-2015 |
20150303276 | METHOD OF FABRICATING A LATERAL INSULATED GATE BIPOLAR TRANSISTOR - A method of fabricating a transistor includes doping non-overlapping first, second, and third wells in a silicon layer of a substrate. The substrate, second and third wells have a first type of conductivity and the first well and silicon layer have a second type of conductivity. First and second insulating layers are thermally grown over the second well between the first well and the third well, and over the third well, respectively. A gate stack is formed over the first insulating layer and the third well. A first source region having the second type of conductivity is formed in the third well. A gate spacer is formed, a fourth well having the first type of conductivity is doped in the third well between the second insulating layer and the gate spacer, a second source region is formed over the fourth well, and a drain is formed in the first well. | 10-22-2015 |
20160020298 | Method for manufacturing an Insulated Gate Bipolar Transistor - Method for manufacturing an insulated gate bipolar transistor, which includes a drift layer of a first conductivity type between an emitter side, at which a gate and emitter electrode are arranged, and a collector side, at which a collector electrode is arranged including steps:
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