Entries |
Document | Title | Date |
20080199985 | LEADFRAME ENHANCEMENT AND METHOD OF PRODUCING A MULTI-ROW SEMICONDUCTOR PACKAGE - A semiconductor package includes a plurality of first leads, each with a top outer portion removed from the lead and an outer end, and a plurality of second leads, each with a bottom outer portion removed from the lead and an outer end. The first and second leads alternate with each other along an edge of the package. Also, the outer ends of the first leads form a first row along the edge of the package and the outer ends of the second leads form a second row along the edge of the package. In one embodiment, the first and second rows are parallel to each other and an encapsulant covers at least a portion of the first and second leads. | 08-21-2008 |
20080227240 | Method of Making Reliable Wafer Level Chip Scale Package Semiconductor Devices
- The present invention relates to a method of making a robust wafer level chip scale package and, in particular, a method that prevents cracking of the passivation layer during solder flow and subsequent multiple thermal reflow steps. In one embodiment, a passivation layer that is formed using a highly compressive insulating material is used. In another aspect, another layer is applied over the passivation layer to assist with preventing cracking of the passivation layer. | 09-18-2008 |
20080233678 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device having a substrate on which conductor wiring is disposed, electrodes provided to the conductor wiring, a semiconductor element connected to the electrodes, and a sealing member that covers the semiconductor element, comprises; mounting a plurality of semiconductor elements on the substrate in the X-axial direction and the Y-axial direction, forming marks in the X-axial direction, supplying the sealing material onto the substrate to continuously-covering the plurality of semiconductor elements arranged in the X-axial direction along the marks, dicing the sealing member and the substrate in the Y-axial direction to form cut planes of the sealing member and the substrate in substantially one plane and being a pair of cut planes opposite one another. | 09-25-2008 |
20080241998 | METHOD FOR FABRICATING A LOW COST INTEGRATED CIRCUIT (IC) PACKAGE - A method for fabricating a low cost integrated circuit package ( | 10-02-2008 |
20080241999 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device is manufactured by sealing a semiconductor chip, which is mounted on a prescribed support such as a lead frame, support bars, and a substrate connected with electrical wiring, in a package. Herein, individual information containing management information representing manufacturing conditions of semiconductor chips and test information representing results of testing of semiconductor chips is automatically recorded on a prescribed position of the prescribed support with respect to each of the semiconductor chips in synchronization with a die bonding process in response to the type of the package. That is, the individual information is recorded on exposed portions of outer leads, exposed portions of support bars, or the backside of the substrate, for example. This improves workability in reading and writing individual information without error, traceability to assure quality of semiconductor devices, and analysis of defects in semiconductor devices. | 10-02-2008 |
20080261351 | WAFER SAWING METHOD - A wafer sawing method for sawing a wafer by using a cutting tool is provided. Sawing paths are formed on a surface of the wafer. In the wafer sawing method, a carrier on which strip-shaped adhesives or at least a fiducial mark is formed is firstly provided. The dimension of the carrier is greater than the dimension of the wafer. Next, the surface of the wafer is bonded to the carrier, and the strip-shaped adhesives or the fiducial mark is extended or located outside a bonding region between the wafer and the carrier. Here, the surface of the wafer faces the carrier. The cutting tool and the carrier are positioned according to the strip-shaped adhesives or the fiducial mark outside the bonding region. The wafer is then sawed by using the cutting tool. The wafer sawing method provides a precise and rapid sawing process and achieves superior productive yield. | 10-23-2008 |
20080268575 | Orientation-dependent etching of deposited AIN for structural use and sacrificial layers in MEMS - In accordance with the present invention, accurate and easily controlled sloped walls may be formed using. AlN and preferably a heated TMAH for such purpose as the fabrication of MEMS devices, wafer level packaging and fabrication of fluidic devices. Various embodiments are disclosed. | 10-30-2008 |
20080274592 | Process and apparatus for wafer-level flip-chip assembly - A method of forming an integrated circuit structure is provided. The method includes providing an interposer wafer; mounting the interposer wafer onto a handling wafer; thinning a backside of the interposer wafer; removing the handling wafer from the interposer wafer after the step of thinning; securing the interposer wafer on a fixture; and bonding a die on the interposer wafer. | 11-06-2008 |
20080274593 | Semiconductor device package with multi-chips and method of the same - The present invention provides a semiconductor device package with the multi-chips comprising a substrate with at least a die receiving through hole, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the substrate. At least a first die having first bonding pads is disposed within the die receiving through hole. A first adhesion material is formed under the die and a second adhesion material is filled in the gap between the die and sidewall of the die receiving though hole of the substrate. Then, a first bonding wire is formed to couple the first bonding pads and the first contact pads. Further, at least a second die having second bonding pads is placed on the first die. A second bonding wire is formed to couple to the second bonding pads and the first contact pads. A dielectric layer is formed on the first and second bonding wire, the first and second die and the substrate. | 11-06-2008 |
20080286902 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate. | 11-20-2008 |
20080286903 | Semiconductor device packaged into chip size and manufacturing method thereof - A semiconductor device includes a semiconductor substrate having an integrated circuit and at least one connection pad, and at least one external connection electrode electrically connected with the connection pad. A first sealing material is provided on the semiconductor substrate around the external connection electrode, each impurity concentration of an Na ion, a K ion, a Ca ion and Cl ion contained in the first sealing material being not greater than 10 ppm. A second sealing material is provided on at least one of a lower surface and a peripheral side surface of the semiconductor substrate, a total impurity concentration of an Na ion, a K ion, a Ca ion and a Cl ion contained in the second sealing material being not smaller than 100 ppm. | 11-20-2008 |
20080293187 | Substrate table and chip manufacturing method - A substrate table used for manufacturing a chip is provided. The substrate table includes a substrate stage, a substrate placement surface formed on the substrate stage, and on which a substrate is placed, and a guiding member that can project and retract from the substrate placement surface. The guiding member positions the substrate when the guiding member is at a projected position abutting an edge portion of the substrate placed on the substrate placement surface, and the guiding member retracts at a time of applying a tape to the substrate. | 11-27-2008 |
20080293188 | Reactive solder material - Reactive solder material. The reactive solder material may be soldered to semiconductor surfaces such as the backside of a die or wafer. The reactive solder material includes a base solder material alloyed with an active element material. The reactive solder material may also be applied to a portion of a thermal management device. The reactive solder material may be useful as a thermally conductive interface between a semiconductor surface and a thermal management device. | 11-27-2008 |
20080299706 | Wafer level package fabrication method - Provided is a wafer level package fabrication method. The method includes providing a device substrate wafer including one or more devices on an upper surface thereof, and a bonding pad electrically connected to the device, providing a bonding seal surrounding the device along the bonding pad, bonding a cap substrate wafer to the device substrate wafer through the bonding seal, the cap substrate wafer having a via formed in a region corresponding to the bonding pad, forming an external terminal on the cap substrate wafer, the external terminal being electrically connected to the bonding pad, and cutting the cap substrate wafer and the device substrate wafer along a cutting line to individually separate a plurality of wafer level packages. The method is conducive to reducing product size for miniaturization, is capable of performing a bonding process without wafer deformation or damage, and increases freedom in wafer material selection. | 12-04-2008 |
20080305577 | METHOD OF MINIMIZING KERF WIDTH ON A SEMICONDUCTOR SUBSTRATE PANEL - A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages. | 12-11-2008 |
20080305578 | METHOD OF MACHINING WAFER - A method of machining a wafer, wherein a wafer provided with devices each having a low dielectric constant insulating film (low-k film) stacked on the face side thereof is divided into the individual devices, the devices thus divided are mounted on a wiring board, and then a grindstone is brought into contact with each of the mounted devices from the side of a side surface of the devices, to grind the back side of the device by a desired amount. Since no vertical load is exerted on the low-k film, the low-k film can be prevented from being broken, and device quality is not lowered. | 12-11-2008 |
20080318362 | Manufacturing Method of Semiconductor Integrated Circuit Device - After performing rough grinding to the back surface of a semiconductor wafer using the first grinding material (for example, particle size of polish fine powder from #320 to #360) and making the thickness of the semiconductor wafer, for example less than 140 □m, less than 120 □m, or less than 100 □m, the back surface of the semiconductor wafer being performed fine finish grinding using the third grinding material (for example, particle size of polish fine powder from #3000 to #100000), the thickness of the semiconductor wafer becomes, for example less than 100 □m, less than 80 □m, or less than 60 □m, and the relatively thin second crush layer, for example the second crush layer of the thickness of less than 0.5 □m, less than 0.3 □m, or less than 0.1 □m is formed on the back surface of the semiconductor wafer. Thereby, without reducing the die strength of a chip, at the same time permeation of the pollution impurities from the back surface of the semiconductor wafer and further, diffusion of the pollution impurities to the circuit formation surface of the semiconductor wafer are prevented, and the poor characteristic of semiconductor elements is prevented. | 12-25-2008 |
20080318363 | Stack circuit member and method - A stack circuit member may include a first circuit member and a second circuit member. The first and the second circuit members may be electrically and mechanically connected together using a thermocompression bonding method. A photosensitive polymer layer may be interposed between the first circuit member and the second circuit member. A gap fill process and an electrical connection process may be performed at the same time. | 12-25-2008 |
20090004778 | Manufacturing Method of Light Emitting Diode - Disclosed is a manufacturing method of a light emitting diode. The manufacturing method comprises the steps of preparing a substrate and mounting light emitting chips on the substrate. An intermediate plate is positioned on the substrate. The intermediate plate has through-holes for receiving the light emitting chips and grooves for connecting the through-holes to one another on its upper surface. A transfer molding process is performed with a transparent molding material by using the grooves as runners to form first molding portions filling the through-holes. Thereafter, the intermediate plate is removed, and the substrate is separated into individual light emitting diodes. Accordingly, it is possible to provide a light emitting diode in which the first molding portion formed through a transfer molding process is positioned within a region encompassed by cut surfaces of the substrate. Since the first molding portion is positioned within the region encompassed by the cut surfaces of the substrate, second molding portions can be symmetrically formed on the side surfaces of the first molding portions in various manners. | 01-01-2009 |
20090011542 | Structure and manufactruing method of chip scale package - A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure. | 01-08-2009 |
20090017581 | Method for manufacturing a semiconductor device - A single-crystal semiconductor layer is provided in a large area over a large-sized glass substrate, whereby a large-scale SOI substrate is obtained. A single-crystal semiconductor substrate provided with an embrittlement layer and a dummy substrate are bonded to each other, and the single-crystal semiconductor substrate is separated at the embrittlement layer as a boundary by heat treatment to form a piece of single-crystal semiconductor over the dummy substrate. The dummy substrate is divided to form a piece of single-crystal semiconductor. The piece of single-crystal semiconductor is bonded to a supporting substrate, and the piece of single-crystal semiconductor is separated from the dummy substrate. Then, a plurality of pieces of single-crystal semiconductor are arranged and transferred to the large-sized glass substrate. | 01-15-2009 |
20090023249 | Wire bonded wafer level cavity package - A microelectronic device includes a chip having a front surface and a rear surface, the front surface having an active region and a plurality of contacts exposed at the front surface outside of the active region. The device further includes a lid overlying the front surface. The lid has edges bounding the lid, at least one of the edges including one or more outer portions and one or more recesses extending laterally inwardly from the outer portions, with the contacts being aligned with the recesses and exposed through them. | 01-22-2009 |
20090029505 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, CIRCUIT SUBSTRATE, AND ELECTRONIC APPARATUS - A semiconductor device includes: a semiconductor substrate including a first face and a second face on a side opposite to the first face; an external connection terminal formed on the first face of the semiconductor substrate; a first electrode formed on the first face of the semiconductor substrate and electrically connected to the external connection terminal; an electronic element formed on or above the second face of the semiconductor substrate; a second electrode electrically connected to the electronic element and having a top face and a rear face; a groove portion formed on the second face of the semiconductor substrate and having a bottom face including at least part of the rear face of the second electrode; and a conductive portion formed in the groove portion and electrically connected to the rear face of the second electrode. | 01-29-2009 |
20090053856 | SEMICONDUCTOR DEVICE COMPRISING LIGHT-EMITTING ELEMENT AND LIGHT-RECEIVING ELEMENT, AND MANUFACTURING METHOD THEREFOR - A semiconductor device includes a substrate for transmitting light, a wiring layer provided on the substrate, a semiconductor chip formed on the wiring layer, a columnar electrode, a sealant, and an external connection terminal electrically connected to the semiconductor chip via the wiring layer and protruding electrode. The device includes a cut surface formed by dicing and constituted by only the substrate and the sealant. Since the cut surface has a single-layer structure as a result of forming the sealant in a single step, moisture cannot infiltrate through the sealant, hence a device resistant to corrosion and operational defects is provided. | 02-26-2009 |
20090061564 | METHOD OF PACKAGING AN INTEGRATED CIRCUIT DIE - A structure ( | 03-05-2009 |
20090081828 | MEMS Fabrication Method - The present invention provides methods for singulating microelectromechanical systems (MEMS) die from a wafer. A plurality of MEMS devices are formed on the top surface of a wafer, and a plurality of intersecting scribe lanes are then formed, on the bottom surface of the wafer, to define a plurality of dies, each including at least one MEMS device. The intersecting scribe lanes penetrate the wafer to a depth of about 80%, and the wafer is cleaved along the scribe lanes to separate each of the plurality of dies from the wafer. | 03-26-2009 |
20090087950 | Wafer packaging method - A wafer packaging method is disclosed. | 04-02-2009 |
20090093087 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In the method of manufacturing a semiconductor device that semiconductor chips are mounted facing-up on the printed wiring board on which a protective insulation film is formed by means of a film-like resist and a plurality of the semiconductor chips are collectively molded by a transfer mold technology, when transfer molding is performed, among the adsorption face of the printed wiring board and the lower die to make adsorb the printed wiring board, the through holes reaching the exterior space of the lower die from the vicinity of the end portion opposing the gate to pour mold resin of a mold cavity are formed as many as possible in order to prevent a short circuit and an open circuit by big deformation of a bonding wire connecting an electrode of the semiconductor chip and an conductor pattern of the printed wiring board. | 04-09-2009 |
20090098682 | Method for Singulating a Group of Semiconductor Packages that Contain a Plastic Molded Body - A method for singulating a group of semiconductor packages containing a plastic molded body. The singulation of the semiconductor packages is effected along a predetermined separation area, wherein, in the predetermined separation area, a metallic layer extending over at least a partial section of the predetermined separation area has to be cut through in addition to a plastic layer formed of a material of the molded body. The method includes the steps of: making a groove into the predetermined separation area of the semiconductor packages by laser engraving, wherein at least a part of the metallic layer extending in the predetermined singulation area is removed, and subsequent separation of the semiconductor packages by mechanical sawing cut along the predetermined separation area. | 04-16-2009 |
20090148984 | BULK GaN AND AlGaN SINGLE CRYSTALS - Bulk GaN and AlGaN single crystal boules, preferably fabricated using a modified HVPE process, are provided. The single crystal boules typically have a volume in excess of 4 cubic centimeters with a minimum dimension of approximately 1 centimeter. If desired, the bulk material can be doped during growth, for example to achieve n-, i-, or p-type conductivity. | 06-11-2009 |
20090162975 | Method of forming a wafer level package - A method is provided for forming a microelectronic package at a wafer level. Such method can include providing a semiconductor wafer having a surface with a pattern of electrical contacts thereon. An interposer component can be provided which has a compliant dielectric layer bonded to a conductive layer. A pattern of holes can be formed through the compliant dielectric layer and the conductive layer which corresponds to the pattern of electrical contacts. The compliant dielectric layer can be contacted with the semiconductor wafer surface so that the pattern of holes is in an aligned position with the pattern of contacts and the compliant dielectric layer and the semiconductor wafer surface then bonded in the aligned position to unite the semiconductor wafer and the interposer component to form a wafer level semiconductor package. The wafer level semiconductor package can be diced to form individual semiconductor chip packages. | 06-25-2009 |
20090176333 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To prevent semiconductor chips from adhering to the trays during transport, a method is employed which transports semiconductor chips in the following state. When trays provided with a plurality of accommodating portions having a recessed cross section for accommodating semiconductor chips on a main surface thereof are stacked in a plurality of stages, the semiconductor chips are accommodated in spaces defined by the accommodating portions formed over the main surface of the lower-stage tray and corresponding accommodating portions formed over the back surface of the upper-stage tray. Here, on bottom surfaces of the accommodating portions formed over the back surface of the upper-stage tray, isolated projections having a height which prevents the projections from coming into contact with the semiconductor chips are arranged in a scattered manner. In this way, it is possible to prevent the semiconductor chips from adhering to the back surface of the upper-stage tray. | 07-09-2009 |
20090186448 | Method for providing an LED chip with a peripheral protective film before cutting the same from a wafer - A method is disclosed to divide a wafer into chips. In the method, a substrate is provided. The substrate is made of an isolating material. An epitaxial laminate is provided on the substrate. At least one slit is made through the epitaxial laminate completely to form at least two chips connected to each other by the substrate only so that each of the chips includes a portion of the substrate and a portion of the epitaxial laminate. Positive and negative electrodes are formed in each of the chips. An upper protective film is provided to cover an upper side of each of the chips except the electrodes. A peripheral protective film is provided into the slit to cover the periphery of the portion of the epitaxial laminate of each of the chips. Finally, the chips are separated from each other. | 07-23-2009 |
20090186449 | METHOD FOR FABRICATING PACKAGE STRUCTURES FOR OPTOELECTRONIC DEVICES - A package structure for an optoelectronic device. The package structure comprises a device chip reversely disposed on a first substrate, which comprises a second substrate and a first dielectric layer between the first and second substrates. The first dielectric layer comprises a pad formed in a corner of the first dielectric layer non-overlapping the second substrate, such that the surface and sidewall of the pad are exposed. A metal layer is formed directly on the exposed surface of the pad and covers the second substrate. A protective layer covers the metal layer, having an opening to expose a portion of the metal layer on the second substrate. A solder ball is disposed in the opening, electrically connecting to the metal layer. The invention also discloses a method for fabricating the same. | 07-23-2009 |
20090191668 | METHOD FOR MANUFACTURING IC TAG INLET - An IC tag inlet ( | 07-30-2009 |
20090197373 | Semiconductor Device Singulation Method - The objective of the invention is to provide a semiconductor device manufacturing method with which the generation of burrs can be suppressed while increasing the singulation speed of the package. In a manufacturing method of a QFN package of the present invention, a molding prepared by sealing a lead frame with plural semiconductor chips carried on it en bloc with a resin; the operation comprises the following processing steps: a first singulation processing step S | 08-06-2009 |
20090203171 | SEMICONDUCTOR DEVICE FABRICATING METHOD - A semiconductor device fabricating method includes forming a plurality of semiconductor devices that include one semiconductor chip and a metal plate having an opening portion that surrounds a region where the semiconductor chip is provided, by cutting, at regions where a frame portion exists, a plate-shaped member that includes: a wiring layer including a wiring portion and an insulating portion; a plurality of semiconductor chips disposed on one surface of the wiring layer; a metal plate disposed at a surface of the wiring layer at a side at which the semiconductor chips are provided, and having a plurality of opening portions that surround regions where the semiconductor chips are provided and the frame portion that forms the opening portions; and a sealing resin layer provided so as to seal at least gaps between the semiconductor chips and the metal plate. | 08-13-2009 |
20090209065 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND ULTRASONIC BONDING APPARATUS - An example of the invention is a method of manufacturing a semiconductor device including, pressing a part of the connection conductor having a plate-like shape or a belt-like shape against a lead terminal which is formed on a lead frame, is formed into a thin and long plate-like shape, and is supported only at one end in a longitudinal direction of the terminal, in such a manner that the part of the conductor is brought into contact with the lead terminal, and applying ultrasonic vibration substantially in the longitudinal direction in a plane perpendicular to the pressing direction to the connection conductor in the state where the part of the connection conductor is pressed against the lead terminal. | 08-20-2009 |
20090221114 | PACKAGING AN INTEGRATED CIRCUIT DIE USING COMPRESSION MOLDING - A structure ( | 09-03-2009 |
20090246912 | METHOD OF PRODUCING SEMICONDUCTOR PACKAGES - Semiconductor chips are fixed to one of two opposite surfaces of a leadframe, and the leadframe is electrically connected to each semiconductor chip with wires. After having applied water-soluble masking ink to the other surface of the leadframe, a sealed structure is molded. Then, when the sealed structure is cut with cutting water into individual semiconductor packages, burrs of the mold resin formed on the other surface side of the leadframe are removed by the cutting water while the masking ink on the other surface of the leadframe is dissolved and removed by the cutting water. | 10-01-2009 |
20090246913 | Adhesive Composition, Adhesive Sheet and Production Method of Semiconductor Device - The object of the present invention is to provide an adhesive composition that enables to produce conforming products with a high manufacturing yield and without breaking or chipping of the chips in the picking-up step and that enables to stably connect a wire without contaminating a wire pad part disposed at the circumference of a bonding surface during a wire bonding step that is performed after die bonding, even in the case of chips being reduced in a thickness. | 10-01-2009 |
20090246914 | Semiconductor package and method of manufacturing the same - A package may include a semiconductor chip mounted on a film substrate. A method of manufacturing the same may involve providing a semiconductor chip. The semiconductor chip may include recesses and bumps. A film substrate including a through hole may be provided. The semiconductor chip may be inserted into the through hole of the film substrate. Circuit wires may be formed on the film substrate to contact the bumps of the semiconductor chip. | 10-01-2009 |
20090253231 | ADHESIVE SHEET FOR LASER DICING AND ITS MANUFACTURING METHOD - An adhesive sheet for laser dicing is used for dicing a workpiece into individual chips by light absorption ablation of laser beam and has at least an adhesive layer on one side of a base material which has a surface opposite to the adhesive layer having no convex parts of width (W) of 20 mm or less and height (h) of 1 μm or more, or no concave parts of width (W) of 20 mm or less and depth (d) of 1 μm or more. | 10-08-2009 |
20090286357 | METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTURE - A method of manufacturing a semiconductor structure. One embodiment produces a substrate having at least two semiconductor chips embedded in a molded body. A layer is applied over at least one main surface of the substrate by using a jet printing process. | 11-19-2009 |
20090291529 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate. | 11-26-2009 |
20090298231 | Cmos process for fabrication of ultra small or non standard size or shape semiconductor die - A method for the singulation of integrated circuit die, the method including: etching a semiconductor layer disposed on a silicon oxide dielectric layer, thereby forming a trench defining a boundary of the die; depositing a silicon nitride layer in the trench; coating the semiconductor layer with an oxide layer such that the trench is filled; removing part of the oxide layer from the semiconductor layer such that the oxide layer only remains in the trench; mounting the semiconductor layer to a carrier; removing the silicon oxide dialectic layer, the nitride layer, and the oxide layer; and releasing the die from the carrier. The method is suitable for irregularly shaped or extremely small die and is compatible with traditional CMOS processes. | 12-03-2009 |
20090298232 | METHOD OF FORMING A LEADED MOLDED ARRAY PACKAGE - In one embodiment, a method for forming a leaded molded array package includes placing a lead frame assembly into a molding apparatus having lead cavities. The method further includes forming seals between conductive leads within the lead frame assembly and the lead cavities, and encapsulating the lead frame assembly to form a molded array assembly. The molded array assembly is then separated into individual leaded molded packages. | 12-03-2009 |
20090311830 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor chip, semiconductor package including the same, and a method of manufacturing the semiconductor chip and semiconductor package to block up electrical contacts between bonding wires and the semiconductor chip by providing insulation over the edge of the semiconductor chip. | 12-17-2009 |
20090325346 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device. | 12-31-2009 |
20100003786 | CHIP-LEVEL UNDERFILL PROCESS AND STRUCTURES THEREOF - A process comprises forming a first electrical interconnect structure on a surface of a singulated semiconductor chip having an alignment pattern. The alignment pattern is scanned and stored in a scanning device prior to application of a curable underfill coating to the surface of the singulated semiconductor chip. This is followed by applying a curable underfill coating to the surface of the singulated semiconductor chip to produce a coated semiconductor chip. The process also includes a step of delivering the scanned and stored alignment pattern to an alignment and joining device positioned adjacent to and operatively associated with a substrate having a second electrical interconnect structure alignable to make electrical contact with the first electrical interconnect structure. The coated semiconductor chip is placed in the alignment and joining device so that when the scanned and stored alignment pattern is activated the alignment and joining device positions the coated semiconductor chip so that the first electrical interconnect structure is aligned to make electrical contact with the second electrical interconnect structure. This is followed by activating the alignment and joining device to join the coated semiconductor chip to the substrate so that the first electrical interconnect structure is in electrical contact with the second electrical interconnect structure. In one embodiment, the first electrical interconnect structure is placed on a surface of a semiconductor chip array in a wafer to produce the electrically connectable semiconductor structure which is followed by dicing to produce at least one of the singulated semiconductor chips. Another embodiment comprises aligning the fist and second electrical interconnect structures prior to applying the curable underfill coating. | 01-07-2010 |
20100009500 | Aluminum Leadframes for Semiconductor QFN/SON Devices - A post-mold plated semiconductor device has an aluminum leadframe ( | 01-14-2010 |
20100015760 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Of three chips ( | 01-21-2010 |
20100029044 | CONDUCTIVE BUMP, METHOD FOR MANUFACTURING THE CONDUCTIVE BUMP, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - Conductive bump ( | 02-04-2010 |
20100035382 | Methods of making compliant semiconductor chip packages - A method of making a semiconductor chip package is provided in which a compliant layer is provided over a contact bearing face of a semiconductor chip. The compliant layer can have a bottom surface adjacent to the chip face, a top surface facing away from the bottom surface, and at least one sloping surface between the top and bottom surfaces. The compliant layer can be disposed remote in a lateral direction along the contact bearing face from at least one contact adjacent to the sloping surface. Bond ribbons can be formed atop the compliant layer, wherein each bond ribbon electrically connects one of the contacts to an associated conductive terminal at the top surface of the compliant layer. The compliant layer can provide stress relief to the bond ribbons, such as during handling and affixing the assembly to an external substrate. A bond ribbon can include a strip extending along the sloping surface of the compliant layer, the strip having a substantially constant thickness in a direction extending away from the sloping surface. | 02-11-2010 |
20100041181 | HEAT DISSIPATING PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME - A heat dissipating package structure includes a chip carrier; a semiconductor chip mounted and electrically connected to the chip carrier; a heat spreader having a first surface, an opposed second surface and a hollow structure, the second surface of the heat spreader being mounted on the chip, wherein the chip is larger in size than the hollow structure such that the chip is partly exposed to the hollow structure; an encapsulant formed between the heat spreader and the chip carrier, for encapsulating the chip, wherein the first surface and sides of the heat spreader are exposed from the encapsulant to dissipate heat produced from the chip; and a plurality of conductive elements disposed on the chip carrier, for electrically connecting the chip to an external device. The present invention also provides a method for fabricating the heat dissipating package structure. | 02-18-2010 |
20100047969 | BACKGRINDING-UNDERFILL FILM, METHOD OF FORMING THE SAME, SEMICONDUCTOR PACKAGE USING THE BACKGRINDING-UNDERFILL FILM, AND METHOD OF FORMING THE SEMICONDUCTOR PACKAGE - A semiconductor package forming method includes mounting a backgrinding-underfill film which includes a laminated backgrinding film and a laminated underfill film on a semiconductor wafer so that the underfill film adheres to a front side of the semiconductor wafer; backgrinding a back side of the semiconductor wafer on which the backgrinding-underfill film has been mounted and removing the backgrinding film of the backgrinding-underfill film from the semiconductor wafer. The method further includes dicing the semiconductor wafer from which the backgrinding film has been removed, so that semiconductor chips are separated from the semiconductor wafer. | 02-25-2010 |
20100055839 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device. One embodiment provides a carrier. A semiconductor chip is provided with a first face and a second face opposite to the first face. The semiconductor chip is placed over the carrier with the first face facing the carrier. A voltage is applied between the second face of the semiconductor chip and the carrier for attaching the semiconductor chip to the carrier. | 03-04-2010 |
20100055840 | Electronic packaging structure and a manufacturing method thereof - A packaging structure includes a main substrate having a plurality of circuit lines thereon, and an electronic module having at least one conductive pad at the bottom thereof and having a plurality of conductive lines on the sides thereof. The pad and the conductive circuits are connected electrically to the circuits on the main substrate when the electronic module is disposed on the main substrate. As above-mentioned, one electronic module can be stacked on top of another so that the integrity of the packaging structure is improved. | 03-04-2010 |
20100055841 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - A method of producing a semiconductor device includes the steps of: preparing a semiconductor wafer having an MEMS (Micro Electro Mechanical Systems) element formed on a surface thereof; forming a groove portion surrounding the MEMS element in the surface of the semiconductor wafer; preparing a sealing wafer having a recess portion formed in a surface thereof and a protruding portion surrounding the recess portion; filling an adhesive in the groove portion; arranging the semiconductor wafer so that the surface of the semiconductor wafer faces the surface of the sealing wafer; fitting the protruding portion into the groove portion so that the recess portion covers the MEMS element; hardening the adhesive to form an MEMS element mounting wafer; and cutting the MEMS element mounting wafer into pieces to obtain the semiconductor device. Further, the adhesive is formed of a silicone type resin. | 03-04-2010 |
20100068853 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device, a substrate having first electrodes on a main surface thereof and a semiconductor chip having second electrodes on a first main surface thereof are arranged such that the main surface of the substrate and the first main surface of the semiconductor chip oppose to each other, and the first electrodes and the second electrodes are connected so as to electrically connect the substrate and the semiconductor chip. The semiconductor chip is made thin by grinding a second main surface opposing to the first main surface of the semiconductor chip which is connected with the substrate. Side surfaces and the second main surface of the semiconductor chip made thin are sealed with resin. | 03-18-2010 |
20100081235 | METHOD FOR MANUFACTURING RF POWDER - A method for manufacturing RF powder wherein the RF powder is composed of a large amount of particles and used as collective RF powder (a powdery entity); and a large amount of RF powder particles can be obtained from a wafer in a stable manner and at a high yield is provided. | 04-01-2010 |
20100093133 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - The electronic device comprises a first substrate | 04-15-2010 |
20100105170 | Method for manufacturing a semiconductor device having a heat spreader - A method for manufacturing a semiconductor device includes cutting a resin sealing body into a plurality of pieces. The resin sealing body includes a plurality of semiconductor chips mounted on a wiring board, a heat spreader disposed above the plurality of the semiconductor chips, and sealing resin filled between the wiring board and the heat spreader. The cutting the resin sealing body includes shaving the resin sealing body from a side of the heat spreader and shaving the resin sealing body from a side of the wiring board. The method prevents the heat spreader from generation of burrs. | 04-29-2010 |
20100105171 | SEMICONDUCTOR CHIP, METHOD OF MANUFACTURING THE SEMICONDUCTOR CHIP AND SEMICONDUCTOR CHIP PACKAGE - In a semiconductor chip, a body has a top surface where a pattern is formed, an underside surface opposing the top surface and a plurality of side surfaces. A plurality of electrode pads are formed on the top surface of the body to connect to an external terminal. A shielding conductive film is formed on the surfaces excluding the top surface of the body where the pattern is formed. A conductive via is extended through the body to connect one of the electrode pads with the conductive film. | 04-29-2010 |
20100112756 | INTEGRATED CIRCUIT PACKAGE FORMATION - Integrated circuit packages are formed from a panel where the panel is separated by laser cutting the panel. In some embodiments, the panel is attached to the carrier for the formation of interconnect layers on the panel. Afterwards, the panel is cut with a laser while on the carrier to separate the integrated circuit packages. A tape or other type of structure may be attached to the top of the packages after the laser cutting. The integrated circuit packages are removed from the carrier by releasing the adhesive and removing the integrated circuit packages with the tape. The packages are then removed from the tape. | 05-06-2010 |
20100120202 | Method for Reducing Chip Warpage - A method of forming an integrated circuit structure including providing a wafer comprising a front surface and a back surface, wherein the wafer comprises a chip; forming an opening extending from the back surface into the chip; filling an organic material in the opening, wherein substantially no portion of the organic material is outside of the opening and on the back surface of the wafer; and baking the organic material to cause a contraction of the organic material. | 05-13-2010 |
20100120203 | SEMICONDUCTOR DEVICE AND MEMORY CARD USING THE SAME - A circuit board has a curved portion provided in at least one side of an external shape thereof. An external connecting terminal is provided on a first main surface of the circuit board. A semiconductor element is mounted on a second main surface of the circuit board. A first wiring network is provided in a region except the terminal region on the first main surface. A second wiring network is provided on the second main surface. Distance from the side including the curved portion to the first wiring network is larger than distance from at least one of the other sides to the first wiring networks, and distance from the side including the curved portion to the second wiring network is larger than distance from at least one of the other sides to the second wiring networks. | 05-13-2010 |
20100136746 | METHOD FOR PRODUCING A SET OF CHIPS MECHANICALLY INTERCONNECTED BY MEANS OF A FLEXIBLE CONNECTION - The method relates to production of a set of chips mechanically interconnected by means of a flexible connection. The chips, integrated on a substrate, each comprise a receiving area. The chips of the set are connected in series in the receiving areas by a connecting element. The chips are then released, the connecting element forming a flexible connection. | 06-03-2010 |
20100136747 | METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE - Provided is a method for manufacturing a semiconductor package. The method includes providing a first substrate having a first top surface on which a chip pad is formed and a first bottom surface opposite to the first top surface. The method additionally includes removing a portion of the first top surface to form a sawing groove, and forming a conductive pattern on the first substrate. Also, the method includes removing a portion of the first bottom surface to divide the first substrate into a plurality of semiconductor chips having a redistribution pattern formed of a portion of the conductive pattern, and mounting a selected one of the plurality of semiconductor chips on a second substrate having a second top surface on which a lead is formed. The method further includes forming an interconnector electrically connecting the lead to the redistribution pattern. | 06-03-2010 |
20100144095 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE IN WHICH BOTTOM SURFACE AND SIDE SURFACE OF SEMICONDUCTOR SUBSTRATE ARE COVERED WITH RESIN PROTECTIVE FILM - First, a trench formed in parts of a semiconductor wafer, a sealing film and others corresponding to a dicing street and both sides thereof. In this state, the semiconductor wafer is separated into silicon substrates by the formation of the trench. Then, a resin protective film is formed on the bottom surface of each silicon substrate including the inner part of the trench. In this case, the semiconductor wafer is separated into the silicon substrates. However, a support plate is affixed to the upper surfaces of the columnar electrode and the sealing film via an adhesive layer. Therefore, when the resin protective film is formed, it is possible to prevent the entirety including the separated silicon substrates from being easily warped. | 06-10-2010 |
20100144096 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE IN WHICH BOTTOM SURFACE AND SIDE SURFACE OF SEMICONDUCTOR SUBSTRATE ARE COVERED WITH RESIN PROTECTIVE FILM - First, a trench is formed in parts of a semiconductor wafer, a sealing film and other elements corresponding to a dicing street and both sides thereof. In this state, the semiconductor wafer is separated into silicon substrates by the formation of the trench. Then, a resin protective film is formed on the bottom surface of each silicon substrate including the inner part of the trench. In this case, the semiconductor wafer is separated into the silicon substrates. However, a support plate is affixed to the upper surfaces of the columnar electrode and the sealing film via an adhesive layer. Therefore, when the resin protective film is formed, it is possible to prevent the entire workpiece including the separated silicon substrates from being easily warped. | 06-10-2010 |
20100144097 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE IN WHICH BOTTOM SURFACE AND SIDE SURFACE OF SEMICONDUCTOR SUBSTRATE ARE COVERED WITH RESIN PROTECTIVE FILM - First, a trench is formed in parts of a semiconductor wafer, a sealing film and other elements corresponding to a dicing street and both sides thereof. In this state, the semiconductor wafer is separated into silicon substrates by the formation of the trench. Then, a resin protective film is formed on the bottom surface of each silicon substrate including the inner part of the trench. In this case, the semiconductor wafer is separated into the silicon substrates. However, a support plate is affixed to the upper surfaces of the columnar electrode and the sealing film via an adhesive layer. Therefore, when the resin protective film is formed, it is possible to prevent the entire workpiece including the separated silicon substrates from being easily warped. | 06-10-2010 |
20100144098 | Method for Fabricating Flip-Attached and Underfilled Semiconductor Devices - A semiconductor device ( | 06-10-2010 |
20100151627 | FABRICATION METHOD OF THIN FILM DEVICE - A method for fabricating a thin film device includes the step of forming a sacrificial layer on a first substrate. A portion other than a region of the sacrificial layer is selectively removed. A material film is formed on the sacrificial layer to be connected to the first substrate via the selectively removed region. The material film portion filled in the selectively removed region is provided as an anchor. A thin film lamination is formed on the material film. The desired thin film device is formed by using a selective etching process. After removing the sacrificial layer, the thin film device floats over the first substrate with being supported by the anchor. A support body is temporarily attached on the thin film lamination. The thin film device is transferred to the support body onto a second substrate. | 06-17-2010 |
20100151628 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - An improved manufacturing method for semiconductor devices is provided. This method can prevent chips and cracks from being generated when the rear face of the semiconductor substrate is polished. The manufacturing method includes preparing a semiconductor substrate having a front face and a rear face. The front face has an inner surface area and a peripheral surface area. Circuit elements are provided in the inner surface area of the semiconductor substrate. The manufacturing method also includes sealing the circuit elements with circuit sealing resin. The manufacturing method also includes providing cured resin in the peripheral surface area of the semiconductor substrate. The manufacturing method also includes polishing the rear face of the semiconductor substrate after the circuit sealing step. The manufacturing method also includes cutting the semiconductor substrate after the substrate polishing step so as to obtain semiconductor devices. | 06-17-2010 |
20100159644 | LOW-COST FLIP-CHIP INTERCONNECT WITH AN INTEGRATED WAFER-APPLIED PHOTO-SENSITIVE ADHESIVE AND METAL-LOADED EPOXY PASTE SYSTEM - Various exemplary embodiments provide materials and methods for flip-chip packaging technology. The disclosed flip-chip packaging technology can use a single B-stage wafer-applied photo-sensitive adhesive along with printed interconnects, which does not include conventional underfill materials and processes. In one embodiment, a photo-sensitive adhesive can be applied on a semiconductor die or a base substrate with conductive bumps printed in through-openings of the photo-sensitive adhesive. One or more semiconductor dies can be laterally packaged or vertically stacked on the base substrate using the printed conductive bumps as interconnects there-between. | 06-24-2010 |
20100159645 | SEMICONDUCTOR APPARATUS AND PROCESS OF PRODUCTION THEREOF - A method of producing a semiconductor apparatus, the method including forming metal ball bumps in direct contact with a circuit pattern of a semiconductor device, forming a resin film to seal spaces between the metal ball bumps, cleaning the surfaces of the metal ball bumps projecting out from the resin film using plasma cleaning by removing components inviting a rise in a connection resistance and a decline in a joint strength, forming eutectic solder layers different in composition from the metal ball bumps on the surfaces of the metal ball bumps, cutting the semiconductor substrate into unit semiconductor chips, and mounting at least one of the chips on a mounting board from a bump forming surface side of the chip so as to connect the eutectic solder layers to the mounting board with the resin film directly contacting the chip and not directly contacting the mounting board. | 06-24-2010 |
20100173455 | SEMICONDUCTOR DEVICE HAVING SEALING FILM AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a plurality of wiring lines which are provided on an upper side of a semiconductor substrate and which have connection pad portions, and columnar electrodes are provided on the connection pad portions of the wiring lines. A first sealing film is provided around the columnar electrodes on the upper side of the semiconductor substrate and on the wiring lines. A second sealing film is provided on the first sealing film. The first sealing film is made of a resin in which fillers are not mixed, and the second sealing film is made of a material in which fillers are mixed in a resin. | 07-08-2010 |
20100178733 | Thin Quad Flat Package with No Leads (QFN) Fabrication Methods - Embodiments of the present invention include a method of packaging semiconductor devices. The method comprises the steps of molding a surface of a wafer, sawing the wafer into individual devices, attaching the individual semiconductor device to an adhesive surface, molding the exposed surface, and sawing the wafer into individual semiconductor devices. The step of molding forms a continuous molded layer. The step of sawing results in each individual semiconductor having a molded layer. This molded layer corresponds to a portion of the continuous molded layer. The step of attaching includes attaching the molded layer of the individual semiconductor devices to the adhesive surface. The step of molding the exposed area includes molding an exposed area above the adhesive surface. This forms a solid expanse of material. The step of sawing the wafer into individual semiconductor devices includes sawing the solid expanse of material. | 07-15-2010 |
20100184255 | MANUFACTURING METHOD FOR PACKAGE STRUCTURE - A manufacturing method for package structure is provided. The manufacturing method includes the follow steps. Firstly, a substrate is provided. Next, a number of chips are provided. Then, the chips are electrically connected with the substrate. After that, the chips are encapsulated with a sealant, so that the chips and the substrate form a package. Then, the package is adhered by a vacuum force. Afterwards, the adhered package is singulated to form many package structures along the portion between adjacent two of airways. | 07-22-2010 |
20100190296 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The present invention provides a method of manufacturing a semiconductor device in which a thinned substrate of a semiconductor or semiconductor device is handled without cracks in the substrate and treated with heat to improve a contact between semiconductor back surface and metal in a high yield and a semiconductor device may be manufactured in a high yield. In the method of manufacturing a semiconductor device according to the present invention, a notched part is formed from a surface to a middle in a semiconductor substrate by dicing and the surface of the substrate is fixed to a support base. Next, a back surface of the substrate is ground to thin the semiconductor substrate and then a metal electrode and a carbon film that is a heat receiving layer are sequentially formed on the back surface of the substrate. Next, the carbon film is irradiated with light at a power density of 1 kW/cm | 07-29-2010 |
20100197078 | DICING FILM HAVING SHRINKAGE RELEASE FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE USING THE SAME. - The present invention relates to a dicing film having an adhesive film for dicing a wafer and a die adhesive film, which are used for manufacturing a semiconductor package, and a method of manufacturing a semiconductor package using the same. More particularly, the present invention relates to a dicing film wherein a shrinkage release film is inserted between an adhesive film for dicing a wafer and a die adhesive film so that the die adhesive film and a die can be easily separated from the adhesive film for dicing a wafer when picking up a semiconductor die, and a method of manufacturing a semiconductor package using the same. | 08-05-2010 |
20100197079 | SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR ELEMENTS MOUNTED ON BASE PLATE - A method of manufacturing a semiconductor device and a semiconductor device including a first semiconductor element mounted on a first surface of a base plate, wherein solder balls are formed on a second opposite surface of the base plate-such that the second opposite surface includes an area without solder balls. At least one second semiconductor element is mounted to the base plate at the area of the second surface without solder balls. The at least one semiconductor element may be mounted to the base plate using low molecular adhesive, or in the alternative, high temperature solder. | 08-05-2010 |
20100203678 | SEMICONDUCTOR SUBSTRATE CUTTING METHOD - A semiconductor substrate cutting method which can efficiently cut a semiconductor substrate having a front face formed with a functional device together with a die bonding resin layer is provided. | 08-12-2010 |
20100233854 | METALLIC SOLDERABILITY PRESERVATION COATING ON METAL PART OF SEMICONDUCTOR PACKAGE TO PREVENT OXIDE - Embodiments of the present invention are directed to metallic solderability preservation coating on connectors of semiconductor package to prevent oxide. Singulated semiconductor packages can have contaminants, such as oxides, on exposed metal areas of the connectors. Oxidation typically occurs on the exposed metal areas when the semiconductor packages are not stored in appropriate environments. Copper oxides prevent the connectors from soldering well. An anti-tarnish solution of the present invention is used to coat the connectors during sawing, after sawing, or both of a semiconductor array to preserve metallic solderability. The anti-tarnish solution is a metallic solution, which advantageously allows the semiconductor packages to not need be assembled immediately after fabrication. | 09-16-2010 |
20100233855 | METHOD FOR FABRICATING CHIP SCALE PACKAGE STRUCTURE WITH METAL PADS EXPOSED FROM AN ENCAPSULANT - A chip scale package structure and a method for fabricating the same are disclosed. The method includes forming metal pads on a predetermined part of a carrier; mounting chips on the carrier, each of the chips having a plurality of conductive bumps soldered to the metal pads; forming an encapsulant on the carrier to encapsulate the chips and the conductive bumps; removing the carrier to expose the metal pads and even the metal pads with a surface of the encapsulant; forming on the encapsulant a plurality of first conductive traces electrically connected to the metal pads; applying a solder mask on the first conductive traces, and forming a plurality of openings on the solder mask to expose a predetermined part of the first conductive traces; forming a plurality of conductive elements on the predetermined part; and cutting the encapsulant to form a plurality of chip scale package structures. | 09-16-2010 |
20100240176 | ELECTRONIC COMPONENT, SEMICONDUCTOR DEVICE, METHODS OF MANUFACTURING THE SAME, CIRCUIT BOARD, AND ELECTRONIC INSTRUMENT - The present invention is a method of manufacturing a semiconductor device, by forming a wiring on or above a wafer so that the wiring is electrically connected to a first electrode disposed on a first surface of the wafer, forming a first resin layer on or above the wafer such that the wiring is disposed between the wafer and the first resin layer, forming an opening in the first resin layer such that the opening overlaps the wiring, forming a conductive member in the opening such that the conductive member being electrically connected to the wiring, forming a second electrode on the conductive member such that the second electrode is electrically connected to the wiring via the conductive member, and separating the wafer into individual elements after the forming of the first resin layer. | 09-23-2010 |
20100248425 | Chip-size-package semiconductor chip and manufacturing method - A method of manufacturing semiconductor chips includes preparing a semiconductor substrate having on its front side a plurality of chip forming areas; sticking a support to the front surface of the substrate via an adhesive sheet; forming through holes extending from the back surface of the substrate; forming a groove along each of boundaries between the chip forming areas, the groove extending from the back surface of the substrate through the adhesive sheet to the support to expose cross-sections of the adhesive sheet; forming an insulating film over the back surface so as to cover side walls of the through holes and the cross-sections of the adhesive sheet; and dicing the substrate along the grooves with the insulating film remaining. | 09-30-2010 |
20100248426 | METHOD OF MAKING CHIP-ON-LEAD PACKAGE - A process for assembling a Chip-On-Lead packaged semiconductor device includes the steps of: mounting and sawing a wafer to provide individual semiconductor dies; performing a first molding operation on a lead frame; depositing epoxy on the lead frame via a screen printing process; attaching one of the singulated dies on the lead frame with the epoxy, where the die attach is done at room temperature; and curing the epoxy in an oven. Throughput improvements may be ascribed to not including a hot die attach process. An optional plasma cleaning step may be performed, which greatly improves wire bonding quality and a second molding quality. In addition, since a first molding operation is performed before the formation of epoxy to avoid the problem of the epoxy hanging in the air, the delamination risk between the epoxy and the die is avoided. | 09-30-2010 |
20100267204 | PACKAGE STRUCTURE FOR INTEGRATED CIRCUIT DEVICE AND METHOD OF THE SAME - A package structure for packaging at least one of a plurality of intergraded circuit devices of a wafer is provided. The package structure includes an extension metal pad, a first conductive bump and an insulator layer. The extension metal pad electrically contacts the at least one of the plurality of intergraded circuit devices. The first conductive bump is located on the extension metal pad. The insulator layer is located over the at least one of the plurality of intergraded circuit devices and on a sidewall of it. | 10-21-2010 |
20100273295 | Surface-Decorated Polymeric Amphiphile Porogens for the Templation of Nanoporous Materials - A nanoparticle which includes a multi-armed core and surface decoration which is attached to the core is prepared. A multi-armed core is provided by any of a number of possible routes, exemplary preferred routes being living anionic polymerization that is initiated by a reactive, functionalized anionic initiator and ∈-caprolactone polymerization of a bis-MPA dendrimer. The multi-armed core is preferably functionalized on some or all arms. A coupling reaction is then employed to bond surface decoration to one or more arms of the multi-armed core. The surface decoration is a small molecule or oligomer with a degree of polymerization less than 50, a preferred decoration being a PEG oligomer with degree of polymerization between 2 and 24. The nanoparticles (particle size ≦10 nm) are employed as sacrificial templating porogens to form porous dielectrics. The porogens are mixed with matrix precursors (e.g., methyl silsesquioxane resin), the matrix vitrifies, and the porogens are removed via burnout. Greater porosity reduces the dielectric constant k of the resulting dielectrics. The porous dielectrics are incorporated into integrated circuits as lower k alternatives to silicon dioxide. | 10-28-2010 |
20100273296 | Thermally Enhanced Wafer Level Package - A method of forming a package structure includes providing a plurality of dies; attaching the plurality of dies onto a heat-dissipating plate; and sawing the heat-dissipating plate into a plurality of packages, each including one of the plurality of dies and a piece of the heat-dissipating plate. | 10-28-2010 |
20100279467 | METHODOLOGY FOR PROCESSING A PANEL DURING SEMICONDUCTOR DEVICE FABRICATION | 11-04-2010 |
20100279468 | LAMINATED FILM AND PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE - The present invention provides a laminated film which includes a pressure-sensitive adhesive sheet including a pressure-sensitive adhesive layer, and a die-adhering layer laminated on the pressure-sensitive adhesive layer of the pressure-sensitive adhesive sheet, the laminated film being for use in a production step of a semiconductor device, in which the pressure-sensitive adhesive layer of the pressure-sensitive adhesive sheet contains a water-supporting body, and the pressure-sensitive adhesive layer has a gel fraction of 90% by weight or more. | 11-04-2010 |
20100279469 | Low-Voiding Die Attach Film, Semiconductor Package, and Processes for Making and Using Same - This invention is a low-voiding adhesive film prepared from a composition. The composition comprises a toughening polymer, a curable resin, a curing agent for the curable resin, a void reduction compound, and a curing agent for the void reduction compound. The void reduction compound has at least two Si—O moieties contiguous with each other and at least one reactive functionality. Additional embodiments of this invention are described, including a process for producing the low-voiding die attach film, a method for reducing voids in a semiconductor package using the film of this invention, and a semiconductor package assembled with the film of this invention. | 11-04-2010 |
20100285636 | MANUFACTURING METHOD OF A PACKAGING STRUCTURE OF ELECTRONIC COMPONENTS - A manufacturing method of a packaging structure of electronic components includes the steps of: providing a substrate including a plurality of electronic components; covering the electronic components disposed on the substrate with a molding body; forming a plurality of pre-cut grooves on the molding body so as to define a plurality of molding units on the molding body; forming an electromagnet barrier layer covering the molding units on the molding units and the pre-cut grooves; and cutting along at least one of the pre-cut grooves deeply down to break the substrate so as to form separately a plurality of packaging structures of the electronic components. | 11-11-2010 |
20100304532 | Semiconductor Die Attachment Method Using Non-Conductive Screen Print and Dispense Adhesive - A uniform layer of non-conductive material, e.g., epoxy, is screen printed onto the backside of an integrated circuit wafer to a required thickness, and then heated until it is hard cured (C-stage). The integrated circuit wafer having the hard cured coating is then sawn apart to separate the individual integrated circuit dice. A non-conductive adhesive is dispensed onto mating faces of die attach paddles of leadframes. The dice are placed into the non-conductive adhesive and then the die and die attach paddle assembly are heated to hard cure the adhesive between the mating faces of the die and die attach paddle. This provides long term electrical isolation of the integrated circuit die from the die attach paddle, and effectively eliminates silver migration from the die attach paddle which causes conductive paths to form that increase unwanted leakage currents in the die and ultimately cause failure during operation thereof. | 12-02-2010 |
20100311207 | Compounds Having A Diphenyl Oxide Backbone and Maleimide Functional Group - A compound having a diphenyl oxide backbone, and pendant from the backbone at least one hydrocarbon chain, the hydrocarbon chain containing an ester functionality and being terminated with a maleimide functional group is prepared from the reaction of diphenyl oxide, formaldehyde or paraformaldehyde, and a compound containing both carboxylic acid and maleimide functionality. Exemplary compounds include: | 12-09-2010 |
20100311208 | METHOD AND APPARATUS FOR NO LEAD SEMICONDUCTOR PACKAGE - A leadframe for use in fabricating a no lead semiconductor package contains connecting bars between individual electrical contact pads. For embodiments having a die pad, the leadframe further includes connecting bars between the contact pads and the die pad. The lower surfaces of the connecting bars are coplanar with the lower surfaces of the contact pads and/or the die pad, and the upper surfaces of the connecting bars are recessed with respect to the upper surfaces of the contact pads and/or the die pad. The semiconductor package is fabricated by encapsulating the die and the leadframe in a molding compound and then removing the connecting bars. The leadframe is typically formed by half etching a metal sheet to form the connecting bars. The connecting bars are removed from the encapsulated package by a selected cutting, sawing, or etching means, based on a predetermined pattern. | 12-09-2010 |
20100317155 | MULTIFUNCTIONAL DIE ATTACHMENT FILM AND SEMICONDUCTOR PACKAGING USING THE SAME - A multifunctional die attachment film used in a semiconductor packaging process includes a first die attachment film attached to a surface of a wafer having fine circuit patterns and solder bump patterns and having a first adhesive strength; and a second die attachment film attached on the first die attachment film and having a second adhesive strength with a wafer, a die chip, PCB and a flexible board, and the multifunctional die attachment film serves as a backgrinding tape in a backgrinding process, and after the backgrinding process is completed, the multifunctional die attachment film is not removed, but is used to attach a die chip to a connection member. And, the present invention utilizes the die attachment film as a backgrinding tape in the backgrinding process and concurrently a wafer protection means in a wafer dicing process, thereby preventing sawing burr, scratches or cracks. | 12-16-2010 |
20100330744 | ULTRATHIN SEMICONDUCTOR CIRCUIT HAVING CONTACT BUMPS AND CORRESPONDING PRODUCTION METHOD - The invention relates to an ultrathin semiconductor circuit having contact bumps and to a corresponding production method. The semiconductor circuit includes a bump supporting layer having a supporting layer thickness and having a supporting layer opening for uncovering a contact layer element being formed on the surface of a semiconductor circuit. An electrode layer is situated on the surface of the contact layer element within the opening of the bump supporting layer, on which electrode layer is formed a bump metallization for realizing the contact bump. On account of the bump supporting layer, a thickness of the semiconductor circuit can be thinned to well below 300 micrometers, with the wafer reliably being prevented from breaking. Furthermore, the moisture barrier properties of the semiconductor circuit are thereby improved. | 12-30-2010 |
20110003433 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A disclosed device includes a manufacturing method of semiconductor device including preparing a semiconductor substrate including semiconductor chip forming regions, scribing regions surrounding these regions, and cutting regions formed in the scribing regions and narrower than the scribing regions, forming check patterns and semiconductor chips, forming a resist film, forming through grooves narrower than the scribing regions and wider than the check patterns and the cutting regions, removing the check patterns with a wet blast process using the resist film and collectively forming grooves at portions of a protection film and the semiconductor substrate facing the through grooves, removing the resist film, forming internal connection terminals on the contacting faces, forming an insulating resin layer, forming a wiring forming face by removing until connecting faces are exposed, forming wiring patterns, and cutting the semiconductor substrate, the insulating resin layer, and a solder resist layer to separate into individual semiconductor devices. | 01-06-2011 |
20110003434 | SEMICONDUCTOR CHIP PACKAGE STRUCTURE FOR ACHIEVING FACE-UP ELECTRICAL CONNECTION WITHOUT USING A WIRE-BONDING PROCESS AND METHOD FOR MAKING THE SAME - A semiconductor chip package structure for achieving face-up electrical connection without using a wire-bonding process includes a package unit, a semiconductor chip, a substrate unit, a first insulative unit, a first conductive unit, a second conductive unit, and a second insulative unit. The package unit has a central receiving groove and an outer receiving groove formed around the central receiving groove. The semiconductor chip has a plurality of conductive pads. The first insulative unit has a first insulative layer formed between the conductive pads. The first conductive unit has a plurality of first conductive layers. The second conductive unit has a plurality of second conductive layers formed on the first conductive layers. The second insulative unit is formed between the first conductive layers and between the second conductive layers. | 01-06-2011 |
20110014749 | Method for Packaging Semiconductor Dies Having Through-Silicon Vias - An integrated circuit structure is provided. The integrated circuit structure includes a die and an anisotropic conducing film (ACF) adjoining the back surface of the die. The die includes a front surface; a back surface on an opposite side of the die than the front surface; and a through-silicon via (TSV) exposed through the back surface of the die. | 01-20-2011 |
20110020984 | Method of Manufacturing A Semiconductor Device - A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate. | 01-27-2011 |
20110027942 | SEMICONDUCTOR PACKAGE - A semiconductor package is disclosed. One embodiment provides a semiconductor package singulated from a wafer includes a chip defining an active surface, a back side opposite the active surface, and peripheral sides extending between the active surface and the back side; a contact pad disposed on the active surface; and a metallization layer extending from the contact pad onto a portion of the peripheral sides of the chip. | 02-03-2011 |
20110033981 | MODULAR DIE AND MASK FOR SEMICONDUCTOR PROCESSING - Modular dies and modular masks that can be used during the manufacture of semiconductor devices are described. The modular mask can be used repeatedly to make multiple, substantially-similar modular dies. The modular die contains a substrate with an integrated circuit as well as a conductive layer containing a source metal and a gate metal connected respectively to the source and gate of the integrated circuit. The gate metal of the conductive layer is located only in an outer portion of the modular die. The modular die can be made by providing the integrated circuit in a first and second portion of the substrate, providing the conductive layer on both the first and second portions, making a first modular die by patterning the conductive layer on the first portion using the modular mask; moving the modular mask to the second portion and using it to make a second modular die by patterning the conductive layer on the second portion. Thus, fewer mask sets need to be made, improving efficiency and reducing costs. Other embodiments are described. | 02-10-2011 |
20110045637 | Ultra Thin Bumped Wafer With Under-Film - A method of making a semiconductor device includes forming an under-film layer over bumps disposed on a surface of a wafer to completely cover the bumps, and forming an adhesive layer over the under-film layer. The method further includes attaching a support layer over the adhesive layer, removing a portion of a back surface of the wafer, and removing the support layer to expose the adhesive layer that remains disposed over the under-film layer. The method further includes removing the adhesive layer to expose the under-film layer while the bumps remain completely covered by the under-film layer, and singulating the wafer to form a semiconductor die. The method further includes pressing the bumps into contact with a substrate while the under-film layer provides an underfill between the semiconductor die and the substrate. | 02-24-2011 |
20110053318 | FABRICATION METHOD OF PACKAGE STRUCTURE - Provided is a fabrication method of a package structure, including cutting a full-panel packaging substrate into a plurality of packaging substrate blocks, each of which has a plurality of packaging substrate units; mounting and packaging a semiconductor chip on each of the packaging substrate units and securing and protecting the semiconductor chips with an encapsulating material, thereby forming a plurality of packaging substrate blocks with packaging substrate units; and cutting the packaging substrate blocks to separate the packaging substrate units from each other. In the fabrication process, the alignment error between packaging substrate units in each packaging substrate block can be reduced by cutting the packaging substrate into packaging substrate blocks of appropriate size, thereby increasing the yield, and also the packaging of the semiconductor chips can be performed at the same time on all packaging substrate units in each substrate block so as to integrate fabrication of substrates with the packaging of semiconductor chips to simplify fabrication steps, thus increasing the productivity and reducing fabrication costs. | 03-03-2011 |
20110070698 | Semiconductor package with adhesive material pre-printed on the lead frame and chip, and its manufacturing method - This invention discloses a semiconductor package with adhesive material pre-printed on the lead frame and chip, and the manufacturing method. The adhesive material is applied onto the chip carrier and the pin of the lead frame and also on the front electrode of the semiconductor chip via pre-printing. The back of the semiconductor chip is adhered on the chip carrier, and the front electrode of the semiconductor chip and the pin are connected respectively with a metal connector. The size, shape and thickness of the adhesive material are applied according to different application requirements according to size and shapes of the contact zone of the semiconductor chip and the metal connector. Particularly, the adhesive zones are formed by pre-printing the adhesive material thus significantly enhance the quality and performance of semiconductor products, and improves the productivity. | 03-24-2011 |
20110097850 | METHOD OF FABRICATING A PACKAGING STRUCTURE - A method of fabricating a packaging structure includes cutting a panel of packaging substrate into a plurality of packaging substrate blocks each having a plurality of packaging substrate units; mounting and packaging a semiconductor chip on each of the packaging substrate unit to form package blocks each having multiple packaging structure units; and cutting package blocks to form a plurality of package units. In the method, the alignment difference between the packaging structure units in each package block is minimized by appropriately cutting and forming substrate blocks to achieve higher precision and better yield, and also packaging of semiconductor chips can be performed on all package units in the substrate blocks, thereby integrating fabrication with packaging at one time to improve production efficiency and reduce the overall costs as a result. | 04-28-2011 |
20110097851 | METHOD OF FABRICATING A PACKAGE STRUCTURE - A method fabricates a packaging structure, including cutting a complete panel of packaging substrates with a large area into a plurality of packaging substrate blocks each having a plurality of packaging substrate units; mounting a semiconductor chip on each of the packaging substrate units and securing the semiconductor chip to the packaging substrate unit with a molding material, to form a plurality of packaging structure blocks each having a plurality of packaging structure units; and cutting the packaging structure block into a plurality of packaging structure units. Accordingly, each of the packaging structure unit has a moderate area, the alignment difference between the packaging structure units in each of the packaging structure blocks can be reduced, and the semiconductor chips for all the packaging substrate units in each of the packaging substrate blocks can be packaged at one time. Therefore, the yield is increased and the overall cost is reduced. | 04-28-2011 |
20110104853 | METHOD OF FORMING SEMICONDUCTOR PACKAGE - A method of forming a semiconductor package includes providing a transfer film and placing electronic components on the transfer film with active sides of the electronic components facing the transfer film. The electronic components include a first assembled package and one or more of a second assembled package and a passive component. A molding operation is performed to encapsulate the electronic components and one side of the transfer film. The transfer film is then removed, which exposes the active sides of the electronic components. An electrical distribution layer is formed over the active sides of the electronic components and electrically connects the electronic components. Conductive bumps are then formed on the electrical distribution layer. | 05-05-2011 |
20110104854 | METHOD AND LEADFRAME FOR PACKAGING INTEGRATED CIRCUITS - A leadframe suitable for use in the packaging of at least two integrated circuit dice into a single integrated circuit package is described. The leadframe includes a plurality of leads. Each of a first set of the plurality of leads has a first side and a second side substantially opposite the first side of the lead. Additionally, each of the first and second sides of the first set of leads each include at least two solder pads. Each solder pad on a lead of the first set of leads is isolated from other solder pads on the same side of the lead with at least one recessed region adjacent the solder pad. In various embodiments, I/O pads from at least two dice are physically and electrically connected to the opposing sides of the leads. | 05-05-2011 |
20110111562 | Partially Patterned Lead Frames and Methods of Making and Using the Same in Semiconductor Packaging - A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging lead-count, wherein the method lends itself to better automation of the manufacturing line and improved quality and reliability of the packages produced therefrom. A major portion of the manufacturing process steps is performed with a partially patterned strip of metal formed into a web-like lead frame on one side so that the web-like lead frame is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant. The resultant package being electrically isolated enables strip testing and reliable singulation. | 05-12-2011 |
20110117702 | APPARATUS AND METHOD FOR PROCESSING A SUBSTRATE - A method of processing a substrate that displays out-gassing when placed in a vacuum comprises placing the substrate in a vacuum and performing an out-gassing treatment by heating the substrate to a temperature T | 05-19-2011 |
20110124157 | METHOD FOR ENCAPSULATING ELECTRONIC COMPONENTS ON A WAFER - A method for encapsulating electronic components, including the steps of: forming, in a first surface of a semiconductor wafer, electronic components; forming, on the first surface, an interconnection stack including conductive tracks and vias separated by an insulating material; forming first and second bonding pads on the interconnection stack; thinning down the wafer, except at least on its contour; filling the thinned-down region with a first resin layer; arranging at least one first chip on the first bonding pads and forming solder bumps on the second bonding pads; depositing a second resin layer covering the first chips and partially covering the solder bumps; bonding an adhesive strip on the first resin layer; and scribing the structure into individual chips. | 05-26-2011 |
20110129961 | Process to form semiconductor packages with external leads - This invention discloses a process for packaging semiconductor device with external leads. The process includes comprises Step 1: providing a lead frame comprising a plurality of lead frame units connected by a plurality of metal beams, each lead frame unit comprising a die pad and a plurality of leads located on opposite sides of the die pad; adhering a semiconductor chip onto each of the die pad, and providing a plurality of metal connections for electrically connecting each chip to its corresponding leads; Step 2 providing a plastic molding material to enclose the plurality of the lead frame units, the metal beams, the chips, and at least portions of the metal connections; Step 3 removing a portion of the plastic molding material above the metal beams to expose the metal beams and portions of the leads in connection with the metal beams; and Step 4 separating each lead frame unit, forming a plurality of individual semiconductor plastic package components with external leads. | 06-02-2011 |
20110129962 | ENCAPSULATION METHOD FOR PACKAGING SEMICONDUCTOR COMPONENTS WITH EXTERNAL LEADS - This invention discloses a method for packaging a semiconductor device with leads extending outside its encapsulation. The method comprises the following steps: Step 1, providing a lead frame comprising a plurality of lead frame units arranged in two dimensional array, each lead frame unit comprising a die pad and a plurality of leads located along two opposite sides of the die pad, attaching a semiconductor chip onto the die pad and electrically connecting the electrodes on each chip to its corresponding leads; Step 2, Encapsulating the chips, the die pads, and the leads with molding material into a plurality of one dimensional plastic encapsulation bars with the leads of each lead frame unit extending out along two opposite sides of the plastic encapsulation bars connecting to a plurality of tie bars substantially parallel to the plastic encapsulation bars; Step 3, Trimming off the tie bars therefore cutting off the connections between the leads to the tie bars while preserving a portion of the leads extending out of the plastic encapsulation bars; and Step 4, Sawing through the plastic encapsulation bars to form a plurality of individual semiconductor components with leads extending outside its encapsulation. | 06-02-2011 |
20110159642 | TAPE FOR HOLDING CHIP, METHOD OF HOLDING CHIP-SHAPED WORKPIECE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING TAPE FOR HOLDING CHIP, AND METHOD OF MANUFACTURING TAPE FOR HOLDING CHIP - The present invention aims to provide a tape for holding a chip that makes pasting and peeling of a chip-shaped workpiece easy. It is a tape for holding a chip having a configuration in which a pressure-sensitive adhesive layer is formed on a base material, wherein the pressure-sensitive adhesive layer has a chip-shaped workpiece pasting region onto which a chip-shaped workpiece is pasted and a frame pasting region onto which a mount frame is pasted, and that is used by pasting the mount frame to the frame pasting region, wherein the 180-degree peeling adhesive power of the pressure-sensitive adhesive layer to a silicon mirror wafer at the frame pasting region is 5 times or more the 180-degree peeling adhesive power of the pressure-sensitive adhesive layer to a silicon mirror wafer at the chip-shaped workpiece pasting region. | 06-30-2011 |
20110171780 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Of three chips ( | 07-14-2011 |
20110171781 | METHOD OF FABRICATING A 3-D DEVICE - A method of fabricating a semiconductor device includes providing a semiconductor substrate having an active surface, thinning the substrate by removing material from a second surface of the substrate opposite the active surface, bonding a metal carrier to the second surface of the thinned substrate, forming a via opening in the thinned substrate, forming a conductive member in the via opening, and patterning the metal carrier bonded to the second surface of the thinned substrate to form a metal pattern. | 07-14-2011 |
20110183468 | Semiconductor device - There is provided a semiconductor device whose cost is low and whose case is restrained from breaking. In the semiconductor device having a semiconductor sensor chip, a signal processing circuit for processing signals output from the semiconductor sensor chip and a hollow case for mounting the semiconductor sensor chip and the signal processing circuit therein, the case is constructed by bonding a concave bottom member whose one end is opened with a plate-like lid member that covers the opening of the bottom member. Then, the bottom and lid members are both made of a semiconductor material and are bonded by means of anode bonding or metal bonding for example. | 07-28-2011 |
20110183469 | Integrated semiconductor substrate structure using incompatible processes - A plurality of FPGA dice is disposed upon a semiconductor substrate. In order both to connect thousands of signal interconnect lines between the plurality of FPGA dice and to supply the immense power required, it is desired that the substrate construction include two different portions, each manufactured using incompatible processes. The first portion is a signal interconnect structure containing a thin conductor layers portion characterized as having a plurality of thin, fine-pitch conductors. The second portion is a power connection structure that includes thick conductors and vertical through-holes. The through-holes contain conductive material and supply power to the FPGA dice from power bus bars located at the other side of the semiconductor substrate. The portions are joined at the wafer level by polishing the wafer surfaces within a few atoms of flatness and subsequent cleaning. The portions are then fusion bonded together or combined using an adhesive material. | 07-28-2011 |
20110189822 | METHOD OF MANUFACTURING LAYERED CHIP PACKAGE - A layered chip package includes a main body and wiring. The main body includes a plurality of layer portions stacked. The wiring is disposed on at least one side surface of the main body. In the method of manufacturing the layered chip package, first, a plurality of substructures each of which includes an array of a plurality of preliminary layer portions are used to fabricate a layered substructure that includes a plurality of pre-separation main bodies arranged in rows. Next, the layered substructure is cut into a plurality of blocks each of which includes a row of a plurality of pre-separation main bodies, and the wiring is formed on the plurality of pre-separation main bodies included in each block simultaneously. The plurality of pre-separation main bodies are then separated from each other. Each of the plurality of blocks includes a row of three, four, or five pre-separation main bodies. | 08-04-2011 |
20110189823 | METHOD OF MAKING SEMICONDUCTOR PACKAGE WITH IMPROVED STANDOFF - A no-lead type semiconductor package is formed by attaching a die to a top surface of a flag of a lead frame and then taping a bottom surface of the flag and leads of the lead frame. Die bonding pads are connected to the leads with wires and then the assembly is put in a mold chase and encapsulated with a plastic material. The mold chase has protrusions between the flag and the leads of a lead frame, and between the leads themselves, which causes indentations to be formed between the leads and between the flag and the leads. The method is particularly useful for making quad flat no lead (QFN) devices and power-QFN type devices. | 08-04-2011 |
20110195545 | PACKAGE PROCESS - A package process is provided. The package process includes: disposing a semiconductor substrate on a carrier, wherein the semiconductor substrate has plural contacts at a side facing the carrier; thinning the semiconductor substrate from a back side of the semiconductor substrate and then forming plural through silicon vias in the thinned semiconductor substrate; forming plural first pads on the semiconductor substrate, wherein the first pads respectively connected to the through silicon vias; bonding plural chips to the semiconductor substrate, wherein the chips are electrically connected to the corresponding pads; forming a molding compound on the semiconductor substrate to cover the chips and the first pads; separating the semiconductor substrate and the carrier and then forming plural solder balls on the semiconductor substrate; and sawing the molding compound and the semiconductor substrate. | 08-11-2011 |
20110201155 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To provide a technology capable of preventing the deterioration of the reliability of semiconductor devices caused by the gasification of a part of components of the material constituting a wiring substrate. | 08-18-2011 |
20110207263 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - The present invention relates to a method of manufacturing a semiconductor device including (1) forming a laminated structure on a major surface of a semiconductor substrate, the laminated structure comprising at least a first metal layer that forms a Schottky junction with the semiconductor substrate, a second metal layer primarily composed of aluminum, and a third metal layer primarily composed of molybdenum or titanium, (2) patterning the laminated structure into a predetermined configuration, (3) forming a solder bonding metal layer comprising at least nickel, ion or cobalt on the major surface of the semiconductor substrate having the patterned laminated structure formed thereon, (4) patterning the solder bonding metal layer into a pattern configuration identical to that of the laminated structure, (5) cutting the semiconductor substrate on which the laminated structure and the solder bonding metal layer are patterned to form a plurality of semiconductor chips, and (6) bonding the semiconductor chip to a first frame using at least one solder layer formed on the solder bonding metal layer on the major surface of the semiconductor substrate, and bonding a rear face of the semiconductor chip to a second frame. | 08-25-2011 |
20110212574 | PROCESSING METHOD FOR PACKAGE SUBSTRATE - A processing method for a package substrate having a base substrate partitioned by a plurality of crossing division lines to form a plurality of chip forming areas where a plurality of semiconductor chips are respectively formed and molded with resin. The package substrate has a resin surface and an electrode surface opposite to the resin surface. The processing method includes a warp correcting step of cutting the package substrate from the resin surface or the electrode surface along the division lines by using a cutting blade to form a cut groove, thereby correcting a warp of the package substrate, and a grinding step of grinding the resin surface of the package substrate in the condition where the electrode surface of the package substrate is held on a holding table after performing the warp correcting step, thereby reducing the thickness of the package substrate to a predetermined thickness. | 09-01-2011 |
20110212575 | METHOD FOR MANUFACTURING THIN FILM INTEGRATED CIRCUIT, AND ELEMENT SUBSTRATE - Application form of and demand for an IC chip formed with a silicon wafer are expected to increase, and further reduction in cost is required. An object of the invention is to provide a structure of an IC chip and a process capable of producing at a lower cost. In view of the above described object, one feature of the invention is to provide the steps of forming a separation layer over an insulating substrate and forming a thin film integrated circuit having a semiconductor film as an active region over the separation layer, wherein the thin film integrated circuit is not separated. There is less limitation on the shape of a mother substrate in the case of using the insulating substrate, when compared with the case of taking a chip out of a circular silicon wafer. Accordingly, reduction in cost of an IC chip can be achieved. | 09-01-2011 |
20110217813 | METHOD OF FABRICATING MULTI-CHIP PACKAGE STRUCTURE - A method of fabricating a multi-chip package structure is provided. In the method, a number of cavities are formed on a predetermined cutting line of a first wafer by partly removing the first wafer and a first metal layer. Conductive walls of a first circuit layer are electrically connected to a cut cross-section of the first metal layer exposed by the cavities. In addition, conductive bumps of a second wafer or a chip are pressed into a cover layer and electrically connected to the first circuit layer. The first metal layer is then patterned to form a second circuit layer having a number of second pads. Next, the first wafer and the second wafer are cut along the predetermined cutting line to form a number of separated multi-chip package structures. | 09-08-2011 |
20110217814 | METHOD FOR SINGULATING ELECTRONIC COMPONENTS FROM A SUBSTRATE - Methods for forming electronic assemblies are provided. A device substrate having a plurality of electronic components embedded therein is provided. The device substrate is attached to a carrier substrate using an adhesive material. A plurality of cuts are formed through the device substrate to divide the device substrate into a plurality of portions. Each of the plurality of portions includes at least one of the electronic components. A force is applied to each of the plurality of portions in a direction away from the carrier substrate to remove the plurality of portions from the carrier substrate. | 09-08-2011 |
20110244630 | Method of Substrate Bonding with Bonding Material Having Rare Earth Metal - A microchip has a bonding material that bonds a first substrate to a second substrate. The bonding material has, among other things, a rare earth metal and other material. | 10-06-2011 |
20110256666 | THERMOSETTING DIE BOND FILM, DICING DIE BOND FILM AND SEMICONDUCTOR DEVICE - The present invention provides a thermosetting type die bond film that can be preferably broken by tensile force. It is a thermosetting type die bond film used for a method of obtaining a semiconductor element from a semiconductor wafer by forming a reforming region by irradiating the semiconductor wafer with a laser beam and then breaking the semiconductor wafer in the reforming region or a method of obtaining a semiconductor element from a semiconductor wafer by forming grooves that do not reach the backside of the semiconductor wafer on a surface thereof and then exposing the grooves from the backside by grinding the backside of the semiconductor wafer, wherein the elongation rate at break at 25° C. before thermal curing is larger than 40% and 500% or less. | 10-20-2011 |
20110256667 | STACKED WAFER MANUFACTURING METHOD - A manufacturing method for a stacked wafer configured by bonding a mother wafer having a plurality of first semiconductor device and a stacking wafer having a plurality of second semiconductor devices. The manufacturing method includes the steps of attaching a protective member to the front side of the stacking wafer to protect the second semiconductor devices, next grinding the back side of the stacking wafer, next bonding the front side of a reinforcing wafer through a bonding layer to the back side of the stacking wafer, next dividing the stacking wafer together with the reinforcing wafer into the plural second semiconductor devices, next bonding the front side of each second semiconductor device to the front side of the mother wafer to thereby connect the electrodes of each second semiconductor device to the electrodes of the corresponding first semiconductor device of the mother wafer, and finally grinding the reinforcing wafer bonded to the back side of each second semiconductor device to thereby remove the reinforcing wafer. | 10-20-2011 |
20110269269 | LASER ABLATION ALTERNATIVE TO LOW COST LEADFRAME PROCESS - The present inventions relate generally to methods for packaging integrated circuits using thin foils that form electrical interconnects for the package. The foil includes a base layer (such as copper) with an optional plating layer (such as silver) suitable for improving adhesion of the bonding wires (or other connectors) to the foil. The base layer (or the plated surface if the foil is preplated) of the foil is patterned by laser ablation to define components (e.g. contacts) of a device area. The patterning is arranged to ablate entirely through selected portions of the plating layer and part, but not all, of the way through corresponding underlying portions of the base layer. In some embodiments, the metallic foil is partially etched after the laser ablation in order to deepen the trenches that define the patterning of the foil. Multiple dice may then be attached to die attach pad areas of the plated foil and electrically coupled to electrical contacts. Some embodiments contemplate encapsulating the dice, bonding wires, and portions of the plated foil with a plastic molding material. Portions of the metallic foil may then be removed by etching, laser ablation, or grinding. The resulting structure may then be singulated to form individual integrated circuit packages. | 11-03-2011 |
20110281398 | THIN QUAD FLAT PACKAGE WITH NO LEADS (QFN) FABRICATION METHODS - Embodiments of the present invention include a method of packaging semiconductor devices. The method comprises the steps of molding a surface of a wafer, sawing the wafer into individual devices, attaching the individual semiconductor device to an adhesive surface, molding the exposed surface, and sawing the wafer into individual semiconductor devices. The step of molding forms a continuous molded layer. The step of sawing results in each individual semiconductor having a molded layer. This molded layer corresponds to a portion of the continuous molded layer. The step of attaching includes attaching the molded layer of the individual semiconductor devices to the adhesive surface. The step of molding the exposed area includes molding an exposed area above the adhesive surface. This forms a solid expanse of material. The step of sawing the wafer into individual semiconductor devices includes sawing the solid expanse of material. | 11-17-2011 |
20110281399 | ADHESIVE BONDING SHEET, SEMICONDUCTOR DEVICE USING SAME, AND METHOD FOR MANUFACTURING SUCH SEMICONDUCTOR DEVICE - An adhesive bonding sheet having an optically transmitting supporting substrate and an adhesive bonding layer, and being used in both a dicing step and a semiconductor element adhesion step, wherein the adhesive bonding layer comprises:
| 11-17-2011 |
20110287584 | SEMICONDUCTOR PACKAGE HAVING SIDE WALLS AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package includes a semiconductor chip having an upper surface, side surfaces connected with the upper surface, and bonding pads formed on the upper surface. A first insulation layer pattern is formed to cover the upper surface and the side surfaces of the semiconductor chip and expose the bonding pads. Re-distribution lines are placed on the first insulation layer pattern and include first re-distribution line parts and second re-distribution line parts. The first re-distribution line parts have an end connected with the bonding pads and correspond to the upper surface of the semiconductor chip and the second re-distribution line parts extend from the first re-distribution line parts beyond the side surfaces of the semiconductor chip. A second insulation layer pattern is formed over the semiconductor chip and exposes portions of the first re-distribution line parts and the second re-distribution line parts. | 11-24-2011 |
20110287585 | SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR ELEMENTS MOUNTED ON BASE PLATE - A method of manufacturing a semiconductor device and a semiconductor device including a first semiconductor element mounted on a first surface of a base plate, wherein solder balls are formed on a second opposite surface of the base plate—such that the second opposite surface includes an area without solder balls. At least one second semiconductor element is mounted to the base plate at the area of the second surface without solder balls. The at least one semiconductor element may be mounted to the base plate using low molecular adhesive, or in the alternative, high temperature solder. | 11-24-2011 |
20110294262 | SEMICONDUCTOR PACKAGE PROCESS WITH IMPROVED DIE ATTACH METHOD FOR ULTRATHIN CHIPS - A semiconductor packaging process with improved die attach method for ultrathin chips package comprises the steps of providing a semiconductor wafer having a wafer frontside and a wafer backside with a plurality of integrated circuit chips (IC chips) formed on the wafer frontside; adhering a supporting substrate onto the wafer frontside through a bonding layer to form a wafer combo; grinding the wafer backside with the supporting substrate and the wafer bonded together; dicing the wafer combo into a plurality of die combos each comprising a substrate piece stacked on top of an IC chip bonded by a bonding layer piece; attaching a die combo onto a die pad of a lead frame with a bottom of the IC chip connected to the lead frame thereof; and removing the substrate piece with the bonding layer piece from the top surface of the IC chip. | 12-01-2011 |
20110294263 | Pattern verification method, program thereof, and manufacturing method of semiconductor device - A verification method of an integrated circuit pattern includes extracting a pattern which is not greater than a preset pattern size, extracting a pattern edge as a target of lithography simulation from the extracted pattern, and performing the lithography simulation on the extracted pattern edge to verify the integrated circuit pattern. | 12-01-2011 |
20110294264 | HEAT SPREADER AS MECHANICAL REINFORCEMENT FOR ULTRA-THIN DIE - A technique to fabricate a package. A thin wafer supported by a wafer support substrate (WSS) is formed. The WSS-supported thin wafer layer is diced into a plurality of WSS-supported thin dice. A WSS-supported thin die is bonded to a first heat spreader (HS) to form a HS-reinforced thin die. | 12-01-2011 |
20110318876 | SEMICONDUCTOR PACKAGE, ELECTRICAL AND ELECTRONIC APPARATUS INCLUDING THE SEMICONDUCTOR PACKAGE, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - In one embodiment, a semiconductor package may include a semiconductor chip having a chip pad formed on a first surface thereof, a sealing member for sealing the semiconductor chip and exposing the first surface of the semiconductor chip, a conductive wiring overlying a part of the first surface of the semiconductor chip and directly contacting a part of an upper surface of the sealing member. The conductive wiring further contacts the pad. The semiconductor package may also include an encapsulant covering the conductive wiring and having openings for exposing parts of the conductive wiring. | 12-29-2011 |
20110318877 | DICING METHODS - The present invention provides a dicing method that achieves excellent dicing properties at low costs by removing a metal film through a metal processing operation with a diamond tool and then performing pulse laser beam irradiation. The dicing method is a method of dicing a substrate to be processed, devices being formed in the substrate to be processed, a metal film being formed on one surface of the substrate to be processed. The dicing method includes: placing the substrate to be processed onto a first stage; forming a groove portion by removing the metal film through a metal processing operation with a diamond tool; placing the substrate to be processed onto a second stage; generating a clock signal; emitting a pulse laser beam synchronized with the clock signal to the groove portion of the substrate to be processed; moving the substrate to be processed and the pulse laser beam relative to each other; switching the pulse laser beam between irradiation and non-irradiation of the substrate to be processed on a light pulse basis by controlling passing and blocking of the pulse laser beam with a pulse picker in synchronization with the clock signal; and forming cracks in the substrate to be processed, the cracks reaching the substrate surface. | 12-29-2011 |
20110318878 | MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGES - Conductive core balls are joined to joint pads formed on an upper substrate. Core balls are joined to joint pads formed on an extending part of an upper-substrate substrate material. The joint pads formed on the extending part of the upper-substrate substrate material are joined to the joint pads formed on an extending part of a lower-substrate substrate material via the core balls. The joint pads formed in an area corresponding to the upper substrate of the upper-substrate substrate material are connected to the joint pads formed in an area corresponding to a lower substrate of the lower-substrate substrate material via the core balls and the conductive core balls. The upper-substrate substrate material is fixed to the lower-substrate substrate material by a mold resin supplied therebetween. The extending parts of the upper-substrate substrate material and the lower-substrate substrate material are removed, and the semiconductor packages are individualized. | 12-29-2011 |
20120015483 | Semiconductor Device Package and Method of Assembly Thereof - A semiconductor die package includes: an assembly including a semiconductor die, a clip structure attached to an upper surface of the semiconductor die, and a heat sink attached to an upper surface of the clip structure; and a molding material partially encapsulating the assembly, wherein an upper surface of the heat sink is exposed through the molding material. | 01-19-2012 |
20120028415 | DICING TAPE-INTEGRATED FILM FOR SEMICONDUCTOR BACK SURFACE, AND PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE - The present invention relates to a dicing tape-integrated film for semiconductor back surface including: a dicing tape including a base material and a pressure-sensitive adhesive layer laminated in this order, and a film for semiconductor back surface provided on the pressure-sensitive adhesive layer of the dicing tape, where the pressure-sensitive adhesive layer has a thickness of from 20 μm to 40 μm. | 02-02-2012 |
20120028416 | FILM FOR FLIP CHIP TYPE SEMICONDUCTOR BACK SURFACE AND ITS USE - The present invention relates to a film for flip chip type semiconductor back surface, which is to be disposed on a back surface of a semiconductor element flip chip-connected onto an adherend, the film for flip chip type semiconductor back surface including an adhesive layer and a protective layer laminated on the adhesive layer, in which the protective layer is constituted of a heat-resistant resin having a glass transition temperature of 200° C. or more or a metal. | 02-02-2012 |
20120028417 | SEMICONDUCTOR COMPONENT WITH CELL STRUCTURE AND METHOD FOR PRODUCING THE SAME - A semiconductor component comprises a semiconductor body comprising a first component electrode arranged on one of the surfaces of the semiconductor body, a second component electrode arranged on one of the surfaces of the semiconductor body, and a component control electrode arranged on one of the surfaces of the semiconductor body. In this case, active semiconductor element cells are arranged in a first active cell array of the semiconductor body, the semiconductor element cells comprising a first cell electrode, a second cell electrode and a cell control electrode and also a drift path between the cell electrodes. At least the component control electrode is arranged on a partial region of the semiconductor body and a second active cell array is additionally situated in the partial region of the semiconductor body below the component control electrode. | 02-02-2012 |
20120045870 | Method of Manufacturing Leadless Integrated Circuit Packages Having Electrically Routed Contacts - A method of manufacturing a leadless integrated circuit (IC) package comprising an IC chip mounted on a metal leadframe and a plurality of electrical contacts electrically coupled to the IC chip. The IC chip, the electrical contacts, and a portion of the metal leadframe are covered with an encapsulation compound, with portions of the electrical contacts exposed on a bottom surface of the encapsulation compound. The electrical contacts of the IC package having metal traces connecting bonding areas on a top surface thereof and contact areas on a bottom surface thereof, wherein at least some of the bonding areas are laterally disposed from the contact areas connected thereto. | 02-23-2012 |
20120088332 | Semiconductor Package and Method of Manufacturing the Same - A method of forming a semiconductor package includes attaching a semiconductor substrate on a support substrate, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region that separates respective ones of the semiconductor chips. A first cutting groove is formed that has a first kerf width between first and second ones of the plurality of first semiconductor chips. A plurality of second semiconductor chips is attached to the plurality of first semiconductor chips. A molding layer is formed so as to fill the first cutting groove and a second cutting groove having a second kerf width that is less than the first kerf width is formed in the molding layer so as to form individual molding layers covering one of the plurality of first semiconductor chips and one of the plurality of second semiconductor chips. | 04-12-2012 |
20120094439 | Method for Positioning Chips During the Production of a Reconstituted Wafer - A method for fabricating a re-built wafer which comprises chips having connection pads, comprising: fabricating a first wafer of chips, production on this wafer of a stack of at least one layer of redistribution of the pads of the chips on conductive tracks designed for the interconnection of the chips, this stack being designated the main RDL layer, cutting this wafer in order to obtain individual chips each furnished with their RDL layer, transferring the individual chips with their RDL layer to a sufficiently rigid support to remain flat during the following steps, which support is furnished with an adhesive layer, with the RDL layer on the adhesive layer, depositing a resin in order to encapsulate the chips, polymerizing the resin, removing the rigid support, depositing a single redistribution layer called a mini RDL in order to connect the conductive tracks of the main RDL layer up to interconnection contacts, through apertures made in the adhesive layer, the wafer comprising the polymerized resin, the chips with their RDL layer and the mini RDL being the re-built wafer. | 04-19-2012 |
20120108011 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE WITH A BACK ELECTRODE - A semiconductor device capable of stabilizing operations thereof is provided. This semiconductor device comprises a substrate provided with a region having concentrated dislocations at least on part of the back surface thereof, a semiconductor element layer formed on the front surface of the substrate, an insulator film formed on the region of the back surface of the substrate having concentrated dislocations and a back electrode formed to be in contact with a region of the back surface of the substrate other than the region having concentrated dislocations. | 05-03-2012 |
20120108012 | FILM FOR SEMICONDUCTOR AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A film for semiconductor includes a support film, a second adhesive layer, a first adhesive layer and a bonding layer which are laminated together in this order. This film for semiconductor is configured so that it supports a semiconductor wafer laminated on the bonding layer thereof when the semiconductor wafer is diced and the bonding layer is selectively peeled off from the first adhesive layer when the semiconductor elements obtained by the dicing are picked up. This film for semiconductor is characterized in that an average thickness of the second adhesive layer is in the range of 20 to 100 μm. This makes it possible to control cutting lines formed during the dicing so as to locate distal ends thereof within the first adhesive layer easily and reliably and to prevent defects which would be generated when the cutting lines come down to the support film. | 05-03-2012 |
20120115280 | FILM FOR SEMICONDUCTOR AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A film for semiconductor includes a support film, a second adhesive layer, a first adhesive layer and a bonding layer which are laminated together in this order. This film for semiconductor is configured so that it supports a semiconductor wafer laminated on the bonding layer thereof when the semiconductor wafer is diced and the bonding layer is selectively peeled off from the first adhesive layer when a chip is picked up. This film for semiconductor is characterized in that in the case where peel strength at 23° C. of the chip is defined as “F | 05-10-2012 |
20120129297 | METHOD OF MANUFACTURING WAFER LEVEL PACKAGE - A method of manufacturing a wafer level package including: separating chips by dicing a wafer; forming a removable resin layer in a space between the separated chips and at upper parts thereof; separating the chips by dicing the removable resin layer; mounting the chips separated in a state of being surrounded by the removable resin layer, on a carrier plate; forming a molding material on the carrier plate to cover the removable resin layer; separating the carrier plate from the chips; forming a dielectric layer having redistribution lines connected to the chips, on the chips exposed by separating the carrier plate; and forming a solder resist layer on the dielectric layer to expose portions of the redistribution lines. | 05-24-2012 |
20120142146 | METHOD OF MANUFACTURING LAYERED CHIP PACKAGE - A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes a plurality of stacked layer portions. A method of manufacturing the layered chip package includes the step of fabricating a layered substructure and the step of cutting the layered substructure. The layered substructure includes: a plurality of arrayed pre-separation main bodies; a plurality of accommodation parts disposed between two adjacent pre-separation main bodies; and a plurality of preliminary wires accommodated in the accommodation parts. The accommodation parts are formed in a photosensitive resin layer by photolithography. In the step of cutting the layered substructure, the plurality of pre-separation main bodies are separated from each other, and the wires are formed by the preliminary wires. | 06-07-2012 |
20120149152 | METHOD TO PREVENT METAL PAD DAMAGE IN WAFER LEVEL PACKAGE - The present disclosure provide a method of manufacturing a microelectronic device. The method includes forming a bonding pad on a first substrate; forming wiring pads on the first substrate; forming a protection material layer on the first substrate, on sidewalls and top surfaces of the wiring pads, and on sidewalls of the bonding pad, such that a top surface of the bonding pad is at least partially exposed; bonding the first substrate to a second substrate through the bonding pad; opening the second substrate to expose the wiring pads; and removing the protection material layer. | 06-14-2012 |
20120156830 | METHOD OF FORMING A RING-SHAPED METAL STRUCTURE - A method includes providing a first semiconductor chip comprising a ring-shaped metal structure extending along a contour of a first main surface of the semiconductor chip. The method includes encapsulating the first semiconductor chip with an encapsulation body thereby defining a second main surface and depositing a metal layer over the first semiconductor chip and the encapsulation body. A plurality of external contact pads are placed over the second main surface of the encapsulation body, the metal layer electrically coupling at least one external contact pad of the plurality of external contact pads to the ring-shaped metal structure. A seal ring is placed between the ring-shaped metal structure and the contour of the first main surface of the first semiconductor chip. | 06-21-2012 |
20120164790 | DOUBLE-FACED ELECTRODE PACKAGE, AND ITS MANUFACTURING METHOD - A dual-face package has an LSI chip sealed with a mold resin, and electrodes for external connections on both of the front face and the back face. The LSI chip is bonded onto the die pad of a leadframe whose outer lead portions are exposed as back-face electrodes at at least the back face. The LSI chip and a plurality of inner lead portions of the leadframe are connected by wiring. At least some of the plurality of inner lead portions have front-face electrodes integrally formed by working a portion of the leadframe. Head faces of the front-face electrodes, or bump electrodes connected to the respective head faces of the front-face electrodes serve as electrodes for external connections to another substrate, element, or the like. | 06-28-2012 |
20120178213 | CHIP SCALE PACKAGE STRUCTURE WITH CAN ATTACHMENT - A chip scale package (CSP) device includes a CSP having a semiconductor die electrically coupled to a plurality of solder balls. A can having an inside top surface and one or more side walls defines a chamber. The CSP is housed in the chamber and is attached to the inside top surface of the can. A printed circuit board is attached to the solder balls and to the one or more side walls to provide support to the CSP and to the can. The CSP may be a Wafer-Level CSP. The can may be built from a metallic substance or from a non-metallic substance. The can provides stress relief to the CSP during a drop test and during a thermal cycle test. | 07-12-2012 |
20120202320 | WAFER-LEVEL CHIP SCALE PACKAGING OF METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT-TRANSISTORS (MOSFET'S) - Wafer-level chip scale packaging of metal-oxide-semiconductor-field-effect-transistors (MOSFET's) provides protection and good solder-ability to a die backside by fabricating a plurality of power MOSFET devices with die contacts on a wafer that can later be cut into individual die. A plurality of contact pads is included on the wafer to provide connectivity to the die contacts. A layer which includes aluminum (Al) or zinc (Zn) is electrolessly plated on a backside of the wafer to form a metalized backside. The plating tank used in this step is not contaminated. The contact pads and metalized backside are plated with a layer of electroless nickel (Ni) followed by a layer of gold (Au). Solder balls are formed on each of the contact pads after their plating with nickel (Ni) and gold (Au). The wafer is diced to yield MOSFET wafer level chip-scale packages which provide protection and good solder-ability to the die backside. | 08-09-2012 |
20120208320 | On-Chip RF Shields with Front Side Redistribution Lines - A system on chip comprising a RF shield is disclosed. In one embodiment, the system on chip includes a RF component disposed on a chip, first redistribution lines disposed above the system on chip, the first redistribution lines coupled to I/O connection nodes. The system on chip further includes second redistribution lines disposed above the RF component, the second redistribution lines coupled to ground potential nodes. The second redistribution lines include a first set of parallel metal lines coupled together by a second set of parallel metal lines. | 08-16-2012 |
20120214278 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device comprises the steps of (a) applying a resin member onto a front surface of a semiconductor wafer having an uneven structure on the front surface thereof, and (b) flattening a surface of the resin member by heating the resin member, and in the method, the resin member is formed also on a side surface of the semiconductor wafer. The method further comprises the steps of (c) performing a thinning process for the semiconductor wafer on a back surface thereof after the step (b), and (d) removing the resin member from the semiconductor wafer after the step (c). By the method, it is possible to uniformize the thickness of a semiconductor wafer which is thinned and reduce the number of foreign matters remaining on a surface of the semiconductor wafer. | 08-23-2012 |
20120214279 | METHOD OF MANUFACTURING SEMICONDUCTOR CHIP STACK - A method of manufacturing a semiconductor chip stack includes providing a circuit layout of a function device, the circuit layout further comprising a first device layout and a second device layout, and an integration density of the first device layout is larger than an integration density of the second device layout; defining a plurality of first chip regions on a first wafer and forming the first device layout in each first chip region; defining a plurality of second chip regions on a second wafer and forming the second device layout in each second chip region; forming a plurality of first TSVs in each first wafer for electrically connecting the first device layout and the second device layout; and respectively cutting the first wafer and the second wafer to form a plurality of first chips and a plurality of second chips. | 08-23-2012 |
20120220080 | Method for Fabricating Flip-Attached and Underfilled Semiconductor Devices - A semiconductor device, which comprises a workpiece with an outline and a plurality of contact pads and further an external part with a plurality of terminal pads. This part is spaced from the workpiece and the terminal pads are aligned with the workpiece contact pads, respectively. A reflow element interconnects each of the contact pads with its respective terminal pad. Thermoplastic material fills the space between the workpiece and the part; this material adheres to the workpiece, the part and the reflow elements. Further, the material has an outline substantially in line with the outline of the workpiece, and fills the space substantially without voids. Due to the thermoplastic character of the filling material, the finished device can be reworked, when the temperature range for reflowing the reflow elements is reached. | 08-30-2012 |
20120244663 | SEMICONDUCTOR DEVICE CHIP MOUNTING METHOD - A semiconductor device chip has a plurality of projecting electrodes mounted on a wiring board or wafer having electrodes respectively corresponding to the projecting electrodes of the semiconductor device chip. An insulator is applied to the front side of the semiconductor device wafer where the projecting electrodes are formed, to fill any spaces between adjacent electrodes with the insulator. The front side of the wafer covered with the insulator is planarized to expose the end surfaces of the projecting electrodes, and the wafer is divided along division lines to obtain a plurality of individual semiconductor device chips. Each chip is mounted on the wiring board or the wafer with an anisotropic conductor interposed between the projecting electrodes of each chip and the electrodes of the wiring board or the wafer to thereby respectively connect the projecting electrodes and the electrodes through the anisotropic conductor. | 09-27-2012 |
20120258572 | ADHESIVE SHEET AND PRODUCTION METHOD FOR ELECTRONIC COMPONENT - Disclosed is an adhesive sheet that has a base film and an ultraviolet curable adhesive layered upon the base film. The ultraviolet curable adhesive includes 100 parts by mass of an acrylic ester copolymer with a weight-average molecular weight of at least one million, 20 to 200 parts by mass of a photopolymerizable acrylate having at least three carbon-carbon double bonds, and 0.1 to 10 parts by mass of an isocyanate curing agent. From among the monomers used during the copolymerization of the acrylic ester copolymer, a monomer having one or both of a hydroxyl group and a carboxyl group is included at no more than 0.1 mass %. | 10-11-2012 |
20120258573 | FABRICATION METHOD OF SUBSTRATE - A fabricating method of a substrate board is provided. The substrate board includes a substrate having rigid areas and flexible areas, and at least an electronic component disposed on the substrate, wherein each of the rigid areas is thicker than the flexible areas. A patterned high-extensive material may be additionally disposed on the substrate to improve reliability thereof. The rigid areas and the flexible areas may be formed by molds or cutters. By using an above structure, the electronic component is less affected when the substrate is under stress, so that good characteristics are maintained. | 10-11-2012 |
20120264257 | MOLD ARRAY PROCESS METHOD TO PREVENT EXPOSURE OF SUBSTRATE PERIPHERIES - Disclosed is a mold array process (MAP) method to prevent exposure of peripheries of substrate units where the major characteristic is to implement two kinds of encapsulating materials in the MAP method in mass production. A first encapsulating material for encapsulating chips is formed on a substrate strip by molding to continuously encapsulate the substrate units and the scribe lines between adjacent substrate units. Prior to forming a second encapsulating material, a plurality of cut grooves are formed along the scribing lines by pre-cutting processes to penetrate through the substrate strip but without penetrating through the first encapsulating material and have such a width that a plurality of peripheries of the substrate units are exposed outside the scribing lines. Then, the second encapsulating material is filled into the cut grooves. Accordingly, the peripheries of the substrate units are still encapsulated with the remains of the second encapsulating material after singulation processes where the substrate units are singulated into individual semiconductor packages to prevent exposure of the peripheries of the substrate units. | 10-18-2012 |
20120264258 | METHOD OF ASSEMBLING SEMICONDUCTOR DEVICE INCLUDING INSULATING SUBSTRATE AND HEAT SINK - Semiconductor dies are mounted on a heat sink array frame structure. The heat sink array frame structure and the semiconductor dies are assembled together with an insulating substrate that has a corresponding array of apertures on an adhesive tape. The semiconductor dies are connected electrically with electrical contacts on the insulating substrate. The semiconductor dies, heat sinks and electrical connections to the contacts are encapsulated with a mold compound and then the encapsulated array is de-taped and singulated. | 10-18-2012 |
20120288998 | WAFER LEVEL IC ASSEMBLY METHOD - A wafer level integrated circuit assembly method is conducted as follows. First, a mother device wafer with plural first posts is provided. The first posts are used for electrical connection and are made of copper according to an embodiment. Solder is sequentially formed on the first posts. The solder is preferably pre-formed on a wafer, and the locations of the solder correspond to the first posts of the mother device wafer. Consequently, the solder can be formed on or adhered to the first posts by placing the wafer having pre-formed solder onto the first posts. Plural dies having plural second posts corresponding to the first posts are placed onto the mother device wafer. Then, the solder is reflowed to bond the first and second posts, and the mother device wafer is diced. | 11-15-2012 |
20120288999 | METHOD FOR MANUFACTURING SEMICONDUCTOR MODULES - A method for fabricating a semiconductor module includes: bonding a semiconductor substrate onto a first insulating resin layer; dicing the semiconductor substrate into a plurality of individual semiconductor devices; widening the spacings between the adjacent semiconductor devices by expanding the first insulating resin layer in a biaxially stretched manner; fixing the plurality of semiconductor devices to a flat sheet, with a second insulating resin layer held between the plurality of semiconductor devices and the flat sheet, and removing the first insulating resin layer; stacking the plurality of semiconductor devices, a third insulating resin layer, and a metallic plate, in this order, so as to form a laminated body having electrodes by which to electrically connect the device electrodes to the metallic plate; forming a wiring layer by selectively removing the metallic plate and forming a plurality of semiconductor modules; and separating the semiconductor modules into individual units. | 11-15-2012 |
20120289000 | DICING TAPE-INTEGRATED FILM FOR SEMICONDUCTOR BACK SURFACE, AND PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE - The present invention relates to a dicing tape-integrated film for semiconductor back surface including: a dicing tape including a base material and a pressure-sensitive adhesive layer laminated in this order, and a film for semiconductor back surface provided on the pressure-sensitive adhesive layer of the dicing tape, where the pressure-sensitive adhesive layer has a thickness of from 20 μm to 40 μm. | 11-15-2012 |
20120289001 | Method for Making Solder-top Enhanced Semiconductor Device of Low Parasitic Packaging Impedance - A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes lithographically patterning the top metal layer into the contact zones and the contact enhancement zones; then forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness. | 11-15-2012 |
20120302008 | Packaging Jig and Process for Semiconductor Packaging - An embodiment is a method for semiconductor packaging. The method comprises attaching a chip to a carrier substrate through a first side of a jig, the chip being attached by bumps; applying balls to bond pads on the carrier substrate through a second side of the jig; and simultaneously reflowing the bumps and the balls. According to a further embodiment, a packaging jig comprises a cover, a base, and a connector. The cover has a first window through the cover. The base has a second window through the base. The first window exposes a first surface of a volume intermediate the cover and the base, and the second window exposes a second surface of the volume. The first surface is opposite the volume from the second surface. The connector aligns and couples the cover to the base. | 11-29-2012 |
20120309130 | Method of Manufacturing a Semiconductor Device - In one embodiment a method for manufacturing a semiconductor device comprises arranging a wafer on a carrier, the wafer comprising singulated chips; bonding the singulated chips to a support wafer, and removing the carrier. | 12-06-2012 |
20120315728 | Saw Type Package without Exposed Pad - In one embodiment, a method for manufacturing a saw type pad is provided. The method includes performing a first molding process to form a first molded layer beneath a pad of a lead frame. A semiconductor device is placed on the pad. A second molding process is performed to form a second molded layer. The first molded layer and the second molded layer form an encapsulation to enclose the semiconductor device and the pad. The lead frame is singulated to form an individualized semiconductor package. The pad is not exposed from a bottom surface of the semiconductor package. | 12-13-2012 |
20120322207 | SEMICONDUCTOR PACKAGE WITH ADHESIVE MATERIAL PRE-PRINTED ON THE LEAD FRAME AND CHIP, AND ITS MANUFACTURING METHOD - This invention discloses a semiconductor package with adhesive material pre-printed on the lead frame and chip, and the manufacturing method. The adhesive material is applied onto the chip carrier and the pin of the lead frame and also on the front electrode of the semiconductor chip via pre-printing. The back of the semiconductor chip is adhered on the chip carrier, and the front electrode of the semiconductor chip and the pin are connected respectively with a metal connector. The size, shape and thickness of the adhesive material are applied according to different application requirements according to size and shapes of the contact zone of the semiconductor chip and the metal connector. Particularly, the adhesive zones are formed by pre-printing the adhesive material thus significantly enhance the quality and performance of semiconductor products, and improves the productivity. | 12-20-2012 |
20120322208 | ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE - A method for manufacturing an electronic device includes forming a resin film over a wafer, the wafer including a plurality of elements formed therein, each of the elements including a functional unit, patterning the resin film to form a plurality of frame members, each of the frame members being provided on each of the elements and surrounding the functional unit, dividing the wafer into the elements, and providing an encapsulation. | 12-20-2012 |
20120329213 | FLEXIBLE ELECTRONIC DEVICE AND METHOD FOR THE FABRICATION OF SAME - A semiconductor device may have a thickness, such that the semiconductor devices are not flexible, and may be bonded and electrically coupled on a flexible substrate. After this bonding, the semiconductor device may be thinned so as to be rendered flexible. | 12-27-2012 |
20130005088 | METHODS OF FORMING SEMICONDUCTOR MODULES AND SEMICONDUCTOR MODULES FORMED BY THE SAME - Provided are methods of forming semiconductor modules. The method includes forming a high polymer material layer having an adhesive property on a support substrate, adhering a semiconductor chip to the support substrate using the high polymer material layer, bonding the semiconductor chip adhered to the support substrate to a flexible panel, and removing the support substrate. | 01-03-2013 |
20130005089 | Wafer Level Package For Heat Dissipation And Method Of Manufacturing The Same - Disclosed herein are a wafer level package for heat dissipation and a method of manufacturing the same. The wafer level package includes a heat dissipation plate including a cavity and a hole, a die including a pad disposed in the cavity of the heat dissipation plate in a face-up manner, a thermal conductive adhesive disposed between the die and an inner wall of the cavity and disposed in the hole, and a redistribution layer connected at one end to the pad and at the other end extended. The wafer level package protects the die from external environments and enables the die to be easily flush with the heat dissipation plate. | 01-03-2013 |
20130005090 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A HEAT SPREADER - A semiconductor device manufacturing method includes cutting a resin sealing body into a plurality of pieces, the resin sealing body including a plurality of semiconductor chips mounted on a wiring board, a heat spreader disposed above the plurality of the semiconductor chips, and a sealing resin filled between the wiring board and the heat spreader, wherein the cutting the resin sealing body includes shaving the resin sealing body from a side of the heat spreader, and shaving the resin sealing body from a side of the wiring board, wherein the shaving the resin sealing body from the side of the wiring board is carried out after the shaving from the side of the heat spreader, and wherein the resin sealing body is completely cut off by the shaving from the side of the wiring board, and mounting a group of ball-like electrodes at a back side of the wiring board. | 01-03-2013 |
20130005091 | Housing Body and Method for Production thereof - A package body ( | 01-03-2013 |
20130029457 | TCE Compensation for Package Substrates for Reduced Die Warpage Assembly - A method for assembling die packages includes attaching contacts on a first side of a plurality of first die to substrate pads on a top surface of a composite carrier. The composite carrier includes a package substrate including at least one embedded metal layer having its bottom surface secured to a semiconductor wafer. The composite carrier minimizes effects of the CTE mismatch between the die and the package substrate during assembly reduces warpage of the die. After the attaching, the semiconductor wafer is removed from the package substrate. Electrically conductive connectors are attached to the bottom surface of the package substrate, and the package substrate is sawed to form a plurality of singulated die packages. | 01-31-2013 |
20130034934 | WAFER LEVEL PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a wafer level package is provided that enables suppressing the wearing of a cutter and extending the lifetime of the cutter, including forming insulating first resin over the top face of a substrate, which includes a groove for wiring to be formed; forming a film of first metal that is to serve as a portion of the wiring on the top face of the first resin using physical vapor deposition; forming a film of second metal that is to form a portion of the wiring on the top face of the first metal, with a lower hardness than the first metal; setting a cutter at a height corresponding to a place where the film of the first metal is not formed on a side face of the groove or the film thickness is low; and cutting at least the first resin by scanning the cutter. | 02-07-2013 |
20130040426 | MANUFACTURING METHOD USING MULTI-STEP ADHESIVE CURING FOR SEALED SEMICONDUCTOR DEVICE - A method for forming a sealing body without cracks in manufacture of a semiconductor device having an external terminal formed through the use of an electrolysis plating method. A front surface of a semiconductor wafer is placed over a front surface of a first support heated to a first temperature. An adhesive sheet is then bonded to a back surface of the semiconductor wafer, after which the semiconductor wafer is subjected to heat treatment at a second temperature higher than the first temperature. After the semiconductor wafer and the adhesive sheet are cut along cutting regions, a plurality of semiconductor chips each having an adhesive patch bonded thereto are obtained. A mother substrate is placed over a front surface of a second support heated to a third temperature and the semiconductor chips are fixed to an upper surface of the mother substrate via the adhesive patch. | 02-14-2013 |
20130045570 | METHOD AND SYSTEM FOR WAFER LEVEL SINGULATION - A method of singulating a plurality of semiconductor dies includes providing a carrier substrate and joining a semiconductor substrate to the carrier substrate. The semiconductor substrate includes a plurality of devices. The method also includes forming a mask layer on the semiconductor substrate, exposing a predetermined portion of the mask layer to light, and processing the predetermined portion of the mask layer to form a predetermined mask pattern on the semiconductor substrate. The method further includes forming the plurality of semiconductor dies, each of the plurality of semiconductor dies being associated with the predetermined mask pattern and including one or more of the plurality of devices and separating the plurality of semiconductor dies from the carrier substrate. | 02-21-2013 |
20130059418 | FABRICATION METHOD OF SEMICONDUCTOR PACKAGE DEVICE, AND FABRICATION METHOD OF SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer. | 03-07-2013 |
20130065361 | CHIP PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor package structure is disclosed. In one embodiment, the method includes the steps of forming a plurality of conductive pastes on a matrix lead frame with a groove located within a predetermined distance from each conductive paste on the lead; partially curing the conductive pastes so that the conductive pastes are in a semi-cured state; preparing at least one chip with a plurality of bumps thereon; electrically connecting the chip and the lead by implanting the bumps into the semi-cured conductive pastes, wherein the groove on the lead of the matrix lead frame is configured to receive overflowed semi-cured conductive pastes; curing the semi-cured conductive pastes to completely secure the bumped chip; and forming an encapsulating material covering the lead frame and the chip. The method can also be applied in pre-molded lead frame package. | 03-14-2013 |
20130065362 | FLIP CHIP PACKAGE MANUFACTURING METHOD - A flip chip package manufacturing method is provided. A non-conductive film is pressed onto a wafer with multiple conductive bumps. The wafer is cut to multiple single chips. A carrier is provided, and a thermo-compression flip chip bonding process is executed to bond the non-conductive film onto the carrier. The carrier is transferred into a chamber with enclosed, pneumatic pressurized and heatingable characteristics to execute a de-void process to eliminate the bubbles and to execute a high-temperature soldering process to solder the single chip onto the carrier. The sequence of the de-void process and the high-temperature soldering process may exchange. | 03-14-2013 |
20130071970 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The present invention makes it possible to inhibit cutting burrs from forming in package dicing. | 03-21-2013 |
20130078767 | METHODS FOR FABRICATING INTEGRATED CIRCUIT SYSTEMS INCLUDING HIGH RELIABILITY DIE UNDER-FILL - A method is provided for fabricating an integrated circuit system that includes fabricating a plurality of integrated circuits in and on a semiconductor substrate. Spaced apart solder bumps are attached to the plurality of integrated circuits, the solder bumps in electrical contact to components of the integrated circuits. A dicing tape having a layer of under-fill material thereon is provided and the semiconductor substrate is laminated to the dicing tape with the layer of under-fill material filling spaces between the solder bumps. The semiconductor substrate and layer of under-fill material are diced to singulate individual ones of the plurality of integrated circuits, and one of the individual ones of the plurality of integrated circuits is attached to a second substrate such as another integrated circuit chip or printed circuit board. | 03-28-2013 |
20130078768 | NEST MECHANISM WITH RECESSED WALL SEGMENTS - A nest mechanism includes a 2-dimensional grid of support positions for supporting singulated electronic units. The support positions each include an inner opening and an outer horizontal base around the inner opening having a support surface that supports units thereon. A segmented wall arrangement is on the outer horizontal base located beyond an area of the unit for preventing movement of the unit while on the support surface. The segmented wall arrangement includes (i) a plurality of raised wall segments that extend to a first height above the support surface, and (ii) at least one recessed segment between the plurality of raised wall segments that has a height less than the first height. The recessed segment(s) help liquid-based washing processes to remove residue material generated by a sawing process that can become stuck under the units while in the nest mechanism awaiting transfer. | 03-28-2013 |
20130089954 | METHOD OF FABRICATING ELECTRONIC DEVICE HAVING FLEXIBLE DEVICE - There is provided a method of fabricating an electronic device having a flexible device, which is fabricated using a support substrate by Joule-heating induced film separation (JIFS). A method of fabricating an electronic device having a flexible device includes providing a support substrate, coating a conductive layer on one surface of the support substrate, forming a plastic substrate on the other surface of the support substrate, forming one or more thin-film transistors (TFTs) on the plastic substrate, forming an electronic device electrically connected to any one of the TFTs, and separating the plastic substrate from the conductive layer by generating Joule-heating through application of an electric field to the conductive layer. Accordingly, the flexible device can be separated from the support substrate without deformation of the support substrate and degradation of the electronic device. Since the separation time is short, it is easy to fabricate a large-area device, and the fabrication yield can be improved. | 04-11-2013 |
20130095612 | WAFER LEVEL PACKAGING METHOD OF ENCAPSULATING THE BOTTOM AND SIDE OF A SEMICONDUCTOR CHIP - A chip-scale packaging method, with bottom and side of a semiconductor chip encapsulated, includes the following steps: attaching backside of a thinned semiconductor wafer to a dicing tape; separating individual chips by cutting from front side of the wafer at scribe line but not cut through the dicing tape; flipping and attaching the wafer onto a top surface of a double-sided tape, then removing the dicing tape; attaching bottom surface of the double-sided tape on a supporting plate; filling the space between adjacent chips and covering the whole wafer backside with a molding material; flipping the whole structure and remove the supporting plate; placing solder balls at corresponding positions on electrodes of each chip and performing backflow treatment; finally separating individual chip packages by cutting through molding material at the space between adjacent chip packages with molding material encapsulating the bottom and side of each individual semiconductor chip. | 04-18-2013 |
20130095613 | FABRICATION METHOD OF SEMICONDUCTOR DEVICES AND FABRICATION SYSTEM OF SEMICONDUCTOR DEVICES - In aspects of the invention, a holding stage of a pick up system can include a first stage on which a semiconductor chip is mounted with an adhesive sheet put in between, a second stage supporting the first stage, and an evacuation pipe. The first stage can be provided with a plurality of grooves, projections each being formed with side walls of adjacent grooves, and air holes connected to the grooves. The semiconductor chip can be mounted on the first stage so that the whole end portion of the semiconductor chip does not position on one groove. Then, a closed space surrounded by the adhesive sheet and the first and second stages and can be evacuated to make the semiconductor chip held on the projections. Thereafter, the semiconductor chip can be picked up by a collet. | 04-18-2013 |
20130095614 | WAFER LEVEL PACKAGING OF SEMICONDUCTOR CHIPS - A method of manufacturing semiconductor packages at the wafer level is disclosed. A wafer has multiple integrated circuits (ICs) formed on its active surface, with each IC in communication with a plurality under-bump metallization (UBM) pads formed on one surface the package. The UBM pads include a larger pads near the center of package and smaller UBM pads near the periphery. The method includes attaching a stiffener to an inactive surface of the wafer; forming under bump metallization pads; and forming solder bumps extending from the UBM pads. | 04-18-2013 |
20130115736 | METHOD FOR SEPARATING A PLURALITY OF DIES AND A PROCESSING DEVICE FOR SEPARATING A PLURALITY OF DIES - A method for separating a plurality of dies is provided. The method may include: selectively removing one or more portions from a carrier including a plurality of dies, for separating the plurality of dies along the selectively removed one or more portions, wherein the one or more portions are located between the dies; and subsequently forming over a back side of the dies, at least one metallization layer for packaging the dies | 05-09-2013 |
20130130443 | METHOD FOR PACKAGING ULTRA-THIN CHIP WITH SOLDER BALL THERMO-COMPRESSION IN WAFER LEVEL PACKAGING PROCESS - The invention generally relates to a packaging method of an ultra-thin chip, more specifically, the invention relates to a method for packaging the ultra-thin chip with solder ball thermo-compression in wafer level packaging process. The method starts with disposing solder balls on metal pads arranged on the front surface of semiconductor chips that are formed at the front surface of a semiconductor wafer. The solder balls are soften by heating the wafer, a compression plate is applied with a pressure on the top ends of the solder balls thus forming a co-planar top surface at the top ends of the solder balls. A molding compound is deposited on the front surface of the wafer with the top ends of the solder balls exposed. The wafer is then ground from its back surface to reduce its thickness to achieve ultra-thin chip. | 05-23-2013 |
20130130444 | CHIP PACKAGE AND FABRICATION METHOD THEREOF - The invention is related to a chip package including: a semiconductor substrate having at least one bonding pad region and at least one device region, wherein the semiconductor substrate includes a plurality of heavily doped regions in the bonding pad region, and two of the heavily doped regions are insulatively isolated; a plurality of conductive pad structures disposed over the bonding pad region; at least one opening disposed at a sidewall of the chip package to expose the heavily doped regions; and a conductive pattern disposed in the opening to electrically contact with the heavily doped region. | 05-23-2013 |
20130137218 | UNDER-FILL MATERIAL AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - The present invention provides an under-fill material with which a semiconductor device having a high connection reliability can be provided while securing a usable material by reducing a difference in thermal-responsive behavior between a semiconductor element and an adherend, and a method for producing a semiconductor device using the under-fill material. In the under-fill material of the present invention, a storage elastic modulus E′ [MPa] and a thermal expansion coefficient α [ppm/K] after carrying out a heat-curing treatment at 175° C. for an hour satisfy the following formula (1) at 25° C.: | 05-30-2013 |
20130137219 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - There is provided a method for producing a semiconductor device, which is capable of suppressing voids during mounting of a semiconductor element to produce a semiconductor device with high reliability. A method for producing a semiconductor device of the present invention includes the steps of: providing a sealing sheet having a base material and an under-fill material laminated on the base material; bonding the sealing sheet to a surface of a semiconductor wafer on which a connection member is formed; dicing the semiconductor wafer to form a semiconductor element with the under-fill material; retaining the semiconductor element with the under-fill material at 100 to 200° C. for 1 second or more; and electrically connecting the semiconductor element and the adherend through the connection member while filling a space between the adherend and the semiconductor element with the under-fill material. | 05-30-2013 |
20130157414 | STACKED-DIE PACKAGE AND METHOD THEREFOR - Consistent with an example embodiment, there is a semiconductor device comprised of a combination of device die. The semiconductor device comprises a package substrate having groups of pad landings. A first device die is anchored to the package substrate, the first device die having been wire-bonded to a first group of pad landings. At least one subsequent device die is anchored to the first device die. The at least one subsequent device die has an underside profile with recesses defined therein, the recesses of a size are defined to accommodate wires bonded to the first device die; the at least one subsequent device is wire bonded to a second group of pad landings. | 06-20-2013 |
20130157415 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - There is provided a method for producing a semiconductor device, capable of suppressing generation of voids at an interface between a semiconductor element and an under-fill sheet to produce a semiconductor device with high reliability. The method includes providing a sealing sheet having a support and an under-fill material laminated on the support; thermally pressure-bonding a circuit surface of a semiconductor wafer, on which a connection member is formed, and the under-fill material of the sealing sheet under conditions of a reduced-pressure atmosphere of 10000 Pa or less, a bonding pressure of 0.2 MPa or more and a heat pressure-bonding temperature of 40° C. or higher; dicing the semiconductor wafer to form a semiconductor element with the under-fill material; and electrically connecting the semiconductor element and the adherend through the connection member while filling a space between the adherend and the semiconductor element using the under-fill material. | 06-20-2013 |
20130178017 | METHOD FOR MANUFACTURING SEMICONDUCTOR CHIPS FROM A SEMICONDUCTOR WAFER - A method for manufacturing semiconductor chips from a semiconductor wafer, including the steps of: fastening, on a first support frame, a second support frame having outer dimensions smaller than the outer dimensions of the first frame and greater than the inner dimensions of the first frame; arranging the wafer on a surface of a film stretched on the second frame; carrying out wafer processing operations by using equipment capable of receiving the first frame; separating the second frame from the first frame and removing the first frame; and carrying out wafer processing operations by using equipment capable of receiving the second frame. | 07-11-2013 |
20130189814 | Method for Fabricating Array-Molded Package-on-Package - a An improved semiconductor device package is manufactured by attaching semiconductor chips ( | 07-25-2013 |
20130196470 | CHIP PACKAGE AND FABRICATION METHOD THEREOF - A chip package includes a substrate having a pad region, a device region, and a remained scribe region located at a periphery of the substrate; a signal and an EMI ground pads disposed on the pad region; a first and a second openings penetrating into the substrate to expose the signal and the EMI ground pads, respectively; a first and a second conducting layers located in the first and the second openings and electrically connecting the signal and the EMI ground pads, respectively, wherein the first conducting layer and the signal pad are separated from a periphery of the remained scribe region, and wherein a portion of the second conducting layer and/or the EMI ground pad extend(s) to a periphery of the remained scribe region; and a third conducting layer surrounding the periphery of the remained scribe region to electrically connect the second conducting layer and/or the EMI ground pad. | 08-01-2013 |
20130217185 | POWER DEVICE MANUFACTURE ON THE RECESSED SIDE OF A THINNED WAFER - A recess is formed into a first side of a wafer such that a thinned center portion of the wafer is formed, and such that the central portion is surrounded by a thicker peripheral edge support portion. The second side of the wafer remains substantially entirely planar. After formation of the thinned wafer, vertical power devices are formed into the first side of the central portion of the wafer. Formation of the devices involves forming a plurality of diffusion regions into the first side of the thinned central portion. Metal electrodes are formed on the first and second sides, the peripheral portion is cut from the wafer, and the thin central portion is diced to form separate power devices. In one example, a first commercial entity manufactures the thinned wafers, and a second commercial entity obtains the thinned wafers and performs subsequent processing to form the vertical power devices. | 08-22-2013 |
20130217186 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING ELECTRONIC ASSEMBLY - A method of manufacturing a semiconductor device, includes: providing an adhesive layer on a support body; providing a semiconductor element on the adhesive layer; providing a resin layer on the adhesive layer, the semiconductor element being provided on the adhesive layer, and forming a substrate on the adhesive layer, the substrate including the semiconductor element and the resin layer; and removing the substrate from the adhesive layer, wherein an adhesive force of the adhesive layer in a direction in which the substrate is removed is less than an adhesive force of the adhesive layer in a planar direction in which the substrate is formed. | 08-22-2013 |
20130224910 | METHOD FOR CHIP PACKAGE - Provided is a method for chip packaging, including the steps of: providing a semi-packaged wafer which has a cutting trail and a metal bonding pad of the chip; forming on the metal bonding pad a sub-ball metal electrode, using a selective formation process; forming a protective layer on the wafer in a region not including the sub-ball metal electrode, with the protective layer covering the cutting trail; forming a solder ball on the sub-ball metal electrode; dicing the wafer along the cutting trail. The present invention can prevent metal in the cutting trail from being affected during the production of the sub-ball metal electrode, and protect the lateral sides of a discrete chip after cutting. The process flow thereof is simple, and enhances the efficiency of the packaging as well as its yield. | 08-29-2013 |
20130237015 | MICROFABRICATED PILLAR FINS FOR THERMAL MANAGEMENT - An electrical package with improved thermal management. The electrical package includes a die having an exposed back surface. The package further includes a plurality of fins extending outwardly from the back surface for dissipating heat from the package. The die can be arranged in a multi-die stacking configuration. In another embodiment, a method of forming a die for improved thermal management of an electrical package is provided. | 09-12-2013 |
20130237016 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device and manufacturing method are disclosed which prevent breakage and chipping of a semiconductor chip and improve device characteristics. A separation layer is in a side surface of an element end portion of the chip. An eave portion is formed by a depressed portion in the element end portion. A collector layer on the rear surface of the chip extends to a side wall and bottom surface of the depressed portion, and is connected to the separation layer. A collector electrode is over the whole surface of the collector layer, and is on the side wall of the depressed portion. The thickness of an outermost electrode film is 0.05 μm or less. The collector electrode on the rear surface of the chip is joined onto an insulating substrate via a solder layer, which covers the collector electrode on a flat portion of the rear surface of the semiconductor chip. | 09-12-2013 |
20130244376 | FULLY MOLDED FAN-OUT - A method for manufacturing a device package may include constructing a spacer element coupled with a surface of a semiconductor die unit, where the spacer element is configured to create a gap between the semiconductor die unit and a surface of a carrier, and encapsulating the semiconductor die unit within a mold compound, where the encapsulating includes introducing the mold compound into the gap. | 09-19-2013 |
20130273694 | Integrated Thermal Solutions for Packaging Integrated Circuits - A method includes attaching a wafer on a carrier through an adhesive, and forming trenches in the carrier to convert the carrier into a heat sink. The heat sink, the carrier, and the adhesive are sawed into a plurality of packages. | 10-17-2013 |
20130288433 | HIGH DENSITY CHIP PACKAGES, METHODS OF FORMING, AND SYSTEMS INCLUDING SAME - Methods and devices for multi-chip stacks are shown. A method is shown that assembles multiple chips into stacks by stacking wafers prior to dicing into individual chips. Methods shown provide removal of defective chips and their replacement during the assembly process to improve manufacturing yield. | 10-31-2013 |
20130302944 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING TERMINALS WITH INTERNAL ROUTING INTERCONNECTIONS - A method of fabricating a semiconductor package includes forming a plurality of terminals on a sheet carrier, molding the sheet carrier with a first molding compound, creating electrical paths for a first routing layer, plating the first routing layer, placing dice on the first routing layer, encapsulating the dice with a second molding compound, removing at least a portion of the sheet carrier, and singulating the package from other packages. | 11-14-2013 |
20130302945 | SINGULATION OF IC PACKAGES - A method of dividing a two dimensional array of encapsulated integrated circuits into individual integrated circuit packages uses a first series of parallel cuts ( | 11-14-2013 |
20130302946 | MULTI-LAYER LEAD FRAME PACKAGE AND METHOD OF FABRICATION - The present invention features a method for fabricating a lead-frame package, having a first, second, third and fourth electrically conductive structures with a pair of semiconductor dies disposed therebetween defining a stacked structure. The first and second structures are spaced-apart from and in superimposition with the first structure. A semiconductor die is disposed between the first and second structures. The semiconductor die has contacts electrically connected to the first and second structures. A part of the third structure lies in a common plane with a portion of the second structure. The third structure is coupled to the semiconductor die. | 11-14-2013 |
20130316497 | THREE DIMENSIONAL MICROELECTRONIC COMPONENTS AND FABRICATION METHODS FOR SAME - Aspects and examples include electrical components and methods of forming electrical components. In one example, a method includes selecting a substrate, forming a pattern of a first conductive material on a top surface of the substrate, forming a pattern of a second conductive material on a bottom surface of the substrate, dicing the substrate into one or more die having a first diced surface and a second diced surface, securing the first diced surface of each of the one or more die to a retaining material, encapsulating the one or more die in an encapsulent to form a reconstituted wafer, and forming a pattern of a third conductive material on the second diced surface by metalizing a surface of the reconstituted wafer. | 11-28-2013 |
20130316498 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING INSULATED GATE BIPOLAR TRANSISTOR AND DIODE - In a method of manufacturing a semiconductor device, a semiconductor substrate of a first conductivity type having first and second surfaces is prepared. Second conductivity type impurities for forming a collector layer are implanted to the second surface using a mask that has an opening at a portion where the collector layer will be formed. An oxide layer is formed by enhanced-oxidizing the collector layer. First conductivity type impurities for forming a first conductivity type layer are implanted to the second surface using the oxide layer as a mask. A support base is attached to the second surface and a thickness of the semiconductor substrate is reduced from the first surface. An element part including a base region, an emitter region, a plurality of trenches, a gate insulating layer, a gate electrode, and a first electrode is formed on the first surface of the semiconductor substrate. | 11-28-2013 |
20130323884 | THREE DIMENSIONAL MICROELECTRONIC COMPONENTS AND FABRICATION METHODS FOR SAME - Aspects and examples include electrical components and methods of forming electrical components. In one example, a method includes selecting a substrate, forming a pattern of a first conductive material on a top surface of the substrate, forming a pattern of a second conductive material on a bottom surface of the substrate, dicing the substrate into one or more die having a first diced surface and a second diced surface, securing the first diced surface of each of the one or more die to a retaining material, encapsulating the one or more die in an encapsulent to form a reconstituted wafer, and forming a pattern of a third conductive material on the second diced surface by metalizing a surface of the reconstituted wafer. | 12-05-2013 |
20130330880 | THREE DIMENSIONAL FLIP CHIP SYSTEM AND METHOD - Solder is simultaneously transferred from a mold to a plurality of 3D assembled modules to provide solder bumps on the modules. The mold includes cavities containing injected molten solder or preformed solder balls. A fixture including resilient pressure pads and vacuum lines extending through the pads applies pressure to the modules when they are positioned on the mold. Following reflow and solder transfer to the modules, the fixture is displaced with respect to the mold. The modules, being attached to the fixture by vacuum pressure through the pads, are displaced from the mold with the fixture. | 12-12-2013 |
20130337609 | LEAD FRAME LAND GRID ARRAY WITH ROUTING CONNECTOR TRACE UNDER UNIT - A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package. | 12-19-2013 |
20130337610 | METHOD OF FABRICATING ELECTRONIC COMPONENT - A method of fabricating an electronic component includes: mounting a device chip on an upper surface of an insulative substrate; forming a sealing portion that seals the device chip; cutting the insulative substrate and the sealing portion; and forming a plated layer covering the sealing portion by barrel plating. | 12-19-2013 |
20130337611 | Thermally Enhanced Semiconductor Package with Conductive Clip - One exemplary disclosed embodiment comprises a semiconductor package including an inside pad, a transistor, and a conductive clip coupled to the inside pad and a terminal of the transistor. A top surface of the conductive clip is substantially exposed at the top of the package, and a side surface of the conductive clip is exposed at a side of the package. By supporting the semiconductor package on an outside pad during the fabrication process and by removing the outside pad during singulation, the conductive clip may be kept substantially parallel and in alignment with the package substrate while optimizing the package form factor compared to conventional packages. The exposed top surface of the conductive clip may be further attached to a heat sink for enhanced thermal dissipation. | 12-19-2013 |
20130344656 | METHOD OF MAKING SURFACE MOUNT STACKED SEMICONDUCTOR DEVICES - A method of assembling semiconductor devices includes providing a structure that includes an array of conductive frame members beside an array of apertures and an array of conductive vias that are exposed at a first face and extend towards a second face. An array of semiconductor dies is positioned in the array of apertures with their active faces positioned in the first face of the structure. The assembly is encapsulated from the second face of the structure and a redistribution layer is formed on the first face of the structure and the active faces of the die. Material is removed from the back face of the encapsulated array to expose the vias at the back face for connection through a further redistribution layer formed on the back face to electronic components stacked vertically on the further redistribution layer. | 12-26-2013 |
20130344657 | PACKAGE ASSEMBLY USING A CARRIER-FREE TECHNIQUE - In an example embodiment, there is method for assembling semiconductor devices, the method comprises providing a temporary carrier having a plurality device die locations and a boundary edge. Surrounding the device die locations, electrical connection pads are applied. Device die in the plurality of device die locations are mounted; the device die have pad landings electrically coupled to active components with the device die. The pad landings of the device die are wire bonded to corresponding electrical connection pads. With the molding compound flowing to the boundary edge of the temporary carrier, the device die are encapsulated. In a particular example embodiment, the electrical connection pads may be ball bonds. | 12-26-2013 |
20130344658 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes: preparing a semiconductor wafer including a plurality of semiconductor chips arranged in the shape of a matrix, the semiconductor wafer having a first bump electrode formed on one face thereof; forming a depressed portion on a first face of the semiconductor wafer, the depressed portion partitioning the semiconductor wafer into respective semiconductor chips; placing the first face of the semiconductor wafer onto a support tape; and cutting the semiconductor wafer along the depressed portion from a second face opposite to the first face of the semiconductor wafer by the use of a dicing blade having a width smaller than the width of the depressed portion to thereby divide the semiconductor wafer into a plurality of semiconductor chips. | 12-26-2013 |
20140011325 | METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE - A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a substrate, a semiconductor element, a package body and a conductive part. The substrate has an electrical contact. The semiconductor element is disposed on the substrate. The package body covers the semiconductor element and defines a through hole from which the electrical contact is exposed. Wherein, the package body includes a resin body and a plurality of fiber layers. The fiber layers are disposed in the resin body and define a plurality of fiber apertures which is arranged as an array. The conductive part is electrically connected to the substrate through the through hole. | 01-09-2014 |
20140017854 | CHIP PACKAGE AND FABRICATION METHOD THEREOF - A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package contains a semiconductor substrate having a chip. A packaging layer is disposed over the semiconductor substrate. A spacer is disposed between the semiconductor substrate and the packaging layer, wherein a side surface consisting of the semiconductor substrate, the spacer and the packaging layer has a recess section. The method includes forming a plurality of spacers between a plurality of chips of a semiconductor wafer and a packaging layer, wherein each spacer corresponding to each chip is separated from each other and the spacer is shrunk inward from an edge of the chip to form a recess section and dicing the semiconductor wafer along a scribe line between any two adjacent chips to form a plurality of chip packages. | 01-16-2014 |
20140030850 | PACKAGE SUBSTRATE PROCESSING METHOD - A package substrate processing method of dividing a package substrate into a plurality of individual package devices along a plurality of division lines, the package substrate being composed of an electrode plate and a synthetic resin layer formed on the back side of the electrode plate for molding the package devices. The package substrate processing method includes an internal stress relieving step of cutting the electrode plate of the package substrate along a selected one of the division lines to form a relief groove, thereby relieving an internal stress in the package substrate, a resin layer planarizing step of grinding the synthetic resin layer of the package substrate to thereby planarize the synthetic resin layer, and a package substrate dividing step of dividing the package substrate held on a holding table under suction along the division lines. | 01-30-2014 |
20140030851 | Method for Fabricating Array-Molded Package-on-Package - An improved method for fabricating a semiconductor device provides a mold having a top portion and a bottom portion. The top portion includes recesses suitable for a cavity and a plurality of protrusions shaped as truncated cones. A thin sheet of compliant inert polymer is placed over the surface of the top portion. A molding compound is introduced into the cavity to form a encapsulation body covering a semiconductor chip and linear arrays of contact pads adjacent to the chip. Each conical protrusion matches a contact pad location. The thin sheet of compliant inert polymer is peeled off the top portion. The mold is opened and the encapsulated semiconductor chip is removed. | 01-30-2014 |
20140038356 | METHOD FOR PLATING A SEMICONDUCTOR PACKAGE LEAD - A method of forming a packaged semiconductor device includes loading an array of package sites in position for saw singulation, saw singulating the array of package sites, and performing a non-electrolytic plating operation on exposed lead tips of individual packages from the array of package sites as the array of package sites is saw singulated. | 02-06-2014 |
20140038357 | SINGULATED IC STIFFENER AND DE-BOND PROCESS - A method and apparatus is described for forming and using a stiffener for the production of thinned integrated circuits. In one embodiment, a handle can be bonded to an integrated circuit wafer before the wafer is thinned. Electrical couplings such as mounting balls can be attached to the wafer. Individual dice can be singulated from the wafer by dicing through the wafer and the handle, producing a wafer/handle assembly. The wafer/handle assembly can be mounted to a printed circuit board before the handle is de-bonded. | 02-06-2014 |
20140038358 | METHOD FOR CONTACTING AGGLOMERATE TERMINALS OF SEMICONDUCTOR PACKAGES - In fabricating a semiconductor device first layers are formed of sintered bondable and solderable metal on a carrier strip. The first layers are patterned into first pads and second pads. A set of first pads is surrounding each second pad. The first pads are spaced from the second pad by gaps. The patterned layers are formed of agglomerate metal vertically on the first layers of sintered bondable and solderable metal of the first pads and of the second pad. The second layers are formed of sintered bondable and solderable metal vertically on the layers of agglomerate metal of the first pads | 02-06-2014 |
20140038359 | Laser-Assisted Cleaving of a Reconstituted Wafer for Stacked Die Assemblies - A method of forming stacked die devices includes attaching first semiconductor die onto a wafer to form a reconstituted wafer, and then bonding second semiconductor die onto the first semiconductor die to form a plurality of singulated stacked die devices on the wafer. A support tape is attached to a bottomside of the second semiconductor die. A dicing tape is attached to the wafer. The wafer is laser irradiated before or after attachment of the dicing tape at intended dicing lanes that align with gaps between the first semiconductor die to mechanically weaken the wafer at the intended dicing lanes, but not cut through the wafer. The dicing tape is pulled to cleave the wafer into a plurality of singulated portions to form a plurality of singulated stacked die devices attached to the singulated wafer portions by the dicing tape. The support tape is removed prior to cleaving. | 02-06-2014 |
20140038360 | Apparatus and Methods for Molding Die on Wafer Interposers - Methods and apparatus for performing molding on die on wafer interposers. A method includes receiving an interposer assembly having a die side and an opposite side including two or more integrated circuit dies mounted on the die side of the interposer, the interposer assembly having spaces formed on the die side of the interposer between the two or more integrated circuit dies; mounting at least one stress relief feature on the die side of the interposer assembly in one of the spaces between the two or more integrated circuit dies; and molding the integrated circuit dies using a mold compound, the mold compound surrounding the two or more integrated circuit dies and the at least one stress relief feature. An apparatus is disclosed having integrated circuits mounted on a die side of an interposer, stress relief features between the integrated circuits and mold compound over the integrated circuits. | 02-06-2014 |
20140057393 | Semiconductor Device Package and Methods of Packaging Thereof - In one embodiment of the present invention, a method of forming a semiconductor device includes forming a device region in a first region of a semiconductor substrate, and forming an opening in a second region of the semiconductor substrate. The method further includes placing a semiconductor die within the opening, and forming a first metallization level over the semiconductor die and the device region. | 02-27-2014 |
20140057394 | METHOD FOR MAKING A DOUBLE-SIDED FANOUT SEMICONDUCTOR PACKAGE WITH EMBEDDED SURFACE MOUNT DEVICES, AND PRODUCT MADE - A manufacturing process includes forming a reconstituted wafer, including embedding semiconductor dice in a molding compound layer and forming through-wafer vias in the layer. A fan-out redistribution layer is formed on a front side of the wafer, with electrical traces interconnecting the dice, through-wafer vias, and contact pads positioned on the redistribution layer. Solder balls are positioned on the contact pads and a molding compound layer is formed on the redistribution layer, reinforcing the solder balls. A second fan-out redistribution layer is formed on a back side of the wafer, with electrical traces interconnecting back ends of the through-wafer vias and contact pads positioned on a back face of the second redistribution layer. Flip-chips and/or surface-mounted devices are coupled to the contact pads of the second redistribution layer and encapsulated in an underfill layer formed on the back face of the second redistribution layer. | 02-27-2014 |
20140057395 | SEMICONDUCTOR HOUSING AND METHOD FOR THE PRODUCTION OF A SEMICONDUCTOR HOUSING - A semiconductor housing is provided that includes a metal support and a semiconductor body, a bottom side thereof being connected to the metal support. The semiconductor body has metal surfaces that are connected to pins by bond wires and a plastic compound, which completely surrounds the bond wires and partially surrounds the semiconductor body. The plastic compound has an opening on the top side of the semiconductor body, and a barrier is formed on the top side of the semiconductor body. The barrier has a top area and a base area spaced from the edges of the semiconductor body and an internal clearance of the barrier determines a size of the opening. Whereby, a portion of the plastic compound has a height greater than the barrier, and a fixing layer is formed between the base area of the barrier and the top side of the semiconductor body. | 02-27-2014 |
20140065768 | METHOD FOR PROCESSING A WAFER AND METHOD FOR DICING A WAFER - In various embodiments, a method for processing a wafer may include: providing a wafer having at least one die region and at least one metallization disposed over the at least one die region; covering the at least one metallization with a protecting layer; plasma etching the wafer to form at least one die. | 03-06-2014 |
20140065769 | CHIP PACKAGE AND FABRICATION METHOD THEREOF - An embodiment of the invention provides a chip package, which includes: a semiconductor substrate having a device region; a package layer disposed on the semiconductor substrate; a spacing layer disposed between the semiconductor substrate and the package layer and surrounding the device region; and an auxiliary pattern having a hollow pattern formed in the spacing layer, a material pattern located between the spacing layer and the device region, or combinations thereof. | 03-06-2014 |
20140087521 | WAFER LEVEL CHIP SCALE PACKAGING - An improved wafer level chip scale packaging technique is described which does not use an encapsulated via to connect between a redirection layer and a pad within the pad ring on the semiconductor die. In an embodiment, a first dielectric layer is formed such that it terminates on each die within the die's pad ring. Tracks are then formed in a conductive layer which contact one of the pads and run over the edge of an opening onto the surface of the first dielectric layer. These tracks may be used to form an electrical connection between the pad and a solder ball. | 03-27-2014 |
20140113412 | CHIP PACKAGE AND FABRICATION METHOD THEREOF - An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a chip protection layer or an additional etching stop layer to cover conducting pads to prevent dicing residue from damaging or scratching the conducting pads. According to another embodiment, a chip protection layer, an additional etching stop layer formed thereon, or a metal etching stop layer level with conducting pads or combinations thereof may be used when etching an intermetal dielectric layer at a structural etching region and a silicon substrate to form an opening for subsequent semiconductor manufacturing processes. | 04-24-2014 |
20140127862 | METHOD OF ASSEMBLING SEMICONDUCTOR DEVICE INCLUDING INSULATING SUBSTRATE AND HEAT SINK - Semiconductor dies are mounted on a heat sink array frame structure. The heat sink array frame structure and the semiconductor dies are assembled together with an insulating substrate that has a corresponding array of apertures on an adhesive tape. The semiconductor dies are connected electrically with electrical contacts on the insulating substrate. The semiconductor dies, heat sinks and electrical connections to the contacts are encapsulated with a mold compound and then the encapsulated array is de-taped and singulated. | 05-08-2014 |
20140134800 | Methods For Temporary Wafer Molding For Chip-On-Wafer Assembly - Methods for temporary wafer molding for chip-on-wafer assembly may include bonding one or more semiconductor die to an interposer wafer, applying a temporary mold material to encapsulate the bonded die, and backside processing the interposer, which may be singulated to generate assemblies comprising the bonded die, the interposer die, which may be bonded to packaging substrates. The temporary mold material may be removed and the bonded die may be tested. Additional die may be bonded to the assemblies based on the electrical testing. The interposer may be singulated utilizing one or more of: a laser cutting process, reactive ion etching, a sawing technique, and a plasma etching process. The backside processing may comprise thinning the interposer wafer to expose through-silicon-vias (TSVs) and placing metal contacts on the exposed TSVs. The die may be bonded to the interposer utilizing a mass reflow or thermal compression process. | 05-15-2014 |
20140134801 | Methods for Fabricating Integrated Passive Devices on Glass Substrates - A method includes forming a plurality of dielectric layers over a semiconductor substrate; and forming integrated passive devices in the plurality of dielectric layers. The semiconductor substrate is then removed from the plurality of dielectric layers. A dielectric substrate is bonded onto the plurality of dielectric layers. | 05-15-2014 |
20140134802 | Chip-on-Wafer Structures and Methods for Forming the Same - A package component includes a substrate, wherein the substrate has a front surface and a back surface over the front surface. A through-via penetrates through the substrate. A conductive feature is disposed over the back surface of the substrate and electrically coupled to the through-via. A first dielectric pattern forms a ring covering edge portions of the conductive feature. An Under-Bump-Metallurgy (UBM) is disposed over and in contact with a center portion of the conductive feature. A polymer contacts a sidewall of the substrate. A second dielectric pattern is disposed over and aligned to the polymer. The first and the second dielectric patterns are formed of a same dielectric material, and are disposed at substantially a same level. | 05-15-2014 |
20140154842 | CARRIER, SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided. | 06-05-2014 |
20140162407 | Method And System For Semiconductor Packaging - Methods and systems for semiconductor packaging are disclosed and may include bonding a semiconductor wafer to a support structure, separating the wafer into discrete die, removing the die from the support structure, and attaching at least a subset of the die to a second support structure. Mold material may be placed in voids between the die utilizing a compression molding process, thereby generating a molded wafer, which may be demounted before depositing redistribution lines on the die and the mold material. Conductive balls may be placed on the redistribution lines before separating into molded packages. The molded wafer may be planarized utilizing a post-mold cure on a heated vacuum chuck after removing it from the second support structure. The redistribution lines may be electrically isolated utilizing polymer layers. The conductive balls may be placed on copper redistribution lines with a surface oxide layer at least 20 angstroms thick. | 06-12-2014 |
20140162408 | METHOD AND APPARATUS FOR DIVIDING A THIN FILM DEVICE INTO SEPARATE CELLS - A method for dividing a thin film device having a first lower electrode layer, a second active layer and a third upper electrode layer, all three layers being continuous over the device, into separate cells which are to be electrically interconnected in series, at least the dividing of the cells being carried out in a single pass of a process head across the device, the process head performing at least the following steps in the single pass: a) making a first cut through the first, second and third layers; b) making a second cut through the second and third layers, the second cut being adjacent to the first cut; c) making a third cut through the third layer, the third cut being adjacent to the second cut and on the opposite side of the second cut to the first cut; wherein at least one of the first and second cuts is formed using two laser beams sequentially during the single pass of the process head across the device, the first laser beam forming a cut through at least one of the layers and the second laser beam forming a cut through at least one other of the layers. | 06-12-2014 |
20140179062 | Isolation Rings for Packages and the Method of Forming the Same - A device includes a first package component, and a second package component underlying, and bonded to, the first package component. A molding material is disposed under the first package component and molded to the first and the second package components, wherein the molding material and the first package component form an interface. An isolation region includes a first edge, wherein the first edge of the isolation region contacts a first edge of the first package component and a first edge of the molding material. The isolation has a bottom lower than the interface. | 06-26-2014 |
20140179063 | RESIN SEALING TYPE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND LEAD FRAME - The invention is directed to firm bonding between semiconductor dies etc bonded to a lead frame and wire-bonding portions of the lead frame by ultrasonic Al wire bonding, and the prevention of shortcircuit between the semiconductor dies etc due to a remaining portion of the outer frame of the lead frame after the outer frame is cut. By extending the wire-bonding portion etc on the lead frame in a wire-bonding direction and connecting the wire-bonding portion etc to the outer frame of the lead frame through a connection lead etc, the ultrasonic vibration force in the ultrasonic Al wire bonding is prevented from dispersing and the Al wire and the wire-bonding portion etc are firmly bonded. The outer frame is cut after a resin sealing process is completed. Even when a portion of the outer frame remains on the side surface of the resin package, connection between the connection lead etc and other hanging lead etc are prevented by providing a notch etc in the outer frame between the connection lead etc and the hanging lead etc. | 06-26-2014 |
20140206146 | FABRICATION METHOD OF SEMICONDUCTOR PACKAGE HAVING ELECTRICAL CONNECTING STRUCTURES - A semiconductor package having electrical connecting structures includes: a conductive layer having a die pad and traces surrounding the die pad; a chip; bonding wires; an encapsulant with a plurality of cavities having a depth greater than the thickness of the die pad and traces for embedding the die pad and the traces therein, and the cavities exposing the die pad and the traces; a solder mask layer formed in the cavities and having a plurality of openings for exposing the trace ends and a portion of the die pad; and solder balls formed in the openings and electrically connected to the trace ends. Engaging the solder mask layer with the encapsulant enhances adhesion strength of the solder mask layer so as to prolong the moisture permeation path and enhance package reliability. | 07-24-2014 |
20140206147 | STACKED MICROELECTRONIC ASSEMBLY WITH TSVS FORMED IN STAGES AND CARRIER ABOVE CHIP - A microelectronic assembly is provided which includes a first element consisting essentially of at least one of semiconductor or inorganic dielectric material having a surface facing and attached to a major surface of a microelectronic element at which a plurality of conductive pads are exposed, the microelectronic element having active semiconductor devices therein. A first opening extends from an exposed surface of the first element towards the surface attached to the microelectronic element, and a second opening extends from the first opening to a first one of the conductive pads, wherein where the first and second openings meet, interior surfaces of the first and second openings extend at different angles relative to the major surface of the microelectronic element. A conductive element extends within the first and second openings and contacts the at least one conductive pad. | 07-24-2014 |
20140220739 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device includes: a semiconductor substrate; a heat sink mounted on an upper surface of the semiconductor substrate; wirings formed on a lower surface of the semiconductor substrate; and the like. The heat sink is mounted on the upper surface of the semiconductor substrate, and a planar size thereof is approximately the same as that of the semiconductor substrate. Moreover, the heat sink has a thickness of 500 μm to 2 mm, and may be formed to be thicker than the semiconductor substrate. By using the heat sink to reinforce the substrate, a thickness of the semiconductor substrate can be reduced to, for example, about 50 μm. As a result, a thickness of the entire semiconductor device can be reduced. | 08-07-2014 |
20140220740 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE AND MULTILAYER WAFER STRUCTURE - Grooves are formed on the front surfaces of first and second semiconductor wafers each including an aggregate of a plurality of semiconductor chips. The grooves each extend on a dicing line set between the semiconductor chips and to have a larger width than the dicing line. Thereafter the first and second semiconductor wafers are arranged so that the front surfaces thereof are opposed to each other, and the space between the first semiconductor wafer and the second semiconductor wafer is sealed with underfill. Thereafter the rear surfaces of the first and second semiconductor wafers are polished until at least the grooves are exposed, and a structure including the first and second semiconductor wafers and the underfill is cut on the dicing line. | 08-07-2014 |
20140220741 | STACKED STRUCTURES AND METHODS OF FORMING STACKED STRUCTURES - A stacked structure includes a first die bonded over a second die. The first die has a first die area defined over a first surface. At least one first protective structure is formed over the first surface, around the first die area. At least one side of the first protective structure has at least one first extrusion part extending across a first scribe line around the protective structure. The second die has a second die area defined over a second surface. At least one second protective structure is formed over the second surface, around the second die area. At least one side of the second protective structure has at least one second extrusion part extending across a second scribe line around the protective structure, wherein the first extrusion part is connected with the second extrusion part. | 08-07-2014 |
20140242756 | METHOD FOR PREPARING SEMICONDUCTOR DEVICES APPLIED IN FLIP CHIP TECHNOLOGY - A method for preparing semiconductor devices in a flip chip process comprises forming deep grooves surrounding each of the semiconductor chips; depositing a first plastic package material to form a first plastic package layer covering front surface of the semiconductor wafer and filling the deep grooves; depositing a metal layer at back surface of the semiconductor wafer after grinding; grinding an outermost portion of the metal layer thus forming a ring area located at back surface around edge of the semiconductor wafer not covered by the metal layer; cutting the first plastic package layer, the semiconductor wafer, the metal layer and the first plastic package material filled in the deep grooves along a straight line formed by two ends of each of the deep grooves filled with the first plastic package material; and picking up the semiconductor devices and mounting on a substrate without flipping the semiconductor devices. | 08-28-2014 |
20140242757 | ADHESIVE FOR ELECTRONIC COMPONENT - An adhesive composition for a pre-applied underfill sealant comprising: (a) a radical polymerizable monomer having one or more functional groups selected from the group consisting of vinyl group, maleimide group, acryloyl group, methacryloyl group and allyl group, (b) a polymer having a polar group, (c) a filler, and (d) a thermal radical initiator. | 08-28-2014 |
20140242758 | WAFER AND METHOD FOR FORMING THE SAME - A wafer and a method for forming the same are disclosed. The wafer forming method can separate respective chips from others by performing a Deep Reactive Ion Etching (DRIE) process on a wafer including a plurality of chips. The wafer includes a plurality of chips configured to be arranged in row and column directions on the wafer, a scribe line configured to be formed among the plurality of chips so as to separate each chip, and an align key line configured to be formed in one side of the wafer so as to form an align key pattern. | 08-28-2014 |
20140248744 | SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method for manufacturing a semiconductor device, which prevents waste generation from being caused peeling of films and prevents failure of peeling from being caused by waste due to peeling of films. A first semiconductor substrate is used which has a structure in which a peeling layer is not formed in a section subjected to a first dividing treatment, so that the peeling layer is not exposed at the end surface of a second semiconductor substrate when the second semiconductor substrate is cut out of the first semiconductor substrate. In addition, a supporting material is provided on a layer to be peeled of the second semiconductor substrate before the second semiconductor substrate is subjected to a second dividing treatment. | 09-04-2014 |
20140287554 | METHOD FOR PLATING A SEMICONDUCTOR PACKAGE LEAD - A method of forming a packaged semiconductor device includes loading an array of package sites in position for saw singulation, saw singulating the array of package sites, and performing a non-electrolytic plating operation on exposed lead tips of individual packages from the array of package sites as the array of package sites is saw singulated. | 09-25-2014 |
20140287555 | SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR CONSTRUCT INSTALLED ON BASE PLATE, AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes a semiconductor construct including a semiconductor substrate and an external connection electrode provided to protrude on a surface of the semiconductor substrate, a base plate on which the semiconductor construct is installed, and a sealing layer stacked on the semiconductor substrate except for the external connection electrode and on the base plate including a side surface of the semiconductor substrate. | 09-25-2014 |
20140302641 | STIFFENED SEMICONDUCTOR DIE PACKAGE - A stiffened semiconductor die package has a semiconductor die including an integrated circuit. The die has an active side with die bonding pads and an opposite inactive side. A conductive frame that acts as a ground plane surrounds all edges of the die and a mold compound covers the conductive frame and the edges of the die. A thermally conductive sheet is attached to the inactive side of the die. A dielectric support structure with external connector pads with solder deposits is attached to the active side of the die. The external connector pads are selectively electrically coupled to the die bonding pads. | 10-09-2014 |
20140308778 | HEAT DISSIPATING SEMICONDUCTOR DEVICE PACKAGES AND RELATED METHODS - An embodiment of a method for making semiconductor device packages includes a heat sink matrix and a substrate. A plurality of semiconductor devices is attached to the substrate. Then, a package body is formed between the heat sink matrix and the substrate, wherein the package body encapsulates the semiconductor devices. Then, a plurality of first cutting slots is formed, wherein the first cutting slots extend through the heat sink matrix and partially extend into the package body. Then, a plurality of second cutting slots is formed, wherein the second cutting slots extend through the substrate and through the package body to the first cutting slot, thereby singulating the heat sink matrix and substrate into a plurality of individual semiconductor device packages. | 10-16-2014 |
20140315351 | FABRICATION METHOD OF SEMICONDUCTOR PACKAGE WITHOUT CHIP CARRIER - A semiconductor package without a chip carrier formed thereon and a fabrication method thereof. A metallic carrier is half-etched to form a plurality of grooves and metal studs corresponding to the grooves. The grooves are filled with a first encapsulant and a plurality of bonding pads are formed on the metal studs. The first encapsulant is bonded with the metal studs directly. Each of the bonding pads and one of the metal studs corresponding to the bonding pad form a T-shaped structure. Therefore, bonding force between the metal studs and the first encapsulant is enhanced such that delamination is avoided. Die mounting, wire-bonding and molding processes are performed subsequently. Since the half-etched grooves are filled with the first encapsulant, the drawback of having pliable metallic carrier that makes transportation difficult to carry out as encountered in prior techniques is overcome, and the manufacturing cost is educed by not requiring the use of costly metals as an etching resist layer. | 10-23-2014 |
20140322867 | CONDUCTIVE VIA STRUCTURES FOR ROUTING POROSITY AND LOW VIA RESISTANCE, AND PROCESSES OF MAKING - An integrated circuit structure includes a first conductive layer (MET4) including a first forked conductive structure ( | 10-30-2014 |
20140335658 | SEMICONDUCTOR DEVICE AND METHOD OF LAND GRID ARRAY PACKAGING WITH BUSSING LINES - A semiconductor device and method of making a semiconductor device is described. An embedded die panel comprising a plurality of semiconductor die separated by saw streets is provided. A conductive layer is formed by an electroless plating process, the conductive layer comprising bussing lines disposed in the saw streets and a redistribution layer (RDL) coupled to the semiconductor die and bussing lines. An insulating layer is formed over the conductive layer and embedded die panel, the insulating layer comprising openings disposed over the conductive layer outside a footprint of the semiconductor die. Interconnect structures are formed in the openings in the insulating layer by using the conductive layer as part of an electroplating process. The embedded die panel is singulated through the saw streets after forming the interconnect structures to remove the bussing lines and to from individual fan-out wafer level packages (FOWLPs). | 11-13-2014 |
20140335659 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor chip including a first surface, a second surface and a first terminal arranged on the first surface, a second semiconductor chip including a first surface, a second surface and a second terminal arranged on the first surface of the second semiconductor chip, a support substrate including a first surface bonded to the second surfaces of the first semiconductor chip and the second semiconductor chip, and an isolation groove formed on the first surface of the support substrate. The isolation includes a pair of side surfaces continuously extending from opposing side surfaces of the first semiconductor chip and the second semiconductor chip, respectively, and the isolation groove is formed into the support substrate to extend from the first surface of the support substrate. The isolation groove has a depth less than a thickness of the support substrate. | 11-13-2014 |
20140342505 | FABRICATION METHOD OF SEMICONDUCTOR PACKAGE - A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a carrier; disposing at least a semiconductor element on the carrier; forming an encapsulant on the carrier and the semiconductor element for encapsulating the semiconductor element; removing the carrier; disposing a pressure member on the encapsulant; and forming an RDL structure on the semiconductor element and the encapsulant, thereby suppressing internal stresses through the pressure member so as to mitigate warpage on edges of the encapsulant. | 11-20-2014 |
20140357023 | SEMICONDUCTOR DEVICE PACKAGE WITH CAP ELEMENT - A method of assembling a semiconductor device includes providing a substrate having an array of substrate elements linked by substrate corner elements and separated by slots extending between the corner elements. Semiconductor dies are positioned on the substrate elements. A cap, frame and contact structure is provided that has a corresponding array of caps supported by corner legs linking the caps to frame corner elements, frame elements linking the frame corner elements, and sets of electrical contact elements supported by the frame elements. The cap, frame and contact structure is fitted on the substrate with the caps extending over corresponding dies, the frame corner elements extending over the substrate corner elements, and the sets of electrical contact elements disposed in the slots. The dies are connected electrically with the electrical contact elements and the assembly is encapsulated and singulated. Singulating removes the frame elements. | 12-04-2014 |
20140370659 | SINGULATION APPARATUS AND METHOD - A singulation apparatus includes a carrier having a plurality of singulation sites and a scribe line between each of the plurality of singulation sites and an adjacent singulation site. The carrier has a top surface configured to receive a semiconductor substrate thereon. Each of the plurality of singulation sites includes a deformable portion and at least one vacuum hole. The at least one vacuum hole and the deformable portion is configured to form a seal around the at least one vacuum holes when a force is applied. The present disclosure further includes a method of manufacturing semiconductor devices, especially for a singulation process. | 12-18-2014 |
20140377909 | SEMICONDUCTOR PACKAGES HAVING THROUGH ELECTRODES AND METHODS FOR FABRICATING THE SAME - Semiconductor packages having through electrodes and methods for fabricating the same are provided. The method may comprise providing a first substrate including a first circuit layer, forming a front mold layer on a front surface of the first substrate, grinding a back surface of the first substrate, forming a first through electrode that penetrates the first substrate to be electrically connected to the first circuit layer, providing a second substrate on the back surface of the first substrate, the second substrate including a second circuit layer that is electrically connected to the first through electrode, forming a back mold layer on the back surface of the first substrate, the back mold layer encapsulating the second substrate, and removing the front mold layer. | 12-25-2014 |
20150024550 | METHODS FOR PRODUCING SEMICONDUCTOR DEVICES - A method for producing a semiconductor device in accordance with various embodiments may include providing a semiconductor workpiece attached to a first carrier; dicing the semiconductor workpiece and the carrier so as to form at least one individual semiconductor chip; mounting the at least one semiconductor chip with a side facing away from the carrier, to an additional carrier. | 01-22-2015 |
20150024551 | SEMICONDUCTOR CHIP BONDING APPARATUS AND METHOD OF FORMING SEMICONDUCTOR DEVICE USING THE SAME - A method of manufacturing a semiconductor device includes: providing a first substrate that includes internal wiring, the first substrate including an array of chip mounting regions that includes a first chip mounting region; placing the first substrate on a first carrier line; providing a first semiconductor chip; placing the first semiconductor chip on a first moveable tray; vertically aligning the first chip mounting region of the first substrate with the first semiconductor chip, and performing initial bonding of the first semiconductor chip to the first chip mounting region of the first substrate; and performing subsequent bonding on the initially-bonded first semiconductor chip and first mounting region of the first substrate, thereby more strongly bonding the first semiconductor chip to the first substrate at the first mounting region. The initial bonding occurs after performing a subsequent bonding of at least one other semiconductor chip on the first substrate. | 01-22-2015 |
20150050779 | Packaged Semiconductor Devices, Methods of Packaging Semiconductor Devices, and PoP Devices - Packaged semiconductor devices, methods of packaging semiconductor devices, and package-on-package (PoP) devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming through-package vias (TPVs) over a carrier, and coupling a semiconductor device to the carrier. The semiconductor device includes contact pads disposed on a surface thereof and an insulating material disposed over the contact pads. A molding material is formed over the carrier between the TPVs and the semiconductor device. Openings are formed in the insulating material using a laser drilling process over the contact pads, and a redistribution layer (RDL) is formed over the insulating material and the openings in the insulating material. A portion of the RDL is coupled to a top surface of each of the contact pads. | 02-19-2015 |
20150056751 | DIE EDGE SEALING STRUCTURES AND RELATED FABRICATION METHODS - Die structures for electronic devices and related fabrication methods are provided. An exemplary die structure includes a diced portion of a semiconductor substrate that includes a device region having one or more semiconductor devices fabricated thereon and an edge sealing structure within the semiconductor substrate that circumscribes the device region. In one or more embodiments, the edge sealing structure includes a conductive material that contacts a handle layer of semiconductor material, a crackstop structure is formed overlying the sealing structure, wherein the crackstop structure and the edge sealing structure provide an electrical connection between the handle layer and an active layer of semiconductor material that overlies a buried layer of dielectric material on the handle layer. | 02-26-2015 |
20150056752 | SUBSTRATELESS POWER DEVICE PACKAGES - A substrate-less composite power semiconductor device may be fabricated from a vertical conductive power semiconductor device wafer that includes a top metal layer located on a top surface of the wafer by a) forming solder bumps on top of the top metal layer; b) forming wafer level molding around the solder bumps such that the solder bumps are exposed through a top of the wafer level molding; c) grinding a back side of the device wafer to reduce a total thickness of a semiconductor material portion of the device wafer to a final thickness; and d) forming a back metal on a back surface of the wafer. | 02-26-2015 |
20150079734 | Die-Tracing in Integrated Circuit Manufacturing and Packaging - A method includes recording a wafer ID and a location ID of a device die in a database, and bonding the device die over a package substrate, wherein the device die and the package substrate are disposed in a package. A package ID is on the package. A mapping is established to link the wafer ID and the location ID of the device die to the package ID. | 03-19-2015 |
20150093858 | Methods for Controlling Warpage in Packaging - A method includes placing a plurality of dummy dies over a carrier, placing a plurality of device dies over the carrier, molding the plurality of dummy dies and the plurality of device dies in a molding compound, forming redistribution line over and electrically coupled to the device dies, and performing a die-saw to separate the device dies and the molding compound into a plurality of packages. | 04-02-2015 |
20150104905 | METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE - A semiconductor package includes a circuit board having an inner circuit pattern and a plurality of contact pads connected to the inner circuit pattern, at least one integrated circuit (IC) device on the circuit board and making contact with the contact pads, a mold on the circuit board, the mold fixing the IC device to the circuit board, and a surface profile modifier on a surface of the IC device and a surface of the mold, and the surface profile modifier enlarging a surface area of the IC device and the mold to dissipate heat. | 04-16-2015 |
20150104906 | PACKAGE FOR HIGH-POWER SEMICONDUCTOR DEVICES - Methods and apparatuses for forming a package for high-power semiconductor devices are disclosed herein. A package may include a plurality of distinct thermal spreader layers disposed between a die and a metal carrier. Other embodiments are described and claimed. | 04-16-2015 |
20150118796 | PACKAGED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING PACKAGED MICROELECTRONIC DEVICES - Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements by heating the first interconnect elements, and coupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed. | 04-30-2015 |
20150132892 | Packaging Methods for Semiconductor Devices - Methods of packaging semiconductor devices are disclosed. In one embodiment, a packaging method for semiconductor devices includes providing a workpiece including a plurality of first dies, and coupling a plurality of second dies to the plurality of first dies. The plurality of second dies and the plurality of first dies are partially packaged and separated. Top surfaces of the second dies are coupled to a carrier, and the partially packaged plurality of second dies and plurality of first dies are fully packaged. The carrier is removed, and the fully packaged plurality of second dies and plurality of first dies are separated. | 05-14-2015 |
20150132893 | FABRICATION METHOD OF SEMICONDUCTOR PACKAGE - A semiconductor package is provided. The semiconductor package includes a semiconductor chip having opposite first and second surfaces; an RDL structure formed on the first surface of the semiconductor chip and having opposite third and fourth surfaces and a plurality of first conductive through holes penetrating the third and fourth surfaces thereof, wherein the RDL structure is formed on the semiconductor chip through the fourth surface thereof and electrically connected to the semiconductor chip through a plurality of first conductive elements, and the third surface of the RDL structure has a redistribution layer formed thereon; a plurality of conductive bumps formed on the redistribution layer; and an encapsulant formed on the first surface of the semiconductor chip for encapsulating the RDL structure, wherein the conductive bumps are embedded in and exposed from the encapsulant. The invention effectively prevents warpage of the semiconductor package and improves the electrical connection significantly. | 05-14-2015 |
20150140738 | CIRCUIT CONNECTING MATERIAL AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD USING SAME - Provided are a circuit connecting material able to provide good bonding with an opposing electrode, and a semiconductor device manufacturing method using the same. The present invention uses a circuit connecting material, in which a first adhesive layer to be adhered to the semiconductor chip side, and a second adhesive layer having a lowest melting viscosity attainment temperature higher than that of the first adhesive layer are laminated. When the semiconductor chip on which the circuit connecting material is stuck is mounted on a circuit board, a thickness of the first adhesive layer is within a range satisfying formula (1), thereby providing good bonding with the opposing electrode. | 05-21-2015 |
20150140739 | DISCRETE SEMICONDUCTOR DEVICE PACKAGE AND MANUFACTURING METHOD - Disclosed is a discrete semiconductor device package ( | 05-21-2015 |
20150147849 | METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE - Disclosed herein is a method for manufacturing a semiconductor package. According to a preferred embodiment of the present invention, a method for manufacturing a semiconductor package includes: preparing a rectangular frame having a plurality of quadrangular holes; attaching a plurality of semiconductor chips and the frame on one surface of a tape; forming a molding part on the tape to cover the semiconductor chip and the frame; peeling the tape; forming a resin layer at a portion at which the tape is peeled; and forming a wiring on the resin layer to be connected to the semiconductor chip. | 05-28-2015 |
20150294892 | WATER SOLUBLE MASK FORMATION BY DRY FILM LAMINATION - Methods and systems for forming water soluble masks by dry film lamination are described. Also described are methods of wafer dicing, including formation of a water soluble mask by dry film lamination. In one embodiment, a method involves moisturizing an inner area of a water soluble dry film. The method involves stretching the water soluble dry film over a surface of the semiconductor wafer, and attaching the moistened inner area of the stretched film to the surface of the semiconductor wafer. A method of wafer dicing may further involve patterning the water soluble dry film, exposing regions of the semiconductor wafer between the ICs, and etching the semiconductor wafer through gaps in the patterned water soluble dry film. | 10-15-2015 |
20150294942 | INDEXING OF ELECTRONIC DEVICES DISTRIBUTED ON DIFFERENT CHIPS - A method for indexing electronic devices includes: forming first chips in a first wafer, forming second chips in a second wafer, forming the electronic devices by coupling each first chip with a corresponding second chip, and forming an index on each electronic device. The index is indicative of a position of the corresponding first chip in the first wafer. The step of forming an index includes forming a first portion of the index on the first chip, and forming a second portion of the index on the second chip. | 10-15-2015 |
20150303075 | METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE - A method of fabricating a semiconductor package includes mounting a plurality of semiconductor devices on a substrate; forming a molding member that covers a top surface of the substrate, top surfaces of the semiconductor devices, and sidewall surfaces of the semiconductor devices; sawing the molding member and the substrate along pre-scribing lines of the substrate; and spraying a metallic epoxy material on the sawn molding members using a sprayer to form an antistatic layer on sidewall surfaces and a top surface of each of the sawn molding members. | 10-22-2015 |
20150303155 | METHOD OF PRODUCING SEMICONDUCTOR MODULE AND SEMICONDUCTOR MODULE - In order to securely ground an exterior shield and reduce burden imposed on a dicing blade and the exterior shield, a method of producing a semiconductor module comprises a hole-forming step of forming a hole | 10-22-2015 |
20150311181 | SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR CONSTRUCT INSTALLED ON BASE PLATE, AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes a semiconductor construct including a semiconductor substrate and an external connection electrode provided to protrude on a surface of the semiconductor substrate, a base plate on which the semiconductor construct is installed, and a sealing layer stacked on the semiconductor substrate except for the external connection electrode and on the base plate including a side surface of the semiconductor substrate. | 10-29-2015 |
20150332937 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR STACKED MODULE STRUCTURE, STACKED MODULE STRUCTURE AND METHOD OF MANUFACTURING SAME - A method of manufacturing a semiconductor device having an insulating substrate, a semiconductor element which is mounted on one main surface of the insulating substrate via adhesive, with an element circuit surface of the semiconductor element facing upwards, a first insulating material layer (A) which seals the element circuit surface of the semiconductor element and the insulating substrate peripheral thereto, a first metal thin film wire layer provided on the first insulating material layer (A) and a portion of which is exposed to an external surface, a first insulating material layer (B) provided on the first metal thin film wire layer, a second insulating material layer provided on a main surface of the insulating substrate where the semiconductor element is not mounted, a second metal thin film wire layer provided inside the second insulating material layer. | 11-19-2015 |
20150333036 | SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A first semiconductor substrate is used which has a structure in which a peeling layer is not formed in a section subjected to a first dividing treatment, so that the peeling layer is not exposed at the end surface of a second semiconductor substrate when the second semiconductor substrate is cut out of the first semiconductor substrate. In addition, a supporting material is provided on a layer to be peeled of the second semiconductor substrate before the second semiconductor substrate is subjected to a second dividing treatment. | 11-19-2015 |
20150348934 | Package in Package (PiP) Electronic Device and Manufacturing Method thereof - A manufacturing method for Package in Package (PiP) electronic device based on multi-row Quad Flat No-lead (QFN) package is provided wherein the lower surface of plate metallic base material are half-etched to form grooves. Insulation filling material is filled in the half-etched grooves. The upper surface of plate metallic base material is half-etched to form chip pad and multi-row of leads. Encapsulating IC chip for wire bonding, adhesive material, metal wire, chip pad and a plurality of leads to form a multi-row QFN package as an inner package. Flip-chip bonding IC chip with solder bumps on the first metal material layer of leads. Encapsulating IC chip with solder bumps, the multi-row QFN package, adhesive material, and leads to form an array of PiP electronic devices. Sawing and separating the PiP electronic device array, forming PiP electronic device unit. | 12-03-2015 |
20150380275 | METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - A method of forming a semiconductor package includes forming a passivation layer over a semiconductor substrate. The semiconductor substrate includes a first chip region, a second chip region and a scribe line region. The scribe line region is positioned between the first chip region and the second chip region. The method also includes forming a bump over the passivation layer on at least one of the first chip region and the second chip region. The method further includes removing a portion of the passivation layer to form a groove in the passivation layer on the scribe line region. The method additionally includes filling the groove with a molding compound layer. The molding compound layer is filled to a point that entirely fills the groove, covers the passivation layer, and covers a lower portion of the bump. The method also includes separating the first chip region from the second chip region along the scribe line region. | 12-31-2015 |
20150380276 | METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE - Disclosed herein is a method for manufacturing a semiconductor package. According to a preferred embodiment of the present invention, a method for manufacturing a semiconductor package includes: preparing a rectangular frame having a plurality of quadrangular holes; attaching a plurality of semiconductor chips and the frame on one surface of a tape; forming a molding part on the tape to cover the semiconductor chip and the frame; peeling the tape; forming a resin layer at a portion at which the tape is peeled; and forming a wiring on the resin layer to be connected to the semiconductor chip. | 12-31-2015 |
20160005629 | PACKAGING STRUCTURAL MEMBER - A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate. | 01-07-2016 |
20160005634 | METHOD OF FABRICATING SEMICONDUCTOR PACKAGE, SEMICONDUCTOR CHIP SUPPORTING CARRIER AND CHIP MOUNTING DEVICE - In fabricating semiconductor packages, a first supporting unit is supported by a supporting substrate with one surface of an adhesive sheet directed upward, the first supporting unit being constituted by attaching the adhesive sheet having an adhesive layer as the one surface thereof and a non-adhesive layer as the other surface thereof to a frame member; semiconductor chips are mounted on the one surface of the adhesive sheet; on the adhesive sheet, a resin portion containing the semiconductor chips is formed by resin-sealing the semiconductor chips; the first supporting unit is removed from the second supporting unit; the resin portion is stripped from the adhesive sheet; external connection members are formed at the semiconductor chips contained in the resin portion; and portions between the respective semiconductor chips contained in the resin portion are cut to obtain individual semiconductor packages. | 01-07-2016 |
20160013089 | SEMICONDUCTOR DEVICE PRODUCTION METHOD, SHEET-SHAPED RESIN COMPOSITION, DICING TAPE-INTEGRATED SHEET-SHAPED RESIN COMPOSITION | 01-14-2016 |
20160013150 | Integrated Fan-Out Package Structures with Recesses in Molding Compound | 01-14-2016 |
20160020190 | METHOD FOR FABRICATING AN INTERPOSER - A method for fabricating an interposer is provided, which includes the steps of: providing a substrate body having a chip mounting side and an opposite external connection side and a plurality of conductive through holes communicating the chip mounting side and the external connection side, wherein the chip mounting side of the substrate body is covered with a protection layer; performing a singulation process on the external connection side of the substrate body; bonding the substrate body to a carrier via the external connection side thereof; removing the protection layer; and removing the carrier to form a plurality of interposers, thereby simplifying the fabrication process and improving the product yield. | 01-21-2016 |
20160020191 | Functional Spacer for SIP and Methods for Forming the Same - A device includes a spacer, which includes a recess extending from a top surface of the spacer into the spacer, and a conductive feature including a first portion and a second portion continuously connected to the first portion. The first portion extends into the recess. The second portion is on the top surface of the spacer. A die is attached to the spacer, and a lower portion of the first die extends into the recess. | 01-21-2016 |
20160027637 | APPARATUS AND METHODS FOR MANUFACTURING SEMICONDUCTOR DEVICES AND TREATING SUBSTRATES - A method of manufacturing a semiconductor device includes: forming a pattern on a surface of a semiconductor substrate; placing the substrate on a platform of a substrate treatment apparatus; rotating the wafer while applying a cleaning liquid from a first nozzle and a wetting liquid from a second nozzle to treat a first region on the surface of the substrate; vertically changing the distance of the second nozzle together with the first nozzle with respect to the platform; after the vertical change, rotating the wafer while applying the cleaning liquid from the first nozzle and the wetting liquid from the second nozzle to treat a second region on the surface of the substrate; and forming a semiconductor device from the treated substrate. | 01-28-2016 |
20160035696 | METHOD FOR FORMING PACKAGE STRUCTURE - A method for forming a package structure is provided, which includes: providing a pre-packaged panel including a first encapsulation layer, which includes multiple integrating units each including at least one semiconductor chip with multiple first pads, and first metal bumps are disposed on the first pads; providing a circuit board including a first surface and a second surface, where the circuit board includes multiple carrying units each including multiple input pads on the first surface and multiple output pads on the second surface; mounting the pre-packaged panel on the first surface to form multiple package units; forming a filling layer by filling a space between the first surface and the pre-packaged panel; forming second metal bumps on the output pads on the second surface; cutting the structure based on the multiple package units to form multiple independent package structures. Accordingly, the package structure improves package efficiency. | 02-04-2016 |
20160035697 | MINIATURIZED SMD DIODE PACKAGE AND PROCESS FOR PRODUCING THE SAME - A process for producing a miniaturized SMD diode package involves using a diode chip whose bottom surface has a positive electrode and a negative electrode, using a circuit board instead of a conventional lead frame during packaging, and using Charge-Coupled Device (CCD) image registration technology to perform chip bonding; the beneficial advantages brought from the process for producing the same including to simplify producing process and reduce manufacturing cost, to improve accuracy and precision of producing the miniaturized SMD diode package due to using a circuit board instead of conventionally used lead frame, and to ensure the produced miniaturized SMD diode package possesses excellent diode characteristics without distortion or defect. | 02-04-2016 |
20160056079 | Method of Manufacturing a Package-on-Package Type Semiconductor Package - A method for manufacturing a semiconductor package, for example a package-on-package type semiconductor device package. As non-limiting examples, various aspects of this disclosure provide high-yield methods for manufacturing a package-on-package type semiconductor package, or a portion thereof. | 02-25-2016 |
20160064251 | METHOD AND STRUCTURE FOR WAFER LEVEL PACKAGING WITH LARGE CONTACT AREA - A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the first packaging layer thickness to expose the second packaging layer filling the grooves and forming a plurality of contact pads overlaying the first packaging layer thereafter cutting through the second packaging layer in the grooves to form individual package. | 03-03-2016 |
20160079144 | GRAPHENE BASED FILLER MATERIAL OF SUPERIOR THERMAL CONDUCTIVITY FOR CHIP ATTACHMENT IN MICROSTRUCTURE DEVICES - An integrated circuit chip attachment in a microstructure device is accomplished through the use of an adhesive-based material in which graphene flakes are incorporated. This results in superior thermal conductivity. The spatial orientation of the graphene flakes is controlled, for example by adhering polar molecules to the graphene flakes and exposing the flakes to an external force field, so that the graphene flakes have desired orientations under the integrated circuit chip, alongside of the integrated circuit chip and above the integrated circuit chip. | 03-17-2016 |
20160086896 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package including a semiconductor substrate having a first surface and a second surface opposite thereto. A conducting pad is located on the first surface. A side recess is on at least a first side of the semiconductor substrate, wherein the side recess extends from the first surface toward the second surface and across the entire length of the first side. A conducting layer is located on the first surface and electrically connected to the conducting pad, wherein the conducting layer extends to the side recess. | 03-24-2016 |
20160086908 | ADHESIVE AGENT COMPOSITION, ADHESIVE SHEET, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An adhesive composition includes an acrylic polymer (A), a heat curable resin (B) having a reactive double bond group, and a filler (C) having a reactive double bond group on a surface thereof. The acrylic polymer (A) has a weight average molecular weight of 500,000 or more, and the heat curable resin (B) comprises an epoxy resin and a heat curing agent, in which at least one of the epoxy resin and the heat curing agent has the reactive double bond group. | 03-24-2016 |
20160099218 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - Provided is a method of manufacturing a semiconductor package. The method includes mounting a semiconductor device on a substrate; disposing a mold on the substrate, wherein the mold is formed to cover the semiconductor device such that at least one inner side surface of the mold has a slope; providing a molding material into the mold to encapsulate the semiconductor device; removing the mold from the substrate; and forming an electromagnetic shielding (EMS) layer to cover a top surface and side surfaces of the molding material. | 04-07-2016 |
20160104643 | WAFER PROCESSING METHOD - A method of processing a wafer having a device area where a plurality of devices are formed and a peripheral marginal area surrounding the device area on the front side of the wafer is disclosed. The devices are formed in regions defined by division lines. Each device has a plurality of bump electrodes on the front side. A first laser beam is applied through dicing tape from the back side along the boundary between the device area and the peripheral marginal area, with the focal point of the first laser beam set inside the wafer, thereby forming an annular modified layer inside the wafer. A second laser beam is applied through the dicing tape from the back side along each division line with the focal point of the second laser beam set inside the wafer, thereby forming a modified layer inside the wafer along each division line. | 04-14-2016 |
20160104690 | BONDING PROCESS FOR A CHIP BONDING TO A THIN FILM SUBSTRATE - A bonding process for a chip bonded to a thin film substrate is disclosed. The thin film substrate has a thickness of about less than 500 um. Curvature occurs in the thin film substrate due to Coefficient of Temperature Expansion (CTE) mismatch for different materials between the dielectric material and the embedded circuitry, where cooling and heating is applied during fabrication. A temporary carrier is prepared for the thin film substrate to paste, a flatten process is applied by a roller thereon so that the curvature of the thin film substrate can be eliminated and facilitated for of chips to be bonded thereto. | 04-14-2016 |
20160111299 | Methods of Fabricating Tape Film Packages - A tape film package is provided including an insulating pattern; a via contact in a via hole in the insulating pattern; first interconnection patterns extending from the via contact to a cutting surface of the insulating pattern; and second interconnection patterns connected to the via contact below the insulating pattern. The second interconnection patterns are parallel to the first interconnection patterns and spaced apart from the cutting surface of the insulating pattern. | 04-21-2016 |
20160111331 | WAFER PROCESSING METHOD - A wafer is divided into individual devices along division lines formed on the front side of the wafer. A protective tape having an adhesive layer is attached to the front side of a functional layer of the wafer with the adhesive layer of the protective tape in contact with the front side of the functional layer. The wafer with the protective tape is held on a holding surface of a chuck table with the protective tape in contact with the holding surface. A laser beam having an absorption wavelength to the substrate and the functional layer of the wafer is applied from the back side of the substrate along each division line to form a laser processed groove having a depth reaching the protective tape along each division line, thereby dividing the wafer into individual device chips corresponding to the individual devices. | 04-21-2016 |
20160118271 | METHOD OF FABRICATING SEMICONDUCTOR PACKAGE HAVING AN INTERPOSER STRUCTURE - A method of fabricating a semiconductor package is provided, including: cutting a substrate into a plurality of interposers; disposing the interposers in a plurality of openings of a carrier, wherein the openings are spaced from one another by a distance; forming a first encapsulant to encapsulate the interposers; removing the carrier; and disposing at least a semiconductor element on each of the interposers. By cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers. | 04-28-2016 |
20160118273 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor package includes providing a package substrate, arranging a plurality of semiconductor devices in an array pattern on an upper surface of the package substrate and electrically connecting the plurality of semiconductor devices to the package substrate, and forming a molding member on the upper surface of the package substrate to cover the semiconductor chips. The molding member includes a warpage-preventing portion configured to prevent or reduce a warpage of the package substrate. The warpage-preventing portion may be raised above a top surface of a base portion of the molding member. | 04-28-2016 |
20160118299 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - The method includes disposing semiconductor chips on a package substrate having sawing lines, forming an encapsulant to cover the semiconductor chips on the package substrate, forming a package assembly by a first curing of the encapsulant, forming first grooves by cutting the encapsulant along the sawing lines, performing a second curing of the encapsulant, and dividing the package assembly into unit semiconductor packages by cutting the package substrate along the sawing lines and forming second grooves to overlap the first grooves. | 04-28-2016 |
20160118300 | WAFER DIE SEPARATION - A method of singulating a wafer starts with fracturing the wafer. The method may also include attaching the dicing tape sheet to a ring frame; relatively raising a portion of the dicing tape sheet supporting the wafer with respect to the ring frame; and attaching support tape to the ring frame and the dicing tape sheet. | 04-28-2016 |
20160118301 | PACKAGE WITH METAL-INSULATOR-METAL CAPACITOR AND METHOD OF MANUFACTURING THE SAME - A package includes a chip that has a metal-insulator-metal (MIM) capacitor formed in a first polymer layer and a metallic pillar formed on the MIM capacitor. A molding compound surrounds the chip, a second polymer layer is formed on the chip and the molding compound, a third polymer layer is formed on the second polymer layer, an interconnect structure is formed between the second polymer layer and the third polymer layer and electrically coupled to the metallic pillar and the MIM capacitor, and a bump is formed over and electrically coupled to the interconnect structure. | 04-28-2016 |
20160126218 | BONDING METHOD OF SEMICONDUCTOR CHIP AND BONDING APPARATUS OF SEMICONDUCTOR CHIP - According to one embodiment, there is provided a bonding method of a semiconductor chip. The bonding method includes arranging an activated front surface of a semiconductor chip and an activated front surface of a substrate so as to face each other with a back surface of the semiconductor chip attached to a sheet. The bonding method includes pushing the back surface of the semiconductor chip through the sheet to closely attach the activated front surface of the semiconductor chip and the activated front surface of the substrate. The bonding method includes stripping the sheet from the back surface of the semiconductor chip while maintaining a state in which the activated front surface of the semiconductor chip is closely attached to the activated front surface of the substrate. | 05-05-2016 |
20160141254 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed over the first surface and extending into the first recess and/or the second recess; an insulating layer positioned between the wire layer and the semiconductor substrate; and a metal light shielding layer disposed over the first surface and having at least one hole, wherein a shape of the at least one hole is a quadrangle. | 05-19-2016 |
20160141385 | METHOD OF MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE - A method of manufacturing a nitride semiconductor device includes: forming a transistor having a gate electrode Schottky-joined to a nitride semiconductor layer; performing high-temperature annealing at a temperature of 200 to 360° C. for 8 to 240 hours on the transistor; and after the high-temperature annealing, performing RF burn-in by applying radiofrequency power to the transistor at a channel temperature of 180 to 360° C. | 05-19-2016 |
20160148843 | PACKAGE SUBSTRATE DIVIDING METHOD - A package substrate is divided into a plurality of device packages. An adhesive tape is attached to a back side of the substrate by cutting the substrate along a plurality of division lines formed on a front side of the substrate. The substrate includes a device portion partitioned into a plurality of device package regions by the division lines, and a marginal portion surrounding the device portion. A first ultraviolet light is applied to reduce the adhesive force of the adhesive tape in the marginal portion. The adhesive tape is partially peeled from the substrate in the marginal portion, and the substrate is cut along each division line by using a cutting blade to thereby divide the substrate into the device packages. In the dividing step, the marginal portion separated from the substrate is scattered by rotation of the cutting blade and thereby removed from the adhesive tape. | 05-26-2016 |
20160155667 | ORGANIC THIN FILM PASSIVATION OF METAL INTERCONNECTIONS | 06-02-2016 |
20160155681 | PACKAGE FOR HIGH-POWER SEMICONDUCTOR DEVICES | 06-02-2016 |
20160163674 | Method of Packaging Integrated Circuits - Integrated circuits are packaged by placing a plurality of semiconductor dies on a support substrate, each one of the semiconductor dies having a plurality of terminals at a side facing the support substrate and covering the semiconductor dies with a molding compound to form a molded structure. The support substrate is then removed from the molded structure to expose the side of the semiconductor dies with the terminals, and a metal redistribution layer is formed on the molded structure and in direct contact with the terminals of the semiconductor dies and the molding compound. The redistribution layer is formed without first forming a dielectric layer on a side of the molded structure with the terminals of the semiconductor dies. A corresponding molded substrate and individual molded semiconductor packages are also disclosed. | 06-09-2016 |
20160163676 | SINGLE LAYER LOW COST WAFER LEVEL PACKAGING FOR SFF SIP - In one embodiment of the invention, a system in package (SiP) is described which includes a plurality of device components with different form factors embedded within a molding compound layer. A surface for each of the device components is coplanar with a surface of the molding compound layer, and a single redistribution layer (RDL) formed on the coplanar surfaces of the molding compound layer and the plurality of device components. An active device die is electrically bonded to the single RDL directly vertically adjacent the plurality of device components. In an embodiment, the SiP is electrically connected to a circuit board with the active device die between the single RDL and the circuit board. In an embodiment, the SiP is electrically connected to a circuit board with the active device die over the single RDL and the circuit board. | 06-09-2016 |
20160163917 | METHOD OF SELECTIVELY TRANSFERRING SEMICONDUCTOR DEVICE - A method of selectively transferring semiconductor devices comprises the steps of providing a substrate having a first surface and a second surface; providing a plurality of semiconductor epitaxial stacks on the first surface, wherein each of the plurality of semiconductor epitaxial stacks comprises a first semiconductor epitaxial stack and a second semiconductor epitaxial stack, and the first semiconductor epitaxial stack is apart from the second semiconductor epitaxial stack, and wherein a adhesion between the first semiconductor epitaxial stack and the substrate is different from a adhesion between the second semiconductor epitaxial stack and the substrate; and selectively separating the first semiconductor epitaxial stack or the second semiconductor epitaxial stack from the substrate. | 06-09-2016 |
20160181209 | Integrated Circuit Having Stress Tuning Layer and Methods of Manufacturing Same | 06-23-2016 |
20160190094 | ADHESIVE FOR ELECTRONIC COMPONENT - An adhesive composition for a pre-applied underfill sealant comprising: (a) a radical polymerizable monomer having one or more functional groups selected from the group consisting of vinyl group, maleimide group, acryloyl group, methacryloyl group and allyl group, (b) a polymer having a polar group, (c) a filler, and (d) a thermal radical initiator. | 06-30-2016 |
20160196988 | EMBEDDED SEMICONDUCTIVE CHIPS IN RECONSTITUTED WAFERS, AND SYSTEMS CONTAINING SAME | 07-07-2016 |
20160379956 | SEMICONDUCTOR DEVICE HAVING RECESSED EDGES AND METHOD OF MANUFACTURE - A device and method of manufacture is provided that utilize recessed regions along a package edge. For example, in an integrated fan-out package, the dielectric layers, e.g., the polymer layers, of the redistribution layers are removed along the scribe line such that after singulation the dielectric layers are recessed back from the edges of the die. The corner regions may be recessed further. The recessed regions may be triangular, rounded, or other shape. In some embodiments one or more of the corner regions may be recessed further relative to the remaining corner regions. The redistribution layers may be recessed along one or both of the front side redistribution layers and the backside redistribution layers. | 12-29-2016 |
20190148175 | SUPPORT FOR MANUFACTURING SEMICONDUCTOR PACKAGES, USE OF SUPPORT FOR MANUFACTURING SEMICONDUCTOR PACKAGES, AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGES | 05-16-2019 |
20220139781 | SYSTEMS AND METHODS FOR MANUFACTURING FLEXIBLE ELECTRONICS - Systems and methods for manufacturing flexible electronics are described herein. Methods in accordance with embodiments of the present technology can include disposing electrical features, such as thin film circuits, on a first side of a glass substrate, applying a first protective material over the electronic features, and exposing a second side of the glass substrate to a chemical etching tank to thin the glass substrate to a predetermined thickness. The thinning process can remove cracks and other defects from the second side of the glass substrate and enhance the flexibility of the electronic assembly. A second protective material can be disposed on the second side of the thinned glass substrate to maintain the enhanced backside surface of the glass substrate. In some embodiments, the method also includes singulating the plurality of electronic features into individual electronic components by submerging the electronic assembly into a chemical etching tank. | 05-05-2022 |