Class / Patent application number | Description | Number of patent applications / Date published |
438018000 | Utilizing integral test element | 44 |
20080206908 | Semiconductor device test structures and methods - Semiconductor device test structures and methods are disclosed. In a preferred embodiment, a test structure includes a feed line, a stress line disposed proximate the feed line, and a conductive feature disposed between the stress line and the feed line. The test structure includes a temperature adjuster proximate at least the conductive feature, and at least one feedback device coupled to the temperature adjuster and at least the conductive feature. | 08-28-2008 |
20080241977 | Semiconductor device with electrode pad having probe mark - A semiconductor device is formed by bonding balls to a plurality of electrode pads formed on a semiconductor chip. After a wafer test is conducted by pressing a probe against the electrode pad, wire-bonding of the electrode pad to a lead is carried out so that a probe mark formed in the electrode pad during the wafer test is completely covered by a bonding ball, which forms an end of a wire connected to the lead. | 10-02-2008 |
20080286888 | TEST STRUCTURES AND METHODOLOGY FOR DETECTING HOT DEFECTS - Test structures for detecting defects arising from hybrid orientation technology (HOT) through detection of device leakage (gate leakage, junction leakage, and sub-threshold leakage), having at least one active region disposed in a re-grown region of a substrate: a layer of oxide; a layer of poly. Some test structures are dog-bone shaped test structure, tower shaped test structure, and inside-hole shaped. A method for detecting HOT defects involves measuring defect size and location in terms of device leakage, such as gate leakage, junction leakage, and sub-threshold leakage. HOT edge defect density and edge defect size distribution may be calculated, and the resulting defect information may be used to calibrate a defect yield model. | 11-20-2008 |
20090029491 | METHOD OF INSPECTING DEFECT OF SEMICONDUCTOR DEVICE - A method of inspecting defects in a semiconductor device includes forming a test pattern in a scribe lane region of a semiconductor substrate. The test pattern includes a second conductive layer formed on an isolation layer of the semiconductor substrate. Further, the method includes measuring a current flowing between the second conductive layer and the semiconductor substrate by applying a first voltage between the second conductive layer and the semiconductor substrate. Defects formed in the isolation layer can be inspected during a semiconductor manufacturing process. Accordingly, the yield of semiconductor devices can be improved with the inspection results. | 01-29-2009 |
20090068772 | ACROSS RETICLE VARIATION MODELING AND RELATED RETICLE - Methods of modeling across reticle variations and a related reticle are disclosed. One embodiment of the method includes defining a test for determination across a multiple chip wafer; identifying a measurement structure for performing the test; implementing the measurement structure on the multiple chip wafer using a reticle including the measurement structure between copies of the multiple chips on the reticle, wherein no one of the multiple chips covers an entirety of the reticle; performing the test on the multiple chip wafer using the measurement structure to acquire data across the reticle; using data from the performing to establish an across reticle variation model; and using the across reticle variation model to predict across chip variation for at least one of the multiple chips. | 03-12-2009 |
20090162954 | AC Impedance Spectroscopy Testing of Electrical Parametric Structures - Defects in components in ICs which may cause circuit failures during operation of the IC are often difficult to detect during and immediately after fabrication of the IC by DC test methods. A method of testing components to detect such defects using AC Impedance Spectroscopy is disclosed. Data may be analyzed using Nyquist plots and Bode plots. Nyquist plots of typical defect types are disclosed. Components may include MOS transistor gate structures, contacts, vias and metal interconnect lines. Components tested may be contained in integrated circuits or in test circuits. Integrated circuits containing components tested by AC Impedance Spectroscopy may be partially fabricated or deprocessed after fabrication. | 06-25-2009 |
20090239317 | Method and jig structure for positioning bare dice - A method and jig structure for positioning bare dice is disclosed. The jig structure for positioning at least one bare dice includes a trap having at least one positioning groove wherein the depth of the positioning groove is less than the height of the bare dice. Basing on the positioning groove formed in the tray, once a bare dice is placed in the positioning groove, the partially exposed bare dice can be located directly and precisely vacuum-grabbed by a sucker, so that the number of positioning steps is reduced. | 09-24-2009 |
20090258447 | METHOD OF DETECTING HEAVY METAL IN SEMICONDUCTOR SUBSTRATE - A method of detecting heavy metal in a semiconductor substrate, includes: a gate oxide film forming step of forming an organic oxide film by spin coating or a sol-gel process, and forming a metal/oxide film/semiconductor junction element by using a mercury probe method; and a step of detecting and quantifying heavy metal by calculating the surface concentration of the heavy metal from junction capacitance characteristics of the element. | 10-15-2009 |
20090280584 | WAFER PROCESSING - Methods for processing semiconductor wafers are described herein. One embodiment includes removing portions of a first side of the semiconductor wafer to form a number of trenches of a particular depth in rows and columns. The method further includes forming a passivation layer on side walls of the number of trenches. The method also includes cutting a second side of the semiconductor wafer in rows and columns aligned with the number of trenches such that the semiconductor wafer singulates into a number of dice. | 11-12-2009 |
20100003772 | Wafer level hermetic bond using metal alloy with raised feature - Systems and methods for forming an encapsulated device include a hermetic seal which seals an insulating environment between two substrates, one of which supports the device. The hermetic seal is formed by an alloy of two metal layers, one deposited on a first substrate and the other deposited on the second substrate, along with a raised feature formed on the first or the second substrate. At least one of the metal layers may be deposited conformally over the raised feature. The raised feature penetrates the molten material of the first or the second metal layers during formation of the alloy, and produces a spectrum of stoichiometries for the formation of the desired alloy, as a function of the distance from the raised feature. At some distance from the raised feature, the proper ratio of the first metal to the second metal exists to form an alloy of the preferred stoichiometry. | 01-07-2010 |
20100167432 | Method of manufacturing semiconductor device - A method of manufacturing a semiconductor device includes: forming a first pad and a second pad over a substrate; forming a first insulating film over the second pad without forming the first insulating film over the first pad; forming a metal film over the first pad and the second pad; forming an electrode over the first pad with the metal film interposed therebetween; selectively removing the metal film over the second pad; and removing the first insulating film over the second pad. | 07-01-2010 |
20100197053 | PROCESS AND TEMPERATURE INSENSITIVE FLICKER NOISE MONITOR CIRCUIT - In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defeats are within an allowable range. | 08-05-2010 |
20100221851 | TEST STRUCTURE AND METHOD FOR DETECTING CHARGE EFFECTS DURING SEMICONDUCTOR PROCESSING - A semiconductor process test structure comprises an electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. Gate-induced drain leakage (GIDL) measurement techniques can then be used to characterize the charging status of the test structure. | 09-02-2010 |
20100297793 | IN LINE TEST CIRCUIT AND METHOD FOR DETERMINING INTERCONNNECT ELECTRICAL PROPERTIES AND INTEGRATED CIRCUIT INCORPORATING THE SAME - A test circuit for, and method of, determining electrical properties of an underlying interconnect layer and an overlying interconnect layer of an integrated circuit (IC) and an IC incorporating the test circuit or the method. In one embodiment, the test circuit includes a gate chain having a ring path and a stage. In one embodiment, the stage includes: (1) a underlying test segment in the underlying interconnect layer, (2) a overlying test segment in the overlying interconnect layer and (3) logic circuitry activatible after formation of the underlying interconnect layer and before formation of the overlying interconnect layer to place the underlying test segment in the ring path and further activatible after the formation of the overlying interconnect layer to substitute the overlying test segment for the underlying test segment in the ring path. | 11-25-2010 |
20100304512 | System for Diagnosis and Treatment of Photovoltaic and Other Semiconductor Devices - A diagnostic and self-healing treatment system for a semiconductor device, the system provides: i) a shunt busting/blocking treatment, ii) self-healing treatment, and iii) an in-situ non-contact diagnostic determination. | 12-02-2010 |
20110244605 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - According to one embodiment, a method of fabricating a semiconductor device, including forming semiconductor chips having a test circuit electrically connected to an input pad and an output pad, the input pad having a first pad located on a first principal surface and a second pad located on a second principal surface of the semiconductor wafer, placing the semiconductor wafers on an inspection apparatus, each input pad brought into contact with each input pad adjacent semiconductor wafer, bringing each of probing tips on the input pad of the semiconductor chips of an uppermost or lowermost semiconductor wafer in the semiconductor wafers and performing a test on the semiconductor chips in one batch. | 10-06-2011 |
20110318852 | WAFER LEVEL INTEGRATION MODULE HAVING CONTROLLED RESISTIVITY INTERCONNECTS - A wafer level integration module and method for fabricating are disclosed according to a construction whereby semiconductor functional device fabrication is carried out only after interconnect structures are processed on a bare wafer. The fabrication and processing include forming interconnect structures in a first side of a wafer. An insulation layer is deposited on the first side of the wafer. A conductive layer is deposited on the insulation layer so as to fill the interconnect structures and contact the insulation layer on the walls thereof. The conductive layer on the interconnect structures forms interconnection contacts on the first side of the wafer and interconnection vias extending into the wafer. The conductive layer including the interconnection contacts is exposed on the first side of the wafer. A semiconductor functional device is fabricated on the first side of the wafer and interconnected with the interconnection contacts during the fabricating. Portions of the first conductive layer associated with the interconnection vias are exposed from the second side of the wafer. A portion of the first conductive layer can be selectively removed to form interconnection via redistribution connection structures that can be filled with a low resistivity material to form low resistivity redistribution interconnect with the semiconductor functional device through the first conductive layer. | 12-29-2011 |
20120064646 | METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The variation in the contact pressures of the plurality of contact terminals to the plurality of chip electrodes is decreased. A thin-film sheet (first sheet) includes: a principal surface (contact-terminal formation surface) on which a plurality of contactors (contact terminals) are formed; and a rear surface positioned on an opposite side to the principal surface. Also, in the thin film sheet, a plurality of wirings and dummy wiring are arranged between the principal surface and the rear surface. A slit formed of an opening portion penetrating from the principal surface of the thin-film sheet to the rear surface thereof is formed along the wiring between the dummy wiring and the contactor arranged at an end of a contactor group (first contact terminal group) in which the plurality of contactors are aligned. | 03-15-2012 |
20120149137 | Methods of Combinatorial Processing For Screening Multiple Samples on a Semiconductor Substrate - In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions. | 06-14-2012 |
20120196390 | 3D SEMICONDUCTOR DEVICE WITH REDUNDANCY - A method for manufacturing system includes 3D-IC comprising at least first layer of first transistors and second layers of second transistors and, perform a test for the circuit constructed with said first transistors and switch in function constructed with said second transistors to replace function constructed with said first transistors. | 08-02-2012 |
20120264241 | TEST STRUCTURE AND METHODOLOGY FOR THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURES - A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer. | 10-18-2012 |
20130130415 | METHODS OF TESTING INTEGRATED CIRCUIT DEVICES USING FUSE ELEMENTS - Methods of fabricating integrated circuit devices utilize fuse elements to support sequential testing of vertically-integrated test elements during fabrication. These methods include forming a first test element, a first fuse and a first test pad electrically connected by the first fuse to the first test element, on a substrate. The first test element is tested by passing a first current between the first test element and first test pad and through the first fuse. The first fuse is then “cut” by increasing an impedance of the first fuse, which may include breaking the first fuse to create an electrical “open” (infinite impedance) or greatly increasing a resistance of the first fuse (e.g., by narrowing the fuse through electromigration). A second test element and a second test pad, which is electrically connected to the second test element and the first test pad, are then formed on the substrate. | 05-23-2013 |
20130196458 | METHOD OF TESTING THROUGH SILICON VIAS (TSVS) OF THREE DIMENSIONAL INTEGRATED CIRCUIT (3DIC) - In a method of testing a plurality of through silicon vias (TSVs) chained together by interconnect on a substrate, a test signal is applied to a first test pad among a plurality of test pads, and a return signal is measured at a second test pad among the plurality of test pads. At least one test pad of the plurality of test pads is grounded to the substrate. The remaining test pads of the plurality of test pads are either connected to the plurality of chained TSVs or are grounded. | 08-01-2013 |
20130252356 | SUPPORTING SUBSTRATE, METHOD FOR FABRICATING SEMICONDUCTOR DEVICE, AND METHOD FOR INSPECTING SEMICONDUCTOR DEVICE - An aspect of one embodiment, there is provided a supporting substrate, including a first supporting substrate, an outer diameter being larger than a diameter of a semiconductor substrate and an inner diameter being smaller than the diameter of the semiconductor substrate, and a second supporting substrate, an outer diameter being smaller than the inner diameter of the first supporting substrate. | 09-26-2013 |
20130260486 | MOS Varactor Structure and Methods - Apparatus and methods for a MOS varactor structure are disclosed. An apparatus is provided, comprising an active area defined in a portion of a semiconductor substrate; a doped well region in the active area extending into the semiconductor substrate; at least two gate structures disposed in parallel over the doped well region; source and drain regions disposed in the well region formed on opposing sides of the gate structures; a gate connector formed in a first metal layer overlying the at least two gate structures and electrically coupling the at least two gate structures; source and drain connectors formed in a second metal layer and electrically coupled to the source and drain regions; and interlevel dielectric material separating the source and drain connectors in the second metal layer from the gate connector formed in the first metal layer. Methods for forming the structure are disclosed. | 10-03-2013 |
20130337587 | METHODS OF ADDING PADS AND ONE OR MORE INTERCONNECT LAYERS TO THE PASSIVATED TOPSIDE OF A WAFER INCLUDING CONNECTIONS TO AT LEAST A PORTION OF THE INTEGRATED CIRCUIT PADS THEREON - A pattern of conductive ink is disposed on the topside of the unsingulated integrated circuits of a wafer, and, typically after wafer probing, the pattern of conductive ink is removed. The conductive ink pattern provides an electrical pathway between bond pads on an integrated circuit and large contact pads disposed on the topside of the integrated circuit. Each of the large contact pads is much greater in area than the corresponding bond pads, and are spaced apart so that the pitch of the large contact pads is much greater than that of the bond pads. In one aspect of the present invention, the conductive ink includes a mixture of conductive particles and wafer bonding thermoset plastic. In another aspect of the present invention, the conductive ink is heated and disposed on a wafer by an ink jet printing system. | 12-19-2013 |
20140017826 | SEMICONDUCTOR WAFER EVALUATION METHOD, SEMICONDUCTOR WAFER EVALUATION DEVICE, AND PROBE FOR SEMICONDUCTOR EVALUATION DEVICE - Provided is a semiconductor wafer evaluation method of performing an evaluation of electrical characteristics of a semiconductor wafer by bringing mercury into contact with a surface of the semiconductor wafer, the method including using a probe constituted of a fixed electrode having a tip end portion and a transparent covering portion that covers a portion other than the tip end portion of the fixed electrode, the fixed electrode being made of a metal having stronger wettability with respect to the mercury than the semiconductor wafer and the covering portion, and measuring the electrical characteristics by attaching the mercury to the tip end portion of the fixed electrode and then bringing the mercury into contact with the surface of the semiconductor wafer. | 01-16-2014 |
20140057372 | METHOD FOR ON-WAFER HIGH VOLTAGE TESTING OF SEMICONDUCTOR DEVICES - A method for wafer high voltage testing of semiconductor devices is disclosed. The method involves adding a patterning layer onto a passivation layer of the semiconductor devices and then etching vias through the passivation layer to expose conductive test points. Testing of the semiconductor devices begins with engaging the conductive test points with high voltage test probes of a testing apparatus and then applying a high voltage test sequence to the conductive test points via the high voltage test probes. The testing of the semiconductor devices concludes by disengaging the high voltage test probes from a last one of the semiconductor devices and then removing the patterning layer from the passivation layer of the semiconductor devices. | 02-27-2014 |
20140065738 | LEAKAGE MEASUREMENT OF THROUGH SILICON VIAS - A method of testing a semiconductor substrate having through substrate vias for current leakage which includes: forming a current leakage measurement structure that includes substrate contacts, sensing circuits to sense current leakage from the through substrate vias, the sensing circuits connected to the through substrate vias and to the substrate contacts so that there is a one-to-one correspondence of a substrate contact and sensing circuit to each through substrate via, and a built-in self test (BIST) engine to sense one of the through substrate vias for current leakage. A reference current is applied to the sensing circuits to set a current leakage threshold for the through substrate vias. A through substrate via is selected for sensing for current leakage. The sensing circuit senses the selected through substrate via to determine whether there is current leakage from the selected through substrate via. | 03-06-2014 |
20140127839 | METHOD FOR SEPARATING AND TRANSFERRING IC CHIPS - A method for separating a multiple number of semiconductor devices or semiconductor integrated circuits from a wafer on which the multiple number of semiconductor devices or semiconductor integrated circuits are formed is provided. The method includes: forming, on a surface of the wafer, a mask layer through which a line-shaped pattern to be removed for separating the semiconductor devices or semiconductor integrated circuits is exposed; and etching the exposed pattern to a depth equal to or larger than about ⅔ of a thickness of the wafer. The line-shaped pattern is formed so as to prevent a test device formed on a gap between the semiconductor devices or semiconductor integrated circuits from remaining on separated semiconductor devices or semiconductor integrated circuits. | 05-08-2014 |
20140206114 | CONTACT RESISTANCE TEST STRUCTURE AND METHOD SUITABLE FOR THREE-DIMENSIONAL INTEGRATED CIRCUITS - A contact resistance test structure, a method for fabricating the contact resistance test structure and a method for measuring a contact resistance while using the contact resistance test structure are all predicated upon two parallel conductor lines (or multiples thereof) that are contacted by one perpendicular conductor line absent a via interposed there between. The test structure and related methods are applicable within the context of three-dimensional integrated circuits. | 07-24-2014 |
20140295584 | LOW ENERGY COLLIMATED ION MILLING OF SEMICONDUCTOR STRUCTURES - A method of delayering a surface of a semiconductor structure may include applying a voltage in the range of about 50 eV to less than 300 eV to an inductively coupled Argon ion source operating at a radio frequency. A collimated ion beam incident on the surface of the semiconductor structure may be generated, from the Argon ion source, for the planar removal of layers of the surface. A structural material underlying the surface of the semiconductor structure is exposed using an end-point detector based on the planar removal of the layers. | 10-02-2014 |
20140329345 | MANUFACTURING METHOD OF ORGANIC LIGHT EMITTING DIODE DISPLAY - A manufacturing method of an organic light emitting diode (OLED) display includes manufacturing a mother substrate including a plurality of panels formed with a plurality of anodes for each pixel and a test pad connected to each anode of the panel. The method further includes loading the mother substrate into a plasma chamber and applying a plasma voltage to the test pad of the mother substrate to perform a plasma surface treatment process. The test pad is applied with a different plasma voltage for each pixel. | 11-06-2014 |
20150044789 | METHOD OF MANUFACTURING ELEMENT SUBSTRATE - A method of manufacturing an array substrate | 02-12-2015 |
20150140697 | TEST MACRO FOR USE WITH A MULTI-PATTERNING LITHOGRAPHY PROCESS - A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro having a first and second gate region during a first step of MPLP, and forming a first and second source/drain regions in the active area during a second step of the MPLP. The method also includes forming a first contact connected to the first gate region, a second contact connected to the second gate region, a third contact connected to the first source/drain region, and a forth contact connected to the source/drain region and determining if an overlay shift occurred between the first step and the second step of the step of the MPLP by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact. | 05-21-2015 |
20150140698 | TEST MACRO FOR USE WITH A MULTI-PATTERNING LITHOGRAPHY PROCESS - A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro having a first and second gate region during a first step of MPLP, and forming a first and second source/drain regions in the active area during a second step of the MPLP. The method also includes forming a first contact connected to the first gate region, a second contact connected to the second gate region, a third contact connected to the first source/drain region, and a forth contact connected to the source/drain region and determining if an overlay shift occurred between the first step and the second step of the step of the MPLP by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact. | 05-21-2015 |
20150340295 | Space and Cost Efficient Incorporation of Specialized Input-Output Pins on Integrated Circuit Substrates - In some embodiments an Integrated Circuit package includes a plurality of system functional pins, at least one system functional pin depopulation zone, and at least one non-system functional pin located in the at least one functional pin depopulation zone. Other embodiments are described and claimed. | 11-26-2015 |
20150348855 | Method of Manufacturing a Semiconductor Device - The present invention supplies a manufacturing method of a semiconductor device, which includes a non-contact inspection process capable of confirming if a circuit or circuit element formed on an array substrate is normally performed and can decrease a manufacturing cost by eliminating wastes to keep a defective product forming. | 12-03-2015 |
20150348857 | SEMICONDUCTOR APPARATUS HAVING TSV AND TESTING METHOD THEREOF - A test method of a semiconductor apparatus before a wafer is ground may include applying voltages to a bump electrically coupled to a through-silicon via (TSV) which is buried in the wafer and a first conductive layer formed to be electrically connected to a rear surface of the TSV, wherein the first conductive layer is withdrawn into an upper surface of the wafer. The method may include measuring a voltage between the bump and the first conductive layer. The method may include comparing the measured voltage to a preset reference voltage. The method may include determining the TSV as a normal TSV in which no fail occurs, according a comparing result, and grinding the wafer to expose the rear surface of the TSV. | 12-03-2015 |
20160020269 | Metal Insulator Metal Capacitor and Method for Making the Same - A semiconductor device includes one or more metal-insulator-metal (MiM) capacitors. The semiconductor device includes a bottom electrode, a dielectric layer located above, and in physical contact with, the bottom electrode, a top electrode located above, and in physical contact with, the dielectric layer, a first top contact contacting the top electrode, a first bottom contact contacting the bottom electrode from a top electrode direction, a first metal bump connecting to the top contact, and a second metal bump connecting to the bottom contact. The top electrode has a smaller area than the bottom electrode. The bottom electrode, the dielectric layer, and the top electrode is a MiM capacitor. Top electrodes of a number of MiM capacitors and bottom electrodes of a number of MiM capacitors are daisy chained to allow testing of the conductivity of the electrodes. | 01-21-2016 |
20160093541 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor package includes providing a semiconductor chip including a circuit pattern, a connection pad, a first test pad and a second test pad, each of the connection pad, the first test pad and the second test pad respectively electrically connected to the circuit pattern, evaluating electrical characteristics of the semiconductor chip by applying a first test voltage to the first test pad and a second test voltage to the second test pad, the second test voltage being higher than the first test voltage, and electrically disconnecting the second test pad from the circuit pattern. | 03-31-2016 |
20160133585 | CHIP USING TRIPLE PAD CONFIGURATION AND PACKAGING METHOD THEREOF - A chip includes a core layer, at least one redistribution layer formed on the core layer, and at least one triple pad connected to a pad of the core layer through the at least one redistribution layer or at least one via connected to the at least one redistribution layer. The at least one triple pad includes a bonding pad, a redistribution layer pad connected to the at least one redistribution layer, and a test pad configured to perform a wafer level test. The bonding pad, the redistribution layer pad and the test pad are connected to one another through the at least one redistribution layer, and the test pad is disposed in a core area that overlaps the core layer. | 05-12-2016 |
20160254200 | Method for Detecting a Crack in a Semiconductor Body of a Semiconductor Component | 09-01-2016 |
20180025950 | TOP CONTACT RESISTANCE MEASUREMENT IN VERTICAL FETS | 01-25-2018 |