Class / Patent application number | Description | Number of patent applications / Date published |
438011000 | Utilizing integral test element | 8 |
20080220544 | METHOD FOR UTILIZING HEAVILY DOPED SILICON FEEDSTOCK TO PRODUCE SUBSTRATES FOR PHOTOVOLTAIC APPLICATIONS BY DOPANT COMPENSATION DURING CRYSTAL GROWTH - A method for using relatively low-cost silicon with low metal impurity concentration by adding a measured amount of dopant before and/or during silicon crystal growth so as to nearly balance, or compensate, the p-type and n-type dopants in the crystal, thereby controlling the net doping concentration within an acceptable range for manufacturing high efficiency solar cells. | 09-11-2008 |
20080248600 | METHOD AND DEVICE FOR WAFER BACKSIDE ALIGNMENT OVERLAY ACCURACY - A method for wafer backside alignment overlay accuracy includes forming a buried layer on a front-side of a wafer; forming a conductive layer on the buried layer and patterning a first test structure and a second test structure therein; forming an etch stop layer on the conductive layer; etching through the wafer from the backside to perform an alignment process with the first test structure; and determining an overlay accuracy of the alignment process with the second test structure. The first test structure includes an optical vernier and the second test structure includes an electrical testing structure. | 10-09-2008 |
20090035881 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A burn-in input signal input to a burn-in circuit is delivered to an internal circuit through a selector. In response to a control signal from the burn-in circuit, the selector selects either the burn-in input signal or an input signal for operating the internal circuit. In the burn-in test process, a portion of an output signal is monitored to determine the degree of degradation of the internal circuit. | 02-05-2009 |
20090291510 | METHOD FOR CREATING WAFER TEST PATTERN - A method for creating a testing pattern for sampling the sheet resistance of a test wafer for tuning an annealing process includes establishing a center point for the wafer and determining a plurality of sample points having a radial displacement from the center point of the wafer and an angular displacement, the radial displacement of successive sample points decreasing in radial distance from one another as the distance from the center point increases and the angular displacement between each successive sample point being constant. | 11-26-2009 |
20140356985 | TEMPERATURE CONTROLLED SUBSTRATE SUPPORT ASSEMBLY - A temperature controlled substrate support assembly used for processing a substrate in a vacuum chamber of a semiconductor processing apparatus. The substrate support assembly comprises a top plate for supporting the substrate. A base plate is disposed below the top plate wherein the base plate comprises a cavity in an upper surface of the base plate. A cover plate is disposed between the top plate and the base plate. At least one thermoelectric module is in the cavity in the upper surface of the base plate wherein the at least one thermoelectric module is in thermal contact with the top plate and the base plate, and the at least one thermoelectric module is maintained at atmospheric pressure. | 12-04-2014 |
20150336207 | ELECTRONIC COMMUNICATIONS DEVICE WITH ANTENNA AND ELECTROMAGNETIC SHIELD - An electronic communications device includes a body of semiconductor material with an integrated electronic circuit, an inductive element, and a capacitive element. The capacitive element is formed by a first electrode and a second electrode positioned between the inductive element and the integrated electronic circuit. Tuning of the device circuitry is accomplished by energizing the inductive/capacitive elements, determining resonance frequency, and using a laser trimming operation to alter the structure of one or more of the first electrode, second electrode or inductive element and change the resonance frequency. | 11-26-2015 |
20150371913 | INDUCTIVE MONITORING OF CONDUCTIVE TRENCH DEPTH - In fabrication of an integrated circuit having a layer with a plurality of conductive interconnects, a layer of a substrate is polished to provide the layer of the integrated circuit. The layer of the substrate includes conductive lines to provide the conductive interconnects. The layer of the substrate includes a closed conductive loop formed of a conductive material in a trench. A depth of the conductive material in the trench is monitored using an inductive monitoring system and a signal is generated. Monitoring includes generating a magnetic field that intermittently passes through the closed conductive loop. A sequence of values over time is extracted from the signal, the sequence of values representing the depth of the conductive material over time. | 12-24-2015 |
20160133529 | CIRCUIT AND METHOD FOR MONOLITHIC STACKED INTEGRATED CIRCUIT TESTING - A method for testing a monolithic stacked integrated circuit (IC) is provided. The method includes receiving a layer of the IC. The layer has a first surface and a second surface, and the layer includes a substrate. The method further includes attaching probe pads to the first surface, and applying a first fault testing to the IC through the probe pads. The method further includes forming another layer of the IC over the second surface, and applying a second fault testing to the IC through the probe pads. | 05-12-2016 |