Entries |
Document | Title | Date |
20080227224 | Method of manufacturing semiconductor device and control system - When a multi-layer structure is formed by forming the interconnect trenches or via holes having different patterns in a plurality of insulating films, an anti-reflective film and an upper resist film are stacked in this order over an insulating interlayer, and the anti-reflective film is etched through the upper resist film used as a mask, wherein the anti-reflective film is etched while varying a value of at least one etching condition correlative to Δ(L | 09-18-2008 |
20080233662 | Advanced Process Control for Semiconductor Processing - An advanced process control (APC) method for semiconductor fabrication is provided. A first substrate and a second substrate are provided. The first substrate and the second substrate include a dielectric layer. A first etch process parameter for the first substrate is determined. A trench is etched in the dielectric layer of the first substrate using the first etch process parameter. At least one aspect of the etched trench of the first substrate is measured. A second etch process parameter for the second substrate is determined using the measured aspect of the etched trench of the first substrate. A planarization process parameter for the first substrate is determined also using the measured aspect of the etched trench of the first substrate. | 09-25-2008 |
20080241973 | METHOD OF CORRECTING A MASK PATTERN AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - The method of manufacturing a semiconductor device has deciding an amount of a correction of a mask pattern for a size of an active region of a semiconductor substrate, correcting the mask pattern on the basis of the decided amount of the correction, and exposing a resist film by using an exposure mask having the corrected mask pattern. | 10-02-2008 |
20080248598 | METHOD AND APPARATUS FOR DETERMINING CHARACTERISTICS OF A STRESSED MATERIAL USING SCATTEROMETRY - A method includes illuminating at least a portion of a first grid including a first plurality of stressed material regions formed at least partially in a semiconducting material. Light reflected from the illuminated portion of the first grid is measured to generate a first reflection profile. A characteristic of the first plurality of stressed material regions is determined based on the first reflection profile. A test structure includes a first plurality of stressed material regions recessed with respect to a surface of a semiconductor layer and defining a first grid. A first plurality of exposed portions of the semiconductor layer is disposed between each of the first plurality of stressed material regions. | 10-09-2008 |
20080268554 | FABRICATION METHOD FOR SEMICONDUCTOR DEVICE, EXPOSURE METHOD, PATTERN CORRECTION METHOD AND SEMICONDUCTOR DEVICE - Disclosed herein is a fabrication method for a semiconductor device, including a lithography step of connecting a plurality of mask patterns to each other to form a pattern image of an area greater than the size of the mask patterns. The lithography step includes the steps of: assuring an overlapping exposure region to be exposed in an overlapping relationship by both of two mask patterns to be connected to each other, carrying out exposure transfer of the pattern portions of the two mask patterns to the overlapping exposure region to form a first measurement mark and a second measurement mark in the overlapping exposure region, and carrying out positional displacement measurement of pattern connection by the two mask patterns based on a manner of combination of main marks and sub marks of the measurement marks formed in the overlapping exposure region. | 10-30-2008 |
20080299681 | MULTI-STEP DEPOSITION CONTROL - For providing control of two-step or a multi-step deposition process, a method and a corresponding deposition system is provided comprising providing a deposition process having at least two sub-processes employing different sets of process parameters, wherein each set of process parameters comprises at least one process parameter. The method comprises controllably generating an actual value for at least one first process parameter by taking into account at least one previous value of the respective first process parameter, wherein each first process parameter is a process parameter of said at least two sets of process parameters. | 12-04-2008 |
20080299682 | METHOD FOR REMOVING POLY SILICON - Methods for removing poly silicon. In one example embodiment, a method for removing poly silicon that is formed on a silicon wafer includes the steps of growing the poly silicon as a silicon oxide through a thermal oxidation process and removing the silicon oxide using an etching solution. | 12-04-2008 |
20080305563 | Method and system for controlling copper chemical mechanical polish uniformity - A system and method for controlling resistivity uniformity in a Copper trench structure by controlling the CMP process is provided. A preferred embodiment comprises a system and a method in which a plurality of CMP process recipes may be created comprising at least a slurry arm position. A set of metrological data for at least one layer of the semiconductor substrate may be estimated, and an optimum CMP process recipe may be selected based on the set of metrological data. The optimum CMP process recipe may be implemented on the semiconductor substrate. | 12-11-2008 |
20080305564 | MANUFACTURING APPARATUS FOR SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - A manufacturing apparatus for a semiconductor device, treating a SiN film formed on a wafer with phosphoric acid solution, including a processing bath to store phosphoric acid solution provided for treatment of the wafer, a control unit for calculating integrated SiN etching amount of the phosphoric acid solation, determining necessity of quality adjustment of the phosphoric acid solution, based on correlation between the integrated SiN etching amount calculated and etching selectivity to oxide film, and calculating a quality adjustment amount of the phosphoric acid solution as needed, and also including a mechanism to adjust the quality of the phosphoric acid solution based on the quality adjustment amount calculated. | 12-11-2008 |
20090053835 | VACUUM APPARATUS INCLUDING A PARTICLE MONITORING UNIT, PARTICLE MONITORING METHOD AND PROGRAM, AND WINDOW MEMBER FOR USE IN THE PARTICLE MONITORING - A semiconductor manufacturing apparatus includes a processing chamber for performing a manufacturing processing on a wafer. A gas supply line for introducing a purge gas is connected to an upper portion of the processing chamber, a valve being installed on the gas supply line. A rough pumping line with a valve is connected to a lower portion of the processing chamber. Installed on the rough pumping line are a dry pump for exhausting a gas in the processing chamber and a particle monitoring unit for monitoring particles between the valve and the dry pump. In the semiconductor manufacturing apparatus, after the valve is opened, the purge gas is supplied to apply physical vibration due to shock wave in the processing chamber so that deposits are detached therefrom to be monitored as particles. | 02-26-2009 |
20090068767 | TUNING VIA FACET WITH MINIMAL RIE LAG - A method for designing an etch recipe is provided. An etch is performed, comprising providing an etch gas with a set halogen to carbon ratio, forming a plasma from the etch gas, and etching trenches over via. Via faceting is measured. The halogen to carbon ratio is reset according to the measured via faceting, where the halogen to carbon ratio is increased if too much faceting is measured and the halogen to carbon ratio is decreased if too little faceting is measured. The previous steps are repeated until a desired amount of faceting is obtained. | 03-12-2009 |
20090087929 | METHOD AND SYSTEM FOR IMPROVING WET CHEMICAL BATH PROCESS STABILITY AND PRODUCTIVITY IN SEMICONDUCTOR MANUFACTURING - A chemical processing bath and system used in semiconductor manufacturing utilizes a dynamic spiking model that essentially constantly monitors chemical concentration in the processing bath and adds fresh chemical on a regular basis to maintain chemical concentrations at desirable levels. Etch rates and etch selectivities are maintained at desirable levels and contamination from undesirable precipitation is avoided. The system and method automatically compare concentration levels to a plurality of control limits associated with various technologies and identify the technology or technologies that may undergo processing. | 04-02-2009 |
20090142859 | PLASMA CONTROL USING DUAL CATHODE FREQUENCY MIXING - Methods for processing a substrate in a processing chamber using dual RF frequencies are provided herein. In some embodiments, a method of processing a substrate includes forming a plasma of a polymer forming chemistry to etch a feature into a substrate disposed on a substrate support in a process chamber while depositing a polymer on at least portions of the feature being etched. A low frequency and a high frequency RF signal are applied to an electrode disposed in the substrate support. The method further includes controlling the level of polymer formation on the substrate, wherein controlling the level of polymer formation comprises adjusting a power ratio of the high frequency to the low frequency RF signal. | 06-04-2009 |
20090162951 | Enhanced Endpoint Detection In Non-Volatile Memory Fabrication Processes - A method of fabricating non-volatile memory is provided for memory cells employing a charge storage element with multiple charge storage regions. A first charge storage layer is formed over a tunnel dielectric layer at both a memory array region and an endpoint region of a semiconductor substrate. The first charge storage layer is removed from the endpoint region to expose the tunnel dielectric region. A second charge storage layer is formed over the first charge storage layer at the memory array region and over the tunnel dielectric layer at the endpoint region. When etching the second charge storage layer to form the stem regions of the memory cells, the tunnel dielectric layer provides a detectable endpoint signal to indicate that etching for the second charge storage layer is complete. | 06-25-2009 |
20090176320 | METHOD FOR FABRICATION OF FLOATING GATE IN SEMICONDUCTOR DEVICE - A method for manufacturing a floating gate includes: forming a tunnel oxide film on a semiconductor substrate; forming a polysilicon layer on a surface of the tunnel oxide film; forming a photosensitive film pattern on a surface of the polysilicon layer; depositing a by-product on the photosensitive film to generate a by-product mask; and using the by-product mask as an etching mask to etch the polysilicon layer, completing fabrication of the floating gate. The polysilicon layer may be etched by a simplified process using a by-product mask so as to fabricate the floating gate, the etch rate of the polysilicon layer may be increased to improve productivity, poly bridge problems may be eliminated, and total amount of a gas used in etching the polysilicon layer may be reduced, resulting in an increase in hardware margin and a decrease in the amount of the gas used in this method. | 07-09-2009 |
20090197353 | METHOD OF MANUFACTURING MATERIAL TO BE ETCHED - A method is provided, of manufacturing a material to be etched that can more preferably prevent a region to be etched from remaining as an un-etched region and reduce deviation of etched/un-etched regions. | 08-06-2009 |
20090239314 | Methods of Manufacturing a Semiconductor Device - Methods of manufacturing a semiconductor device and an apparatus for the manufacturing of semiconductor devices are provided. An embodiment regards providing a process which changes the volume of at least one layer of a semiconductor substrate or of at least one layer deposited on the semiconductor substrate, and measuring a change in volume of such at least one layer using fluorescence. In another embodiment, a change in volume of such at least one layer is measured using reflection of electromagnetic waves. | 09-24-2009 |
20090305439 | METHOD FOR CORRECTING MASK PATTERN AND METHOD FOR MANUFACTURING ACCELERATION SENSOR AND ANGULAR VELOCITY SENSOR BY USING THE METHOD FOR CORRECTING THE MASK PATTERN - A method for correcting a mask pattern used for dry-etching an object with higher accuracy, and for manufacturing an acceleration sensor and an angular velocity sensor. The object is first etched by a dry-etching process using an uncorrected reference mask pattern. Then, distribution of the size of expansion of a tapered portion formed in a surface of the object is measured. Thereafter, the measured distribution is approximated by using a quadratic curve (Y=AX | 12-10-2009 |
20090311808 | METHOD FOR PRODUCING SEMICONDUCTOR WAFER - A semiconductor wafer is produced by a method comprising a slicing step, an one-side polishing step and a chemical treating step, in which the kerf loss is reduced and the flatness is improved. | 12-17-2009 |
20100029020 | SUBSTRATE PROCESSING CONTROL METHOD AND STORAGE MEDIUM - In a substrate processing control method, a first process acquires a first-reflectance-spectrum of a beam reflected from the first-fine-structure and a second-reflectance-spectrum of a beam reflected from the second-fine-structure for each of varying-pattern-dimensions of the first-fine-structure when the pattern-dimension of the first-fine-structure is varied. A second process acquires reference-spectrum-data for each of the varying-pattern-dimensions of the first-fine-structure by overlapping the first-reflectance-spectrum with the second-reflectance-spectrum. A third process actually measures beams reflected from the first and the second-fine-structure, respectively, after irradiating light beam on to the substrate and acquiring reflectance-spectrums of the actual-measured beams as actual-measured spectrum data. A fourth process compares the actual-measured spectrum data with the respective reference-spectrum data and acquiring, as the measured pattern-dimension, one of the varying-pattern-dimensions corresponding to reference-spectrum data that is closely matches with the actual-measured spectrum data. A final process ends the processing of the substrate if the measured pattern-dimension reaches a value. | 02-04-2010 |
20100129939 | USING OPTICAL METROLOGY FOR WITHIN WAFER FEED FORWARD PROCESS CONTROL - A method of controlling the polishing of a substrate includes polishing a substrate on a first platen using a first set of parameters, obtaining first and second sequences of measured spectra from first and second regions of the substrate with an in-situ optical monitoring system, generating first and second sequences of values from the first and second sequences of measured spectra, fitting first and second linear functions to the first and second sequences of values, determining a difference between the first linear function and the second linear function, adjusting at least one parameter of a second set of parameters based on the difference, and polishing the substrate on a second platen using the adjusted parameter. | 05-27-2010 |
20100216259 | WET PROCESSING SYSTEM, WET PROCESSING METHOD AND STORAGE MEDIUM - A wet processing system detects a globule of a process solution in a drippy or dripping state from the tip of any one of process solution pouring nozzles being moved to a pouring position for pouring the process solution onto a substrate by obtaining image data on the process solution pouring nozzle, and takes proper measures to prevent the process solution from dripping. A wet processing system | 08-26-2010 |
20110014726 | METHOD OF FORMING SHALLOW TRENCH ISOLATION STRUCTURE - A method for forming a shallow trench isolation (STI) structure with a predetermined target height is provided. A substrate having a pad oxide layer formed on the substrate is provided. A nitride-containing layer with a thickness is formed on the pad oxide. A STI structure is formed and extends through the nitride-containing layer, the pad oxide layer, into the substrate. The thickness of the nitride-containing layer is measured to calculate the height of STI structure according to a correlation between the thickness of the nitride-containing layer and the height of STI structure. A thickness of the top portion STI structure to be removed is determined according to the difference between the height of the STI structure and the predetermined target height and is removed in a first etching process. The nitride-containing layer is removed without etching the STI structure or the pad oxide layer in a second etching process. | 01-20-2011 |
20110151594 | METHOD AND SYSTEM FOR CONTROLLED ISOTROPIC ETCHING ON A PLURALITY OF ETCH SYSTEMS - A method for forming identical isotropic etch patterns in an etch system is disclosed. The method comprises providing a wafer paddle, a wafer, a plurality of identical etch systems, utilizing identical etch recipes within each of the plurality of etch systems, providing a fixed temperature stability time FTST for each system so that the heat transfer from the paddle to the wafer is constant, wherein the FTST is the same on each of the plurality of etch systems; and utilizing the plurality of identical etch systems to produce identical etches on each of the wafers based upon the FTST, wherein a five-second preheat step in the etch process is not utilized. | 06-23-2011 |
20110183444 | METHOD FOR ELECTRON BEAM INDUCED ETCHING - The invention relates to a method for electron beam induced etching of a material ( | 07-28-2011 |
20110195528 | POLISHING SYSTEM WITH IN-LINE AND IN-SITU METROLOGY - A computer-implemented method for process control in chemical mechanical polishing in which an initial pre-polishing thickness of a substrate is measured at a metrology station, a parameter of an endpoint algorithm is determined from the initial thickness of the substrate, a substrates is polished at a polishing station, and polishing stops when an endpoint criterion is detected using the endpoint algorithm. | 08-11-2011 |
20110212548 | METHOD FOR SEMICONDUCTOR GATE HARDMASK REMOVAL AND DECOUPLING OF IMPLANTS - A method is provided for fabricating a semiconductor device having implanted source/drain regions and a gate region, the gate region having been masked by the gate hardmask during source/drain implantation, the gate region having a polysilicon gate layered on a metal layered on a high-K dielectric layer. The gate region and the source/drain regions may be covered with a self planarizing spin on film. The film may be blanket etched back to uncover the gate hardmask while maintaining an etched back self planarizing spin on film on the implanted source/drain regions. The gate hardmask may be etched back while the etched back film remains in place to protect the implanted source/drain regions. The gate region may be low energy implanted to lower sheet resistance of the polysilicon layer. The etched back film may be then removed. | 09-01-2011 |
20110256644 | MASKS FOR MICROLITHOGRAPHY AND METHODS OF MAKING AND USING SUCH MASKS - Masks for microlithography apparatus, methods for making such masks, and methods for exposing photosensitive materials to form arrays of microfeatures on semiconductor wafers using such masks. In one embodiment, a method of making a mask comprises forming a mask layer on a substrate and identifying a first opening in the mask layer corresponding to a first feature site at which an intensity of the radiation at a focal zone is less than the intensity of the radiation at the focal zone for a second feature site corresponding to a second opening in the mask. The second opening is adjacent or at least proximate the first opening. The method can further include forming a first surface at the first opening and a second surface at the second opening such that radiation passing through the second opening constructively interferes with radiation passing through the first opening at the focal zone. | 10-20-2011 |
20110275168 | SINGLE STEP CMP FOR POLISHING THREE OR MORE LAYER FILM STACKS - A one-step CMP process for polishing three or more layer film stacks on a wafer having a multilayer film stack thereon including a silicon nitride (SiNx) layer on its semiconductor surface, and a silicon oxide layer on the SiNx layer, wherein trench access vias extend through the silicon oxide layer and SiNx layer to trenches formed into the semiconductor surface, and wherein a polysilicon layer fills the trench access vias, fills the trenches, and is on the silicon oxide layer. CMP polishes the multilayer film stack with a slurry including slurry particles including at least one of silica and ceria. The CMP provides a removal rate (RR) for the polysilicon layer>a RR for the silicon oxide layer>a RR for the SiNx layer. The CMP process is continued to remove the polysilicon layer, silicon oxide layer and a portion of the SiNx layer to stop on the SiNx layer. Optical endpointing during CMP can provide a predetermined remaining thickness range for the SiNx layer. | 11-10-2011 |
20110318849 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - The semiconductor device of the present invention includes a first insulating film on a substrate having a first region and a second region, a light shielding film formed in the first region and an interconnect film formed in the second region in the first insulating film and a second insulating film having a first concave portion above the light shielding film in the first region and an interconnect hole having a via hole and a second concave portion in the second region in the second insulating film on the first insulating film, wherein an area of the light shielding film is overlapping an area of the first plurality of concave portions. | 12-29-2011 |
20120003759 | ENDPOINT CONTROL DURING CHEMICAL MECHANICAL POLISHING BY DETECTING INTERFACE BETWEEN DIFFERENT LAYERS THROUGH SELECTIVITY CHANGE - Embodiments described herein relate to methods of detecting an endpoint for a target substrate during chemical mechanical polishing process. In one embodiment, the method includes polishing one or more target substrates at a first film removal rate to provide reference spectra, polishing one or more target substrates at a second film removal rate to provide current spectra of the one or more target substrates, wherein the second film removal rate is different from the first film removal rate, identifying an interface transition between different layers formed on the one or more target substrates using a sequence of endpoint values obtained based on the reference spectra collected during polishing of the one or more reference substrates, and comparing each current spectrum obtained from current spectra of the one or more target substrates to the reference spectra to obtain the sequence of endpoint values. After identifying the interface transition between different layers formed on the one or more target substrates, the one or more target substrates is optionally overpolished to past a target polishing thickness. | 01-05-2012 |
20120009690 | IN-SITU SPECTROMETRY - The present disclosure provides a system for in-situ spectrometry. The system includes a wafer-cleaning machine that cleans a surface of a semiconductor wafer using a cleaning solution. The system also includes a spectrometry machine that is coupled to the wafer-cleaning machine. The spectrometry machine receives a portion of the cleaning solution from the wafer-cleaning machine. The portion of the cleaning solution collects particles from the wafer during the cleaning. The spectrometry machine is operable to analyze a particle composition of a portion of the wafer based on the portion of the cleaning solution, while the wafer remains in the wafer-cleaning machine during the particle composition analysis. | 01-12-2012 |
20120028377 | USING OPTICAL METROLOGY FOR WITHIN WAFER FEED FORWARD PROCESS CONTROL - A method of controlling the polishing of a substrate includes polishing a substrate on a first platen using a first set of parameters, obtaining first and second sequences of measured spectra from first and second regions of the substrate with an in-situ optical monitoring system, generating first and second sequences of values from the first and second sequences of measured spectra, fitting first and second linear functions to the first and second sequences of values, determining a difference between the first linear function and the second linear function, adjusting at least one parameter of a second set of parameters based on the difference, and polishing the substrate on a second platen using the adjusted parameter. | 02-02-2012 |
20120094401 | METHODS OF PROCESSING AND INSPECTING SEMICONDUCTOR SUBSTRATES - A method of inspecting a semiconductor substrate having a back surface and including at least one piece of metal embedded in the substrate comprises directing measuring light towards the back surface of the substrate and detecting a portion of the measuring light received back from the substrate. The method also includes determining a distance between the piece of metal and the back surface based upon the detected measuring light received back from the substrate. | 04-19-2012 |
20120122249 | DOPANT MARKER FOR PRECISE RECESS CONTROL - A semiconductor device is formed by implanting recess markers in a material during deposition and using the recess markers during etching of the material for precise in-situ removal rate definition and removal homogeneity-over-radius definition. An embodiment includes depositing a layer of material on a substrate, implanting first and second dopants in the material at first and second predetermined times during deposition of the material, etching the material, detecting the depths of the first and second dopants during etching, calculating the removal rate of the material in situ from the depths of the first and second dopants, and determining from the removal rate a stop position for etching. Embodiments further include depositing a layer of material on a substrate, laterally implanting a first dopant and a second dopant in the material at a predetermined depth during deposition of the material, etching the material, detecting the positions and intensities of the first and second dopants during etching, and calculating lateral homogeneity of the material in situ from the intensities of the first and second dopants. Embodiments further include in situ corrective action for the removal process based on the determined removal rate and lateral homogeneity. | 05-17-2012 |
20120202301 | METHOD OF FORMING MASK PATTERN - A disclosed method of forming a mask pattern includes forming a first resist film on a film to be etched, opening portions on the first resist film at a predetermined pitch, a first film on the first resist film so as to cover sidewalls of the first opening portions, a second resist film, second opening portions alternately arranged with the first opening portions on the second resist film, and a second film on the second resist film so as to cover sidewalls of the second opening portions, and removing a part of the second film so that the second film is left as first sidewall portions, a part of the first resist film using the first sidewall portions as a mask to form third opening portions, and a part of the first film while leaving the first film as second sidewall portions to form fourth opening portions. | 08-09-2012 |
20120264237 | METHODS FOR DESIGNING, FABRICATING, AND PREDICTING SHAPE FORMATIONS IN A MATERIAL - A method for designing, fabricating, and predicting a desired structure in and/or on a host material through defining etch masks and etching the host material is provided. The desired structure can be micro- or nanoscale structures, such as suspended nanowires and corresponding supporting pillars, and can be defined one layer at a time. Arbitrary desired structures can also be defined and obtained through etching. Further, given the desired structure, a starting structure can be predicted where etching of the starting structure yields the desired structure. | 10-18-2012 |
20120282712 | DOPANT MARKER FOR PRECISE RECESS CONTROL - Recess markers are implanted in a material during deposition and used during etching of the material for in-situ removal rate and removal homogeneity-over-radius definitions. An embodiment includes depositing a material on a substrate, implanting two dopants at two predetermined times, respectively, during deposition of the material, etching the material, detecting depths of the two dopants during etching, calculating the removal rate of the material in situ from the depths of the two dopants, and determining from the removal rate an etching stop position. Embodiments further include laterally implanting two dopants in a material at a predetermined depth during deposition, etching the material, detecting the positions and intensities of the two dopants during etching, and calculating lateral homogeneity of the material in situ from intensities of the dopants. Embodiments further include in situ corrective action for the removal process based on the determined removal rate and lateral homogeneity. | 11-08-2012 |
20120282713 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SYSTEM FOR MANUFACTURING SEMICONDUCTOR DEVICE - A target space ratio of a monitor pattern on a substrate for inspection is determined to be different from a ratio of 1:1. A range of space ratios in a library is determined to include the target space ratio and not include a space ratio of 1:1. The monitor pattern is formed on a film to be processed by performing predetermined processes on the substrate for inspection. Sizes of the monitor pattern are measured. The sizes of the monitor pattern are converted into sizes of a pattern of the film to be processed having a space ratio of 1:1, and processing conditions of the predetermined processes are compensated for based on the sizes of the converted pattern of the film to be processed. After that, the predetermined processes are performed on a wafer under the compensated conditions to form a pattern having a space ratio of 1:1 on the film to be processed. | 11-08-2012 |
20130011938 | METHOD FOR MANUFACTURING THROUGH-SILICON VIA - A method for manufacturing TSVs, wherein the method comprises several steps as follows: A stack structure having a substrate and an ILD layer (inter layer dielectric layer) is provided, in which an opening penetrating through the ILD layer and further extending into the substrate is formed. After an insulator layer and a metal barrier layer are formed on the stack structure and the sidewalls of the opening, a top metal layer is then formed on the stack structure to fulfill the opening. A first planarization process stopping on the barrier layer is conducted to remove a portion of the top metal layer. A second planarization process stopping on the ILD layer is subsequently conducted to remove a portion of the metal barrier layer, a portion of the insulator layer and a portion of the top metal layer, wherein the second planarization process has a polishing endpoint determined by a light interferometry or a motor current. | 01-10-2013 |
20130029436 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A hard mask made of a material in which the pattern precision is degraded by oxidation, a protective film, which protects the hard mask film from oxidation, a first mask film and a first organic film are sequentially stacked. The first organic film is processed into a first pattern, and the first mask film is firstly etched using the patterned the first organic film as a mask. After the first organic film is removed, a second organic film is formed. The second organic film is processed into a second pattern. The first mask film is secondary etched using the patterned second organic film as a mask so that the surface of the first mask film is exposed but the surface of the protective film is not exposed, thereby selectively patterning only the first mask film. After that, when removing the residual second organic film by ashing, it is possible to ensure the function of the protective film that protects the hard mask film from oxidation. | 01-31-2013 |
20130034918 | MONITORING APPARATUS AND METHOD FOR IN-SITU MEASUREMENT OF WAFER THICKNESSES FOR MONITORING THE THINNING OF SEMICONDUCTOR WAFERS AND THINNING APPARATUS COMPRISING A WET ETCHING APPARATUS AND A MONITORING APPARATUS - According to the invention, a monitoring device ( | 02-07-2013 |
20130065328 | FOCUS CONTROL METHOD FOR PHOTOLITHOGRAPHY - A method comprises providing a semiconductor substrate having at least one layer of a material over the substrate. A sound is applied to the substrate, such that a sound wave is reflected by a top surface of the layer of material The sound wave is detected using a sensor. A topography of the top surface is determined based on the detected sound wave. The determined topography is used to control an immersion lithography process. | 03-14-2013 |
20130130409 | ETCH RATE DETECTION FOR REFLECTIVE MULTI-MATERIAL LAYERS ETCHING - A method and apparatus for etching a photomask substrate with enhanced process monitoring, for example, by providing for optical monitoring at different regions of the photomask to obtain desired etch rate or thickness loss is provided. In one embodiment, the method includes performing an etching process on a reflective multi-material layer that includes at least one molybdenum layer and one silicon layer through a patterned mask, directing radiation having a wavelength from about 170 nm and about 800 nm to an area of the multi-material layer uncovered by the patterned mask, collecting an optical signal reflected from the area uncovered by the patterned mask, analyzing a waveform obtained from the reflected optical signal, and determining a first endpoint of the etching process when an intensity of the reflected optical signal is between about 60 percent and about 90 percent less than an initial reflected optical signal. | 05-23-2013 |
20130183773 | CONTROL OVER HYDROGEN FLUORIDE LEVELS IN OXIDE ETCHANT - The invention is directed towards methods and compositions for identifying the amount of hydrofluoric acid in a buffered oxide etching composition. In buffered oxide etching compositions it is very difficult to measure the amount of hydrofluoric acid because it has varying equilibriums and it is toxic so it hard to handle and sample. When used to manufacture microchips however, incorrect amounts of hydrofluoric acid will ruin those chips. The invention utilizes a unique method of spectrographically measuring the hydrofluoric acid when in contact with added chromogenic agents to obtain exact measurements that are accurate, immediate, and safe. | 07-18-2013 |
20130189801 | ADVANCED FINISHING CONTROL - A finishing operation for a workpiece involves supplying an organic boundary lubricant to an operative finishing interface located between a finishing apparatus finishing element finishing surface and a surface of the workpiece being finished, and sensing in situ finishing information with an operative sensor. A change for a process control parameter is determined using the in situ finishing information, information from metrology equipment operatively coupled to the finishing apparatus, and information related to the finishing apparatus. An operative controller thereafter changes the process control parameter to change a processing control at least in part related to the finishing operation. | 07-25-2013 |
20130210172 | WAFER THINNING APPARATUS HAVING FEEDBACK CONTROL AND METHOD OF USING - A wafer thinning apparatus includes a first metrology tool configured to measure an initial thickness of the wafer. The wafer thinning apparatus further includes a controller connected to the first metrology tool, and configured to determine a polishing time based on the initial thickness, a predetermined thickness and a material removal rate. The wafer thinning apparatus further includes a polishing tool connected to the controller configured to polish the wafer for a period of time equal to the polishing time. The wafer thinning apparatus includes a second metrology tool connected to the controller and the polishing tool, and configured to measure a polished thickness. The controller is configured to update the material removal rate based on the polished thickness, the predetermined thickness and the polishing time. | 08-15-2013 |
20130224890 | Feedback Control Using Detection Of Clearance And Adjustment For Uniform Topography - A method of controlling polishing includes storing a desired ratio representing a ratio for a clearance time of a first zone of a substrate to a clearance time of a second zone of the substrate. During polishing of a first substrate, an overlying layer is monitored, a sequence of measurements is generated, and the measurements are sorted a first group associated with the first zone of the substrate and a second group associated with the second zone on the substrate. A first time and a second time at which the overlying layer is cleared is determined based on the measurements from the first group and the second group, respectively. At least one adjusted polishing pressure is calculated for the first zone based on a first pressure applied in the first zone during polishing the first substrate, the first time, the second time, and the desired ratio. | 08-29-2013 |
20130316470 | METHOD WHICH CAN FORM CONTACT HOLES IN WAFER OF SEMICONDUCTOR - The present invention relates to the field of semiconductor integrated circuits, and particularly relates to a method which can form a contact hole in a wafer of semiconductor material. The invention has proposed a method which can form a contact hole in a wafer of semiconductor: measuring and comparing a Critical Dimension (CD) of a position corresponding to the contact hole in the hard mask with the CD required in the technology, and then, based on the measurement, adjusting the CD of the position corresponding to the contact hole in the hard mask, by conformal deposition or etching technology, to fit a requirement of the technology; the method can reduce process costs while improving production capacity. | 11-28-2013 |
20130344625 | ENDPOINTING DETECTION FOR CHEMICAL MECHANICAL POLISHING BASED ON SPECTROMETRY - Methods and apparatus for spectrum-based endpointing. An endpointing method includes selecting a reference spectrum. The reference spectrum is a spectrum of white light reflected from a film of interest on a first substrate and has a thickness greater than a target thickness. The reference spectrum is empirically selected for particular spectrum-based endpoint determination logic so that the target thickness is achieved when endpoint is called by applying the particular spectrum-based endpoint logic. The method includes obtaining a current spectrum. The current spectrum is a spectrum of white light reflected from a film of interest on a second substrate when the film of interest is being subjected to a polishing step and has a current thickness that is greater than the target thickness. The method includes determining, for the second substrate, when an endpoint of the polishing step has been achieved. The determining is based on the reference and current spectra. | 12-26-2013 |
20140011303 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is disclosed. The method may comprise: forming a gate stack on a substrate; depositing a first dielectric layer and a second dielectric layer sequentially on the substrate and the gate stack; and etching the second dielectric layer and the first dielectric layer sequentially with an etching gas containing helium to form a second spacer and a first spacer, respectively. According to the method disclosed herein, a dual-layer complex spacer configuration is achieved, and two etching operations where the etching gas comprises the helium gas are performed. As a result, it is possible to reduce damages to the substrate and also to reduce the process complexity. Further, it is possible to optimize a threshold voltage, effectively reduce an EOT, and enhance a gate control capability and a driving current. | 01-09-2014 |
20140038316 | EXAMINATION OF A SILICON SUBSTRATE FOR A SOLAR CELL - The invention relates to a method for examining a wire-sawn silicon substrate for a solar cell. The method includes irradiating the silicon substrate with an infrared radiation, detecting the infrared radiation transmitted through the silicon substrate, and analyzing the detected infrared radiation for characterizing the crystal orientation of the silicon substrate. The invention in addition relates to a device for carrying out such a method, and a method for manufacturing a solar cell. | 02-06-2014 |
20140065732 | SEMICONDUCTOR MANUFACTURING PROCESS SYSTEM AND METHOD - According to one embodiment, a wafer processing device includes a processed number counting unit that counts a number of processed wafers, and a maintenance post-processing unit that executes a dummy lot process and a QC lot process after a maintenance process. A wafer preparation device prepares the dummy lot and the QC lot, when a first processed number is counted by the processed number counting unit. When a second processed number is counted by the processed number counting unit, a carrier device carries the dummy lot and the QC lot to the wafer processing device simultaneous with the maintenance process, before the maintenance process is completed. | 03-06-2014 |
20140065733 | DISCRETE SAMPLING BASED NONLINEAR CONTROL SYSTEM - System, method and computer program product for configuring and controlling a facility to perform a manufacturing process and updating a tool controlling the process according to a model employed for mapping calculated coefficients that characterize non-linear variations observed of a product to actual control parameters governing the processes/tools used by the facility during the manufacturing process. The method enables real-time control of variation in an exposure step of a patterning process using an exposure tool to minimize a nonlinear variation in one or more pattern attributes by adjusting the exposure tool or the patterning process corresponding to the calculated coefficients. In the method, measurements of product attributes, obtained by finite sampling over a well defined domain, are projected onto a predefined reference mesh spanning the domain, using a physically based model comprised of functions constructed to be orthogonal and normalized over a discrete set of reference mesh locations. | 03-06-2014 |
20140080232 | PEAK-BASED ENDPOINTING FOR CHEMICAL MECHANICAL POLISHING - A polishing system receives one or more target parameters for a selected peak in a spectrum of light, polishes a substrate, measures a current spectrum of light reflected from the substrate while the substrate is being polished, identifies the selected peak in the current spectrum, measures one or more current parameters of the selected peak in the current spectrum, compares the current parameters of the selected peak to the target parameters, and ceases to polish the substrate when the current parameters and the target parameters have a pre defined relationship. | 03-20-2014 |
20140099737 | Method for Monitoring Contact Hole Etching Process of TFT Substrate - The present invention provides a method for monitoring a contact hole etching process of a TFT substrate, which includes: ( | 04-10-2014 |
20140106475 | METHOD FOR ETCHING POLYSILICON GATE - A method for etching a polysilicon gate is disclosed, wherein the polysilicon gate includes an undoped polysilicon portion and a doped polysilicon portion that is situated on the undoped polysilicon portion. The method includes: obtaining a thickness of the undoped polysilicon portion and a thickness of the doped polysilicon portion by using an optical linewidth measurement device; and etching the undoped polysilicon portion and the doped polysilicon portion by using two respective steps with different parameters, respective etching time for the undoped polysilicon portion and the doped polysilicon portion of every wafer being adjusted in real time by using an advanced process control system. This method enables the doped and undoped polysilicon portions of each polysilicon gate on every wafer to have substantially consistent profiles between each other. | 04-17-2014 |
20140147942 | MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a memory device includes a nanomaterial assembly layer, a first electrode layer and a second electrode layer. The nanomaterial assembly layer is formed of an assembly of a plurality of micro conductors via gaps between the micro conductors. The first electrode layer is provided on the nanomaterial assembly layer. The second electrode layer is provided on the first electrode layer. | 05-29-2014 |
20140242730 | SPECTRAPHIC MONITORING BASED ON PRE-SCREENING OF THEORETICAL LIBRARY - An optical model for a layer stack has a plurality of input parameters, the plurality of input parameters defining a parameter space. A plurality of model spectra are generated by calculating a model spectrum using the optical model for each of a first plurality of different points in the parameter space. A test spectrum of a test substrate is measured. For each model spectrum of the plurality of model spectra, the test spectrum is compared to the model spectrum to determine a difference value, thereby generating a plurality of difference values. A plurality of minima in the plurality of difference values are determined. Reference spectra can be generated clustered around points in the parameter space corresponding to a local minimum from the plurality of minima, or the local minimum can be used as a seed value in fitting the optical model to a measured spectrum. | 08-28-2014 |
20140242731 | SYSTEM AND METHOD FOR PERFORMING A WET ETCHING PROCESS - A system and method for performing a wet etching process is disclosed. The system includes multiple processing stations accessible by a transfer device, including a measuring station to optically measure the thickness of a substrate, a controller to calculate an etch recipe for the substrate, in real time, and cause a single wafer wet etching station to etch the substrate according to the recipe. In addition, the system can measure the after etch thickness and calculate etch recipes, in real time, as a function of the final measurements of a previous substrate. The system can also include an in situ end point detection device for detecting the TSV reveal point while etching TSVs substrates. The system provides an automated solution to adjust etch recipe parameters in real time according to feedback concerning previously etched wafers and precisely control the TSV reveal height and etch duration using end point detection. | 08-28-2014 |
20140273296 | METRIC FOR RECOGNIZING CORRECT LIBRARY SPECTRUM - A method of controlling polishing of a substrate is described. A controller stores a library having a plurality of reference spectra. The controller polishes a substrate and measures a sequence of spectra of light from the substrate during polishing. For each measured spectrum of the sequence of spectra, the controller finds a best matching reference spectrum from the plurality of reference spectra and generates a sequence of best matching reference spectra. The controller uses a cell counting technique for finding the best matching reference spectrum. The controller determines at least one of a polishing endpoint or an adjustment for a polishing rate based on the sequence of best matching reference spectra. | 09-18-2014 |
20140273297 | EMBEDDED TEST STRUCTURE FOR TRIMMING PROCESS CONTROL - In some embodiments, a method of controlling a photoresist trimming process in a semiconductor manufacturing process may include forming a photoresist layer atop a first surface of a substrate, wherein the photoresist layer comprises a lower layer having a first pattern to be etched into the first surface of the substrate, and an upper layer having a second pattern that is not etched into the first surface of the substrate; trimming the photoresist layer in a direction parallel to the first surface of the substrate; measuring a trim rate of the second pattern using an optical measuring tool during the trimming process; and correlating the trim rate of the second pattern to a trim rate of the first pattern to control the trim rate of the first pattern during the trimming process. | 09-18-2014 |
20140315331 | Screening of Surface Passivation Processes for Germanium Channels - Candidate wet processes for native oxide removal from, and passivation of, germanium surfaces can be screened by high-productivity combinatorial variation of different process parameters on different site-isolated regions of a single substrate. Variable process parameters include the choice of hydrohalic acid used to remove the native oxide, the concentration of the acid in the solution, the exposure time, and the use of an optional sulfur passivation step. Measurements to compare the results of the process variations include attenuated total reflectance Fourier transform infrared spectroscopy (ATR-FTIR), contact angle, atomic force microscopy (AFM), scanning electron microscopy (SEM), and X-ray fluorescence (XRF). A sample screening experiment indicated somewhat less native oxide regrowth using HCl or HBr without sulfur passivation, compared to using HF with sulfur passivation. | 10-23-2014 |
20140377887 | METHOD FOR PLANARIZING SEMICONDUCTOR DEVICES - A method for planarizing semiconductor devices, wherein the method comprises steps as follows: At least one patterned metal layer is formed on a substrate. A material layer having a first area and a second area is provided on the patterned metal layer and the substrate, in which there is a step height existing between the first area and the second area. A first polishing process having a first selection ratio of relative speeds for removing the material layer at the first area to that at the second area is then performed on the material layer. Subsequently, a second polishing process having a second selection ratio of relative speeds for removing the material layer at the first area to that at the second area is performed on the material layer, and the second selection ratio is greater than the first selection ratio. | 12-25-2014 |
20150017745 | POLISHING METHOD AND POLISHING APPARATUS - A polishing method capable of preventing damage to a substrate is disclosed. The polishing method includes inspecting a periphery of a substrate for an abnormal portion, polishing the substrate if the abnormal portion is not detected, and not polishing the substrate if the abnormal portion is detected. The abnormal portion of the substrate may be an foreign matter, such as an adhesive, attached to the periphery of the substrate. After polishing of the substrate, the periphery of the substrate may be inspected again for an abnormal portion. | 01-15-2015 |
20150044785 | SUBSTRATE BACKSIDE TEXTURING - Embodiments described relate to a method and apparatus for reducing lithographic distortion. A backside of a semiconductor substrate may be texturized. Then a lithographic process may be performed on the semiconductor substrate having the texturized backside. | 02-12-2015 |
20150087084 | Measuring Method for Width of Color Filter Unit and Manufacturing Method for Liquid Crystal Panel - The present invention provides a method of measuring a width of a color filter unit of a liquid crystal panel. The method includes providing a bottom glass substrate having a TFT array thereon; forming the color filter plate locating within an effective region of the liquid crystal panel by photo-etching process, and forming one or more measure modules locating of the liquid crystal panel and on the TFT array by the photo-etching process; and measuring widths of the one or more measure modules out of the effective region to obtain the width of the filter units within the effective region. The method provided is capable of effectively controlling widths of the color filter units formed in process of manufacturing the liquid crystal panel, thus quality of the liquid crystal panel is raised. | 03-26-2015 |
20150104887 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes generating a mask layout of patterns in which the distance between adjacent ones of the patterns is equal to or less than a resolution of a lithography process, the patterns are apportioned among a plurality of masks such that in each of the masks the space between adjacent ones of the patterns is greater than the resolution, and a dual pattern is added to one of the masks. A semiconductor pattern is formed on a substrate using the mask(s) and the mask to which the dual pattern has been added. Patterns having a pitch equal to or less than the resolution may be formed on the semiconductor device. | 04-16-2015 |
20150111314 | A METHOD OF POLISHING A SUBSTRATE HAVING A FILM ON A SURFACE OF THE SUBSTRATE FOR SEMICONDUCTOR MANUFACTURING - A method of polishing a substrate having a film is provided. The method includes: performing polishing of the substrate in a polishing section; transporting the polished substrate to a wet-type film thickness measuring device prior to cleaning and drying of the substrate; measuring a thickness of the film by the wet-type film thickness measuring device; comparing the thickness with a predetermined target value; and if the thickness has not reached the predetermined target value, performing re-polishing of the substrate in the polishing section prior to cleaning and drying of the substrate. | 04-23-2015 |
20150140691 | SYSTEMS AND METHODS FOR CHEMICAL MECHANICAL PLANARIZATION WITH FLUORESCENCE DETECTION - Systems and methods are provided for performing chemical-mechanical planarization on an article. An example system for performing chemical-mechanical planarization on an article includes a polishing head configured to perform a chemical-mechanical planarization (CMP) on an article, a polishing pad configured to support the article, a light source configured to emit an incident light, a polishing fluid including a plurality of emitter particles capable of emitting a fluorescent light in response to the incident light, a fluorescence light detector configured to detect the fluorescent light, and at least one processor configured to control the polishing head based on the detected fluorescent light. | 05-21-2015 |
20150147829 | Limiting Adjustment of Polishing Rates During Substrate Polishing - A method of controlling polishing includes polishing a region of a substrate at a first polishing rate, measuring a sequence characterizing values for the region of the substrate during polishing with an in-situ monitoring system, determining a polishing rate adjustment for each of a plurality of adjustment times prior to a polishing endpoint time, and adjusting a polishing parameter to polish the substrate at a second polishing rate. The time period is greater than a period between the adjustment times and the projected time is before the polishing endpoint time. The second polishing rate is the first polishing rate as adjusted by the polishing rate adjustment. | 05-28-2015 |
20150325490 | APPARATUS FOR AND METHOD OF PROCESSING SUBSTRATE - Provided are an apparatus for and a method of processing a substrate. The substrate processing apparatus includes a substrate processing unit to process a substrate using a processing solution containing a mixture of first and second sources; a source supplying part to supply the first and second sources to the substrate processing unit; at least one analyzer to measure a concentration of the second source in the processing solution or a pH value of the processing solution and adjust a measurement reference value of the second source in the processing solution using a standard solution, in which the first and second sources are mixed to have a predetermined concentration or pH value; and a standard solution supplying part to prepare the standard solution using the first and second sources to be supplied from the source supplying part and to supply the standard solution to the at least one analyzer. | 11-12-2015 |
20150348856 | PLANARIZATION METHOD, METHOD FOR POLISHING WAFER, AND CMP SYSTEM - A planarization method is provided. The planarization method includes providing a wafer, in which the wafer includes a work function layer, a surface layer formed on the work function layer and oxidized from the work function layer, and a planarization layer disposed on or above the surface layer, performing a chemical-mechanical planarization (CMP) process on the planarization layer, providing an incident light to a surface of the wafer under the CMP process, detecting absorption of the incident light by the surface layer; and stopping the CMP process in response to an increase in the detected absorption of the incident light. | 12-03-2015 |
20150364387 | WAFER POLISHING METHOD - A wafer polishing method includes first polishing for polishing a wafer backside of a wafer, detecting if a defect exists on the wafer backside, determining whether a level of the detected defect is not within an allowable range, if a defect exists on the wafer backside, and second polishing for repolishing the wafer backside if the level of the defect is within an allowable range. Accordingly, a wafer may be reprocessed so that a level of defects, which may be caused by performing grinding and polishing on the wafer backside, is within an allowable range. Thus, the wafer backside may have uniform quality, and a failure rate of the wafer during a manufacturing processed may be efficiently decreased. | 12-17-2015 |
20150364390 | ENDPOINTING DETECTION FOR CHEMICAL MECHANICAL POLISHING BASED ON SPECTROMETRY - Methods and apparatus for spectrum-based endpointing. An endpointing method includes selecting a reference spectrum. The reference spectrum is a spectrum of white light reflected from a film of interest on a first substrate and has a thickness greater than a target thickness. The reference spectrum is empirically selected for particular spectrum-based endpoint determination logic so that the target thickness is achieved when endpoint is called by applying the particular spectrum-based endpoint logic. The method includes obtaining a current spectrum. The current spectrum is a spectrum of white light reflected from a film of interest on a second substrate when the film of interest is being subjected to a polishing step and has a current thickness that is greater than the target thickness. The method includes determining, for the second substrate, when an endpoint of the polishing step has been achieved. The determining is based on the reference and current spectra. | 12-17-2015 |
20150380323 | WAFER ETCHING APPARATUS AND METHOD FOR CONTROLLING ETCH BATH OF WAFER - A wafer etching apparatus and a method for controlling an etch bath of a wafer is provided. The wafer etching apparatus includes an etching tank comprising an etch bath, an etch bath recycle system connected to the etching tank, a real time monitor (RTM) system connected to the etching tank, and a control system coupled with the RTM system and the etch bath recycle system. The wafer etching apparatus and the method for controlling an etch bath of the wafer both control the silicate concentration in the etch bath to stable an etching selectivity with respect to silicon oxide and silicon nitride. | 12-31-2015 |
20160005667 | SYSTEMS AND METHODS FOR CHEMICAL MECHANICAL PLANARIZATION WITH PHOTOLUMINESCENCE QUENCHING - A method includes performing a chemical-mechanical planarization (CMP) on an article, providing a polishing fluid including luminescent particles capable of generating a fluorescent light in response to a light incident on the article, and detecting an intensity of the fluorescent light. An apparatus that is capable of performing the method and a system that includes the apparatus are also disclosed. | 01-07-2016 |
20160005669 | METHOD OF FORMING SHALLOW TRENCH ISOLATION STRUCTURE - A method of forming a shallow trench isolation (STI) structure in a substrate includes forming a pad oxide layer over the substrate. The method includes forming a nitride-containing layer over the pad oxide layer, wherein the nitride-containing layer has a first thickness. The method further includes forming the STI structure extending through the nitride-containing layer, into the substrate. The STI structure has a height above a top surface of the pad oxide layer. The method includes establishing a correlation between the first thickness, the height of the STI structure above the top surface of the pad oxide layer, and an offset between the first thickness and the height of the STI structure above the top surface of the pad oxide layer. The method includes calculating the height of the STI structure above the pad oxide layer based on the correlation, and selectively removing a determined thickness of the STI structure. | 01-07-2016 |
20160064293 | SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF - Forming a semiconductor arrangement includes non-destructively determining a first spacer height of a first sidewall spacer adjacent a dummy gate and a second spacer height of a second sidewall spacer adjacent the dummy gate based upon a height of a photoresist as measured using optical critical dimension (OCD) spectroscopy. When the photoresist is sufficiently uniform, a hard mask etch is performed to remove a hard mask from the dummy gate and to remove portions of sidewall spacers of the dummy gate. A gate electrode is formed between the first sidewall spacer and the second sidewall spacer to form a substantially uniform gate. Controlling gate formation based upon photoresist height as measured by OCD spectroscopy provides a non-destructive manner of promoting uniformity. | 03-03-2016 |
20160074988 | PROCESSING MODULE, PROCESSING APPARATUS, AND PROCESSING METHOD | 03-17-2016 |
20160086857 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD - The present disclosure provides a method for fabricating semiconductor devices. The method includes providing a substrate with a gate electrode film on the substrate and a gate electrode pattern film on the gate electrode film; forming at least one pattern layer on the gate electrode pattern film; and using the at least one pattern layer as the etch mask to etch portions of the gate electrode pattern film to expose portions of the gate electrode film and form a gate electrode pattern layer on the gate electrode film, the gate electrode pattern layer including a hard mask layer and a silicon layer, and sidewalls of the silicon layer in a direction perpendicular to a first direction having a first poly line width roughness. The method also includes performing an etch-repairing treatment on the sidewalls of the silicon layer in the direction perpendicular to the first direction. | 03-24-2016 |
20160086865 | Automatically Adjusting Baking Process for Low-k Dielectric Material - A method includes etching a low-k dielectric layer on a wafer to form an opening in the low-k dielectric layer. An amount of a detrimental substance in the wafer is measured to obtain a measurement result. Process conditions for baking the wafer are determined in response to the measurement result. The wafer is baked using the determined process conditions. | 03-24-2016 |
20160099187 | 3D NAND STAIRCASE CD CONTROL BY USING INTERFEROMETRIC ENDPOINT DETECTION - Embodiments of the present disclosure provide methods for forming stair-like structures in manufacturing three dimensional (3D) stacking of semiconductor chips. In one example, a method includes performing a trimming process on a substrate to trim a patterned photoresist layer disposed on a film stack from a first width to a second width in a processing chamber, performing an etching process to etch a portion of the film stack exposed by the trimmed patterned photoresist layer, directing an optical signal to a surface of the trimmed patterned photoresist layer continuously during the trimming and the etching process, collecting a return reflected optical signal reflected from the trimmed patterned photoresist layer, determining a change of reflected intensify of the return reflected optical signal as collected; and calculating a photoresist thickness loss based on the change of the reflected intensity. | 04-07-2016 |
20160126150 | SYSTEM AND METHOD FOR GENERATING AN ARM SCAN PROFILE - A system and method for performing a wet etching process is disclosed. The system includes multiple processing stations accessible by a transfer device, including a measuring station to optically measure the thickness of a wafer before and after each etching steps in the process. The system also includes a controller to analyze the thickness measurements in view of a target wafer profile and generate an etch recipe, dynamically and in real time, for each etching step. In addition, the process controller can cause a single wafer wet etching station to etch the wafer according to the generated etching recipes. In addition, the system can, based on the pre and post-etch thickness measurements and target etch profile, generate and/or refine the etch recipes. | 05-05-2016 |
20160133467 | Method For Improving Critical Dimension Variability - Methods of processing a workpiece are disclosed. Variability of the critical dimension of semiconductor structures may be affected by the critical dimension of the patterned mask. Ions may be implanted into the patterned mask to change the critical dimension. The ions may be implanted in accordance with an ion implant map, which determines an appropriate dose, energy and type based on the measured critical dimension of the patterned mask at a plurality of locations. | 05-12-2016 |
20160147140 | PATTERN VERIFYING METHOD - The present invention provides a pattern verifying method. First, a target pattern is decomposed into a first pattern and a second pattern. A first OPC process is performed for the first pattern to form a first revised pattern, and a second OPC process is performed for the second pattern to form a second revised pattern. An inspection process is performed, wherein the inspection process comprises an after mask inspection (AMI) process, which comprises considering the target pattern, the first pattern and the second pattern. | 05-26-2016 |