Class / Patent application number | Description | Number of patent applications / Date published |
377067000 | Multirank (i.e., rows of storage units form a shift register) | 11 |
20100166136 | SHIFT REGISTER CIRCUIT - A shift register circuit is provided that can decrease a power consumption caused by a clock signal and can achieve a high driving capacity. A unit shift register has a first transistor that activates an output signal when a power supply potential is provided to an output terminal. A pull-up driving circuit for driving the first transistor has a second transistor for providing a clock signal to a node connected to the gate of the first transistor and a boosting circuit for the node. When an output signal of a preceding stage is activated, the second transistor turns on. Thereafter, when the clock signal is activated, and the node is charged, the second transistor turns off. The boosting circuit increases the potential at the node when the second transistor turns off. Therefore, the first transistor can operate in non-saturation region and activate the output signal. | 07-01-2010 |
20110002438 | DUAL SHIFT REGISTER - Disclosed is a dual shift register that includes a first shift register configured to include a plurality of stages which sequentially output scan pulses using at least two clock signals with sequential and circular phases, and a second shift register configured to a plurality of stages which form pair with the respective stages of the first shift register and sequentially output the scan pulses using at least two clock signals. Each stage includes: a scan direction controller configured to respond to the scan pulses from previous and next stages and to selectively output forward and reverse direction voltages with opposite electric potentials to each other; and an output portion configured to respond to the output signal of the scan direction controller, to generate two sequential scan pulses using two of the at least two clock signals, and to distribute the sequential scan pulses to the previous and next stages. | 01-06-2011 |
20110286572 | SHIFT REGISTER UNIT, GATE DRIVING DEVICE FOR DISPLAY AND LIQUID CRYSTAL DISPLAY - A shift register unit includes an input module for inputting a second clock signal or a third clock signal, and for inputting a frame starting signal, a first clock signal, a low voltage signal, a reset signal as well as a first signal and a second signal transmitted from a next neighboring shift register unit; a processing module for generating a gate driving signal and allowing a level of at least one of first junctions formed by at least two TFTs to be maintained at low level in a frame interval during which the second clock signal or the third clock signal inputted from the input module is maintained at low level; and an output module for transmitting the gate driving signal generated by the processing module. | 11-24-2011 |
20110317803 | SHIFT REGISTER CIRCUIT AND SHIFT REGISTER - An exemplary shift register circuit includes a plurality of shift registers for sequentially outputting a plurality of driving pulse signals. Among each M number of the shift registers for sequentially outputting M number of the driving pulse signals, the shift register for lastly outputting one of the M number of driving pulse signals is enabled, by (M−1) number of start pulse signals sequentially outputted from the remained (M−1) number of the shift registers, to generate the driving pulse signal. Herein, M is a positive integer greater than 2. Moreover, a circuit structure of a shift register also is provided. | 12-29-2011 |
20120183117 | SHIFT REGISTER CIRCUIT - A shift register circuit is provided that can decrease a power consumption caused by a clock signal and can achieve a high driving capacity. A unit shift register has a first transistor that activates an output signal when a power supply potential is provided to an output terminal. A pull-up driving circuit for driving the first transistor has a second transistor for providing a clock signal to a node connected to the gate of the first transistor and a boosting circuit for the node. When an output signal of a preceding stage is activated, the second transistor turns on. Thereafter, when the clock signal is activated, and the node is charged, the second transistor turns off. The boosting circuit increases the potential at the node when the second transistor turns off. Therefore, the first transistor can operate in non-saturation region and activate the output signal. | 07-19-2012 |
20130322593 | SHIFT REGISTER - Discussed herein is a shift register which is capable of stabilizing an output thereof. The shift register includes a plurality of stages for sequentially outputting scan pulses in such a manner that high durations of the scan pulses partially overlap with each other. Each of the stages includes a node controller for controlling a charging duration of a set node, and an output unit for outputting a corresponding one of the scan pulses through an output terminal for the charging duration of the set node. | 12-05-2013 |
20140098928 | SERIAL-IN-PARALLEL-OUT SHIFT REGISTERS WITH ENHANCED FUNCTIONALITY - A configuration of logic elements enables existing Serial-In-Parallel-Out (SIPO) shift registers to perform their own bit count, report the receipt of a valid transmission consisting of an expected number of bits and report the receipt of an invalid transmission consisting of greater than the expected number of bits. Logic elements additional to the foregoing enable SIPO shift registers to receive valid transmissions of varying expected numbers of bits. Special purpose integrated circuits (ICs) are disclosed which also contain the aforementioned configurations of logic elements. Newly designed SIPO shift registers which contain within them the foregoing configurations of logic elements are further disclosed. Potential messages of multiple acceptable message lengths are accommodated. Some embodiments are equipped with tri-state data outputs. | 04-10-2014 |
20140112429 | Low Voltage Register File Cell Structure - A register file cell structure to enable lower voltage writes is disclosed. In one embodiment, a register file includes a state element made up of two cross-coupled inverters. Each of the inverters includes a p-channel metal oxide semiconductor (PMOS) transistor having a source terminal coupled to a virtual voltage node. One or more PMOS transistors are coupled in series between the virtual voltage node and a global voltage node. Each of the one or more PMOS transistors includes a gate terminal that is hardwired to a ground node, and thus these devices remain active when power is applied to the global voltage node. The presence of the one or more PMOS devices coupled between the virtual and global voltage nodes results in the ability to overwrite contents stored in the state element at lower voltages than otherwise attainable without the one or more PMOS devices. | 04-24-2014 |
20140133621 | SHIFT REGISTER UNIT AND GATE DRIVE DEVICE FOR LIQUID CRYSTAL DISPLAY - A shift register unit and a gate drive device for a liquid crystal display are disclosed. Both gate and drain of the tenth thin film transistor are connected to the source of the fifth thin film transistor, a source thereof is connected to a low voltage signal input terminal, threshold voltages of the eighth thin film transistor and the ninth thin film transistor are equal to or less than threshold voltage of the tenth thin film transistor. The shift register unit and the gate drive device for liquid crystal display provided in the present invention, could enable the thin film transistor used to suppress the noise in the shift register unit to maintain turning on, therefore it guarantees the reliability of the shift register unit. | 05-15-2014 |
20140270050 | DESIGN AND DEPLOYMENT OF CUSTOM SHIFT ARRAY MACRO CELLS IN AUTOMATED APPLICATION SPECIFIC INTEGRATED CIRCUIT DESIGN FLOW - An automated method is provided for designing an integrated circuit. A net list of an integrated circuit design is generated, wherein the net list includes a scan chain having a sequence of individual scan cells. A sequence of two or more individual scan cells of the scan chain is identified as a candidate for replacement by a custom shift array macro cell. The identified sequence of two or more individual scan cells is then replaced with a custom shift array macro cell that provides a functionally equivalent shift function as the replaced sequence of two or more individual scan cells. The custom shift array macro cell includes only two input pins and one output pin. | 09-18-2014 |
20140355733 | STAGE CIRCUIT AND SCAN DRIVER USING THE SAME - A stage circuit and a scan driver, the stage circuit including a switch unit configured to selectively electrically couple a first node to one of a first input terminal and a second input terminal, a first driver coupled to the first node, to a second node, to a third node, to a first clock terminal, and to a second clock terminal, and a second driver coupled to the second node, to the third node, to a third clock terminal, and to a common terminal, and configured to output a scan signal to an output terminal. | 12-04-2014 |