Class / Patent application number | Description | Number of patent applications / Date published |
370413000 | Having both input and output queuing | 34 |
20080310440 | Network interface system with filtering function - A network interface system with packet filtering function is disclosed herein. The network interface system includes interfaces, a packet buffer and a controller. The packet buffer stores data packets received by the network interface system. The controller provides security defense for the host system and the network by filtering the data packets stored in the packet buffer. The controller controls the packet buffer abandoning a data packet if the data packet is identified as an unsafe packet. The controller also includes a regulator for controlling a transferring order of the data packets. Thus, the network interface system can drop unsafe data packet and transfer data packets considered as safe information. The data packets can be processed in a sequence according to preset priority rules. | 12-18-2008 |
20090086748 | Multi-Function Queue To Support Data Offload, Protocol Translation And Pass-Through FIFO - A multi-port serial buffer having a plurality of queues is configured to include a first set of queues assigned to store write data associated with a first port, and a second set of queues assigned to store write data associated with a second port. The available queues are user-assignable to either the first set or the second set. Write operations to the first set of queues can be performed in parallel with write operations to the second programmable set of queues. In addition, a first predetermined set of queues is assigned to the first port for read operations, and a second predetermined set of queues is assigned to the second port for read operations. Data can be read from the first predetermined set of queues to the first port at the same time that data is read from the second predetermined set of queues to the second port. | 04-02-2009 |
20090097495 | FLEXIBLE VIRTUAL QUEUES - Flexible virtual queues of a switch are allocated to provide non-blocking virtual output queue (VOQ) support. A port ASIC has a set of VOQs, one VOQ per supported port of the switch. For each VOQ, a set of virtual input queues (VIQs) includes a VIQ for each input port of the port ASIC that forms a non-blocking flow with the corresponding output port (and potentially, with the specified level of service) in the switch. The port ASIC selects a VOQ for transmission and then arbitrates among the VIQs of the selected VOQ to select a VIQ from which to transmit the packet. Having identified an appropriate VIQ, the port ASIC transmits cells of the packet at the head of the VIQ to a port ASIC that includes the corresponding output port for reassemble and eventual transmission through the output port. | 04-16-2009 |
20090103555 | LABEL AND EXP FIELD BASED MPLS NETWORK DEVICE - A network device receives a label-switched-path (LSP) labeled data packet, maps the LSP labeled data packet to an input queue, maps a data packet in the input queue to an output queue based on a received LSP label value and a received exp label value, and transmits the LSP labeled data packet from the output queue. | 04-23-2009 |
20090103556 | DATA SWITCH - A data switch for an integrated circuit comprising at least one link for receiving input data packets from an independently modulated spread spectrum clock (SSC) enabled source having predetermined spread spectrum link clock frequency characteristics, and at least one output for transmitting the data packets after passage through the switch, the switch further comprising at least one receive buffer having a link side and a core side for receiving the SSC modulated input data packets from the link, at least one transmit buffer and a core clock, wherein the core clock operates at a given frequency between predetermined error limits determined by oscillation accuracy alone and is not SSC-enabled, the core clock frequency being set at a level at least as high as the highest link clock frequency such that the receive buffer cannot be filled faster from its link side than it can be emptied from its core side. | 04-23-2009 |
20090147796 | Input/output buffer controller for optimized memory utilization and prevention of packet under-run errors - To avoid under-run conditions that result in corrupt packets at I/O interfaces, a FIFO buffer controller monitors key aspects of the contents of FIFO buffers of I/O interfaces. The FIFO buffer controller initiates transmission of data from the FIFO buffer when at least one complete packet is stored in the FIFO buffer or when the size of a partial packet stored therein is large enough so that the remainder of the packet would normally be received by the FIFO buffer before the stored part can be transmitted from the FIFO buffer; thereby avoiding an under-run error condition. | 06-11-2009 |
20090168794 | METHOD AND SYSTEM FOR COMMUNICATING BETWEEN TWO INDEPENDENT SOFTWARE COMPONENTS OF A SIDESHOW DEVICE - A method and system for communicating between two independent software components of the SideShow device are disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of independently queuing an incoming packet from a second software component via an emulated serial transport in a first software component before parsing and responding to the incoming packet and independently queuing an outgoing packet in the first software component before transmitting the outgoing packet to the second software component also via the emulated serial transport. | 07-02-2009 |
20090175287 | Packet switch - A virtual output queuing controlling device in an input buffering switch with a virtual output queuing technique includes a specialized class for CBR traffic, and a connection request generation section that makes a connection request for a switch scheduler, which can execute a three-step priority control. The connection request generation section makes the connection request of the specialized class for CBR traffic prior to the connection request of the other classes for the switch scheduler. | 07-09-2009 |
20090279560 | Adaptive Rate Control - Techniques are given for determining the data transmission or sending rates in a router or switch of two or more input queues in one or more input ports sharing an output port, which may optionally include an output queue. The output port receives desired or requested data from each input queue sharing the output port. The output port analyzes this data and sends feedback to each input port so that, if needed, the input port can adjust its transmission or sending rate. | 11-12-2009 |
20100034213 | Apparatus and Method for Communicating Arbitrarily Encoded Data Over a 1-Gigabit Ethernet - The invention allows data originating according to a first communications standard to be transmitted over a physical layer using a second communications standard. According to an embodiment of the invention, a data stream is received from a physical transmission medium that uses particular first communications standard. Next, a data type identification (DTID) is appended to each byte in the data stream, thereby creating a technology independent data stream having a particular bit rate. This bit rate is then matched to a different bit rate that corresponds to a second communications standard. The technology independent data stream is then transmitted over a physical transmission medium that uses the second communications standard. | 02-11-2010 |
20100054270 | Relay Apparatus and Output Control Method - A buffer temporarily stores data received from a network by a receiving unit. An output mode switching unit switches the mode in which the data received by the receiving unit is output to the buffer, between FIFO and FILO, in accordance with the storage amount of data temporarily stored in the buffer. For example, if the data temporarily stored in the buffer falls below a given threshold value of the buffer, data is stored in the buffer in FIFO. If the data temporarily stored in the buffer exceeds a given threshold value of the buffer, data is stored in the buffer in FILO. A sending unit outputs data taken from the buffer in FIFO or FILO, to a network. | 03-04-2010 |
20100272117 | Buffered Crossbar Switch System - Described embodiments provide for transfer of data between data modules. At least two crossbar switches are employed, where input nodes and output nodes of each crossbar switch are coupled to corresponding data modules. The ith crossbar switch has an N | 10-28-2010 |
20110090916 | LABEL AND EXP FIELD BASED MPLS NETWORK DEVICE - A network device receives a label-switched-path (LSP) labeled data packet, maps the LSP labeled data packet to an input queue, maps a data packet in the input queue to an output queue based on a received LSP label value and a received exp label value, and transmits the LSP labeled data packet from the output queue. | 04-21-2011 |
20110122887 | COORDINATED QUEUING BETWEEN UPSTREAM AND DOWNSTREAM QUEUES IN A NETWORK DEVICE - A system determines a scheduling value based on a current length of a downstream queue in a network device. The system sends the scheduling value from the downstream queue to an upstream queue and schedules dequeuing of one or more data units, destined for the downstream queue, from the upstream queue based on the scheduling value. | 05-26-2011 |
20110122888 | Method And System To Allocate Exchange Identifications For Fibre Channel N-Port Aggregation - A method and system for allocating exchange identifications (IDs) in a fibre channel switch for fibre channel aggregation. The method included determining a number (m) of N_ports present in a back end of the switch, and distributing available exchange IDs across the number (m) of present N_ports. Each exchange ID includes (j) bits and (n) bits are used to identify each of the present backend ports, where m≦2 | 05-26-2011 |
20120020372 | PROHIBITION TURN DETERMINATION APPARATUS - A prohibition turn determination apparatus determines an initial path so that the communication amounts of respective links connecting switches to each other are most efficiently distributed between a communication pair, that is, a pair of servers communicating with each other via a network. Then, the prohibition turn determination apparatus calculates the communication amounts of respective turns formed along the initial path based on the communication amounts set between end nodes which are the communication pair. Next, the prohibition turn determination apparatus determines prohibition turns, which are not used for packet communication, based on the communication amounts of respective turns by an Up/down method or a TP method. Finally, the prohibition turn determination apparatus determines the final routing to avoid the prohibition turns. | 01-26-2012 |
20120076152 | SYSTEM AND METHOD FOR PRIORITY SCHEDULING OF PLURALITY OF MESSAGE TYPES WITH SERIALIZATION CONSTRAINTS AND DYNAMIC CLASS SWITCHING - The present invention provides a preemptive priority scheduling system and method for optimal load balancing of messages and preserving the lightweight allocation resources in an intersystem communication. The invention also provides a system and method for scheduling of messages of a plurality of classes in an intersystem communication. | 03-29-2012 |
20120195322 | Method and Apparatus for Achieving Fairness in Interconnect Using Age-Based Arbitration and Timestamping - An apparatus comprising a chip comprising a plurality of nodes, wherein a first node from among the plurality of nodes is configured to receive a first flit comprising a first timestamp, receive a second flit comprising a second timestamp, determine whether the first flit is older than the second flit based on the first timestamp and the second timestamp, transmit the first flit before the second flit if the first flit is older than the second flit, and transmit the second flit before the first flit if the first flit is not older than the second flit. | 08-02-2012 |
20120300788 | SERIAL REDIRECTOR DEVICE AND ASSOCIATED METHODS - Systems and methods for a serial redirector device to provide services using serial communication redirection through a packet-based interface. In one implementation, the serial redirector device is configured to receive messages via a packet-based interface and redirect the same to a device in serial communication with the serial redirector device. The serial redirector mediates the communication between serially connected devices and devices connected via packet-based interfaces. | 11-29-2012 |
20130266021 | BUFFER MANAGEMENT SCHEME FOR A NETWORK PROCESSOR - The invention provides a method for adding specific hardware on both receive and transmit sides that will hide to the software most of the effort related to buffer and pointers management. At initialization, a set of pointers and buffers is provided by software, in quantity large enough to support expected traffic. A Send Queue Replenisher (SQR) and Receive Queue Replenisher (RQR) hide RQ and SQ management to software. RQR and SQR fully monitor pointers queues and perform recirculation of pointers from transmit side to receive side. | 10-10-2013 |
20140105220 | MESSAGE HANDLING MULTIPLEXER - A method and apparatus for processing message is described. In one embodiment, an application programming interface is configured for receiving and sending messages. A multiplexer receives messages from different servers. A service name is coupled to each message with the corresponding destination service. A single shared channel is formed. The messages are processed over the single shared channel. | 04-17-2014 |
20140140352 | COMMUNICATION DEVICE - A relay device relays between two TCP communication items of a LAN side and a WAN side. When a line bandwidth of the WAN side is smaller than a line bandwidth of the LAN side, buffer overflow in a LAN side reception buffer and a WAN side transmission buffer of the relay device is prevented, and a connection is prevented from being forced to be canceled. A value of a reception window size (rwnd) described in an ACK packet returned to a transmission terminal of the LAN side is controlled based on a transmission throughput, a discarding rate, and an RTT measured in TCP communication of the WAN side, and a total size of unarranged data and a size of arranged data in a reception buffer of the LAN side and a size of untransmitted data and ACK awaiting data in a transmission buffer of the WAN side. | 05-22-2014 |
20140198803 | Scheduling and Traffic Management with Offload Processors - A memory bus connected module for scheduling services for network packet processing is disclosed. The module can include a memory bus connection, a scheduling circuit configured to reorder network packets received from the memory bus connection and place the reordered network packets into multiple input/output queues, and multiple offload processors connected to the memory bus connection, each offload processor configured to modify network packets in the multiple input/output queues. | 07-17-2014 |
20140269750 | IMPLICIT AND DYNAMIC RECEIVE QUEUE ASSIGNMENT IN VIRTUALIZED SYSTEMS - A system and method are disclosed for assigning incoming packets to receive queues of a virtual machine. In accordance with one embodiment, a hypervisor that is executed by a computer system receives a request from a virtual machine to transmit an outgoing packet to a destination, and an identification of a receive queue of a plurality of receive queues of the virtual machine, where the identification of the receive queue is provided to the hypervisor by the virtual machine along with the request. The hypervisor obtains a flow identifier from a header of the outgoing packet that identifies a flow associated with the outgoing packet, and the outgoing packet is transmitted to the destination. The computer system then receives an incoming packet whose header specifies the flow identifier, and the hypervisor inserts the incoming packet into the receive queue using the identification of the receive queue. | 09-18-2014 |
20140269751 | PREDICTION-BASED SWITCH ALLOCATOR - An arbitration technique for determining mappings for a switch is described. During a given arbitration decision cycle, an arbitration mechanism maintains, until expiration, a set of mappings from a subset of the input ports to a subset of the output ports of the switch. This set of mappings was determined during an arbitration decision cycle up to K cycles preceding the given arbitration decision cycle. Because the set of mappings are maintained, it is easier for the arbitration mechanism to determine mappings from a remainder of the input ports to the remainder of the output ports without collisions. | 09-18-2014 |
20140269752 | APPARATUS AND METHOD AGGREGATION AT ONE OR MORE LAYERS - A method for performing aggregation at one or more layers starts with an AP placing at a first layer one or more received frames in a queue at the AP. When a transmit scheduler is ready to transmit an aggregated frame corresponding to the queue, the AP may iteratively select a plurality of frames selected from the one or more received frames, and aggregate at the first layer the plurality of frames into the aggregated frame. The number of frames included in an aggregated frame may be based on at least one of: a dynamically updated rate of transmission associated with a size of the frames, a class of the frames, a transmission opportunity value associated with the class of the frames and a total projected airtime for transmitting the aggregated frame. Other embodiments are also described. | 09-18-2014 |
20140307746 | Method and Apparatus for Providing Timing Analysis for Packet Streams Over Packet Carriers - A network device such as a router or switch, in one embodiment, includes a timing analyzer which is capable of providing timing analysis over one or more network circuits. The timing analyzer, in one aspect, receives a data packet traveling across a circuit emulation service (“CES”) circuit such as T1 or E1 circuit. Upon obtaining an arrival timestamp associated with the data packet, the arrival timestamp is stored in a timestamp buffer in accordance with a first-in first-out (“FIFO”) storage sequence. After identifying the oldest arrival timestamp in the timestamp buffer, an offset is generated based on the result of comparison between the arrival timestamp and the oldest timestamp. The timing analyzer can also be configured to generate timing reports on-demand based on generated offset(s). | 10-16-2014 |
20150110126 | CUT THROUGH PACKET FORWARDING DEVICE - An electronic device communicates according to a network protocol that defines data packets, for example EtherCAT. The device has a processor for performing input control on incoming data packets and performing output control on outgoing data packets, and a shared FIFO buffer comprising a multiuser memory. An input unit receives input data, detects the start of a respective data packet, subdivides the data packet into consecutive segments, one segment having a predetermined number of data bytes, and transfers the segment to the FIFO buffer before the next segment has been completely received. The processor accesses, in the input control, the multiuser memory for processing the segment, and, in the output control, initiates outputting the output packet before the corresponding input data packet has been completely received. An output unit transfers the segment from the FIFO buffer, and transmits the segment to the communication medium. | 04-23-2015 |
20160142329 | METHODS AND APPARATUS FOR PROVIDING TIMING ANALYSIS FOR PACKET STREAMS OVER PACKET CARRIERS - A network device such as a router or switch, in one embodiment, includes a timing analyzer which is capable of providing timing analysis over one or more network circuits. The timing analyzer, in one aspect, receives a data packet traveling across a circuit emulation service (“CES”) circuit such as T1 or E1 circuit. Upon obtaining an arrival timestamp associated with the data packet, the arrival timestamp is stored in a timestamp buffer in accordance with a first-in first-out (“FIFO”) storage sequence. After identifying the oldest arrival timestamp in the timestamp buffer, an offset is generated based on the result of comparison between the arrival timestamp and the oldest timestamp. The timing analyzer can also be configured to generate timing reports on-demand based on generated offset(s). | 05-19-2016 |
20160191422 | SYSTEM AND METHOD FOR SUPPORTING EFFICIENT VIRTUAL OUTPUT QUEUE (VOQ) PACKET FLUSHING SCHEME IN A NETWORKING DEVICE - A system and method can support packet switching in a network environment. The system can include an ingress buffer on a networking device, wherein the ingress buffer, which includes one or more virtual output queues, operate to store one or more incoming packets that are received at an input port on the networking device. Furthermore, the system can include a packet flush engine, which is associated with the ingress buffer, wherein said packet flush engine operates to flush a packet that is stored in a said virtual output queue in the ingress buffer, and notify one or more output schedulers that the packet is flushed, wherein each output scheduler is associated with an output port. | 06-30-2016 |
20160191423 | SYSTEM AND METHOD FOR SUPPORTING EFFICIENT BUFFER REALLOCATION IN A NETWORKING DEVICE - A system and method can support efficient packet switching in a network environment. The system can comprise an ingress buffer on a networking device. The ingress buffer operate to store one or more incoming packets that are received at an input port on the networking device, wherein the input port is associated with a plurality of source virtual lanes (VLs). Furthermore, the ingress buffer operate to reallocate buffer resource in the ingress buffer from being associated with a first source VL in the plurality of source VLs to being associated with a second source VL in the plurality of source VLs, and send an initial credit update to the input port for the first source VL and the second source VL. | 06-30-2016 |
20160205045 | APPARATUS AND METHOD FOR ARBITRATING BETWEEN MULTIPLE REQUESTS | 07-14-2016 |
20170237675 | Power-Aware Network Communication | 08-17-2017 |
370414000 | Contention resolution for output | 1 |
20140086260 | MANAGING STARVATION AND CONGESTION IN A TWO-DIMENSIONAL NETWORK HAVING FLOW CONTROL - An apparatus that includes input ports, input buffers coupled with respective input ports, output ports, and routing control circuitry coupled with the input ports, the input buffers and/or the output ports. The plurality of input buffers and the plurality of output ports, the routing control circuitry to maintain a two-tier priority scheme having at least two queues for prioritizing requests stored in the plurality of input buffers. | 03-27-2014 |