Entries |
Document | Title | Date |
20080205175 | Auto-precharge control circuit in semiconductor memory and method thereof - An auto-precharge control circuit in a semiconductor memory and method thereof, where the auto-precharge starting point may vary. The auto-precharge starting point may vary in response to at least one control signal. The auto-precharge starting point may vary in accordance with frequency and/or latency information. The auto-precharge starting point may vary in response to at least one control signal including clock frequency information. The auto-precharge starting point may vary depending on a latency signal received from a mode register setting command. The auto-precharge control circuit may include a control circuit for receiving a write signal, a clock signal and at least one control signal, including at least one of clock frequency information and latency information, and outputting at least one path signal; an auto-precharge pulse signal driver for receiving the at least one path signal, the write signal, and an enable signal and producing an auto-precharge pulse signal, the auto-precharge pulse signal identifying a starting point for an auto-precharge operation; and an auto-precharge mode enabling circuit for receiving the clock signal, an auto-precharge command, an active signal, and the auto-precharge pulse signal and generating the enable signal. | 08-28-2008 |
20080219071 | Data flow scheme for low power DRAM - Circuits and methods to minimize power required for sensing and precharge of DRAMs have been achieved. A control circuit ensures that during READ operations the duration of sensing of DRAM cell and precharging is kept to a minimum. A test DRAM cell is used to determine the exact time required for data sensing. Furthermore no precharging is performed during WRITE-operations. In case data is changing from “1” to “0” or vice versa data lines are inverted accordingly during WRITE operation. | 09-11-2008 |
20080225616 | METHOD FOR INCREASING RETENTION TIME IN DRAM - The disclosure generally relates to a method and apparatus for decreasing the frequency of refreshing a memory cell in communication with a word line and a bit line. A method according to one embodiment includes: providing a DRAM circuit having a memory cell, a sense amplifier including a pre-charge circuit connected to a first voltage source and a back-to-back inverter including a first NMOS transistor having a source, a second NMOS transistor having a source, a first PMOS transistor having a source and a second PMOS transistor having a source; maintaining the voltage of the sources of the first and second PMOS transistors at a first voltage during normal operation; and raising the voltage of the sources of the first and second PMOS transistors from the first voltage to a second voltage during a refresh operation. | 09-18-2008 |
20080225617 | METHOD FOR HIGH SPEED SENSING FOR EXTRA LOW VOLTAGE DRAM - A method and apparatus are provided for sensing in low voltage DRAM memory cells. A method according to one embodiment includes: providing a DRAM circuit having a memory cell, a sense amplifier including a pre-charge circuit connected to a first voltage source and a back-to-back inverter including a first and second NMOS transistor, each having a source and a first and second PMOS transistor, each having a source. The method further includes the steps of maintaining the voltage of the sources of the first and second NMOS transistors at a first voltage during normal operation and lowering the voltage of the sources of the first and second NMOS transistors from the first voltage to a second voltage during a read operation. | 09-18-2008 |
20080232182 | Precharge voltage supplying circuit - A precharge voltage supplying circuit comprises a control signal generating unit for generating a first control signal in response to a power-up signal and a clock enable signal, and a precharge voltage control unit having a bleeder circuit and driving the bleeder circuit in response to the first control signal to control a precharge voltage. The precharge voltage supplying circuit can be widely used in various devices which need the generation of a voltage, a level of which is adjustable according to a PVT characteristic change, and a range of change of which is not so large. | 09-25-2008 |
20080239847 | SEMI-SHARED SENSE AMPLIFIER AND GLOBAL READ LINE ARCHITECTURE - A memory includes a global read line and a plurality of banks. For each bank, the memory includes a sense amplifier. A discharge circuit discharges the global read line if any one of a plurality of the sense amplifiers is enabled and is outputting a signal having a first digital logic value onto an input lead of the discharge circuit. In this way, the sense amplifiers share the discharge circuit. In one example, the memory includes a pair of differential read lines that are precharged to begin a read operation. After precharging, if either of two sense amplifiers is enabled and outputting the first digital logic value, then a first discharge circuit discharges a first of the global read lines. If either of two sense amplifiers is enabled and outputting the second digital logic value, then a second discharge circuit discharges a second of the global read lines. | 10-02-2008 |
20080239848 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A semiconductor memory device includes a write driver, a first precharging unit, and a second precharging unit. The write driver loads data applied to a first data line onto a second data line. The first precharging unit precharges the second data line to a precharging voltage in response to a precharging signal. The second precharging unit overdrives the second data line to a voltage higher than the precharging voltage in response to an overdriving signal enabled for a predetermined time period during an initial precharging interval of the second data line. | 10-02-2008 |
20080247248 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A semiconductor memory device includes: a driving voltage supplying unit configured to detect a simultaneous activation of banks and selectively supply one of a high voltage and an external voltage lower than the high voltage as a driving voltage; a flag detecting unit configured to detect inputs of flag signals activated in response to an active command and generate a precharge control signal; and a signal generating unit configured to generate a bit line precharge signal swinging between the driving voltage and a ground voltage in response to the precharge control signal. | 10-09-2008 |
20080253210 | SEMICONDUCTOR MEMORY APPARATUS - Disclosed is a semiconductor memory apparatus capable of improving precharge performance. The semiconductor memory apparatus includes a plurality of memory banks, data input/output lines commonly connected to the memory banks, and a plurality of precharge circuit units connected to the data input/output lines and aligned in an extension direction of the data input/output lines while being spaced apart from each other by a predetermined distance. | 10-16-2008 |
20080259706 | Semiconductor memory - A semiconductor memory includes: first and second bit lines; a precharge circuit for precharging the first and second bit lines to a predetermined potential; a plurality of memory cells each connected to the first or second bit line, a selected one of the memory cells maintaining or discharging one of the precharged first and second bit lines according to a signal held by the selected memory cell; word lines for selecting the memory cells; first and second reference cells connected to the first and second bit lines, respectively, a selected one of the first and second reference cells discharging the first or second bit line connected to the selected reference cell; and first and second reference cell word lines for selecting the first and second reference cells, respectively. | 10-23-2008 |
20080266991 | Synchronous Page-Mode Phase-Change Memory with ECC and RAM Cache - Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on the write data and is relatively long. A page-mode caching PCM device has a lookup table (LUT) that caches write data that is later written to an array of PCM banks. Host data is latched into a line FIFO and written into the LUT, reducing write delays to the relatively slow PCM. Host read data can be supplied by the LUT or fetched from the PCM banks. A multi-line page buffer between the PCM banks and LUT allows for larger block transfers using the LUT. Error-correction code (ECC) checking and generation is performed for data in the LUT, hiding ECC delays for data writes into the PCM banks. | 10-30-2008 |
20080285367 | METHOD AND APPARATUS FOR REDUCING LEAKAGE CURRENT IN MEMORY ARRAYS - Techniques for reducing leakage current in memory arrays are described. A memory array has multiple rows and multiple columns of memory cells. Bit lines are coupled to the columns of memory cells, and word lines are coupled to the rows of memory cells. The bit lines have disconnected paths to a power supply and float during a sleep mode for the memory array. The bit lines may be coupled to (i) precharge circuits used to precharge the bit lines prior to each read or write operation, (ii) pass transistors used to couple the bit lines to sense amplifiers for read operations, and (iii) pull-up transistors in drivers used to drive the bit lines for write operations. The precharge circuits, pass transistors, and pull-up transistors are turned off during the sleep mode. The word lines are set to a predetermined logic level to disconnect the memory cells from the bit lines during the sleep mode. | 11-20-2008 |
20080291762 | SEMICONDUCTOR MEMORY DEVICE FOR PRECHARGING BIT LINES EXCEPT FOR SPECIFIC READING AND WRITING PERIODS - A semiconductor memory device includes a memory cell having an FET of a floating body type, and a capacitor for storing a data charge; a bit line to which the source or the drain of the FET is connected; a precharging device for performing precharge control so that the bit line has a predetermined precharge voltage; a sense amplifier for amplifying and storing the potential of the bit line, which is set in accordance with the data charge read from the memory cell; a switching device, provided between the bit line and the sense amplifier, for performing selective connection therebetween; and a control part for controlling the precharging device, the sense amplifier, and the switching device. Except for each period for performing data reading or writing, the control part makes the precharging device perform the precharge control and makes the switching device disconnect the bit line from the sense amplifier. | 11-27-2008 |
20080291763 | MEMORY DEVICE - A memory device is provided which has: a memory cell to store data; a word line to select the memory cell; a bit line connectable to the selected memory cell; a precharge power supply to supply a precharge voltage to the bit line; a precharge circuit to connect or disconnect the precharge power supply to or from the bit line; and a current limiting element to control the magnitude of a current flowing between the precharge power supply and the bit line at least by two steps according to an operation status. | 11-27-2008 |
20080298149 | CURRENT REDUCTION WITH WORDLINE BIT LINE SHORT-CIRCUITS IN DRAMS AND DRAM DERIVATIVES - An integrated circuit memory device includes a memory array with associated word lines and bit lines. A switching arrangement is connected between a word line and a first voltage source that selectively connects the word line to the first voltage source, and also is responsive to a short-circuit between the word line and the bit line. | 12-04-2008 |
20080304346 | Apparatus and method reducing aging in a data storage device - An apparatus for reducing aging of at least one transistor device employed in a read path for a data storage device may include: a signal unit coupled with the at least one transistor device and coupled with the data storage device. The signal unit may be coupled for receiving an input signal from the data storage device related with operation of the data storage device. The signal unit may provide a first signal to the at least one transistor device when the input signal is in a first state. The signal unit may provide a second signal to the at least one transistor device when the input signal is in a second state. The first signal may be a variable signal. | 12-11-2008 |
20080310243 | Semiconductor memory device for reducing precharge time - A semiconductor memory device for reducing a precharge time is provided. The semiconductor memory device may include a sense amplifier, a precharge unit and an equalizing circuit. The sense amplifier may sense and amplify a difference between data transmitted through a first bit line and data transmitted through a second bit line in response to a sense amplifier enable signal. The precharge unit may precharge voltage levels of the first bit line and the second bit line to a precharge voltage level in response to a precharge enable signal. The equalizing circuit may be connected to the sense amplifier and the precharge unit and may control the voltage levels of the first bit line and the second bit line to be equal to each other in response to the sense amplifier enable signal. The semiconductor memory device may reduce a time required to perform a precharge operation and/or minimize an increase of the circuit size. | 12-18-2008 |
20090003105 | SEMICONDUCTOR DEVICE - A high-speed and low-voltage DRAM memory cell capable of operating at 1 V or less and an array peripheral circuit are provided. A DRAM cell is comprised of a memory cell transistor and planar capacitor which utilize a FD-SOI MOST structure. Since there is no junction leakage current, loss of stored charge is eliminated, and the low-voltage operation can be realized. Further, a gate and a well in a cross-coupled type sense amplifier using FD-SOI MOSTs are connected. By this means, a threshold value dynamically changes and high-speed sensing operation can be realized. | 01-01-2009 |
20090003106 | Precharge control circuit - A precharge control circuit includes a precharge control unit and a precharge unit. The precharge control unit controls and outputs a precharge signal in response to a read command signal, a write command signal, and a first signal. The precharge unit precharges local input/output lines in response to a signal output from the precharge control unit. | 01-01-2009 |
20090003107 | SEMICONDUCTOR DEVICE - A semiconductor device includes a column decoder that generates a column selecting signal that selects any of a plurality of bit line pairs to which memory cells are connected according to a column address that is input; a bit line selecting switch that connects by the column selecting signal any of a plurality of bit line pairs and a data I/O line pair that outputs data that has been read from a memory cell to the outside; a data amplifier that amplifies a voltage differential of a data I/O line pair and outputs data that has been read to an output buffer; a data I/O line switch that is provided in the data I/O lines; an I/O line precharge circuit that precharges a data I/O line pair that is not on the side of the data amplifier; and an amplifier precharge circuit that precharges a data I/O line pair that is on the side of the data amplifier. | 01-01-2009 |
20090016131 | BIT LINE SENSE AMPLIFIER OF SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF - A bit line sense amplifier circuit for use in a semiconductor memory device, and a control method thereof, in which the bit line sense amplifier circuit is controlled to maintain a precharge state thereof until a sense amplifier enable signal to enable the sense amplifier circuit is applied, thereby preventing the bit line sense amplifier circuit of the semiconductor memory device from floating, and preventing or substantially reducing a coupling effect, thereby providing a precise data sensing and amplification operation. | 01-15-2009 |
20090016132 | Semiconductor memory devices, memory systems and computing systems including the same - A semiconductor memory device includes a reference current generating circuit configured to generate a bias signal in response to a precharge signal during a precharge operation. Each of a plurality of sense amplifier circuits is connected to a corresponding one of a plurality of bit lines. Each sense amplifier is configured to precharge a corresponding bit line in response to the bias signal. The reference current generating circuit is configured to maintain the bias signal at a level higher than a voltage of the bit lines, but lower than a supply voltage during a sensing operation. | 01-15-2009 |
20090016133 | SEMICONDUCTOR MEMORY AND SYSTEM - A first precharge circuit couples a bit line pair to a precharge voltage line in a standby period, and separates at least an access side of the bit line pair from the precharge voltage line in accordance with operation start of a word line driving circuit. A sense amplifier amplifies a voltage difference of a node pair after the operation start of the word line driving circuit. A switch circuit is provided between the bit line pair and the node pair. The switch circuit has coupled the access side of the bit line pair to an access side of the node pair at an instant of the operation start of the word line driving circuit, and has separated a non-access side of the bit line pair from a non-access side of the node pair at an instant of operation start of the sense amplifier. | 01-15-2009 |
20090027983 | HALF-SELECT COMPLIANT MEMORY CELL PRECHARGE CIRCUIT - A programmable precharge circuit includes a plurality of transistors. Each transistor has a different threshold voltage from other transistors of the plurality of transistors. Each transistor is configured to connect a supply voltage to a node, and the node is selectively coupled to bitlines in accordance with a memory operation. Control logic is configured to enable at least one of the plurality of transistors to provide a programmable precharge voltage to the node in accordance with a respective threshold voltage drop from the supply voltage of one of the plurality of transistors. | 01-29-2009 |
20090027984 | SEMICONDUCTOR DEVICE - The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to bit line LBL. | 01-29-2009 |
20090034351 | NON-VOLATILE MEMORY DEVICE AND METHOD OF HANDLING A DATUM READ FROM A MEMORY CELL - A memory device includes a pre-charge transistor for connecting/disconnecting the input line of a global data line driver to a supply voltage line. To reduce the flow of current through the pre-charge transistor even in a stand-by state, the pre-charge transistor is turned on when, at a same time, an enabling signal of a page buffer is asserted, and a low voltage functioning mode is selected and the memory device is not in a stand-by state. Alternatively, the memory device may be in a stand-by state but the datum read from the memory is high. The pre-charge transistor is securely turned off in all other cases. | 02-05-2009 |
20090040853 | METHOD OF PRECHARGING LOCAL INPUT/OUTPUT LINE AND SEMICONDUCTOR MEMORY DEVICE USING THE METHOD - A method and semiconductor memory device for precharging a local input/output line. The semiconductor memory device, which may have an open bit line structure, transmits data through local input/output lines that are coupled to bit lines of first to n-th memory cell array blocks (n being a natural number). The semiconductor memory device may include a precharge unit configured to generate a plurality of precharge signals and a controller configured to control precharging of the at least one local input/output line responsive to block information corresponding to activation of at least one of the memory cell array blocks and responsive to at least one of the precharge signals. | 02-12-2009 |
20090040854 | SENSE AMPLIFIER CIRCUIT - The disclosed embodiments relate to an equalization circuit, which may include a first sense amplifier having an input, the input being electrically isolated from an input to a second sense amplifier. An equalizer may be connected to the input to the first sense amplifier to provide an equalizing voltage to the input to the first sense amplifier. The input to the first sense amplifier may be equalized by the equalizing voltage independent from the input to the second sense amplifier. | 02-12-2009 |
20090046527 | AUTO PRECHARGE CIRCUIT SHARING A WRITE AUTO PRECHARGE SIGNAL GENERATING UNIT - In the auto precharge circuit, a plurality of read auto precharge signal generating units and a plurality of auto precharge signal output units share a single write auto precharge signal generating unit. Each read auto precharge signal generating unit logically combines an internal CAS command signal, an internal address signal and a pre auto precharge signal to generate an auto precharge detect signal and a read auto precharge signal. The write auto precharge signal generating unit delays the read auto precharge signal by a predetermined time to generate a write auto precharge signal. Each auto precharge signal output unit logically combines the internal CAS command signal, an internal address signal, a read auto precharge signal, and a write auto precharge signal to output an auto precharge signal. | 02-19-2009 |
20090059700 | PRECHARGE CONTROL CIRCUIT IN SEMICONDUCTOR MEMORY APPARATUS - A precharge circuit in a semiconductor memory apparatus includes a burst setting unit for controlling a state of a burst setting signal using delay elements in response to a burst start signal, wherein the delay elements operate in synchronization with a clock signal when the burst setting signal is deactivated, a burst termination unit for generating a burst termination signal in response to the burst setting signal, a precharge control unit for generating a read precharge control signal and a write precharge control signal in response to the burst termination signal, and a precharge signal generating unit for generating a precharge signal using the read precharge control signal or the write precharge control signal according to a read or write operation. | 03-05-2009 |
20090067273 | SEMICONDUCTOR STORAGE DEVICE - A voltage of a bit line connected to a memory cell is stepped up up to a power supply voltage by a precharge circuit. Before data is read from the memory cell, the voltage of the bit line is stepped down to a voltage level lower than the power supply voltage by a step-down circuit. A precharge switching element controls a connection between a high-potential-side power supply and the precharge circuit and a connection between a low-potential-side power supply and the precharge circuit. A power supply connecting circuit is provided between the precharge switching element and the high-potential-side power supply. A ground connecting circuit is provided between a connecting point at which the precharge switching element is connected to the power supply connecting circuit and the low-potential-side power supply. | 03-12-2009 |
20090073790 | MULTI-LEVEL MEMORY CELL UTILIZING MEASUREMENT TIME DELAY AS THE CHARACTERISTIC PARAMETER FOR LEVEL DEFINITION - A method for operating a memory cell and memory array. The method of memory cell operation entails receiving a request to read a binary value stored in the memory cell. A pre-charging operation pre-charges a bit-line capacitor in an electronic circuit formed by the memory cell to a pre-charge voltage. A word-line in the electronic circuit is then activated. A discharging operation discharges the bit-line capacitor through the said memory cell in the electronic circuit to the word-line. Additionally, an electron discharge time measurement is started when the word-line is activated. The electron discharge time measurement is stopped when the voltage level in the bit-line falls below a pre-defined reference voltage. A determining operation determines the binary value from the measured electron discharge time. | 03-19-2009 |
20090073791 | LOW VOLTAGE DATA PATH AND CURRENT SENSE AMPLIFIER - Methods, circuits, devices, and systems are provided, including a low voltage data path and current sense amplifier. One data path includes a local input/output (LIO) line and a global input/output (GIO) line each having first and second signal lines. A source follower circuit, coupled between the LIO line and the GIO line, includes first and second n-channel MOS (NMOS) transistors having a drain coupled to the first and the second signal lines of the GIO and a gate coupled to the first and the second signal lines of the LIO. A third NMOS transistor has a source coupled to the source of the first and the second NMOS transistors, a gate coupled to a reference voltage supply and a drain coupled to a drain of a fourth NMOS transistor. The fourth NMOS has a gate to which a selection signal is applied and a source coupled to a ground. | 03-19-2009 |
20090097346 | MEMORY WITH INDEPENDENT ACCESS AND PRECHARGE - Digital memory devices and systems, as well as methods of operating digital memory devices, that include access circuitry to access a first subset of a plurality of memory cells associated with a current access address during a current access cycle and precharge circuitry, disposed in parallel relative to the access circuitry, to precharge in full or in part a second subset of the plurality of memory cells associated with a next precharge address during the current access cycle. | 04-16-2009 |
20090103381 | ASYNCHRONOUS SENSE AMPLIFIER FOR READ ONLY MEMORY - The asynchronous sense amplifier for a ROM comprises a current-mirror circuit, a first negative feedback inverter, a second negative feedback inverter, a first transistor group, a second transistor group and a feedback transistor. The feedback transistor connects the junction of the first transistor group and the first set of the current-mirror circuit and/or the junction of the second transistor group and the second set of the current-mirror circuit to ground, where the feedback transistor is controlled by the output of the first negative feedback inverter and/or the second negative feedback inverter, and the feedback transistor is smaller than one transistor of the second transistor group. | 04-23-2009 |
20090109775 | Precharge voltage supply circuit and semiconductor memory device using the same - A precharge voltage supply circuit and a semiconductor memory device using the same are described. The precharge voltage supply circuit includes a first voltage supplier configured to reduce a precharge voltage and supply the reduced precharge voltage in response to a power down mode signal that is activated in a power down mode, a second voltage supplier configured to supply a power voltage in a predetermined section from a point of time when exiting the power down mode, and a third voltage supplier configured to supply the precharge voltage after a lapse of the predetermined section. | 04-30-2009 |
20090116324 | Apparatus for Guaranteed Write Through in Domino Read SRAM'S - In a digital device for facilitating recovery of a precharged dot line, periodically precharged by a precharge signal, that has been prematurely discharged as a result of an early read condition, a data input signal can have a selected one of a first value and a second value. The first value is a value that would be reflected by the dot line being in a charged state. A logic device that is responsive to the data input signal causes charge to be applied to the dot line when the data signal has the first value. | 05-07-2009 |
20090122626 | Method and Apparatus for Selectable Guaranteed Write Through - A device maintains a state of a precharged dot line that is periodically precharged by a global precharge signal. The device includes a data input signal that can have a selected one of a first value and a second value. The first value is a value that would be reflected by the dot line being in a charged state. A precharge circuit is responsive to a global precharge signal and is configured to precharge the dot line. A guaranteed write through logic device is responsive to the data input signal. The guaranteed write through logic device ensures that charge is applied to the dot line whenever the data. A guaranteed write through inhibitor that is responsive to a write through gate signal is configured to inhibit selectively the guaranteed write through logic device from applying charge to the dot line when the write through gate signal is in a guarantee inhibit state. | 05-14-2009 |
20090122627 | MEMORY WITH PROGRAMMABLE STRIDES - Embodiments of the present disclosure provide methods, apparatuses and systems including a storage configured to store and output multiple address strides of varying sizes to enable access and precharge circuitry to access and precharge a first and a second group of memory cells based at least in part on the multiple address strides during operation of the host apparatus/system, the first and second group of memory cells being different groups of memory cells. | 05-14-2009 |
20090122628 | DEVICE WITH PRECHARGE/HOMOGENIZE CIRCUIT - A device with a precharge/homogenize circuit. One embodiment provides at least one switching element is acting as a homogenizer, and at least one switching element is acting as a precharger. The diffusion region of the switching element acting as a homogenizer is separated from the diffusion region of the switching element acting as a precharger. | 05-14-2009 |
20090122629 | SEQUENTIAL ACCESS MEMORY METHOD - A sequential access memory (“SAM”) device, system and method is provided that includes a memory array configured to store a group of bytes on each of a plurality of rows. A plurality of bit-lines transfer each of the group of bytes into and out of the memory array, and a pre-charging unit is configured to pre-charge the plurality of bit-lines once per each transfer of one of the group of bytes into or out of one of the plurality of rows. The device operates by accessing a memory array in a SAM device by activating a selected row in the memory array, pre-charging a plurality of bit-lines that provide access to the memory array, and accessing the memory array before the plurality of bit-lines are pre-charged a second time. | 05-14-2009 |
20090129187 | INTERNAL VOLTAGE GENERATOR - An internal voltage generation device includes a plurality of output nodes; a bit line precharge voltage generation unit for generating a bit line precharge voltage; a first voltage drop unit for transferring the bit line precharge voltage to a first output node after decreasing the bit line precharge voltage by a first voltage drop amount in response to a test mode signal; and a second voltage drop unit for transferring the bit line precharge voltage to a second output node after decreasing the bit line precharge voltage by a second voltage drop amount in response to the test mode signal, wherein the second voltage drop amount is greater than the first voltage drop amount. | 05-21-2009 |
20090147602 | SENSE AMPLIFIER FOR CONTROLLING FLIP ERROR AND DRVING METHOD THEREOF - A sense amplifier and a driving method is described for resolving a flip failure occurrence where the voltage applied across the bit line is within an acceptable threshold range when the data is delivered to the data bus. The driving method includes disconnecting a bit line from a sense amplifying circuit according to a bit line select control signal after performing a read operation according to a read request. Then, connecting the sense amplifying circuit to a data bus according to a column select control signal after the bit line is disconnected from the sense amplifying circuit and deactivating an output terminal of the sense amplifier circuit that is disconnected from the bit line and connected to the data bus during a restore section synchronized to a command following the read command. Finally, delivering the data on the bit line to the output terminal of the sense amplifying circuit to update the output terminal of the sense amplifying circuit by connecting the sense amplifying circuit to to the bit line according to the bit line select control signal. | 06-11-2009 |
20090147603 | MEMORY WITH LOW POWER MODE FOR WRITE - The present invention describes circuitry and a method of providing a low power WRITE mode of operation for an integrated circuit comprising an SRAM memory to provide a reduced IDDQ relative to the IDDQ of a full active mode. In one aspect, the circuitry includes an SRAM memory array, mode control circuitry coupled to the array and configured to alter a supply voltage level to the SRAM array based on a mode of operation. The circuitry also includes control inputs coupled to the mode control circuitry for selecting one of the low power write mode, the full active mode, and optionally a retention mode of operation. The mode control circuitry is configured to receive the control inputs to select one of the three modes of operation, and to alter one or more supply voltage levels to the array, for example, the Vss supply voltage using a Vss supply circuit and the Vdd supply voltage using a Vdd supply circuit, based on the selected mode of operation. The mode control circuitry may also comprise a bitline precharge circuit configured to alter a bitline precharge voltage. | 06-11-2009 |
20090154274 | Memory Read Stability Using Selective Precharge - A memory device utilizes selective precharge and charge sharing to reduce a bit line voltage before accessing a bit cell. A reduction in bit line voltage is achieved by precharging different sections of the bit line to different voltages (e.g., a supply voltage and ground) and using charge sharing between these sections. Read stability improves as a result of the reduction of bit line voltage. The relative capacitance difference between bit line sections determines the bit line voltage after charge sharing. Thus, the memory device is tolerant to process or temperature variations. The bit line voltage may be controlled in design by selecting the sections that are precharged to supply voltage or ground. | 06-18-2009 |
20090161461 | SEMICONDUCTOR MEMORY DEVICE MAINTAINING WORD LINE DRIVING VOLTAGE - A semiconductor memory for maintaining a word line driving voltage includes a cell array and a sense amplifier adjacent to the cell array. A dummy cell is formed at a peripheral portion of the cell array in such a manner that a dummy bit line and a word line intersect. A control circuit switches the connection state between a first section of the dummy bit line passing through the cell array and a second section of the dummy bit line passing through the sense amplifier. The connection state switches according to the operation mode of the cell array. The dummy bit line is floated when the operation mode is an active mode and a precharge voltage is provided to the dummy bit line when the operation mode is a precharge mode. | 06-25-2009 |
20090168574 | METHOD OF DRIVING 1-TRANSISTOR TYPE DRAM HAVING AN NMOS OVERLAIN ON TOP OF AN SOI LAYER - Driving a 1-transistor DRAM composed of an NMOS on top of a SOI layer such that the 1-transistor DRAM has a corresponding parasitic bipolar transistor component includes precharging, shifting, and deactivating steps. Implementing these steps can result in enhancing the performance of reading, writing and storing binary logic information within the 1-transistor DRAM memory device. | 07-02-2009 |
20090175107 | Apparatus for and Method of Current Leakage Reduction in Static Random Access Memory Arrays - A novel and useful mechanism for reducing current leakage in a static random access memory array which significantly reduces the power requirements of the memory array. The method enables the steady state of all local and global bit lines in an SRAM array to be discharged during both active and inactive modes. The memory array consists of memory cells having an N channel field effect transistor read stack. A mechanism is provided to evaluate data from memory cells where the steady state of local and global read bit lines is discharged. | 07-09-2009 |
20090185440 | ACTIVE CYCYLE CONTROL CIRCUIT FOR SEMICONDUCTOR MEMORY APPARATUS - An active cycle control circuit for a semiconductor memory apparatus is configured to precharge a word line corresponding to a read cycle, and activate a word line corresponding to a refresh request signal in response to the refresh request signal generated during the read cycle. | 07-23-2009 |
20090190424 | SEMICONDUCTOR CIRCUIT - Embodiments relate to semiconductor devices and methods for fabricating semiconductor devices. According to embodiments, a semiconductor device may include a bit line and a bit line bar. The device may also include a precharge controller that may generate a precharge control signal, and NMOS transistors and PMOS transistors to precharge the bit line and the bit line bar in response to the precharge control signal. According to embodiments, a precharge speed of a bit line in a semiconductor device may be improved and an operating cycle time of a memory device may also be improved. | 07-30-2009 |
20090190425 | SENSE AMPLIFIER READ LINE SHARING - A memory is provided that practices global read line sharing by including: a global read line, the memory being adapted to be pre-charge the global read line prior to a read operation; an I/O circuit to receive the global read line; and a plurality of sense amplifiers, each sense amplifier being multiplexed with respect to the global read line such that only a selected one of the sense amplifiers in the plurality is activated during a read operation to determine a bit decision, the memory being adapted to discharge the pre-charged global read line if the bit decision from the activated sense amplifier equals one, the pre-charged global read line thereby staying pre-charged if the bit decision from the activated sense amplifier equals zero. | 07-30-2009 |
20090213673 | Data processor memory circuit - A memory circuit for use in a data processing circuit is described, in which memory cells have at least two states, each state being determined by both a first voltage level corresponding to a first supply line and a second voltage level corresponding to a second supply line. The memory circuit comprises a readable state in which information stored in a memory cell is readable and an unreadable state in which information stored in said memory cell is reliably retained but unreadable. Changing the first voltage level but keeping the second voltage level substantially constant effects a transition between the readable state and the unreadable state. In use, the static power consumption of the memory cell in the unreadable state is less than static power consumption of the memory cell in the readable state. | 08-27-2009 |
20090213674 | Method and device for controlling a memory access and correspondingly configured semiconductor memory - Method and device for controlling a memory access and correspondingly configured semiconductor memory | 08-27-2009 |
20090231938 | METHOD OF OPERATING A NON-VOLATILE MEMORY DEVICE - A method of operating a non-volatile memory device reduces a time for discharging a precharged voltage when a program operation or a read operation is performed, thereby decreasing a total operation time of the non-volatile memory device. The non-volatile memory device discharges a bit line and a word line using only a control signal without reading an algorithm block when a precharged voltage is discharged. The method of operating a non-volatile memory device includes detecting an operation command; generating algorithm blocks for generating an operation voltage, for precharging a bit line and a word line, and for performing a specific operation in accordance with the operation command; outputting a discharge enable control signal for the bit line and the word line; and reading an algorithm of turning off and discharging a voltage generating means for generating the operation voltage. | 09-17-2009 |
20090238019 | Bit line precharge circuit having precharge elements outside sense amplifier - A bit line precharge circuit capable of improving bit line precharge operation includes a first precharge element for precharging a first bit line in response to a first precharge signal, a precharge unit for precharging second and third bit lines in response to a second precharge signal, and a second precharge element for precharging a fourth bit line in response to a third precharge signal. | 09-24-2009 |
20090251979 | METHOD FOR SUPPRESSING CURRENT LEAKAGE IN MEMORY - A method for suppressing a current leakage of a memory is provided. The memory at least includes a memory cell, an equalizing circuit, a current limiter, a word line and a pair of complementary bit lines. The method includes: having the memory cell entering a pre-charging mode; having the equalizing circuit and the current limiter being normally operated, so as for pre-charging the pair of complementary bit lines; applying a periodic control signal to the current limiter for controlling the current limiter to be either conducting or non-conducting, in which when the current limiter is non-conducting, a standby current leakage of the memory is suppressed, in which the standby current leakage is caused by a short circuit between the word line and the pair of complementary bit lines. | 10-08-2009 |
20090251980 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a discharge circuit that discharges bit lines to a ground potential, a sense amplifier of a single-ended input configuration, and a charging transistor connected between a power supply and an input node of the sense amplifier. The charging transistor charges a bit line from a side of the input node of the sense amplifier via the selected column select transistor which is set to an on state. When a current path to the ground from the bit line to which a selected memory cell is connected is turned off during reading, the input node of the sense amplifier is charged by the charging transistor, and a potential at the input node of the sense amplifier is thereby raised. After the input node of the sense amplifier has been further charged with the one of the column select transistors turned off, the reading operation is performed. | 10-08-2009 |
20090268535 | SEMICONDUCTOR DEVICE GUARANTEEING STABLE OPERATION - A semiconductor device includes a data line pair formed of a data line and a complementary data line; a first sensing amplification unit including a first sensing amplifier and a second sensing amplifier that are cross-coupled with the data line and the complementary data line; a first variable current source supplying or flowing out a first variable current to the first sensing amplifier; and a second variable current source supplying or flowing out a second variable current to the second sensing amplifier. A current amount of the first variable current is different from a current amount of the second variable current. | 10-29-2009 |
20090268536 | Precharge voltage supply circuit and semiconductor device using the same - A precharge voltage supply circuit and a semiconductor device using the same are disclosed. The semiconductor device includes a first comparator for comparing a precharge voltage with a first reference voltage having a first voltage level and outputting a first compare signal as a result of the comparison, a second comparator for comparing the precharge voltage with a second reference voltage having a second voltage level and outputting a second compare signal as a result of the comparison, a decoder configured to receive and decode the first compare signal and the second compare signal and output a plurality of control signals as a result of the decoding, and a precharge voltage supply circuit configured to receive the plurality of control signals and supply the precharge voltage. | 10-29-2009 |
20090273997 | Controlling Apparatus and Controlling Method for Controlling a Pre-Charge Activity on a SRAM Array - A controlling apparatus and a controlling method for controlling a pre-charge activity on a SRAM array are provided. The controlling apparatus comprises: a detecting module, a controlling module and a pre-charge module. The detecting module is to detect whether the row address of the SRAM array in operation is changed and generate a row-changing signal according to the detection result; the controlling module is to detect an operation mode of the SRAM array and generate a disable signal according to the row-changing signal and the operation mode; and the pre-charge module is to generate a pre-charge signal according to a pseudo-pre-charge signal and the disable signal, wherein the pre-charge signal substantially controls the pre-charge activity on the SRAM cell in operation. | 11-05-2009 |
20090303819 | WRITE AND READ ASSIST CIRCUIT FOR SRAM WITH POWER RECYCLING - A memory circuit for reading and writing data into a SRAM memory array using charge recycling is presented. The write and read circuit includes a cell voltage level switch, a recycle charge storage, a precharge switch, a write enable switch, and column decoder. The cell voltage level switch is connected to a low power supply and a high power supply and has two states of operation: a write operation state and a read operation state. For each state of operation, the voltage level switch selectively provides a power supply if a column has been selected or if the operation is a read or write. The recycle charge storage stores excess charge from SRAM cells after a read operation or after a write operation in unselected columns. After the read or write operation, the recycle charge storage discharges excess charge to the bitlines during bitline precharging. | 12-10-2009 |
20090303820 | APPARATUS AND METHOD FOR LOW POWER SENSING IN A MULTI-PORT SRAM USING PRE-DISCHARGED BIT LINES - A method for sensing the contents of a memory cell within a static random access memory (SRAM) includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being accessed; energizing the bit line to a first voltage potential different than the zero voltage potential during an access of the memory cell; and sensing the memory cell contents when the associated bit line has reached the first voltage potential. | 12-10-2009 |
20090303821 | Apparatus and Method for Low Power, Single-Ended Sensing in a Multi-Port SRAM Using Pre-Discharged Bit Lines - An apparatus and method for low power, single-ended sensing in a multi-port static random access memory (SRAM) using pre-discharged bit lines includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being accessed; releasing the bit line from being held at a zero voltage potential when the memory cell is being accessed; charging the bit line to a first voltage potential greater in value than the zero voltage potential during an access of the memory cell, wherein charging the bit line to a first voltage potential occurs for a first predetermined period of time after access to the memory cell has begun; and sensing the memory cell contents during an access of the memory cell, wherein sensing of the memory cell contents occurs for a second predetermined period of time after access to the memory cell has begun. | 12-10-2009 |
20090303822 | BIT LINE EQUALIZING CONTROL CIRCUIT OF A SEMICONDUCTOR MEMORY APPARATUS - A bit line equalizing control circuit of a semiconductor memory apparatus includes a control signal generating unit that receives a bank active signal to generate a control signal such that a bit line equalizing signal is delayed and enabled, a bit line equalizing selecting unit that generates a bit line equalizing detection signal in response to a plurality of mat select signals and the control signal, and a driver that receives the bit line equalizing detection signal to generate the bit line equalizing signal. | 12-10-2009 |
20090316509 | MEMORY WITH HIGH SPEED SENSING - A memory including a data line, a sense amplifier, and an array of memory cells. The memory includes a transistor for coupling the data line to memory cells of the array for reading. The transistor is biased at a voltage that is higher than a voltage that the data line is biased during precharging. The transistor is part of a regulation circuit. The regulation circuit includes transistors with a higher dielectric breakdown voltage than transistors of the sense amplifier. | 12-24-2009 |
20100008171 | READ ASSIST CIRCUIT OF SRAM WITH LOW STANDBY CURRENT - A SRAM memory with a read assist circuit is presented. The read assist circuit uses bitline voltage level switches, which are connected to a low power supply and a high power supply. The bitline voltage level switches have a write operation state, a read operation state, and a standby operation state. The write operation state selectively provides the high power supply to bitlines in columns selected for a write operation, and provides the low power supply to bitlines in the remaining columns. The read operation state selectively provides the low power supply to bitlines in columns selected for the read operation, and provides the low power supply to bitlines in the other columns. The standby operation state selectively provides the low power supply to bitlines in all columns when not in the read operation state or the write operation state. | 01-14-2010 |
20100008172 | DYNAMIC TYPE SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD OF THE SAME - A dynamic type semiconductor memory device includes a sense amplifier connected with a bit line pair to amplify and sense a voltage difference on the bit line pair; a precharge circuit configured to precharge the bit line pair to a power supply voltage on a lower side in response to a first control signal; a memory cell capacitance having one end which is connected with the bit line pair through a first switch circuit which is controlled in response to a signal on a word line; and a reference cell capacitance having one end which is connected with the bit line pair through a second switch circuit which is controlled in response to a signal on a reference word line. The other end of the memory cell capacitance and the other end of the reference cell capacitance are electrically separated. | 01-14-2010 |
20100014370 | PRECHARGE AND EVALUATION PHASE CIRCUITS FOR SENSE AMPLIFIERS - A precharge and evaluation circuit for a memory sense amplifier includes a first precharge-phase transistor having a source coupled to a power-supply potential, a gate coupled to a precharge control line, and a drain. A second precharge-phase transistor has a drain coupled to the drain of the first precharge-phase transistor, a source, and a gate coupled to the source through a feedback circuit. A first read-phase transistor has a source coupled to the power-supply potential, and a gate and drain coupled to a comparator. A second read-phase transistor has a drain coupled to the drain of the first read-phase transistor, a source coupled to the source of the second precharge-phase transistor, and a gate coupled to the source of the second read-phase transistor through a feedback circuit. A column decoder is coupled to the sources of the second precharge-phase and second read-phase transistors. | 01-21-2010 |
20100027360 | INTEGRATED CIRCUIT HAVING AN ARRAY SUPPLY VOLTAGE CONTROL CIRCUIT - An integrated circuit comprises a plurality of memory cells and an array supply voltage control circuit. The plurality of memory cells are organized in rows and columns. A row comprises a word line and all of the memory cells coupled to the word line. A column comprises a bit line pair and all of the memory cells coupled to the bit line pair. The array supply voltage control circuit is coupled to the plurality of memory cells. The array supply voltage control circuit is for receiving a power supply voltage and for providing a reduced power supply voltage to memory cells of a selected column during a write operation in response to a voltage differential on the bit line pair of the selected column. | 02-04-2010 |
20100027361 | Information Handling System with SRAM Precharge Power Conservation - An information handling system (IHS) includes a processor with on-chip or off-chip SRAM array. After a read operation, a control circuit may instruct the SRAM array to conduct a precharge operation, or alternatively, instruct the SRAM array to conduct an equalize bitline voltage operation. A read operation may follow the precharge operation or the equalize bitline voltage operation. The control circuit may instruct the SRAM array to conduct an equalize bitline voltage operation if an equalized voltage of a bitline pair exhibits more that a predetermined amount of voltage. Otherwise, the control circuit instructs the SRAM array to conduct a precharge operation before the next read operation. | 02-04-2010 |
20100027362 | SEMICONDUCTOR MEMORY DEVICE FOR LOW VOLTAGE - A semiconductor memory device includes a first cell array including a plurality of unit cells and a bit line sense amplifying unit for sensing and amplifying data signals stored in the unit cells. Each unit cell is provided with a PMOS transistor and a capacitor. Therefore, the semiconductor memory device efficiently operates with low voltage without any degradation of operation speed. | 02-04-2010 |
20100046309 | RESET CIRCUIT FOR TERMINATION OF TRACKING CIRCUITS IN SELF TIMED COMPILER MEMORIES - A method and circuit for termination of internal cycle and its associated tracking circuits in high performance self timed compiler memories is disclosed. In one embodiment, a method of timing the precharging of BLs in a self timed compiler memory array includes initiating an internal clock during the start of a read/write cycle by a control block, triggering DWL and WLs to go high upon initiating the internal clock by the control block, triggering DBL and BLs to go low upon the DWL and WLs going high by the control block, generating a reset BL signal upon the DWL going high and the DBL going low by the tracking circuit, disabling the DBL from going further low upon receiving the reset BL signal by the tracking circuit, and precharging the DBL to go high upon receiving the reset BL signal by the precharge circuit. | 02-25-2010 |
20100046310 | Semiconductor memory device including memory cell array having dynamic memory cell, and sense amplifier thereof - A semiconductor memory device and a sense amplifier thereof are provided. The semiconductor memory device includes a memory cell array and a plurality of sense amplifiers. The memory cell array includes a memory cell array block having a plurality of memory cells. Each of the plurality of sense amplifiers is configured to apply, based on a restore signal, a first voltage to a corresponding bit line to restore a first data value in a selected memory cell of the plurality of memory cells if a read value in the selected memory cell is the first data value and apply a second voltage based on the restore signal to the corresponding bit line to prevent a second data value from being restored in the selected memory cell if the read value in the selected memory cell is the second data value. | 02-25-2010 |
20100054064 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory apparatus includes: a bit line; a word line; a local bit line; a first switch unit provided between the local bit line and the bit; a memory cell connected to the bit line and the word line; a memory cell array including the memory cell; a first sense circuit connected to the bit line and configured to amplify a signal read out from the memory cell; and a second sense circuit connected to the local bit lines and configured to amplify a signal amplified by the first sense circuit, wherein the first switch unit disconnects the local bit line from the bit line when the first sense circuit amplifies the signal, and connects the local bit line to the bit line when the second sense circuit amplifies the signal amplified by the first sense circuit. | 03-04-2010 |
20100061169 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - An object of the present invention is to provide a technique of reducing the leakage current of a drive circuit for driving a circuit that must retain a potential (or information) when in its standby state. | 03-11-2010 |
20100067316 | CHARGE MAPPING MEMORY ARRAY FORMED OF MATERIALS WITH MUTABLE ELECTRICAL CHARACTERISTICS - A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic. | 03-18-2010 |
20100074040 | Method and Apparatus for Measuring Statistics of Dram Parameters with Minimum Perturbation to Cell Layout and Environment - The present invention provides a method for measuring statistics of dynamic random access memory (DRAM) process parameters for improving yield and performance of a DRAM. The basic principles for measuring capacitance are similar to charge based capacitance (CBCM), however the present invention differs in several fundamental aspects. In one embodiment, the method includes receiving a selection of a storage cell of the DRAM; measuring a storage cell capacitance (C | 03-25-2010 |
20100103755 | Read Assist for Memory Circuits - A method increases stability of a memory circuit by pre-charging at least one bit line of the memory circuit to a first voltage, pre-charging at least one other bit line of the memory circuit to a second voltage, and equalizing charge across the bit lines so that the bit lines are pre-charged with a third voltage. | 04-29-2010 |
20100103756 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of memory cells that are arranged at intersections of a word line with bit line pairs, a precharge circuit that is arranged for each of the bit line pairs and is configured to precharge each of the bit line pairs, and a Y-switch circuit that is arranged for each of the bit line pairs and is configured to select each of the bit line pairs. The semiconductor memory device further includes a mode switching unit that switches the normal mode and the test mode in accordance with a mode selection signal that is externally supplied, a plurality of individual control units that control operation of each of the precharge circuits in accordance with operation of each of the Y-switch circuits in the normal mode, and a block control unit that collectively turns off all of the precharge circuits in the test mode. | 04-29-2010 |
20100110813 | PRECHARGE CONTROL CIRCUITS AND METHODS FOR MEMORY HAVING BUFFERED WRITE COMMANDS - Memories, precharge control circuits, methods of controlling, and methods of utilizing are disclosed, including precharge control circuits for a memory having at least one bank of memory. One such control circuit includes at least one precharge preprocessor circuit. The precharge preprocessor circuit is coupled to a respective bank of memory and is configured to prevent precharge of the respective bank of memory until after execution of buffered write commands issued to the respective bank of memory is completed. | 05-06-2010 |
20100118631 | Semiconductor memory devices with mismatch cells - A semiconductor memory device having the mismatch cell makes a capacitance difference between a bit line pair relatively large during a read operation using at least one dummy memory cell as a mismatch cell selected together with a corresponding memory cell. Therefore, data of a semiconductor memory device may be detected more easily. | 05-13-2010 |
20100124134 | Semiconductor device - A semiconductor device includes a plurality of memory cells and a sense amplifier circuit which further includes a plurality of elements such as MOS transistor formed in a well, wherein sensitive element, which are sensitive to dispersion of an impurity density in the well, is distanced from a boundary and are disposed in the center region of the well, while non-sensitive element is disposed in the peripheral region close to the boundary in the well. Since sensitive element requiring precise control of threshold voltage is disposed in the center region having uniform impurity density, and non-sensitive element allowing for less precise control of threshold voltage is disposed in the peripheral region suffering from uneven impurity density, it is possible to effectively use the overall area of the well and to thereby suppress an increase in the layout area of chips. | 05-20-2010 |
20100124135 | Semiconductor memory devices having hierarchical bit-line structures - The semiconductor memory device includes a memory cell array and a switching circuit. The memory cell array includes a plurality of first memory cells connected between word lines and first local bit lines, and a plurality of second memory cells connected between the word lines and second local bit lines. The switching circuit is configured to respectively connect the first local bit lines to first global bit lines during a first sensing period, and to respectively connect the second local bit lines to second global bit lines during a second sensing period of a reading operation. The semiconductor memory device further includes a sensing circuit configured to sense and amplify data from the first global bit lines during the first sensing period, and to sense and amplify data from the second global bit lines during the second sensing period of the reading operation. | 05-20-2010 |
20100135094 | HIGH INTEGRATED SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device, having a 6F2 open bit line structure, connects each bit line of a bit line pair to a respective bit line of a neighboring bit line pair for a precharge operation so that a layout size of the semiconductor memory device decreases. Plural first precharge units each precharge one bit line of a first bit line pair and one bit line of a second bit line pair in response to a bit line equalizing signal. Plural sense amplifiers each sense a data bit supplied to a respective one of the first and second bit line pairs and amplify sensed data. | 06-03-2010 |
20100157705 | Register file circuits with P-type evaluation - Provided herein is a new RF implementation. Instead of using a pre-charged High node for one or more of its evaluation nodes, it employs an evaluation (or evaluate) node that is discharged (Low) prior to evaluation and enters evaluation in a discharged state. In some embodiments, with such “normally Low” evaluation nodes, it uses pull-up stack devices, rather than pull-down devices, to charge the evaluate node during an evaluate phase if the logic so dictates. | 06-24-2010 |
20100157706 | METHODS AND APPARATUSES FOR IMPROVING REDUCED POWER OPERATIONS IN EMBEDDED MEMORY ARRAYS - Methods and apparatuses are presented for improving reduced power operations in embedded memory arrays. Some embodiments may include a microprocessor, the microprocessor including at least one execution unit, a memory coupled to the execution unit, the memory including, a memory cell comprising a memory cell bus, a power circuit selectively coupling the memory cell bus to a first power plane and a second power plane, where the memory cell bus is coupled to the second power plane when the power circuit is substantially off, and a bit line pre-charge circuit coupled to the power circuit, where the power circuit selectively couples the first power plane to the pre-charge circuit for a predetermined period of time. | 06-24-2010 |
20100165767 | Asymmetric Sense Amplifier - Sensing circuits for determining the state of memory cells include a sense amplifier. The sense amplifier includes an imbalanced cross-coupled latch (ICL), a first gate field effect transistor (FET) between a bit line (BL) and a first output node, and a second gate FET between a bit line inverse (BLB) and a second output node. The ICL includes a first pull down FET between the first output node and an enable FET connected to electrical ground, and a second pull down FET between the second output node and the enable FET. Channel widths of the second pull down FET and the second gate FET are greater than channel widths of the first pull down FET and the first gate FET to enhance the ability to detect a one (1) and a zero (0) stored in a memory cell connected to the sense amplifier. | 07-01-2010 |
20100165768 | BIT LINE PRECHARGE CIRCUIT AND A SEMICONDUCTOR MEMORY APPARATUS USING THE SAME - A bit line precharge circuit includes a precharge signal generation unit configured to generate first and second precharge signals that are enabled at different timing points by receiving a bit line equalizing signal; a first precharge unit configured to connect a pair of bit lines to each other in response to the first precharge signal and supply a bit line precharge voltage to the pair of bit lines; and a second precharge unit configured to supply the bit line precharge voltage to the bit line in response to the second precharge signal. | 07-01-2010 |
20100165769 | SEMICONDUCTOR MEMORY DEVICE HAVING AUTO-PRECHARGE FUNCTION - To provide a semiconductor memory device including: a first clock generation circuit and a second clock generation circuit that generate a first internal clock and a second internal clock, respectively; a latency counter that counts latency synchronously with the first internal clock; and a recovery counter that counts a write recovery period synchronously with the second internal clock. The second clock generation circuit activates the second internal clock when auto-precharge is designated, and deactivates the second internal clock when the auto-precharge is not designated. With this configuration, the recovery counter does not perform any counting operation when an auto-precharge function is not operated, and thus unnecessary power consumption can be prevented. | 07-01-2010 |
20100172198 | DATA STORAGE ELEMENT SENSING DEVICE - A sensing device for a data storage system may include a sensing circuit, a pull-down circuit, and a pull-up circuit. The sensing circuit may sense discharging of a desired bit line or a complementary bit line and may generate a desired output. The pull-down circuit may be coupled to the bit line and the complementary bit line for enhancing the discharging rate and may increase the sensing speed of the storage system. The pull-up circuit may control the discharging of an undesired bit line or complementary bit line. | 07-08-2010 |
20100177580 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND OPERATING METHOD THEREOF - Even when memory capacity of a memory that uses a replica bit-line is made higher, fluctuations of a generating timing of a sense-amplifier enable signal are reduced. A semiconductor integrated circuit device comprises a plurality of word lines, a plurality of bit-lines, a plurality of ordinary memory cells, an access control circuit, a plurality of sense-amplifiers, first and second replica bit-lines, first and second replica memory cells, and first and second logic circuits. The first and second replica memory cells are connected to the first and second replica bit-lines, respectively; inputs of the first and second logic circuits are connected to the first and second replica bit-lines, respectively; a sense-amplifier enable signal is generated from an output of the second logic circuit; and this signal is supplied to a plurality of sense-amplifiers. | 07-15-2010 |
20100182860 | Semiconductor memory device implementing full-VDD bit line precharge scheme using bit line sense amplifier - A semiconductor memory device using a full-VDD bit line precharge scheme by using a bit line sense amplifier includes a precharge unit precharging a bit line and a complementary bit line from a power voltage to a voltage that is less than the power voltage by a predetermined voltage, and the bit line sense amplifier including first and second transistors serially connected between the bit line and the complementary bit line to be cross-coupled to each other, wherein a gate of the first transistor is connected to the complementary bit line and a gate of the second transistor is connected to the bit line. The precharge unit precharges, in response to a first precharge signal, the bit line and the complementary bit line to a voltage that is less than the power voltage by a threshold voltage of the first or second transistor, and precharges, in response to a second precharge signal, the bit line and the complementary bit line from the power voltage to a voltage that is less than the power voltage by half of a threshold voltage of the first or second transistor. | 07-22-2010 |
20100188912 | SEMICONDUCTOR MEMORY CIRCUIT AND CONTROL METHOD FOR READING DATA - A semiconductor memory device includes a first memory circuits connecting to a first bit line, a second bit line and a word line, a first pre-charge control circuit connecting to a first pre-charge control line, the first bit line and the second bit line and that pre-charges the first bit line and the second bit line on the basis of the input from the first pre-charge control line, and a read control circuit having a first transistor, a second transistor, a third transistor and a fourth transistor, wherein the fourth transistor is brought into conduction on the basis of the input from a charged global-bit-line driver control line, the column having the first bit line and the second bit line is thus selected, and the information held in the memory circuit connecting to the driven word line among the memory circuits is output to the third bit line. | 07-29-2010 |
20100202229 | METHOD AND APPARATUS FOR SELECTIVE DRAM PRECHARGE - Apparatus and method for using a precharge command in which a plurality of address lines are individually used to specify which banks of memory cells within a memory device have an open row that is to be closed | 08-12-2010 |
20100202230 | MEMORIES WITH FRONT END PRECHARGE - Methods, apparatuses and systems of operating digital memory where the digital memory device including a plurality of memory cells receives a command to perform an operation on a set of memory cells, where the set of memory cells contains fewer memory cells than the device as a whole and where the device performs the operation including selectively precharging on the front end of the operation, in response to the received command, only a set of bit lines associated with the set of memory cells. | 08-12-2010 |
20100208538 | SENSING CIRCUIT FOR SEMICONDUCTOR MEMORY - A sensing circuit for a semiconductor memory includes a multiplexer coupled to a bit line and a data line coupling the multiplexer to a sense amplifier. The data line is configured to be precharged to a voltage level higher than a precharge voltage level of the bit line. | 08-19-2010 |
20100214859 | Implementing Boosted Wordline Voltage in Memories - A method and wordline voltage boosting circuit for implementing boosted wordline voltage in memories, and a design structure on which the subject circuit resides are provided. The wordline voltage boosting circuit receives a precharge signal, uses a switching transistor coupled to a bootstrap capacitor, and generates a boosted voltage level responsive to the precharge signal. The boosted voltage level is applied to a voltage supply of an output stage of a wordline driver, causing the wordline voltage level of a selected wordline to be boosted. The switching transistor is controlled by the precharge signal and a node of the bootstrap capacitor supplying the boosted voltage level is driven high by the switching transistor. | 08-26-2010 |
20100226191 | Leakage Reduction in Memory Devices - A memory device includes a core array that includes memory cells. The memory device also includes a headswitch coupled to the core array and a positive supply voltage. The headswitch reduces leakage current from the core array by disconnecting the core array from the positive supply voltage. Additionally, head switches are added for pre-charge devices to further reduce leakage current. | 09-09-2010 |
20100226192 | Semiconductor memory device having improved local input/output line precharge scheme - A data path circuit of a semiconductor memory device includes: a bit line sense amplifier driven by a first power supply voltage; a local input/output line sense amplifier; a column selecting unit operatively connecting a pair of bit lines connected to the bit line sense amplifier and a pair of local input/output lines connected to the local input/output line sense amplifier in response to a column selection signal; and a local input/output line precharge unit precharging the pair of local input/output lines with a second power supply voltage different from the first power supply voltage during a period for which the column selection signal is in an inactive state. | 09-09-2010 |
20100238749 | SEMICONDUCTOR STORAGE DEVICE - After a bit line is pre-charged by a pre-charge circuit that pre-charges the bit line, the voltage of a power supply for actuating a sense amplifier, which amplifies a signal read out from a memory cell, is switched. | 09-23-2010 |
20100254206 | Cache Optimizations Using Multiple Threshold Voltage Transistors - In one embodiment, a memory circuit includes one or more memory cells that include transistors having a first nominal threshold voltage, and interface circuitry such as word line drivers and bit line control circuitry that includes one or more transistors having a second nominal threshold voltage that is lower than the first nominal threshold voltage. For example, the word line driver circuit may be driven by signals from a lower voltage domain than the memory circuit's voltage domain. Lower threshold voltage transistors may be used for those signals, in some embodiments. Similarly, lower threshold voltage transistors may be used in the write data driver circuits. Other bit line control circuits may include lower threshold voltage transistors to permit smaller transistors to be used, which may reduce power and integrated circuit area occupied by the memory circuits. | 10-07-2010 |
20100271892 | PRECHARGE METHOD OF SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME - A precharge method of a semiconductor memory device that controls a precharge start time of each bank during a bank precharge operation, and a semiconductor memory device using the method, are provided. The device may latch an active or write order of respective banks and differently control precharge start times of the respective banks according to the latched active or write order during a plural-bank precharge operation to allow a plurality of banks to start precharge operations at different times. | 10-28-2010 |
20100290300 | SEMICONDUCTOR INTEGRATED DEVICE - Provided is a semiconductor integrated device including a semiconductor memory circuit and a peripheral circuit of the semiconductor memory circuit. The peripheral circuit includes a first transistor having a first voltage as a breakdown voltage of a gate oxide film. The semiconductor memory circuit includes a pair of bit lines, one of the pair of bit lines being connected to a gate transistor of a memory cell, and a precharge circuit that includes a transistor having a breakdown voltage substantially equal to that of the first transistor, and precharges the pair of bit lines to a predetermined voltage in response to an activation signal. The activation signal of the precharge circuit is a second voltage higher than the first voltage. | 11-18-2010 |
20100296354 | SRAM AND METHOD FOR ACCESSING SRAM - A static random access memory includes: a memory cell connected with a pair of bit lines and supplied with a power supply voltage from a first power supply; a precharge circuit connected with the pair of bit lines and configured to precharge the pair of bit lines with a precharge voltage; and a voltage reducing circuit connected between the precharge circuit and the first power supply. The voltage reducing circuit includes: a control circuit comprising a differential amplifier circuit which is configured to amplify a difference input of a reference voltage generated through resistance division of the power supply voltage and the precharge voltage supplied to a node to output a control signal; and a voltage reduction control transistor connected between the node and the first power supply and configured to generate the precharge voltage in response to the control signal. The precharge circuit includes: precharge transistors connected between the bit lines and the node and configured to control supply of the precharge voltage to the bit lines in response to a first precharge control signal. | 11-25-2010 |
20100309740 | Low Power, Single-Ended Sensing in a Multi-Port SRAM Using Pre-Discharged Bit Lines - An apparatus and method for low power, single-ended sensing in a multi-port static random access memory (SRAM) using pre-discharged bit lines includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being accessed; releasing the bit line from being held at a zero voltage potential when the memory cell is being accessed; charging the bit line to a first voltage potential greater in value than the zero voltage potential during an access of the memory cell, wherein charging the bit line to a first voltage potential occurs for a first predetermined period of time after access to the memory cell has begun; and sensing the memory cell contents during an access of the memory cell, wherein sensing of the memory cell contents occurs for a second predetermined period of time after access to the memory cell has begun. | 12-09-2010 |
20100309741 | SEMICONDUCTOR DEVICE - The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL. | 12-09-2010 |
20100315893 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device including a CMOS-type local sensing amplifier circuit is provided. The semiconductor memory device includes a first input/output (I/O) line pair, a second I/O line pair pre-charged to a one-half power voltage level and receives data from the first I/O line pair, and a pull-up circuit pulling up a voltage of one of the second I/O pair to a full power voltage level. | 12-16-2010 |
20100315894 | Low Power Sensing In a Multi-Port Sram Using Pre-Discharged Bit Lines - A method for sensing the contents of a memory cell within a static random access memory (SRAM) includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being accessed; energizing the bit line to a first voltage potential different than the zero voltage potential during an access of the memory cell; and sensing the memory cell contents when the associated bit line has reached the first voltage potential. | 12-16-2010 |
20100322026 | MECHANISM FOR MEASURING READ CURRENT VARIABILITY OF SRAM CELLS - A mechanism for measuring the variability of the read current of SRAM cells on an integrated circuit includes the integrated circuit having an SRAM array including a plurality of SRAM cells. The integrated circuit may also include a selection circuit configured to select a particular SRAM cell in response to a selection input. An oscillator circuit such as a ring oscillator, for example, on the integrated circuit may be configured to oscillate at a frequency that is dependent upon a read current of a selected SRAM cell during operation in a first mode. A frequency determining circuit that is coupled to the oscillator circuit may be configured to output a value corresponding to the frequency of oscillation of the oscillator circuit. | 12-23-2010 |
20100329056 | SENSE AMPLIFIER AND SEMICONDUCTOR INTEGRATED CIRCUIT USING THE SAME - A sense amplifier resistant to malfunctions associated with offsets in inverter pairs is presented. The sense amplifier includes inverter pairs and a controller. Any one input terminal of the inverter pairs is electrically connected to a bit line and the other one input terminal is electrically connected to a /bit line. The controller is configured to precharge the bit line and the /bit line to a level corresponding to an offset of the inverter pairs in response to a first control signal. The controller senses a voltage difference of the bit line and the /bit line using the inverter pairs by connecting output terminals of the inverter pairs to the bit line pairs in response to a second control signal. | 12-30-2010 |
20100329057 | Method of discharging bit-lines for a non-volatile semiconductor memory device performing a read-while-write operation - In a method of discharging bit-lines for a non-volatile semiconductor memory device performing a read-while-write operation. The method include discharging a global write bit-line to a ground voltage based on a write command within a first period. the method also includes maintaining the discharged voltage of the global write bit-line in the ground voltage during a second period. | 12-30-2010 |
20100329058 | PROCESSOR INSTRUCTION CACHE WITH DUAL-READ MODES - A processor includes a cache memory. The cache memory includes an array of cells, word lines and bit lines. A control module enables a word line of the word lines to access a first cell in the enabled word line. The control module disables the word line and maintains the word line in a disabled state to access a second cell in the word line. | 12-30-2010 |
20110002183 | CIRCUIT PRECHARGING DRAM BIT LINE - A bit line pre-charge circuit for a dynamic random access memory (DRAM) uses a charge sharing scheme. The pre-charge circuit includes switching elements disposed between a power voltage node and an output node, capacitors connected between intermediate nodes and ground. The switching elements being operated by successively activated control signals to effectively charge a bit line pair to one half a power voltage using charge sharing between the capacitors. | 01-06-2011 |
20110007590 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING WORD LINE POTENTIAL - According to one embodiment, a semiconductor storage device includes a memory cell array, word lines, a driver, and a word-line-potential control circuit. In the memory cell array, memory cells are arranged in a matrix shape in a row direction and a column direction. The word lines perform row selection for the memory cell array during readout of data. The driver drives the word lines. The word-line-potential control circuit controls potential of the word lines such that, during the readout of data, gradient of rising of potential of the word lines to first potential is larger than gradient of further rising of the potential from the first potential to second potential. | 01-13-2011 |
20110019493 | Semiconductor memory device - Provided is a semiconductor memory device including a plurality of memory cells that are connected to a word line and read data, a plurality of bit line pairs that are connected respectively to the plurality of memory cells, a column selector that selects one of the plurality of bit line pairs according to a column selection signal, a sense amplifier circuit that has an input terminal pair connected to the column selector and is activated according to a sense amplifier activation signal, an offset voltage adjustment circuit that is connected to the sense amplifier circuit and adjusts an offset voltage of the sense amplifier circuit according to the weight control signal, and a weight control circuit that is connected to an output terminal pair of the sense amplifier circuit and outputs a weight control signal with a value corresponding to an output of the activated sense amplifier circuit. | 01-27-2011 |
20110026344 | DATA CONTROL CIRCUIT - The data control circuit includes an input/output line and a driver. The input/output line precharging circuit precharges a global input/output line to a predetermined voltage when either a reading operation or a writing operation is inoperative. The driver includes a number of MOS transistors and drives the global input/output line in response to receiving data from a local input/output line and a complementary local input/output line during the reading operation. | 02-03-2011 |
20110026345 | PRECHARGE CONTROL CIRCUITS AND METHODS FOR MEMORY HAVING BUFFERED WRITE COMMANDS - Memories, precharge control circuits, methods of controlling, and methods of utilizing are disclosed, including precharge control circuits for a memory having at least one bank of memory. One such control circuit includes at least one precharge preprocessor circuit. The precharge preprocessor circuit is coupled to a respective bank of memory and is configured to prevent precharge of the respective bank of memory until after execution of buffered write commands issued to the respective bank of memory is completed. | 02-03-2011 |
20110038219 | APPARATUS AND METHOD FOR INCREASING DATA LINE NOISE TOLERANCE - Circuits and methods for improving noise tolerance in memories are disclosed such as those that include biasing a data line above a normal threshold voltage, either by providing a higher data line charge voltage with a voltage source, or by providing a higher data line charge voltage with a current source. | 02-17-2011 |
20110044120 | SEMICONDUCTOR DEVICE - A semiconductor device includes a data transmission line and a data transmission line precharge circuit. The data transmission line precharge circuit sets a precharge potential of the data transmission line to a first potential at the time of a first write mode in which data masking is not performed. The data transmission line precharge circuit sets the precharge potential to a potential different from the first potential at the time of a second write mode in which data masking is performed. When data masking is not carried out, precharging to a potential at which data can be written in excellent fashion can be performed. When data masking is carried out, precharging to a potential that inhibits a fluctuation in bit-line potential can be performed. | 02-24-2011 |
20110051542 | MEMORY CIRCUITS, SYSTEMS, AND METHODS FOR ACCESSING THE MEMORY CIRCUITS - A memory circuit includes at least one memory cell for storing a charge representative of a datum. The memory cell is coupled with a word line and a bit line. A sense amplifier is coupled with the bit line. The sense amplifier is capable of precharging the bit line to a first voltage that is substantially equal to and higher than a threshold voltage (V | 03-03-2011 |
20110069569 | SEMICONDUCTOR MEMORY DEVICE COMPRISING TRANSISTOR HAVING VERTICAL CHANNEL STRUCTURE - A semiconductor memory device including a transistor having a vertical channel structure is provided. The device includes a first sub memory cell array including a first memory cell connected to a first bit lines and including a transistor having a vertical channel structure, a second sub memory cell array including a second memory cell connected to a first inverted bit lines and including a transistor having a vertical channel structure, and a plurality of precharge blocks. In addition, first and second precharge blocks are disposed at first and second sides of the first bit line and precharge the first bit line, and third and fourth precharge blocks are disposed at first and second sides of the first inverted bit line and precharge the first inverted bit line. | 03-24-2011 |
20110080795 | SEMICONDUCTOR MEMORY DEVICE AND DATA READ METHOD THEREOF - A semiconductor memory device includes a first bitline pair equalized to a first voltage level by a first equalizer circuit, a second bitline pair equalized to a second voltage level by a second equalizer circuit, an isolation circuit disposed between the first bitline pair and the second bitline pair, the isolation unit configured to electrically connect or isolate the first bitline pair to or from the second bitline pair, and a sense amplifier electrically connected to the second bitline pair, the sense amplifier configured to sense a voltage difference of the second bitline pair, wherein the isolation circuit isolates one of the connections between the first bitline pair and the second bitline pair while the sense amplifier senses the voltage difference of the second bitline pair. | 04-07-2011 |
20110090752 | Semiconductor memory device - There is provided a semiconductor memory device including: plural memory cells; a selection signal outputting section; a first precharging section that precharges a potential of a data line that outputs, to an exterior, a signal of a level corresponding to data stored in the memory cell; and a bit line selecting section that has, per bit line, a bit line selecting section that comprises (1) a second precharging section, (2) a potential lowering section, and (3) a third precharging section connected to the bit line selection line and the bit line between the second precharging section and a connection point at which the potential lowering section is connected to the bit line, and when the non-selection signal is inputted, the third precharging section precharges the bit line between the second precharging section and the connection point at which the potential lowering section is connected to the bit line. | 04-21-2011 |
20110116334 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a bitline sensing amp detecting and amplifying data of a pair of bitlines from a memory cell, a column selecting unit transmitting the data of the pair of bitlines to a pair of local datalines in response to a column selecting signal, a dataline precharging unit precharging the pair of local datalines to a precharging voltage level in response to a precharging signal, and a dataline sensing amp detecting and amplifying data transmitted to the pair of local datalines. The dataline sensing amp includes a charge sync unit discharging the pair of local datalines at the precharging voltage level in response to a first dataline sensing enabling signal and data of the pair of local datalines, and a data sensing unit transmitting data of the pair of local datalines to a pair of global datalines in response to a second dataline sensing enabling signal. | 05-19-2011 |
20110122719 | PRE-CHARGE VOLTAGE GENERATION AND POWER SAVING MODES - A system includes a voltage generator to produce a pre-charge voltage signal for pre-charging one or more signals in a memory circuit. The one or more signals can be data bus lines used to access memory. The voltage generator can include an input indicating whether the memory circuit is set to a power-saving mode. According to one embodiment, the input adjusts a magnitude of the pre-charge voltage signal produced by the voltage generator. Such an embodiment is useful over conventional methods because adjusting the pre-charge voltage can result in power savings. As an example, when in the power-saving mode, the voltage generator circuit can adjust the pre-charge voltage to a value that reduces an amount of leakage current associated with a pre-charge voltage. Reducing the leakage with respect to the pre-charge voltage means that the saved power can be used for other useful purposes. | 05-26-2011 |
20110128807 | MEMORY DEVICE AND SENSE CIRCUITRY THEREFOR - A memory device includes a memory array, sense circuitry coupled to the memory array, and timing circuitry coupled to the sense circuitry. The timing circuitry generates a sense trigger signal to enable the sense circuitry. A strap region is formed adjacent the memory array. A reference word line is coupled to the timing circuitry. The reference word line formed in the strap region. | 06-02-2011 |
20110149666 | BITLINE FLOATING DURING NON-ACCESS MODE FOR MEMORY ARRAYS - Techniques are disclosed that allow for power conservation in integrated circuit memories, such as SRAM. The techniques can be embodied in circuitry that allows for floating of bitlines to eliminate or otherwise reduce power leakage associated with precharging bitlines. For instance, the techniques can be embodied in a bitline floating circuit having a single logic gate for qualifying the precharge control signal with a wake signal, so that precharging of the bitline does not occur if the wake signal is not in an active state. The techniques further allow for the elimination or reduction of unnecessary power consumption by the I/O circuitry or the memory array, such as when the memory array is not being accessed or when the array or a portion thereof is permanently disabled for yield recovery. | 06-23-2011 |
20110149667 | REDUCED AREA MEMORY ARRAY BY USING SENSE AMPLIFIER AS WRITE DRIVER - Techniques are disclosed for reducing area needed for implementing a memory array, such as SRAM arrays. The techniques may be embodied, for example, in a memory array design that includes a sense amplifier configured to operate in a reading mode for readout of memory cells and a writing mode for writing to memory cells. In addition, a common column multiplexer can be used for both read and write functions (as opposed to having separate multiplexers for reading and writing). | 06-23-2011 |
20110149668 | MEMORY DEVICE AND METHOD OF OPERATION THEREOF - Memory devices and methods of operating a memory cell are disclosed in which a bitline can be grounded after charge sharing with an electrically floating ground line and before writing data to the memory cell. An electric potential of an upper power supply node of a memory cell can be lowered and an electric potential of a lower power supply node of the memory cell can be raised before writing data to the memory cell. | 06-23-2011 |
20110158019 | SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF - A semiconductor memory device that can minimize the area of a circuit for generating a BLEQ signal by using one power source voltage terminal floated for the generation of a BLEQ signal. The semiconductor memory device includes a power source supplier configured to supply a power source of a main power source voltage terminal to a sub-power source voltage terminal in response to a mat selection signal for selecting a corresponding memory cell mat among a plurality of memory cell mats, a bit line equalization (BLEQ) signal generator configured to be coupled with the sub-power source voltage terminal and generate a BLEQ signal corresponding to a voltage level of the sub-power source voltage terminal in response to a BLEQ control signal, and a bit line equalizer configured to precharge and equalize a bit line pair in response to the BLEQ signal. | 06-30-2011 |
20110158020 | CIRCUIT AND METHOD FOR CONTROLLING PRECHARGE IN SEMICONDUCTOR MEMORY APPARATUS - A circuit for controlling precharge in a semiconductor memory apparatus includes a read clock driver configured to drive an internal clock signal and generate a read burst clock signal; a read precharge control unit configured to generate a read auto precharge signal in response to the read burst clock signal, a burst end signal, and a read write mode signal; a write clock driver configured to drive the internal clock signal and generate a write burst clock signal in response to the read write mode signal and a data input off signal; a write precharge control unit configured to generate a write auto precharge signal in response to the write burst clock signal, the burst end signal, a write latency signal, and a write address combination signal; and a precharge signal generation unit configured to combine the read and write auto precharge signals and generate an auto precharge signal. | 06-30-2011 |
20110158021 | Reducing peak currents required for precharging data lines in memory devices - A semiconductor memory storage device is disclosed. The semiconductor memory storage devices comprises: a plurality of data storage cells arranged in an array. The array comprises a plurality of columns and a plurality of rows, each column comprising at least one output line for outputting a data value from a data storage cell in a selected row of the column. Precharge circuitry for precharging the output lines to a predetermined voltage, the precharge circuitry comprising a plurality of switching devices corresponding to the plurality of columns each switching device controlled by a data output request signal and a power mode signal. The plurality of switching devices each comprising at least two switches, the at least two switches comprising a data output switch controlled by the data output request signal and a power switch controlled by the power mode signal, the plurality of switching devices connecting the output lines to the predetermined voltage in response to both the power mode signal indicating an operational mode and the data output request signal indicating data is to be output; wherein the power mode switch is configured to have a higher capacitance than the data output switch. | 06-30-2011 |
20110176378 | Memory Program Discharge Circuit - A memory integrated circuit has an array of nonvolatile memory cells, bit lines accessing the array of nonvolatile memory cells, and bit line discharge circuitry. The bit lines have multiple discharge paths for a bit line at a same time, during a program operation. | 07-21-2011 |
20110194368 | Regulator and semiconductor device - A regulator including a differential amplifier including a differential input stage that differentially receives a reference voltage and an output terminal voltage of the regulator, a drive transistor that has an output connected to an output terminal of the regulator and that has a control terminal connected to an output of the differential amplifier, a first transistor connected between the control terminal of the drive transistor and a first power supply terminal and a second transistor connected between the control terminal of the drive transistor and a second power supply terminal, wherein a control terminal of the first transistor and a control terminal of the second transistor are connected to a first control signal and a second control signal, respectively, the first transistor being on-off controlled by the first control signal and the second transistor being on-off controlled by the second control signal. | 08-11-2011 |
20110199846 | Y-DECODE CONTROLLED DUAL RAIL MEMORY - An embodiment of the invention is related to a memory that includes a memory array having a plurality of memory banks, each of which includes a plurality of rows and a plurality of columns of memory cells. Each memory column includes a switch circuit providing a first voltage and a second voltage to memory cells in the column and to the pre-charge circuit associated with the column. In an application, at one particular point in time (e.g., an accessed cycle), only one column in a memory bank uses the operating voltage Ovoltage while the other N−1 columns in the same memory bank use the retention voltage Rvoltage. Other embodiments are also disclosed. | 08-18-2011 |
20110211407 | SEMICONDUCTOR MEMORY DEVICE AND ASSOCIATED LOCAL SENSE AMPLIFIER - A semiconductor memory device comprises a plurality of memory cells, a bit line sense amplifier, a local sense amplifier, and a sense amplifier. The memory cells are connected between a word line and a bit line pair, and the bit line sense amplifier is configured to amplify voltages of data from the bit line pair and then transmits the data to a local data line pair. The local sense amplifier is configured to amplify voltages of the data from the local data line pair and transmit the data to a global data line pair in response to first and second control signals, and the sense amplifier is configured to amplify the voltages of the data from the global data line pair and transmit the data to an input/output line pair during a read operation. The local sense amplifier comprises a first read circuit, a second read circuit, and a write circuit, and when the memory device performs the read operation, the data is transmitted from the first read circuit to the write circuit via the second read circuit. | 09-01-2011 |
20110211408 | SEMICONDUCTOR STORAGE DEVICE - A voltage of a bit line connected to a memory cell is stepped up to a power supply voltage by a precharge circuit. Before data is read from the memory cell, the voltage of the bit line is stepped down to a voltage level lower than the power supply voltage by a step-down circuit. A precharge switching element controls a connection between a high-potential-side power supply and the precharge circuit and a connection between a low-potential-side power supply and the precharge circuit. A power supply connecting circuit is provided between the precharge switching element and the high-potential-side power supply. A ground connecting circuit is provided between a connecting point at which the precharge switching element is connected to the power supply connecting circuit and the low-potential-side power supply. | 09-01-2011 |
20110216615 | SEMICONDUCTOR MEMORY DEVICE HIGHLY INTEGRATED IN DIRECTION OF COLUMNS - First and second read word lines are provided in each set made of two adjacent rows. First, second, third, and fourth read bit lines are provided in each column. Each of the first and second read word lines is connected to memory cells in a corresponding one of the sets. Each of the first and third read bit lines is connected to a memory cell in one row in each of the sets, out of memory cells in a corresponding one of the columns. Each of the second and fourth read bit lines is connected to a memory cell in the other row in each of the sets, out of the memory cells in the corresponding one of the columns. | 09-08-2011 |
20110235448 | USING DIFFERENTIAL SIGNALS TO READ DATA ON A SINGLE-END PORT - In some embodiments related to reading data in a memory cell, the data is driven to a local bit line, which drives a local sense amplifier. Depending on the logic level of the data in the memory cell and thus the local bit line, the local sense amplifier transfers the data on the local bit line to a global bit line. A neighbor global bit line is used as a reference for a global sense amplifier to read the differential data on the global bit line and the neighbor global bit line. | 09-29-2011 |
20110249523 | SEMICONDUCTOR MEMORY DEVICE WITH A SENSE AMPLIFIER CONTROLLER FOR MAINTAINING THE CONNECTION OF A PREVIOUSLY SELECTED MEMORY CELL ARRAY - A semiconductor memory device includes a bit line sense amplifier block array, upper and lower memory cell arrays and a sense amplifier controller. The bit line sense amplifier block array senses and amplifies data of a memory cell array. The upper and the lower memory cell arrays are respectively connected to upper and lower sides of the bit line sense amplifier block array and store the data in the memory cell array. The sense amplifier controller selectively connects one of the upper and lower memory cell arrays to the bit line sense amplifier block array in response to an active command, and releases the connection when a corresponding one of the upper and lower memory cell arrays are not selected but overdriven. | 10-13-2011 |
20110255358 | Semiconductor device having floating body type transistor - A semiconductor device comprises a floating body type transistor and first and second circuits. The transistor has a floating body and a source-drain path inserted between first and second circuit nodes. The first circuit supplies a first signal to the gate of the transistor, and the first signal changes between a first logic level that holds the transistor in a non-conductive state and a second logic level that directs the transistor into a conductive state. The second circuit supplies a first voltage level near the second logic level to the first circuit node and supplies a second voltage level near the second logic level to the second circuit node, each as a level in a state where the transistor is not utilized. Thereby the gate capacitance of the transistor can be kept small as viewed from the gate, and high-speed operation and a reduction in consumption current can be achieved. | 10-20-2011 |
20110267913 | PROGRAM METHOD OF SEMICONDUCTOR MEMORY DEVICE - A program method of a semiconductor memory device may include precharging first bit lines, coupled to first strings, to increase a potential level of the first strings to a first potential level; programming memory cells of a selected word line, wherein the memory cells are coupled to second bit lines; pre-discharging the first bit lines to decrease a potential level of the word lines to a second potential level, wherein the second potential level is lower than the first potential level; and discharging the first bit lines and the word lines to a ground voltage after the pre-discharging. | 11-03-2011 |
20110286292 | METHOD OF FORMING A UNIQUE NUMBER - A unique number is formed with logic states from a static random access memory (SRAM), which is laid out to be balanced so that memory cells within the SRAM assume a non-random logic state when power is applied to the SRAM. The unique number is formed by grounding the word lines and bit lines before power is applied to the memory cells, applying power to the memory cells to assume the non-random logic state, reading the non-random logic states held by the memory cells, and forming the unique number from the logic states read from the memory cells. | 11-24-2011 |
20110292748 | IMPLEMENTING LOW POWER DATA PREDICTING LOCAL EVALUATION FOR DOUBLE PUMPED ARRAYS - A method and static random access memory (SRAM) circuit for implementing low power data predicting local evaluation for double pumped arrays, and a design structure on which the subject circuit reside are provided. A novel variation of a domino read local evaluation circuit accurately predicts the write data for the next cycle. The domino read local evaluation circuit uses static write data set up prior to a write enable signal to determine the value of the data that is being written into the array. When the data being written to the array matches the data last read the local bitlines stay in their previous state. When the data being written is opposite of the data last read then the bit lines are precharged to the precharge value. | 12-01-2011 |
20110292749 | NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes a plurality of mats, each of which includes a unit cell in an intersection area between each of a plurality of word lines and each of a plurality of bit lines such that a read or write operation of data is achieved in each mat, a column switching unit configured to select any one of bit lines from among the plurality of bit lines according to a column selection signal, and selectively control a connection between the selected bit line and a global bit line, and a discharge unit, in an active mode in which the read or write operation is achieved, configured to discharge the remaining bit lines other than the selected bit line from among the plurality of bit lines in response to a bit line discharge signal. | 12-01-2011 |
20110299350 | PRECHARGE CONTROL CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME - A precharge control circuit includes a precharge voltage supply unit for generating a precharge voltage according to a voltage level of a precharge control signal, a voltage generator for generating an operating voltage for controlling the voltage level of the precharge control signal in response to a first enable signal and a voltage control signal, and a signal generator for fixing the precharge control signal to a specific voltage level in response to a second enable signal and for linearly changing the voltage level of the precharge control signal according to a slope, determined by a level of the operating voltage, when the second enable signal is disabled. | 12-08-2011 |
20110305098 | SEMICONDUCTOR MEMORY DEVICE WITH SENSE AMPLIFIER AND BITLINE ISOLATION - A semiconductor memory device, including: a memory cell connected to a first bitline and associated with a second bitline; a sense amplifier, including a first input/output node and a second input/output node; and an isolator connected to the bitlines and to the input/output nodes, the isolator being configured to carry out bitline isolation during a refresh operation of the memory cell, where the bitline isolation includes electrically disconnecting the first bitline from the first input/output node and electrically disconnecting the second bitline from the second input/output node, followed by: electrically re-connecting the first bitline to the first input/output node while the second bitline remains electrically disconnected from the second input/output node. | 12-15-2011 |
20110305099 | HIERARCHICAL BUFFERED SEGMENTED BIT-LINES BASED SRAM - A semiconductor memory device is disclosed. In one aspect, the device includes memory blocks with memory cells connected to a local bit-line, each local bit-line being connectable to a global bit-line for memory readout. There are also pre-charging circuitry for pre-charging the bit-lines and a read buffer for discharging the global bit-line during a read operation. The local bit-lines are pre-charged to a predetermined first voltage substantially lower than the supply voltage (VDD) of the memory device. A segment buffer is provided between each local bit-line and an input node of the respective read buffer. The segment buffer activates the read buffer during the read operation upon occurrence of a discharge on the connected local bit-line. | 12-15-2011 |
20110317505 | INTERNAL BYPASSING OF MEMORY ARRAY DEVICES - An output control circuit for a memory array includes a latched output node precharged to a first logic state prior to both a read and write operation; first logic that couples memory cell data from a memory read path to the output node during the read operation, the first logic controlled by a timing signal; second logic that internally bypasses the memory read path during a write operation by decoupling it from the output node, such that a logical derivative of write data written to the memory array is also coupled to the output node, the second logic also controlled by the timing signal; and wherein a transition of the output node from the first logic state to a second logic state during the write operation occurs within a time range as that of the same transition during the read operation. | 12-29-2011 |
20110317506 | Method for Asymmetric Sense Amplifier - Methods for determining the state of memory cells include using an asymmetric sense amplifier. The methods include sensing the voltages on bit line (BL) and bit line bar (BLB) signals by coupling the BL to a first output node of an imbalanced cross-coupled latch (ICL), the ICL outputting a logic low value if the a difference between the a voltage on the BL and a voltage on the BLB exceeds a threshold. Sensing the voltages includes providing at least a first and a second pull down field effect transistor (FET) each having a channel coupled between the first and second output nodes and a ground node, respectively, in a cross coupled arrangement, wherein the second pull down FET has a channel width that is greater than a channel width of the first pull down FET. Additional methods are disclosed. | 12-29-2011 |
20120002496 | Circuit and method for eliminating bit line leakage current in random access memory devices - A method for eliminating bit line leakage current of a memory cell in random access memory devices comprises the steps of: periodically activating a pre-charge equalization circuit, which provides a pre-charge voltage to a pair of complementary bit lines of a memory cell, if the memory cell is in a self-refresh mode or a standby mode; and temporarily activating the pre-charge equalization circuit after the memory cell is refreshed if the memory cell is in the self-refresh mode or the standby mode. | 01-05-2012 |
20120002497 | Circuit and method for controlling standby leakage current in random access memory devices - A method for controlling standby current coming from bit line leakage in random access memory devices comprises the steps of: continuously deactivating a pre-charge equalization circuit providing a pre-charge voltage to a pair of complementary bit lines of a memory cell if the memory cell is in a self-refresh mode, a standby mode or an active mode; temporarily activating the pre-charge equalization circuit before the memory cell is refreshed if the memory cell is in a self-refresh mode or a standby mode; and temporarily activating the pre-charge equalization circuit before the memory cell is refreshed or accessed if the memory cell is in an active mode. | 01-05-2012 |
20120008443 | IMPLEMENTING SMART SWITCHED DECOUPLING CAPACITORS TO EFFICIENTLY REDUCE POWER SUPPLY NOISE - A method and circuit are provided for implementing smart switched decoupling capacitors to efficiently reduce power supply noise in a logic circuit, and a design structure on which the subject circuit resides. The logic circuit includes a logic macro, a high-current event control signal activating a logic function, and a switched decoupling capacitor circuit integrated within the logic macro. The switched decoupling capacitor circuit uses the high-current event control signal to control capacitor switching to discharge to a voltage supply rail responsive to activating the logic function, and to charge the capacitors. | 01-12-2012 |
20120008444 | DUAL BIT LINE PRECHARGE ARCHITECTURE AND METHOD FOR LOW POWER DYNAMIC RANDOM ACCESS MEMORY (DRAM) INTEGRATED CIRCUIT DEVICES AND DEVICES INCORPORATING EMBEDDED DRAM - A dual bit line precharge architecture and method for low power DRAM which provides the low operating voltage of a non-half supply voltage (VCC/2) precharge with the low memory array current consumption and low memory array noise spike of VCC/2 precharge techniques. The architecture and technique of the present invention provides both reference voltage (VSS) precharged sub arrays and VCC precharged sub arrays on the same DRAM memory either with or without the novel charge sharing or charge recycling circuitry between these two different sub arrays as disclosed herein. | 01-12-2012 |
20120008445 | DUAL BIT LINE PRECHARGE ARCHITECTURE AND METHOD FOR LOW POWER DYNAMIC RANDOM ACCESS MEMORY (DRAM) INTEGRATED CIRCUIT DEVICES AND DEVICES INCORPORATING EMBEDDED DRAM - A dual bit line precharge architecture and method for low power DRAM which provides the low operating voltage of a non-half supply voltage (VCC/2) precharge with the low memory array current consumption and low memory array noise spike of VCC/2 precharge techniques. The architecture and technique of the present invention provides both reference voltage (VSS) precharged sub arrays and VCC precharged sub arrays on the same DRAM memory either with or without the novel charge sharing or charge recycling circuitry between these two different sub arrays as disclosed herein. | 01-12-2012 |
20120008446 | PRECHARGING CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A semiconductor memory device includes a write driver for transmitting data loaded on a global line to a local line pair, a read driver for transmitting data loaded on the local line pair to the global line, a core region for storing data loaded on the local line pair or provide stored data to the local line pair, and a precharging circuit configured to precharge the local line pair by selectively using a first voltage and a second voltage in response to a precharge control signal and an operation mode signal, wherein the second voltage is lower than the first voltage. | 01-12-2012 |
20120033517 | ADAPTIVE WRITE BIT LINE AND WORD LINE ADJUSTING MECHANISM FOR MEMORY - A memory includes a capacitor coupled to a write bit line or a word line. An initializer is configured to initialize a voltage level at a first node between the capacitor and the write bit line or a word line. An initial level adjuster is configured to adjust a voltage level of a second node at one terminal of the capacitor. A pulse generator configured to supply a pulse to the initial level adjuster to control the initial level adjuster. A boost signal is configured to be supplied to a third node on the other terminal of the capacitor opposite the first node to boost a voltage level of the write bit line lower than ground or to boost a voltage level of the word line higher than a power supply voltage. | 02-09-2012 |
20120039141 | VOLTAGE CONTROL METHOD AND MEMORY DEVICE USING THE SAME - A memory device is provided, which includes a plurality of global bit lines, a discharge line, a switching circuit configured to connect the plurality of global bit lines to the discharge line in response to a discharge enable signal, a first discharge circuit configured to apply a first voltage that is higher than a ground voltage to the discharge line, a precharge circuit configured to apply a precharge voltage to a selected global bit line among the plurality of global bit lines, and a second discharge circuit configured to discharge the selected global bit line to a second voltage that is higher than the ground voltage. | 02-16-2012 |
20120039142 | SCALEABLE LOOK-UP TABLE BASED MEMORY - An integrated circuit having a logic element that includes an array of storage elements convertibly functioning as either a configuration random access memory (CRAM) or a static random access memory (SRAM) is provided. The logic element includes first and second pairs of data paths having dedicated multiplexers. In one embodiment, the first and second pairs of data paths are multiplexed into bit lines of a row of the array. The logic element also includes a data path control block generating control signals for each of the dedicated multiplexers. The control signals determine whether the storage elements function as a CRAM or a SRAM. A method for selectively configuring a memory array between a CRAM mode and SRAM mode are provided. | 02-16-2012 |
20120057421 | DEVICES AND SYSTEM PROVIDING REDUCED QUANTITY OF INTERCONNECTIONS - Methods, devices and systems for reducing the quantity of external interconnections of a memory device are disclosed. Implementation of one such method, device and system includes inputting over an address bus a first portion of an address of a next row of memory cells to be activated. The first portion of the address of the next row of memory cells to be activated is embedded in a command related to the previously activated row of memory cells. The next row of memory cells is subsequently activated according to a concurrently received second portion of the address of the next row of memory cells also received over the address bus. The portioning of the address signals can reduce the width of the address bus and, therefore, the number of required respective external interconnections. | 03-08-2012 |
20120063249 | MEMORY AND METHOD FOR SENSING DATA IN A MEMORY USING COMPLEMENTARY SENSING SCHEME - In a memory ( | 03-15-2012 |
20120063250 | NON-VOLATILE MEMORY DEVICE AND CHARGE PUMP CIRCUIT FOR THE SAME - A charge pump apparatus comprises a plurality of charge pump stages. The charge pump stages each include a respective output node. Output nodes are connected to charge boosting circuitry and to precharge circuitry. The charge boosting circuit receives one or more clock signals. The precharge circuits have a first state allowing the respective pump-stage output node to fluctuate at a level above a standby wordline voltage, and a second state coupling the respective pump-stage output node to the standby wordline voltage. | 03-15-2012 |
20120075945 | Passgate for Dynamic Circuitry - A dynamic circuit utilizing a passgate on a bit line is disclosed. In one embodiment, a precharge circuit is coupled to a first bit line, while a discharge circuit is coupled to a second bit line. A passgate transistor is coupled between the first bit line and the second bit line. A gate terminal of the passgate transistor may be hardwired or otherwise held to a static voltage such that it remains active when the circuit is operating. During a precharge phase, the precharge circuit may precharge the first bit line to a voltage that is at or near a supply voltage of the circuit. The second bit line may be precharged, through the passgate transistor, responsive to the precharging of the first bit line. The second bit line may be precharged to a voltage that is at least a threshold voltage less than the supply voltage. | 03-29-2012 |
20120075946 | Memory Device with Phase Distribution Circuit for Controlling Relative Durations of Precharge and Active Phases - A memory device comprises a memory array and a phase distribution circuit coupled to the memory array. In one aspect, the phase distribution circuit is operative to control respective durations of a precharge phase and an active phase of a memory cycle of the memory array based on relative transistor characteristics of a tracked precharge transistor of a first conductivity type and a tracked memory cell transistor of a second conductivity type different than the first conductivity type. For example, the phase distribution circuit may comprise a first tracking transistor of the first conductivity type for tracking the precharge transistor of the first conductivity type and a second tracking transistor of the second conductivity type for tracking the memory cell transistor of the second conductivity type. The relative transistor characteristics may comprise relative strengths of the tracked precharge and memory cell transistors. | 03-29-2012 |
20120081984 | THREE-DIMENSIONAL STACKED SEMICONDUCTOR INTEGRATED CIRCUIT - Various embodiments of a three-dimensional, stacked semiconductor integrated circuit are disclosed. In one exemplary embodiment, the circuit may include a master slice, a plurality of slave slices, and a plurality of through-silicon vias for connecting the master slice to the plurality of slave slices. At least one of the plurality of through-silicon vias may be configured to transmit an operation control signal from the master slice to the plurality of slave slices. The at least one of the plurality of through-silicon vias is configured to be shared by the plurality of slave slices. | 04-05-2012 |
20120092946 | MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING DISCHARGE LINES AND METHODS OF FORMING - A non-volatile memory device can include a word line that is operatively coupled to a non-volatile memory cell. A local bit line can be operatively coupled to the non-volatile memory cell. A discharge line that is associated with the local bit line can be configured to discharge the local bit line and a discharge diode can be electrically coupled between the local bit line and the discharge line. | 04-19-2012 |
20120099390 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first page buffer group including a plurality of page buffers coupled to memory cells of a first memory array through bit lines, a second page buffer group, a coupling circuit configured to couple an output terminal and an inverse output terminal of a selected page buffer of the first page buffer group to a first local I/O line and a first inverse local I/O line, respectively, or an output terminal and an inverse output terminal of a selected page buffer of the second page buffer group to a second local I/O line and a second inverse local I/O line, respectively, in response to a column select signal, and a sense amplifier configured to detect a voltage difference between the first local I/O line and the first inverse local I/O line or between the second local I/O line and the second inverse local I/O line. | 04-26-2012 |
20120099391 | METHOD OF READING DATA IN A NON-VOLATILE MEMORY DEVICE - A method of reading data in a non-volatile memory device compensates for a change in a reading/verifying result in accordance with a change of temperature. The method includes sensing a temperature of a memory cell, setting a first voltage and a second voltage of a bit line sensing signal in accordance with the sensed temperature so that a difference of the first voltage and the second voltage is increased as the temperature increases, precharging a bit line in accordance with the set first voltage, and sensing data of the memory cell in accordance with the set second voltage. The method may read/verify data constantly even though a temperature is changed. | 04-26-2012 |
20120106280 | SELF-ADAPTIVE SENSING DESIGN - A clock signal having a clock pulse width duration is received. A delay time is received. A first relationship and a second relationship between the clock pulse width duration and the delay time are determined. A new clock is generated that has a first new clock pulse width duration determined by the first relationship and the delay time and a second new clock pulse width duration determined by the second relationship and the clock pulse width duration. Switching between the first new clock pulse width duration and the second new clock pulse width duration is automatic based on the first relationship and the second relationship. | 05-03-2012 |
20120106281 | SEMICONDUCTOR MEMORY DEVICES AND SEMICONDUCTOR MEMORY SYSTEMS - A semiconductor memory device includes at least one memory cell block and at least one connection unit. The at least one memory cell block has a first region including at least one first memory cell connected to a first bit line, and a second region including at least one second memory cell connected to a second bit line. The at least one connection unit is configured to selectively connect the first bit line to a corresponding bit line sense amplifier based on a first control signal, and configured to selectively connect the second bit line to the corresponding bit line sense amplifier via a corresponding global bit line based on a second control signal. | 05-03-2012 |
20120113735 | Semiconductor device having current change memory cell - A semiconductor device comprises a first transistor connected between a bit line and a sense node, and a second transistor amplifying a signal of the sense node. A first potential applied to a gate of the first transistor, a second potential supplied to the sense node, and a third potential supplied to the bit line are controlled so that the first potential applied to a gate of the first transistor is between the second and third potentials, the second potential is set larger than the third potential, and a predetermined potential obtained by subtracting a threshold voltage of the first transistor from the first potential is smaller than the third potential and higher than a low potential supplied to the second transistor. A potential of the bit line transitions from the third potential toward the low potential in accordance with data of a current change memory cell. | 05-10-2012 |
20120113736 | Semiconductor device having hierachical bit line structure - A semiconductor device of the invention comprise a memory cell array configured with hierarchical local bit lines and global bit lines, in which there are provide local bit lines, global bit lines, switches controlling a connection between the global bit lines, sense amplifiers, and a control circuit controlling the switches. In a first period, each sense amplifier amplifies a signal of one of adjacent global bit lines, and in a second period, each sense amplifier amplifies a signal of the other thereof. Accordingly, coupling between the global bit lines can be suppressed. | 05-10-2012 |
20120120750 | SEMICONDUCTOR DEVICE HAVING ELECTRICAL FUSE AND CONTROL METHOD THEREOF - To provide an electrical fuse that is connected to a detection node via a selective transistor, a precharge transistor that precharges the detection node in a state where the selective transistor is off; a bias transistor that passes a bias current to the detection node in a state where the selective transistor is on and the precharge transistor is off, and a detection circuit that detects a potential of the detection node in a state where the bias current is flowing into the detection node, wherein the bias transistor reduces an amount of the bias current in a stepwise manner or a continuous manner. | 05-17-2012 |
20120127815 | SENSE AMPLIFIER AND METHOD OF SENSING DATA USING THE SAME - Some embodiments regard a circuit comprising a pre-charge circuit and a latch circuit. The pre-charge circuit charges a voltage node to a pre-determined voltage level based on which the latch circuit generates a feedback signal to stop the pre-charge circuit from charging. | 05-24-2012 |
20120147686 | SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE AND CONTROL METHOD THEREOF - Disclosed herein is a semiconductor device comprising a global bit line and a local bit line, and a switch coupled therebetween. Upon performing a precharge operation, a precharge voltage is supplied to the global bit line with turning the switch ON, so that the local bit line receives the precharge voltage through the global bit line and the switch, and after a lapse of a predetermined time, a precharge voltage is further supplied to the local bit line without an intervention of the global bit line and the switch. | 06-14-2012 |
20120155204 | SEMICONDUCTOR MEMORY APPARATUS HAVING A PRE-DISCHARGING FUNCTION, SEMICONDUCTOR INTEGRATED CIRCUIT HAVING THE SAME, AND METHOD FOR DRIVING THE SAME - A semiconductor memory apparatus includes a bit line coupled to a plurality of memory cells, a discharge controller configured to generate a bit line discharge signal to pre-discharge the bit line before the memory cells are activated, and a bit line discharge block coupled to the bit line and configured to discharge the bit line in response to the bit line discharge signal. | 06-21-2012 |
20120163109 | MEMORY CIRCUIT AND A TRACKING CIRCUIT THEREOF - Memory circuit and a tracking circuit thereof. The tracking circuit includes a dummy bit line (DBL). The tracking circuit further includes a first circuit to discharge the dummy bit line in response to a first signal and a wordline activation signal. The wordline activation signal causes activation of a memory cell. The tracking circuit also includes a second circuit which is responsive to discharge of the dummy bit line to enable access to the memory cell. | 06-28-2012 |
20120163110 | MEMORY DEVICE WITH ROBUST WRITE ASSIST - A memory circuit includes a memory cell configured to be re-writable. A write enable circuit is configured to enable writing a signal via a pair of bit lines to the memory cell depending on a write signal. A charge supply circuit is configured to supply a charge to at least one of the pair of bit lines. A charge supply controller is configured to control the charge supply circuit to disable the supply of charge and couple the write enable circuit to at least one of the pair of bit lines after a first determined period following the reception of the write signal. | 06-28-2012 |
20120182818 | LOW POWER AND HIGH SPEED SENSE AMPLIFIER - A sense amplifier circuit includes a precharge circuit configured to precharge a bit line coupled to a sensing node in response to a precharge control signal and a sense output circuit. The sense output circuit includes a sense output inverter coupled to the sensing node. The sense output inverter is disabled during bit line precharging and for a period after bit line precharging is complete, and thereafter the sense output inverter is enabled. | 07-19-2012 |
20120188836 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a bit line sense amplifier unit and a driving voltage supply unit. The bit line sense amplifier unit senses and amplifies a signal provided from a memory cell using a pull-up driving voltage provided through a pull-up power line and a pull-down driving voltage provided through a pull-down power line. The driving voltage supply unit supplies the pull-down driving voltage having a first pull-down driving force during a first amplification period, and supplies the pull-down driving voltage having a second pull-down driving force greater than the first pull-down driving force during a second amplification period after the first amplification period. | 07-26-2012 |
20120188837 | METHOD OF READING MEMORY CELL - A method for reading a memory cell ( | 07-26-2012 |
20120195146 | LOCAL SENSE AMPLIFIER CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A local sense amplifier circuit in a semiconductor memory device, the local sense amplifier circuit including a local data sensing unit configured to amplify a voltage difference between a local input/output (I/O) line pair based on a local sensing enable signal to provide the amplified voltage difference to a global I/O line pair, the local I/O line pair including a first local I/O line and a second local I/O line, and a local I/O line control unit including a first capacitor and a second capacitor, the first capacitor increasing a voltage level of the first local I/O line based on the local sensing enable signal, the second capacitor increasing a voltage level of the second local I/O line based on the local sensing enable signal. | 08-02-2012 |
20120195147 | BIT LINE PRECHARGE CIRCUIT AND A SEMICONDUCTOR MEMORY APPARATUS USING THE SAME - A bit line precharge circuit includes a precharge signal generation unit configured to generate first and second precharge signals that are enabled at different timing points by receiving a bit line equalizing signal; a first precharge unit configured to connect a pair of bit lines to each other in response to the first precharge signal and supply a bit line precharge voltage to the pair of bit lines; and a second precharge unit configured to supply the bit line precharge voltage to the bit line in response to the second precharge signal. | 08-02-2012 |
20120206986 | AMPLIFIER SENSING - A circuit comprises a first read bit line, a second read bit line, and a sense amplifier. First and second read bit lines couple a plurality of memory cells and a reference cell of a memory array, respectively. The sense amplifier is configured to receive the first read bit line as a first input and the second read bit line as a second input. When a memory cell of the first plurality of memory cells is read, the memory cell is read activated, the first reference cell is configured to be off, the second reference cell is configured to be on, and the sense amplifier is configured to provide an output reflecting a data logic stored in the memory cell based on a voltage difference between a first voltage of the first read bit line and a second voltage of the second read bit line. | 08-16-2012 |
20120206987 | MEMORY DEVICE AND RELATED OPERATING METHODS - A memory device is provided that includes a memory cell, a voltage input, a plurality of bit lines, an amplifier connected to only a particular one of the bit lines, and a switch that is coupled to the amplifier and the voltage input. The switch is configured to prevent the voltage input from being electrically coupled to the amplifier when the plurality of bit lines are electrically floating. | 08-16-2012 |
20120206988 | NEGATIVE VOLTAGE GENERATOR AND SEMICONDUCTOR MEMORY DEVICE - A negative voltage generator includes a variable-capacitance negative voltage generating unit, a switching unit and a positive voltage applying unit. The negative voltage generating unit includes a plurality of coupling capacitors for varying the capacitance in which the negative voltage is charged. The negative voltage generating unit selects at least one coupling capacitor of the plurality of coupling capacitors according to the number of rows (size) of a memory bank to which data is written, and charges the at least one selected coupling capacitor to a negative voltage. The switching unit selects one bitline of a bitline pair having complementary first and second bitlines in response to the data, and connects the at least one selected coupling capacitor to the selected bitline. The positive voltage applying unit applies a positive (high) voltage to an other bitline of the bitline pair. | 08-16-2012 |
20120213023 | SYSTEMS AND METHODS FOR MEMORY DEVICE PRECHARGING - Systems and methods for determining optimal memory device precharge voltages are provided herein. In addition, systems and methods for providing localized sense amplification and circuit assist circuitry are described herein. Embodiments provide for determining precharge multipliers that may be used to determine the optimal precharge voltage based on a precharge source voltage. According to embodiments, the precharge source voltage may be Vdd or Vcs. Optimizing the precharge voltage maximizes memory device performance and functional characteristics, including, but not limited to, stability, efficiency, power, writability, and reliability. | 08-23-2012 |
20120213024 | MEMORY DEVICE WITH DATA PREDICTION BASED ACCESS TIME ACCELERATION - A memory device includes a memory array comprising a plurality of memory cells, sensing circuitry coupled to at least a given bitline associated with a particular column of the memory cells of the memory array, and access time acceleration circuitry coupled to the bitline. The access time acceleration circuitry is configured to control an amount of time required by the sensing circuitry to access data stored in a given one of the memory cells in the particular column of memory cells, by providing in a current access cycle at least a selected one of a plurality of different supplemental charging and discharging paths for the bitline based at least in part on data accessed using the bitline in a previous access cycle. By way of example, the different supplemental charging and discharging paths may comprise an additional pull-up path configured to supplement operation of a pull-up path of the given memory cell and an additional pull-down path configured to supplement operation of a pull-down path of the given memory cell. | 08-23-2012 |
20120230138 | MEMORY ELEMENT AND SIGNAL PROCESSING CIRCUIT - A memory element having a novel structure and a signal processing circuit including the memory element are provided. A first circuit, including a first transistor and a second transistor, and a second circuit, including a third transistor and a fourth transistor, are included. A first signal potential and a second signal potential, each corresponding to an input signal, are respectively input to a gate of the second transistor via the first transistor in an on state and to a gate of the fourth transistor via the third transistor in an on state. After that, the first transistor and the third transistor are turned off. The input signal is read out using both the states of the second transistor and the fourth transistor. A transistor including an oxide semiconductor in which a channel is formed can be used for the first transistor and the third transistor. | 09-13-2012 |
20120230139 | SEMICONDUCTOR MEMORY DEVICE HAVING A HIERARCHICAL BIT LINE SCHEME - A semiconductor memory device including a bit line connected to a memory cell and a sense amplifier configured to drive a voltage level of a global bit line in response to a voltage level of the bit line. The sense amplifier provides data that is complementary to data stored in the memory cell to the global bit line and provides the complementary data of the global bit line to the memory cell during an active operation of the memory cell. | 09-13-2012 |
20120243356 | SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a memory cell stores therein data. In a bit line, a potential changes according to write data to be written in the memory cell. A precharge circuit precharges the bit line. A precharge control circuit controls precharge of the bit line based on the potential of the bit line and the write data. | 09-27-2012 |
20120250440 | Differential read write back sense amplifier circuits and methods - A differential read write back sense amplifier circuit and corresponding methods. A memory array comprises a plurality of memory cells arranged in rows and columns; a plurality of read word lines coupled to the memory cells; a plurality of write word lines coupled to the memory cells arranged along rows of the memory array; a plurality of read bit line pairs coupled to the memory cells arranged in columns; a plurality of write bit line pairs coupled to the memory cells arranged in columns; and at least one differential read write back sense amplifier coupled to a read bit line pair and coupled to a write bit line pair corresponding to one of the columns of memory cells, configured to differentially sense small signal read data on the read bit line pair, and output the sensed data onto the write bit line pair. Corresponding methods are disclosed. | 10-04-2012 |
20120250441 | Separate Pass Gate Controlled Sense Amplifier - A memory system that includes a first bit line coupled to a first set of dynamic random access memory (DRAM) cells, a second (complementary) bit line coupled to a second set of DRAM cells, and a sense amplifier coupled to the first and second bit lines. The sense amplifier includes a pair of cross-coupled inverters (or a similar latching circuit) coupled between the first and second bit lines, as well as a first select transistor coupling the first bit line to a first global bit line, and a second select transistor coupling the second bit line to a second global bit line. The first and second select transistors are independently controlled, thereby enabling improved read and write access sequences to be implemented, whereby signal loss associated with bit line coupling is eliminated, ‘read bump’ conditions are eliminated, and late write conditions are eliminated. | 10-04-2012 |
20120250442 | Methods For Accessing DRAM Cells Using Separate Bit Line Control - A memory system that includes a first bit line coupled to a first set of dynamic random access memory (DRAM) cells, a second (complementary) bit line coupled to a second set of DRAM cells, and a sense amplifier coupled to the first and second bit lines. The sense amplifier includes a pair of cross-coupled inverters (or a similar latching circuit) coupled between the first and second bit lines, as well as a first select transistor coupling the first bit line to a first global bit line, and a second select transistor coupling the second bit line to a second global bit line. The first and second select transistors are independently controlled, thereby enabling improved read and write access sequences to be implemented, whereby signal loss associated with bit line coupling is eliminated, ‘read bump’ conditions are eliminated, and late write conditions are eliminated. | 10-04-2012 |
20120257469 | Leakage and NBTI Reduction Technique for Memory - In one embodiment, an integrated circuit includes a logic circuit and a memory circuit that includes multiple bit lines and bit line precharge circuits. The memory circuit may include level shifters for control signals generated from logic circuit inputs, including one or more level shifters that generate precharge enable signals to control the bit line precharge circuits. The level shifters for the bit line precharge circuits may also be controlled, during periods of time that the memory circuit is idle, by a control signal (FloatBL herein). If the FloatBL signal is asserted, the bit line precharge circuits may be disabled. In some embodiments, the FloatBL signal may also disable bit line bit line hold circuits on the bit lines. In some embodiments, when the memory circuit is exiting an idle state, the bit line precharge circuits may be enabled in a staggered fashion. | 10-11-2012 |
20120275250 | SEMICONDUCTOR MEMORY DEVICE HAVING A DATA LINE SENSE AMPLIFIER - A memory device includes a data line sense amplifier configured to receive a sense amplifying power source voltage and a sense amplifying ground voltage through a sense amplifying power source line and a sense amplifying ground line, respectively, and sense-amplify data loaded on a pair of data lines, and a pre-charging unit configured to pre-charge and equalize the sense amplifying power source line and the sense amplifying ground line with a sense amplifying pre-charge voltage, generate the sense amplifying pre-charge voltage by voltage dividing the sense amplifying power source voltage and the sense amplifying ground voltage through a voltage dividing path including the sense amplifying power source line and the sense amplifying ground line, and apply the sense amplifying power source voltage to the sense amplifying power source line and the sense amplifying ground voltage to the sense amplifying ground line in response to a sense amplifying pre-charge control signal. | 11-01-2012 |
20120275251 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF - A semiconductor memory device includes a bit line sense amplification unit configured to sense/amplify data loaded on a bit line, and a driving control unit configured to supply a power line of the bit line sense amplification unit with an overdriving voltage in an overdriving period and supply an internal voltage line with a voltage of the power line of the bit line sense amplification unit in a discharge driving period. | 11-01-2012 |
20120275252 | DIFFERENTIAL SENSE AMPLIFIER WITHOUT SWITCH TRANSISTORS - A differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line (BL) and an input connected to a second bit line complementary to the first bit line and a second CMOS inverter having an output connected to the second bit line (/BL) and an input connected to the first bit line. Each CMOS inverter includes pull-up and pull-down transistors, wherein the sources of either of the pull-up transistors or the pull-down transistors are electrically coupled and connected to a pull-up voltage source or a pull-down voltage source without an intermediate transistor between the sources of the transistors and the voltage source. | 11-01-2012 |
20120275253 | DIFFERENTIAL SENSE AMPLIFIER WITHOUT DEDICATED PASS-GATE TRANSISTORS - A differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line and an input connected to a second bit line complementary to the first bit line, and a second CMOS inverter having an output connected to the second bit line and an input connected to the first bit line. Each CMOS inverter includes a pull-up transistor and a pull-down transistor, and the sense amplifier has a pair of pass-gate transistors arranged to connect the first and second bit lines to a first and a second global bit lines. Advantageously, the pass-gate transistors are constituted by the pull-up transistors or the pull-up transistors. | 11-01-2012 |
20120275254 | DIFFERENTIAL SENSE AMPLIFIER WITHOUT DEDICATED PRECHARGE TRANSISTORS - The invention relates to a differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line and an input connected to a second bit line complementary to the first bit line, and a second CMOS inverter having an output connected to the second bit line and an input connected to the first bit line (BL). Each CMOS inverter includes a pull-up transistor and a pull-down transistor, with the sense amplifier having a pair of precharge transistors arranged to be respectively coupled to the first and second bit lines, to precharge the first and second bit lines to a precharge voltage. The precharge transistors are constituted by the pull-up transistors or by the pull-down transistors. | 11-01-2012 |
20120275255 | SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM COMPRISING SEMICONDUCTOR DEVICE - A semiconductor device comprises a sense amplifier circuit amplifying a signal transmitted through the bit line, first/second data lines transmitting the signal amplified by the sense amplifier circuit, a read amplifier circuit driven by a first voltage and amplifying the signal; first/second switch circuits controlling connection between the above components, first/second voltage setting circuits setting the second/third data lines to a second voltage lower than the first voltage. A predetermined voltage obtained by adding the second voltage to a threshold voltage of a transistor in the second/third switch circuit is applied to the gate terminal thereof, and ends of the data lines are connected to the source and drain terminals thereof. | 11-01-2012 |
20120281489 | Low Power Memory Device - “A method of operation within a memory device comprises receiving address information and corresponding enable information. The address information includes a row address that specifies a row of storage cells within a storage array of the memory device, and the enable information includes first and second enable values that correspond respectively to first and second storage locations within the row of storage cells. The method involves selectively transferring data between the first storage location and the sense amplifier circuitry if the first enable value is in an enable state and transferring data between the second storage location and the sense amplifier circuitry if the second enable value is in the enable state. The states of the first and second enable values may be separately controlled.” | 11-08-2012 |
20120287739 | CIRCUIT AND METHOD FOR CONTROLLING LEAKAGE CURRENT IN RANDOM ACCESS MEMORY DEVICES - A circuit for controlling leakage current in random access memory devices comprises a pre-charge equalization circuit. The pre-charge equalization circuit provides a pre-charge voltage to a pair of complementary bit lines of a memory cell of a random access memory device in accordance with a pre-charge signal. When the memory cell is in a self-refresh mode, the pre-charge signal is activated by a periodically triggered pre-charge request and also activated before and after the memory cell is self-refreshed. | 11-15-2012 |
20120287740 | SENSE AMPLIFIERS, MEMORIES, AND APPARATUSES AND METHODS FOR SENSING A DATA STATE OF A MEMORY CELL - Sense amplifiers, memories, and apparatuses and methods for sensing a data state of a memory cell are disclosed. An example apparatus includes a differential amplifier configured to amplify a voltage difference between voltages applied to first and second amplifier input nodes to provide an output. The example apparatus further includes first and second capacitances coupled to the first and second amplifier input nodes. A switch block coupled to the first and second capacitances is configured to couple during a first phase a reference input node to the first and second capacitances and to the first amplifier input node. The switch block is further configured to couple during the first phase an output of the amplifier to the second amplifier input node to establish a compensation condition. During a second phase, the switch block couples its input nodes to the first and second capacitances. | 11-15-2012 |
20120287741 | SEMICONDUCTOR STORAGE - An SRAM macro operates in a normal operation mode in which a plurality of memory-cell array blocks are accessible and in a low power mode in which bit lines in the memory-cell array blocks are left floating. When the SRAM macro returns from the low power mode to the normal operation mode, the bit lines in only memory-cell array blocks to be accessed among the plurality of memory-cell array blocks are precharged in sequence. This allows the peak of precharging current flowing into the SRAM macro to be dispersed. | 11-15-2012 |
20120294101 | METHOD AND APPARATUS FOR SELECTIVE DRAM PRECHARGE - Apparatus and method for using a precharge command in which a plurality of address lines are individually used to specify which banks of memory cells within a memory device have an open row that is to be closed | 11-22-2012 |
20120294102 | MEMORY DEVICE AND SIGNAL PROCESSING CIRCUIT - A memory device which can keep a stored logic state even when the power is off is provided. A signal processing circuit including the memory device, which achieves low power consumption by stopping supply of power, is provided. A memory device includes a logic circuit including a first node and a second node, a first memory circuit connected to the first node, a second memory circuit connected to the second node, and a precharge circuit connected to the first node, the second node, the first memory circuit, and the second memory circuit. When reading data is performed, the precharge circuit outputs a precharge potential to the first node and the second node. The first memory circuit and the second memory circuit each include a transistor in which a channel is formed in an oxide semiconductor film. | 11-22-2012 |
20120294103 | CONTROLLING AC DISTURBANCE WHILE PROGRAMMING - A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation. | 11-22-2012 |
20120300566 | CURRENT SENSE AMPLIFIER WITH REPLICA BIAS SCHEME - Some embodiments of the present disclosure relate to a sense amplifier architecture that facilitates fast and accurate read operations. The sense amplifier architecture includes a folded cascode amplifier for its first sense amplifier stage, and a pre-charge circuit to establish a pre-charge condition for a senseline and a reference senseline of the sense amplifier. The pre-charge circuit and the folded cascode amplifier each include one or more cascode transistors of the same size and which receive the same bias voltage on a gate thereof. This architecture provides fast and accurate read operations in a relatively small footprint, thereby providing a good blend of cost and performance. | 11-29-2012 |
20120307580 | PRE-CHARGE AND EQUALIZATION DEVICES - A circuit comprises a set of pre-charge and equalization devices, a control signal line, and a word line. The set of pre-charge and equalization devices is configured to pre-charge and equalize a pair of data lines. The control signal line is configured to control the pre-charge and equalization devices. The word line is configured to electrically couple a memory cell to a data line of the pair of data lines. A first voltage value provided to the control signal line is from a first voltage source different from a second voltage source that generates a second voltage value for the word line. | 12-06-2012 |
20120314521 | MEMORY THROUGHPUT INCREASE VIA FINE GRANULARITY OF PRECHARGE MANAGEMENT - Methods and apparatus to improve throughput in memory devices are described. In one embodiment, memory throughput is increased via fine granularity of precharge management. In an embodiment, three separate precharge timings may be used, e.g., optimized per memory bank, per memory bank group, and/or per a memory device. Other embodiments are also disclosed and claimed. | 12-13-2012 |
20120320695 | Pre-Charge Voltage Generation and Power Saving Modes - A system includes a voltage generator to produce a pre-charge voltage signal for pre-charging one or more signals in a memory circuit. The one or more signals can be data bus lines used to access memory. The voltage generator can include an input indicating whether the memory circuit is set to a power-saving mode. According to one embodiment, the input adjusts a magnitude of the pre-charge voltage signal produced by the voltage generator. Such an embodiment is useful over conventional methods because adjusting the pre-charge voltage can result in power savings. As an example, when in the power-saving mode, the voltage generator circuit can adjust the pre-charge voltage to a value that reduces an amount of leakage current associated with a pre-charge voltage. Reducing the leakage with respect to the pre-charge voltage means that the saved power can be used for other useful purposes. | 12-20-2012 |
20120327730 | SRAM Differential Voltage Sensing Apparatus - An SRAM differential voltage sensing apparatus is coupled to a memory circuit. The memory circuit comprises a memory bank, a plurality of bit lines, a plurality of data lines coupled to the plurality of bit lines via a plurality of transmission gates and a sense amplifier. When the sense amplifier operates in a characterization mode, the transmission gates and pre-charge circuits are turned off. The differential voltage sensing apparatus applies a characterization signal to the sense amplifier and obtains the parameters of the memory circuit through a trial and error process. | 12-27-2012 |
20120327731 | SEMICONDUCTOR MEMORY APPARATUS AND BIT LINE EQUALIZING CIRCUIT - A semiconductor memory apparatus comprise s bit line sense amplifier unit, and a pair of precharge elements coupled in series between a first bit line and a second bit line and having an asymmetrical contact resistance ratio. | 12-27-2012 |
20120327732 | SEMICONDUCTOR INTEGRATED DEVICE - Provided is a semiconductor integrated device including a semiconductor memory circuit and a peripheral circuit of the semiconductor memory circuit. The peripheral circuit includes a first transistor having a first voltage as a breakdown voltage of a gate oxide film. The semiconductor memory circuit includes a pair of bit lines, one of the pair of bit lines being connected to a gate transistor of a memory cell, and a precharge circuit that includes a transistor having a breakdown voltage substantially equal to that of the first transistor, and precharges the pair of bit lines to a predetermined voltage in response to an activation signal. The activation signal of the precharge circuit is a second voltage higher than the first voltage. | 12-27-2012 |
20130010559 | MEMORY OUTPUT CIRCUIT - The invention provides a memory output circuit. The memory output circuit is capable of receiving bit line data and bit bar line data output by a memory cell array. In one embodiment, the memory output circuit comprises a pre-charge circuit, a pre-amplifier circuit, and a sense amplifier. The pre-charge circuit is capable of pre-charging a first node and a first inverse node wherein the bit line data and bit bar line data are respectively output to the first node and the first inverse node. The pre-amplifier circuit is capable of generating a second voltage on a second node and a second inverse voltage on a second inverse node according to a first voltage on the first node and a first inverse voltage on the first inverse node. The sense amplifier is capable of detecting the second voltage on the second node and the second inverse voltage on the second inverse node to generate a third voltage on a third node and a third inverse voltage on a third inverse node. | 01-10-2013 |
20130016576 | TIME DIVISION MULTIPLEXING SENSE AMPLIFIERAANM O'CONNELL; Cormac MichaelAACI KanataAACO CAAAGP O'CONNELL; Cormac Michael Kanata CA - A circuit comprises a plurality of memory cells, a word line, a plurality of pairs of bit lines, a pre-charge and equalization device, a column select device, and a sense amplifier. The word line is configured to control the plurality of memory cells. Each pair of bit lines of the plurality of pairs of bit lines corresponds to a memory cell of the plurality of memory cells and is coupled to a pair of switches. The sense amplifier is coupled to the plurality of pairs of bit lines, the pre-charge and equalization device, and the column select device. | 01-17-2013 |
20130033949 | DATA CONTROL CIRCUIT - The data control circuit includes an input/output line and a driver. The input/output line precharging circuit precharges a global input/output line to a predetermined voltage when either a reading operation or a writing operation is inoperative. The driver includes a number of MOS transistors and drives the global input/output line in response to receiving data from a local input/output line and a complementary local input/output line during the reading operation. | 02-07-2013 |
20130044555 | PROCESSOR WITH MEMORY DELAYED BIT LINE PRECHARGING - A processor includes an array of memory cells, a control module, a precharge circuit, and an amplifier module. The control module generates a clock signal at a first rate, reduces the first rate to a second rate for a predetermined period, and adjusts the second rate back to the first rate at an end of the predetermined period. The precharge circuit: based on the first rate, precharges first bit lines connected to memory cells in a first row of the array of memory cells; based on the second rate, refrains from precharging the first bit lines; and precharges the first bit lines subsequent to the end of the predetermined period. The amplifier module: based on the first rate, access first instructions stored in the first row; and based on the second rate, accesses second instructions stored in the first row or a second row of the array. | 02-21-2013 |
20130044556 | SENSE AMPLIFIER SCHEME FOR LOW VOLTAGE SRAM AND REGISTER FILES - In at least one embodiment, a sense amplifier circuit includes a pair of bit lines, a sense amplifier output, a keeper circuit, and a noise threshold control circuit. The keeper circuit is coupled to the pair of bit lines and includes an NMOS transistor coupled between a power node and a corresponding one of the pair of bit lines. The keeper circuit is sized to supply sufficient current to compensate a leakage current of the corresponding bit line and configured to maintain a voltage level of the corresponding bit line. The noise threshold control circuit is connected to the sense amplifier output and the pair of bit lines. The noise threshold control circuit comprises a half-Schmitt trigger circuit or a Schmitt trigger circuit. | 02-21-2013 |
20130058179 | SYSTEM AND METHOD FOR INCREASING DDR MEMORY BANDWIDTH IN DDR SDRAM MODULES - A system and method for increasing DDR memory bandwidth in DDR SDRAM modules are provided. DDR memory has an inherent feature called the Variable Early Read command, where the read command is issued on CAS latency before the completion of the ongoing data burst and the effect of the CAS latency is minimized in terms of the effect on bandwidth. The system and method optimizes the remaining two access latencies (t | 03-07-2013 |
20130064028 | SEMICONDUCTOR MEMORY DEVICE AND SENSE AMPLIFIER - A semiconductor memory device comprises a memory cell; a first bit line and a second bit line connected to the memory cell; and a sense amplifier operative to amplify the voltage between the first and second bit lines. The sense amplifier includes a first and a second drive transistor configuring a transistor pair for differential amplification, and a first and a second capacitor connected between the sources of the first and second drive transistors and a source control terminal, respectively. The sense amplifier precharges the first and second drive transistors on the drain side prior to sensing, thereby holding the threshold information on the first and second drive transistors in the first and second capacitors, and compensates for the source voltages on the first and second drive transistors by the threshold information held in the first and second capacitors at the time of sensing. | 03-14-2013 |
20130064029 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - An operating method of a semiconductor memory device includes precharging a channel region of a program-inhibited cell of first memory cells coupled to a first word line, selected from a first one of word line groups between a drain select line and a source select line, to a first level based on first data; performing a first program operation for storing the first data in the first memory cells; precharging the channel region of a program-inhibited cell of second memory cells coupled to a second word line, selected from a second one of the word line groups, to a second level based on second data to be stored in the second memory cells; and performing a second program operation for storing the second data in the second memory cells. | 03-14-2013 |
20130070549 | Single-Ended Sense Amplifier with Read-Assist - A sense amplifier is provided that comprises, responsive to receiving a set signal to turn on a set device and a precharged voltage level read bit line signal, a keeper device that turns on responsive to receiving a LOW signal from an inverting amplifier and pulls up the voltage at a first node so that a HIGH signal is output onto a global bit line. Responsive to receiving the set signal to turn on the set device and a read bit line signal that is discharging through a read stack path to ground and responsive to the read bit line signal discharging below a first predesigned voltage level, a read assist device in the sense amplifier turns on responsive to receiving a HIGH signal from the inverting amplifier and pulls down the voltage at the first node so that a LOW state is output onto a global bit line. | 03-21-2013 |
20130070550 | ADAPTIVE WRITE BIT LINE AND WORD LINE ADJUSTING MECHANISM FOR MEMORY - A memory including a capacitor coupled to a write bit line or a word line and an initializer configured to initialize a voltage level at a first node between the capacitor and the write bit line or the word line. The memory further includes a controllable initial level adjuster configured to adjust a voltage level of a second node at one terminal of the capacitor in response to a pulse. The capacitor is configured to receive a boost signal at a third node at a terminal opposite the first node. The boost signal configured to change a voltage level of the write bit line or the word line in response to the boost signal. | 03-21-2013 |
20130077423 | REFRESH METHOD AND APPARATUS FOR A SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a bit line sense amplifier configured to sense and amplify data of a first bit line coupled to a first memory cell of a first cell block when a refresh operation is performed on the first cell block, and sense and amplify data of a second bit line coupled to a second memory cell of a second cell block when a refresh operation is performed on the second cell block. A first switch may be configured to block coupling between the first bit line and the bit line sense amplifier when a refresh operation is performed on the second cell block and a second switch may be configured to block coupling between the second bit line and the bit line sense amplifier when a refresh operation is performed on the first cell block. | 03-28-2013 |
20130077424 | SEMICONDUCTOR MEMORY CIRCUIT AND CONTROL METHOD FOR READING DATA - A semiconductor memory device includes a first memory circuits connecting to a first bit line, a second bit line and a word line, a first pre-charge control circuit connecting to a first pre-charge control line, the first bit line and the second bit line and that pre-charges the first bit line and the second bit line on the basis of the input from the first pre-charge control line, and a read control circuit having a first transistor, a second transistor, a third transistor and a fourth transistor, wherein the fourth transistor is brought into conduction on the basis of the input from a charged global-bit-line driver control line, the column having the first bit line and the second bit line is thus selected, and the information held in the memory circuit connecting to the driven word line among the memory circuits is output to the third bit line. | 03-28-2013 |
20130083613 | Method and Apparatus of Reducing Leakage Power in Multiple Port SRAM Memory Cell - Systems and method for reducing leakage currents and power consumption in a memory array comprising memory cells, such as 8T SRAM cells. The memory array includes logic for dynamically placing a group of memory cells in the memory array in a reduced power state during sleep mode or inactive states of the group of memory cells, such that leakage parts are effectively eliminated. The memory array further includes logic for dynamically enabling a selected group of the memory cells during read or write access operations on the selected memory cells, wherein corresponding read or write bitlines are precharged before and after the respective rear or write operations. | 04-04-2013 |
20130083614 | VOLTAGE SUPPLY CIRCUIT, SEMICONDUCTOR MEMORY DEVICE, AND OPERATING METHOD THEREOF - A voltage supply circuit includes a high voltage generator configured to generate an operating voltage, a global word line switch configured to transfer the operating voltage to global word lines, a plurality of local line switches coupled to the global word lines and configured to transfer the operating voltage to corresponding local word lines, a precharge unit configured to supply a precharge voltage to an unselect local line switch adjacent to a select local line switch to which the operating voltage will be supplied, from among the plurality of local line switches, in a preparation section before an operation is started, and a coupling unit configured to couple the unselect local line switch and the global word line switch when the operation is started. | 04-04-2013 |
20130083615 | REDUCED NOISE DRAM SENSING - A dynamic random access memory device is described. A first array has a first plurality of bitlines, each coupled to a column of memory cells. A second has a second plurality of bitlines, each coupled to a column of memory cells. Sense amplifiers are selectively connectable in an open bitline configuration to at least one bitline of the first plurality of bitlines and at least one complementary bitline of the second plurality of bitlines. A voltage supply having a voltage V | 04-04-2013 |
20130088931 | ASYMMETRIC MEMORY CELLS - An asymmetric memory cell is disclosed. The memory cell includes a refresh control line, a pass gate transistor, and a refresh transistor. The refresh transistor is coupled to the refresh control line, and provides a feedback between the pass gate transistor and a plurality of inverters, when the refresh control line is in a default state. | 04-11-2013 |
20130088932 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell connected to a word line and a bit line, for storing and holding data, a word line driver circuit connected to the word line, a bit line precharge circuit connected to the bit line, and a peripheral control circuit. First power supply VDD is connected to the memory cell and the peripheral control circuit, and first power supply VDD is connected to word line driver circuit and bit line precharge circuit through switching element controlled by first control signal PD. A leakage current is effectively reduced at the time of standby, while an area is prevented from being increased. | 04-11-2013 |
20130100753 | DATA TRANSMISSION CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME - A data transmission circuit includes a read data transmission unit configured to, when a read signal is asserted, detect and amplify a voltage level of a first data line, transmit an amplified voltage level to a second data line, and substantially prevent a voltage level of the second data line from being amplified to be substantially equal to or more than a preset voltage level, and a write data transmission unit configured to transmit the voltage level of the second data line to the first data line when a write signal is asserted. | 04-25-2013 |
20130107650 | SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE | 05-02-2013 |
20130114361 | SENSE AMPLIFIER HAVING AN ISOLATED PRE-CHARGE ARCHITECTURE, A MEMORY CIRCUIT INCORPORATING SUCH A SENSE AMPLIFIER AND ASSOCIATED METHODS - Disclosed are a sense amplifier and a memory circuit that incorporates it. The amplifier comprises cross-coupled inverters, each with a pull-down transistor and a pull-up transistor connected in series. One inverter has a voltage-controlled switch controlling the electrical connection between drain nodes of the transistors. During a read operation, the pull-up transistor drain node is pre-charged high and the pull-down transistor drain node receives an input signal. The switch is tripped, thereby making the electrical connection only when the voltage at the pull-down transistor drain node is less than the switch's trip voltage. In this case, the sense node discharges to the same level as the input signal. Otherwise, the switch prevents the electrical connection and the sense node remains high. The trip voltage depends on a reference voltage, which can be variable, thereby allowing the sensitivity of the sense amplifier to be selectively adjusted. Also disclosed are associated methods. | 05-09-2013 |
20130141997 | SINGLE-ENDED VOLATILE MEMORY ACCESS - A memory includes an array of memory cells that form rows and columns. The rows include memory cell pairs. The memory cells may include two cross-coupled inverters and two pass-devices that couple to alternate sides of the cross-coupled inverters. For a read operation, a wordline drive circuit selects one memory cell of the pair, the selected memory cell being an addressed memory cell while the remaining cell is an unaddressed memory cell. In response to a wordline enable signal, a pass gate in the addressed memory cell couples the addressed memory cell via a complement bitline to an evaluation gate that resolves the data from the read operation. During the read operation, the unaddressed memory cell couples via another pass gate to a true bitline that terminates without an evaluation gate to conserve energy. | 06-06-2013 |
20130148452 | VOLTAGE SHIFTING SENSE AMPLIFIER FOR SRAM VMIN IMPROVEMENT - A sense amplifier for a SRAM device includes a PMOS differential pair and an NMOS differential pair to support operation with bit line precharge voltage as low as a few hundred millivolts without performance degradation, and generates a full rail output signal without any additional level shifter circuits. The PMOS differential amplifier includes tail current device coupled to a voltage higher than the bit line precharge voltage, and the NMOS differential amplifier includes tail current device coupled to a voltage lower than the bit line precharge voltage. | 06-13-2013 |
20130155797 | USING A PRECHARGE CHARACTERISTICS OF A NODE TO VALIDATE A PREVIOUS DATA/SIGNAL VALUE REPRESENTED BY A DISCHARGE OF SAID NODE - An integrated circuit precharges a node | 06-20-2013 |
20130163358 | SYSTEMS, CIRCUITS, AND METHODS FOR CHARGE SHARING - Systems, circuits, and methods are disclosed for charge sharing. In one such example system, a first line is configured to be driven to a first voltage representative of data to be placed on the first line and then precharged to a first precharge voltage. A second line is configured to be driven to a second voltage representative of data to be placed on the second line and then precharged to a second precharge voltage. A charge sharing device is coupled between the first line and the second line. The charge sharing device is configured to selectively allow charge from the first line to flow to the second line after the first and second lines are driven to the respective first and second voltages representative of data to be placed on the respective lines. | 06-27-2013 |
20130163359 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device and a method of operating the same are provided. The method includes performing an overall erase operation such that each threshold voltage of all memory cells connected to even word lines and odd word lines in a selected memory cell block are lower than a first target level, performing an erase operation such that each threshold voltage of the memory cells connected to the even word lines are lower than a second target level which is lower than the first target level, and performing an erase operation such that each threshold voltage of the memory cells connected to the odd word lines are lower than the second target level. | 06-27-2013 |
20130163360 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - A semiconductor device and an operating method thereof comprise peripheral circuits configured to apply an erase voltage to memory cells when performing an erase operation, and sense a voltage change of bit lines by an erase verification voltage applied to word lines of the memory cells when performing an erase verification operation to thereby detect cells which are not erased, and a control circuit configured to control the peripheral circuits by changing a sensing reference level for determining the voltage change of the bit lines when the cells which are not erased are detected when performing the erase verification operation, so that the erase verification operation is repeatedly performed. | 06-27-2013 |
20130163361 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor device comprises a first pair of signal lines and a first control circuit. The first control circuit precharges each of the first pair of signal lines to a first voltage in response to a precharge signal, and changes the voltage level of each of the first pair of signal lines to a second voltage different from the first voltage when a deep power down signal is input. | 06-27-2013 |
20130163362 | PRECHARGE CIRCUIT AND NON-VOLATILE MEMORY DEVICE - A precharge circuit includes a precharge unit configured to apply a voltage of a precharge voltage terminal to a data line during a precharge operation, and a sensing unit configured to disable the precharge unit by sensing the voltage of the precharge voltage terminal, The precharge circuit may control a precharge operation by sensing a change in the voltage level of the precharge voltage terminal. | 06-27-2013 |
20130176801 | PRECHARGE CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME - A semiconductor memory device includes: input/output line coupled to a first bit line of a first mat including a plurality of memory cells; a second input/output line coupled to a second bit line of a second mat including a plurality of memory cells; and a switching unit configured to couple the first input/output line and the second input/output line in response to a precharge signal. | 07-11-2013 |
20130176802 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a switching unit coupled between a local sense amplifier and a bit line sense amplifier and configured to be turned on in response to a switching signal which is enabled in synchronization with an enable signal for enabling the local sense amplifier and disabled at a time point where a preset period passes after a first power for enabling the bit line sense amplifier is precharged. | 07-11-2013 |
20130176803 | SEMICONDUCTOR MEMORY DEVICE AND REFRESH METHOD THEREOF - A semiconductor memory device and a self-refresh method of the semiconductor memory device. The semiconductor memory device includes: a memory cell array including one or more memory cells; a sense amplifier connected to a sensing line and a complementary sensing line and sensing/amplifying data stored in the one or more memory cells; and a sense amplifier control circuit sequentially supplying a first voltage and a second voltage having different levels to the sense amplifier through the sensing line during a refresh operation. | 07-11-2013 |
20130182519 | MEMORY DEVICE AND VOLTAGE INTERPRETING METHOD FOR READ BIT LINE - A memory device comprises a memory cell array, a first and a second pre-charging switch circuits, a selecting circuit, an auxiliary memory cell array, a dynamic voltage controller and a sense amplifier. The auxiliary memory cell array comprises an auxiliary read bit line and a plurality of memory cells arranged in a column and electrically connected to the auxiliary read bit line. The second pre-charging switch circuit determines whether or not to supply a reference voltage to each of the aforementioned memory cells according to a pre-charging control signal. The dynamic voltage controller determines whether or not to supply a voltage to the auxiliary read bit line according to the voltage level of the output signal of the selecting circuit. The sense amplifier compares the voltage levels of the output signal of the selecting circuit and the voltage on the auxiliary read bit line to output a sensing result accordingly. | 07-18-2013 |
20130194884 | Synchronous Global Controller For Enhanced Pipelining - A system includes a memory block and a controller. The controller is adapted to skew a pre-charge signal for a bit line of the memory block. The controller can skew the pre-charge signal during a read operation or a write operation. The system can also include a sense amplifier in communication with a bit line of the memory block, and the sense amplifier can automatically shut off after indicating a sensed data state for the bit line. The controller may be a global controller or a local controller. | 08-01-2013 |
20130215697 | CIRCUIT FOR DRIVING WORD LINE - A word line driving circuit includes, inter alia: a word line driving signal generator, a main word line enable signal controller, and a sub word line driver. The word line driving signal generator activates a word line boosting signal, a pre-main word line enable signal, and a word line off signal in response to an active signal and a precharge signal. The main word line enable signal controller receives the pre-main word line enable signal and outputs it as the main word line enable signal in response to a main word line test mode signal. The sub word line driver uses the word line boosting signal as a driving voltage, and drives a sub word line in response to the main word line enable signal and the word line off signal. | 08-22-2013 |
20130215698 | SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE - A semiconductor device comprises first and second global bit lines, a sense amplifier amplifying a voltage difference of the first and second global bit lines, first and second local bit lines corresponding to the first and second global bit lines, and first and second hierarchical switches controlling electrical connections between the first and second global bit lines and the first and second local bit line. In a precharge operation prior to accessing a selected memory cell belong to the first local bit lines, a pair of the first and second hierarchical switches, which is not in an access path, is kept ON, and remaining ones thereof are kept OFF. Subsequently, in an access to the selected memory cell, a first hierarchical switch of the pair is switched from ON to OFF, and simultaneously a first hierarchical switches in the access path is switched from OFF to ON. | 08-22-2013 |
20130215699 | MEMORY BANK SIGNAL COUPLING BUFFER AND METHOD - A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments within the array. Respective bidirectional buffers couple read data from one of the segments to another in a first direction, and to couple write data from one of the segments to another in a second direction that is opposite the first direction. The data lines may be local data read/write lines that couple different banks of memory cells to each other and to respective data terminals, digit lines that couple memory cells in a respective column to respective sense amplifiers, word lines that activate memory cells in a respective row, or some other signal line within the array. The memory array also includes precharge circuits for precharging the segments of respective data lines to a precharge voltage. | 08-22-2013 |
20130235686 | BIPOLAR PRIMARY SENSE AMPLIFIER - A sense amplifier for a memory includes two bipolar transistors and isolation switches for selectively coupling and decoupling the base of the bipolar transistors to bit lines during portions of a read cycle. The sense amplifier has a feedback circuit that couples the collector of one of the bi polar transistors to the base of the other bipolar transistor and vice versa. | 09-12-2013 |
20130235687 | Asymmetric Sense Amplifier Design - A circuit includes a first inverter including a first PMOS transistor and a first NMOS transistor, and a second inverter including a second PMOS transistor and a second NMOS transistor. A first node is connected to gates of the first PMOS transistor and the first NMOS transistor and drains of the second PMOS transistor and the second NMOS transistor. A second node is connected to gates of the second PMOS transistor and the second NMOS transistor and drains of the first PMOS transistor and the first NMOS transistor. The circuit further includes a first capacitor having a first capacitance connected to the first node; and a second capacitor having a second capacitance connected to the second node. The second capacitance is greater than the first capacitance. | 09-12-2013 |
20130242681 | METHODS AND APPARATUS FOR REDUCING PROGRAMMING TIME OF A MEMORY CELL - A method is provided for programming a memory cell having a first terminal coupled to a word line and a second terminal coupled to a bit line. During a first predetermined time interval, the word line is switched from a first standby voltage to a first voltage, the bit line is switched from a second standby voltage to a predetermined voltage, and a voltage drop across the first and second terminals is a safe voltage that does not program the memory cell. During a second predetermined time interval, the word line is switched from the first voltage to a second voltage, and a voltage drop across the first and second terminals is a programming voltage that is sufficient to program the memory cell. Numerous other aspects are provided. | 09-19-2013 |
20130265839 | SEMICONDUCTOR MEMORY DEVICE WITH SENSE AMPLIFIER AND BITLINE ISOLATION - A semiconductor memory device, including: a memory cell connected to a first bitline and associated with a second bitline; a sense amplifier, including a first input/output node and a second input/output node; and an isolator connected to the bitlines and to the input/output nodes, the isolator being configured to carry out bitline isolation during a refresh operation of the memory cell, where the bitline isolation includes electrically disconnecting the first bitline from the first input/output node and electrically disconnecting the second bitline from the second input/output node, followed by: electrically re-connecting the first bitline to the first input/output node while the second bitline remains electrically disconnected from the second input/output node. | 10-10-2013 |
20130272081 | METHOD OF OPERATING A SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is operated by, inter alia, selecting an even bit line or an odd bit line in response to a read command, and precharging the selected bit line by applying a precharge voltage to the selected bit line; changing potential of the selected bit line in response to a threshold voltage of a selected memory cell coupled to the selected bit line; precharging a non-selected bit line by applying a precharge voltage to the non-selected bit line; and sensing read data in accordance with the potential of the selected bit line. | 10-17-2013 |
20130272082 | REFRESH CIRCUIT IN SEMICONDUCTOR MEMORY DEVICE - A refresh circuit in a semiconductor memory device performs a multi-enable skew refresh operation during each periodic refresh operation. The refresh circuit includes a signal generation unit configured to generate a plurality of refresh signals having different timings during a refresh operation period, a first refresh circuit configured to enable refresh target lines associated with a first memory group in a memory cell array through operation periods of at least two time periods by using some of the refresh signals, and a second refresh circuit configured to enable refresh target lines associated with a second memory group differing from the first memory group through operation periods of at least two time periods by using some or all of the rest of the refresh signals. Enable timings of the first and second refresh circuits do not coincide each other. | 10-17-2013 |
20130279281 | SEMICONDUCTOR MEMORY INTEGRATED DEVICE HAVING A PRECHARGE CIRCUIT WITH THIN-FILM TRANSISTORS GATED BY A VOLTAGE HIGHER THAN A POWER SUPPLY VOLTAGE - Provided is a semiconductor integrated device including a semiconductor memory circuit and a peripheral circuit of the semiconductor memory circuit. The peripheral circuit includes a first transistor having a first voltage as a breakdown voltage of a gate oxide film. The semiconductor memory circuit includes a pair of bit lines, one of the pair of bit lines being connected to a gate transistor of a memory cell, and a precharge circuit that includes a transistor having a breakdown voltage substantially equal to that of the first transistor, and precharges the pair of bit lines to a predetermined voltage in response to an activation signal. The activation signal of the precharge circuit is a second voltage higher than the first voltage. | 10-24-2013 |
20130294185 | SENSE AMPLIFIER CIRCUIT AND SEMICONDUCTOR DEVICE USING THE SAME - A sense amplifier circuit includes an enable signal generation unit configured to generate an enable signal when a change in a voltage level of input signals is sensed; a sink unit configured to provide a sense voltage in response to the enable signal; and a sense unit configured to generate an output signal in response to the sense voltage and the input signals. | 11-07-2013 |
20130308403 | SEMICONDUCTOR DEVICE HAVING SENSE AMPLIFIER CIRCUIT - Disclosed herein is a device that includes: a first control element that controls an amount of current flowing between a second line and a first node according to a potential of a first line; a second control element that controls an amount of current flowing between the first line and the first node according to a potential of the second line; a first control circuit that performs a first operation to fix potentials of the first and second lines at a first potential; a second control circuit that performs a second operation to connect the first node to the second node; and a third control circuit that fixes a potential of the first node at a second potential after the first control circuit stops the first operation until the second control circuit starts the second operation. | 11-21-2013 |
20130315017 | SENSE AMPLIFIER CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A sense amplifier control circuit according to the present invention is disposed in a bit line sense amplifier (BLSA) array region including a plurality of BLSAs and is configured to supply a precharge voltage to the plurality of BLSAs in response to a control signal. | 11-28-2013 |
20130322194 | Conditional Read-Assist Feature to Accelerate Access Time in an Electronic Device - An electronic storage device includes a bit cell circuit, feedback circuit, and read accelerator circuit. The bit cell circuit is adapted for connection with true and complementary bit lines. The feedback circuit includes a first transistor which is coupled to a first voltage potential and responsive to the complementary bit line. The read accelerator circuit includes second, third, and fourth transistors coupled between the feedback circuit and a second voltage potential. The second transistor is responsive to a read line, the third transistor is responsive to the true bit line, and the fourth transistor is responsive to the complementary bit line. The read accelerator circuit is configured to provide a discharge path for at least one of the true bit line and the complementary bit line during a read access of the bit cell. Embodiments of a corresponding electronic read access accelerator device and method are also provided. | 12-05-2013 |
20130322195 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE - A semiconductor device includes: a data transmission unit configured to transmit differential data between a first data line pair and a second data line pair; and first and second power supply voltage generation units configured to generate precharging voltages to be applied to the first and second data line pairs, respectively. | 12-05-2013 |
20140003175 | STORAGE CELL BRIDGE SCREEN TECHNIQUE | 01-02-2014 |
20140036610 | DEVICES AND METHODS FOR CONTROLLING MEMORY CELL PRE-CHARGE OPERATIONS - A memory having a memory array having bit cells coupled to bit lines. The memory further includes a precharge circuit that precharges bit lines. The memory also includes a control circuit coupled to the precharge circuit that enables the precharge circuit at a beginning portion of a read cycle, keeps the precharge circuit disabled until an end of the read cycle, and keeps the precharge circuit disabled during a write cycle. A method of operating a memory, in which the memory includes an array of memory cells coupled to bit lines, includes precharging the bit lines at a beginning of a read cycle. The method also includes blocking precharging of the bit lines for a duration of a write cycle. | 02-06-2014 |
20140056089 | SENSE AMPLIFIERS, MEMORIES, AND APPARATUSES AND METHODS FOR SENSING A DATA STATE OF A MEMORY CELL - Sense amplifiers, memories, and apparatuses and methods for sensing a data state of a memory cell are disclosed. An example apparatus includes a differential amplifier configured to amplify a voltage difference between voltages applied to first and second amplifier input nodes to provide an output. The example apparatus further includes first and second capacitances coupled to the first and second amplifier input nodes. A switch block coupled to the first and second capacitances is configured to couple during a first phase a reference input node to the first and second capacitances and to the first amplifier input node. The switch block is further configured to couple during the first phase an output of the amplifier to the second amplifier input node to establish a compensation condition. During a second phase, the switch block couples its input nodes to the first and second capacitances. | 02-27-2014 |
20140064000 | Fast Bit-Line Pre-Charge Scheme - A device includes a first switch configured to control a connection between a first voltage node and a capacitor, and a second switch configured to control a connection between a common charge node and the capacitor. The device further includes a plurality of bit-lines, and a plurality of bit-line charge switches, each configured to control a connection between a respective one of the plurality of bit-lines and the common charge node. | 03-06-2014 |
20140064001 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first memory block group including memory blocks coupled to first sub bit lines, a second memory block group including memory blocks coupled to second sub bit lines, an operation circuit coupled to main bit lines, and configured to perform an operation for data input/output to/from a memory block selected from the first memory block group or the second memory block group, and a bit line control circuit configured to differently control sub bit lines of the selected memory block group and sub bit lines of the unselected memory block groups in response to group select signals for selecting a memory block group including the selected memory block of the first memory block group and the second memory block group and voltages of the main bit lines controlled by the operation circuit. | 03-06-2014 |
20140064002 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device and a method of manufacturing the same are provided. The device includes a memory block and one or more peripheral circuits. The memory block includes a bit line, a common source line, a vertical channel layer coupled between the bit line and the common source line, word lines surrounding the bit line at different heights from a semiconductor substrate, and memory cells formed in portions where the word lines surround the vertical channel layer. The one or more peripheral circuits are configured to set the word lines to a floating state to supply holes to the vertical channel layer when a precharge voltage is applied to the common source line, and set word lines of memory cells to be erased to a ground state when an erase voltage is applied to the common source line. | 03-06-2014 |
20140064003 | FUSE CIRCUIT, OPERATING METHOD THEREOF, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE FUSE CIRCUIT - A semiconductor memory device includes a fuse unit including a fuse configured to be programmed with a repair target address, an enable unit configured to enable the fuse unit, an output unit configured to output a signal corresponding to whether the fuse unit is programmed or not, and a control unit configured to control a voltage difference between both ends of the fuse unit in response to a control signal. | 03-06-2014 |
20140071777 | SYSTEMS, CIRCUITS, AND METHODS FOR CHARGE SHARING - Systems, circuits, and methods are disclosed for charge sharing. In one such example system, a first line is configured to be driven to a first voltage representative of data to be placed on the first line and then precharged to a first precharge voltage. A second line is configured to be driven to a second voltage representative of data to be placed on the second line and then precharged to a second precharge voltage. A charge sharing device is coupled between the first line and the second line. The charge sharing device is configured to selectively allow charge from the first line to flow to the second line after the first and second lines are driven to the respective first and second voltages representative of data to be placed on the respective lines. | 03-13-2014 |
20140078844 | MEMORY CIRCUITS, SYSTEMS, AND METHODS FOR ACCESSING THE MEMORY CIRCUITS - A sense amplifier includes a first transistor. The first transistor includes a gate connected to a bit line, and a first source/drain (S/D) electrically coupled with a global bit line. The sense amplifier further includes a second transistor. The second transistor includes a gate connected to a first signal line, and a first S/D coupled to the global bit line, wherein the second transistor is configured to pre-charge the bit line. | 03-20-2014 |
20140092696 | POWER MANAGEMENT DOMINO SRAM BIT LINE DISCHARGE CIRCUIT - A domino static random access memory (SRAM) having one or more SRAM memory cells connected with a local bit line is disclosed. The SRAM may include a global bit line, a first precharge device connected between a voltage supply and the local bit line, and a second precharge device connected between the voltage supply and the global bit line. In addition the SRAM may include a global bit line discharge logic connected with the global bit line and the local bit line. The global bit line discharge logic is adapted to draw the global bit line to a voltage below a precharge voltage and above a ground voltage during a read operation. | 04-03-2014 |
20140092697 | READ TIMING GENERATION CIRCUIT - Disclosed is a read timing generation circuit, capable of reducing dynamic power consumption. After a multi-bit address Add | 04-03-2014 |
20140104971 | SEMICONDUCTOR MEMORY DEVICE - Disclosed is a semiconductor memory device that includes a sense amplifier section. The sense amplifier section includes first n-type diffusion layers, second n-type diffusion layers, first to fifth gates, and first to eighth contacts. The first to fourth contacts are formed over the first n-type diffusion layers. The fifth to eighth contacts are formed over the second n-type diffusion layers. The first and fourth gates are formed in a region between the first n-type diffusion layers. The third gate is formed in a region between the first n-type diffusion layers and in a region between the second n-type diffusion layers. The second and fifth gates are formed in a region between the second n-type diffusion layers. | 04-17-2014 |
20140119145 | SEMICONDUCTOR MEMORY INTEGRATED DEVICE HAVING A PRECHARGE CIRCUIT WITH THIN-FILM TRANSISTORS GATED BY A VOLTAGE HIGHER THAN A POWER SUPPLY VOLTAGE - Provided is a semiconductor integrated device including a semiconductor memory circuit and a peripheral circuit of the semiconductor memory circuit. The peripheral circuit includes a first transistor having a first voltage as a breakdown voltage of a gate oxide film. The semiconductor memory circuit includes a pair of bit lines, one of the pair of bit lines being connected to a gate transistor of a memory cell, and a precharge circuit that includes a transistor having a breakdown voltage substantially equal to that of the first transistor, and precharges the pair of bit lines to a predetermined voltage in response to an activation signal. The activation signal of the precharge circuit is a second voltage higher than the first voltage. | 05-01-2014 |
20140140157 | Complementary Metal-Oxide-Semiconductor (CMOS) Min/Max Voltage Circuit for Switching Between Multiple Voltages - A voltage selection mechanism is provided for switching between multiple voltages without causing a direct current (DC) that may further stress storage elements due to excessive power consumption and electro-migration effects. The voltage selection mechanism comprises cross-coupled circuitry, which comprises a first positive-channel field effect transistor (PFET) and a second PFET. The voltage selection mechanism further comprises diode circuitry, which comprises a third PFET and a fourth PFET. | 05-22-2014 |
20140140158 | PRE-CHARGING A DATA LINE - A control circuit includes a data driver, a charge circuit, and a first data line coupled with the data driver and the charge circuit. The charge circuit is configured to charge the first data line when the first data line is selected for accessing a memory cell corresponding to the first data line and to not charge the first data line when the first data line is not selected for accessing the memory cell. The data driver, based on a first control signal, is configured to transfer a signal on the first data line to an output of the data driver. | 05-22-2014 |
20140153349 | Simultaneous Two/Dual Port Access on 6T SRAM - A method includes generating a first and a second internal clock signal from a clock signal, wherein a first internal clock signal edge of the first internal clock signal and a second internal clock signal edge of the second internal clock signal are generated from a same edge of the clock signal. A first one of the first and the second internal clock edges is used to trigger a first operation on a six-transistor (6T) Static Random Access Memory (SRAM) cell of a SRAM array. A second one of the first and the second internal clock edges is used to trigger a second operation on the 6T SRAM cell. The first and the second operations are performed on different ports of the 6T SRAM. The first and the second operations are performed within a same clock cycle of the clock signal. | 06-05-2014 |
20140177366 | DATA INPUT/OUTPUT CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A data input/output circuit includes a precharge voltage supply unit configured to supply a precharge voltage driven by a first internal voltage in a standby state, and supply the precharge voltage driven by a second internal voltage when an active operation is performed; and a precharge unit configured to receive the precharge voltage, precharge a first input/output line and a first inverted input/output line to a level of the first internal voltage in the standby state, and precharge the first input/output line and the first inverted input/output line by the second internal voltage when the active operation is performed. | 06-26-2014 |
20140177367 | SEMICONDUCTOR DEVICE INCLUDING PLURAL CHIPS STACKED TO EACH OTHER - A device includes a plurality of Dynamic Random Access Memory (DRAM) chips in a stacked configuration connected by through silicon vias (TSVs), and each of the plurality of DRAM chips being configured to provide a local bank active signal to indicate when any one of a plurality of banks on a respective one of the plurality of DRAM chips is active, and local bank active signals from the plurality of DRAM chips being supplied through TSVs of intervening ones of the plurality of DRAM chips to a lowermost one of the plurality of DRAM chips. | 06-26-2014 |
20140192603 | DIFFERENTIAL SENSE AMPLIFIER FOR SOLID-STATE MEMORIES - Described embodiments provide a memory having at least one sense amplifier with inputs coupled to at least one pair of bit lines. One of the pair of bit lines is precharged to a power supply voltage and a second one of the pair is precharged to ground. A first switch DC-couples the first one of the pair of bit lines to a first input of a cross-coupled amplifier. A first capacitor AC-couples the second one of the pair of bit lines to a second input of the cross-coupled amplifier. Then a memory cell coupled between the first and second one of the pair of bit lines is enabled. A switch then decouples the first input from the bit line, a second capacitor is used to inject a charge of current into the first input of the cross-coupled amplifier, and then the cross-coupled amplifier is enabled. | 07-10-2014 |
20140192604 | MEMORY CELL OPERATION - Methods, devices, and systems associated with memory cell operation are described. One or more methods of operating a memory cell include charging a capacitor coupled to the memory cell to a particular voltage level and programming the memory cell from a first state to a second state by controlling discharge of the capacitor through a resistive switching element of the memory cell. | 07-10-2014 |
20140198594 | VARIABLE PRE-CHARGE LEVELS FOR IMPROVED CELL STABILITY - Embodiments of a memory device are disclosed that may allow for multiple pre-charge voltages. The memory device may include a plurality of data lines, and a plurality of pre-charge circuits. Each of the plurality of data lines may be coupled to a plurality of data storage cells. Each of the plurality of pre-charge circuits may be coupled to a respective data line, and be configured to charge the data line to a first voltage level responsive to a first control signal. Each of the plurality of pre-charge circuits may also be configured to charge the respective data line to a second voltage responsive to a second control signal. | 07-17-2014 |
20140198595 | MULTIPLE READ PORT MEMORY SYSTEM WITH A SINGLE PORT MEMORY CELL - An improved multi-port register file system and method of operating. The multi-port register file memory system comprises: n single memory bit cells each storing a data value and having a single bit cell write port and a single read port connecting a respective local bit line, wherein corresponding parallel activated single bit cells output a stored data value in parallel at n read port outputs to a respective local bit line of n local bit lines, each single bit cell accessed in parallel according to a decoded read address signal. A receiver device is provided implementing n selection logic devices corresponding to n read ports, each selection logic device receiving each the n local bit line output values from the n single bit cells, and implementing logic based directly on the decoded read address signal to select a respective local bit line output as a global output bit. | 07-17-2014 |
20140241087 | SENSE AMPLIFIER - A sense amplifier comprises a cross coupled pair of inverters, a first transistor, a second transistor, and a capacitive device. The cross coupled pair of inverters includes a first end, a second end, and a third end. The first end is configured to receive a first supply voltage. The second end is coupled with a first terminal of the capacitive device and a first terminal of the first transistor. The third end is coupled with a second terminal of the capacitive device and a first terminal of the second transistor. A second terminal of the first transistor and a second terminal of the second transistor are coupled together and are configured to receive a first control signal. A third terminal of the first transistor and a third terminal of the second transistor are coupled together and are configured to receive a second supply voltage different from the first supply voltage. | 08-28-2014 |
20140241088 | SEMICONDUCTOR DEVICE HAVING COMPLEMENTARY BIT LINE PAIR - Disclosed herein is a semiconductor device comprising complementary pair of bit lines, memory cells connected to the bit lines, dummy cells having the same structure as the memory cells, a differential sense amplifier, an equalizing circuit equalizing potentials of the bit lines, and a control circuit. The memory cells are disconnected from the bit lines and the dummy cells are connected to the bit lines, and subsequently the bit lines are equalized by the equalizing circuit. When accessing a selected memory cell, the equalizing circuit is inactivated, a corresponding dummy cell is disconnected from the bit line, and subsequently the selected memory cell is connected to the bit line. Thereafter, the sense amplifier is activated so that potentials of the bit lines are amplified respectively. | 08-28-2014 |
20140269125 | Device and Method for Improving Reading Speed of Memory - A memory device includes a plurality of sense amplifiers coupled with an array of memory cells, a plurality of output data lines receiving outputs of corresponding sense amplifiers, and a plurality of precharge circuits configured to apply a precharge voltage on the output data lines. A controller provides control signals to the sense amplifiers and to the precharge circuits, including to cause the precharge circuits to precharge the output data lines before the sense amplifiers drive output data signals to the output data lines. The plurality of sense amplifiers includes banks of sense amplifiers, and each bank includes a sense amplifier having an output driving each output data line. The memory device includes data output multiplexers having inputs coupled to the output data lines, and the precharge circuits are coupled to the output data lines between outputs of the sense amplifiers and the data output multiplexers. | 09-18-2014 |
20140269126 | CIRCUIT ARRANGEMENT AND METHOD FOR OPERATING A CIRCUIT ARRANGEMENT - A circuit arrangement is provided, including a storage circuit and an output circuit. The storage circuit is configured to provide a first output signal and a second output signal. The output circuit is configured to receive the first output signal and the second output signal and configured to provide an output signal having one of a first signal level and a second signal level, and to only switch from the first signal level to the second signal level if the difference between the first output signal and the second output signal exceeds a threshold. The circuit arrangement is configured to hold the first output signal and the second output signal independent of a difference between the first output signal and the second output signal after the switching has been carried out. | 09-18-2014 |
20140269127 | Memory Operation Latency Control - An integrated circuit with memory can operate with reduced latency between consecutive operations such as read operations. At a first time, a first operation command is finished on a memory array on an integrated circuit. At a second time, a second operation command is begun on the memory array. A regulated output voltage from the charge pump is coupled to word lines in the memory array. From the first time to the second time, a regulated output voltage is maintained at about a word line operation voltage such as a read voltage. | 09-18-2014 |
20140269128 | SENSE AMPLIFIER - A sense amplifier includes a cross latch, a first pass gate, a second pass gate, a first data line, a second data line, a first circuit, and a second circuit. The cross latch has a first input/output (I/O) node and a second I/O node. The first pass gate is coupled between the first data line and the first I/O node. The second pass gate is coupled between the second data line and the second I/O node. The first circuit is coupled with the first I/O node and the second data line. The second circuit is coupled with the second I/O node and the first data line. The first circuit is configured to be turned off when the second data line has a first logical value and to be at least lightly turned on when the second data line has a voltage level between the first logical value and a second logical value different from the first logical value. The second circuit is configured to be turned off when the first data line has the first logical value and to be at least lightly turned on when the first data line has a voltage level between the first logical value and the second logical value. | 09-18-2014 |
20140286115 | NONVOLATILE RANDOM ACCESS MEMORY - According to one embodiment, a memory includes a memory cell array with banks, each bank including rows, a first word lines provided in corresponding to the rows, an address latch circuit which latches a first row address signal, a row decoder which activates one of the first word lines, and a control circuit which is configured to execute a first operation which activates one of the banks based on a bank address signal when a first command is loaded, and a second operation which latches the first row address signal in the address latch circuit, and execute a third operation which activates one of the first word lines by the row decoder based on a second row address signal and the first row address signal latched in the address latch circuit when a second command is loaded after the first command. | 09-25-2014 |
20140293721 | SENSE AMPLIFIER CIRCUIT AND SEMICONDUCTOR DEVICE - A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes. | 10-02-2014 |
20140293722 | SEMICONDUCTOR STORAGE DEVICE AND SEMICONDUCTOR STORAGE DEVICE CONTROL METHOD - When using a read circuit of a semiconductor memory device to read data in a memory cell through a bit line BLX, out of a bit line pair BL, BLX that have a complementary relationship to each other and are connected to the memory cell storing the data, control is performed by a discharge circuit disposed within the read circuit, based on the signal from the bit line BL and a signal indicating the memory cell, to prevent a rise in potential of an SOUT node of the read circuit, or to prevent a fall in potential of the SOUT node, according to the potentials of the bit line pair BL, BLX. The SOUT accordingly does not become a floating node, enabling reading malfunction due to leak current to be prevented and enabling increased reading speed. | 10-02-2014 |
20140301150 | MEMORY DEVICE AND OPERATING METHOD OF MEMORY DEVICE AND MEMORY SYSTEM - An operating method of a memory device includes entering a repair mode, receiving an active command and a fail address, and temporarily storing the received command and address, receiving a write command, and determining whether to perform a program operation, when the program operation is determined to be performed, programming the temporarily-stored fail address into a programmable storage unit, and receiving a precharge command before the programming of the temporarily-stored fail address is completed. | 10-09-2014 |
20140328134 | Sense Amplifiers, Memories, and Apparatuses and Methods for Sensing a Data State of a Memory Cell - Sense amplifiers, memories, and apparatuses and methods for sensing a data state of a memory cell are disclosed. An example apparatus includes a differential amplifier configured to amplify a voltage difference between voltages applied to first and second amplifier input nodes to provide an output. The example apparatus further includes first and second capacitances coupled to the first and second amplifier input nodes. A switch block coupled to the first and second capacitances is configured to couple during a first phase a reference input node to the first and second capacitances and to the first amplifier input node. The switch block is further configured to couple during the first phase an output of the amplifier to the second amplifier input node to establish a compensation condition. During a second phase, the switch block couples its input nodes to the first and second capacitances. | 11-06-2014 |
20140347945 | APPARATUSES INCLUDING A MEMORY ARRAY WITH SEPARATE GLOBAL READ AND WRITE LINES AND/OR SENSE AMPLIFIER REGION COLUMN SELECT LINE AND RELATED METHODS - Apparatuses and methods related to memory arrays with separate global read and write lines and/or sense amplifier region column select lines are disclosed. An example apparatus includes first and second memory sections, and further includes a sense amplifier region. A memory section includes a word line extending in a first direction and a digit line extending in a second direction, and the sense amplifier region is disposed between the first and second memory sections. The sense amplifier region includes a sense amplifier coupled to the digit line, a local input/output (LIO) line, a column select circuit coupled to the sense amplifier, and a column select line. The column select line extends in the first direction and is configured to provide a column select signal to the column select circuit. Capacitance of a LIO line may be reduced by coupling fewer sense amplifiers of a group to the LIO line. | 11-27-2014 |
20140369146 | SYSTEMS, CIRCUITS, AND METHODS FOR CHARGE SHARING - Systems, circuits, and methods are disclosed for charge sharing. In one such example system, a first line is configured to be driven to a first voltage representative of data to be placed on the first line and then precharged to a first precharge voltage. A second line is configured to be driven to a second voltage representative of data to be placed on the second line and then precharged to a second precharge voltage. A charge sharing device is coupled between the first line and the second line. The charge sharing device is configured to selectively allow charge from the first line to flow to the second line after the first and second lines are driven to the respective first and second voltages representative of data to be placed on the respective lines. | 12-18-2014 |
20150009771 | SENSE AMPLIFIER STRUCTURE FOR A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes a first signal line and a second signal line, and a sense amplifier that includes a plurality of PMOS transistors and a plurality of NMOS transistors. The sense amplifier is configured to sense amplify a potential difference between the first signal line and the second signal line. The junction regions of the NMOS and PMOS transistors having the same conductivity type, and to which the same signal is applied, are formed in one integrated active region. | 01-08-2015 |
20150023119 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM HAVING THE SAME - A semiconductor device includes a column command generation unit suitable for generating a column command delayed by a first delay time from a source command, in response to a first control signal and the source command, a bank address generation unit suitable for generating a bank address delayed by the first delay time from a bank source address, in response to the first control signal and the bank source address, a precharge command generation unit suitable for generating a precharge command delayed by a second delay time from the column command, in response to a second control signal and the column command, and a precharge bank address generation unit suitable for generating a precharge bank address delayed by the second delay time from the bank address, in response to the second control signal and the bank address. | 01-22-2015 |
20150023120 | MEMORY DEVICE AND READ OPERATION METHOD THEREOF - A read operation for a memory device is provided. A selected word line, first and second global bit line groups and a selected first bit line group are precharged. A first cell current flowing through the selected word line, the first and the selected first bit line groups is generated. A first reference current flowing through the second global bit line group is generated. A first half page data is read based on the first cell current and the first reference current. The selected word line, the first and the second global bit line groups are kept precharged. | 01-22-2015 |
20150029803 | Single-Ended Low-Swing Power-Savings Mechanism with Process Compensation - A single-ended low-swing power-savings mechanism is provided. The mechanism comprises a precharge device that turns off in an evaluation phase and a first biasing device is always on. Within the mechanism, a strength of a keeper device is changed to a first level in response to an input of the second biasing device being at a first voltage level. Within the mechanism the strength of the keeper device is changed to a second level in response to the input of the second biasing device being at a second voltage level. Responsive to receiving a (precharged voltage level read data line signal, a precharged voltage level of the first node falls faster when the keeper device is weakened to a first level. The keeper device turns on in response to receiving a LOW signal and pulls up the voltage at the first node so that a HIGH signal is output. | 01-29-2015 |
20150063046 | MEMORY TIMING CIRCUIT - Disclosed are various apparatuses and methods for a memory with a multiple word line design. A memory timing circuit may include a dummy word line including a first portion and a second portion and further including capacitative loading that is lumped in the second portion of the dummy word line, a first transistor connected to the first portion of the dummy word line and configured to charge the dummy word line, and a second transistor connected to the second portion of the dummy word line and configured to discharge the dummy word line. A method may include charging a dummy word line using a first transistor, and discharging the dummy word line using a second transistor, wherein the dummy word line includes a first portion and a second portion and further includes capacitative loading that is lumped in the second portion of the dummy word line. | 03-05-2015 |
20150063047 | SEMICONDUCTOR MEMORY DEVICE, METHOD OF OPERATING THE SAME AND MEMORY SYSTEM INCLUDING THE SAME - A semiconductor memory device according to an embodiment of the present invention includes a memory block, a driving circuit performing a program operation on memory cells and a voltage detector generating a detection signal when an external power supply voltage is reduced to less than a reference voltage level. The driving circuit discharges a voltage applied to a drain selection line during the program operation in response to the detection signal. | 03-05-2015 |
20150085592 | Bit-Line Discharge Assistance in Memory Devices - One embodiment is an apparatus that has a memory array, a discharge device, and a discharge assistance controller. The memory array has memory cells arranged in at least one column that is coupled to a read bit line, and the discharge device is configured to provide discharge assistance to the read bit line. The discharge assistance controller is configured to modify duration of the discharge assistance in correlation with capacitance of the read bit line. | 03-26-2015 |
20150092507 | Memory having a voltage switch circuit with one bias voltage changed in each state of conditioning - A voltage switch circuit includes four transistors. The four transistors may be transistors used to build logic gates. The operation of the voltage switch circuit may include precharging the output terminal of the voltage switch circuit, conditioning of the voltage switch circuit and boosting the voltage of the output terminal. | 04-02-2015 |
20150131394 | METHOD AND APPARATUS FOR READ ASSIST TO COMPENSATE FOR WEAK BIT - A memory assist apparatus includes a detection circuit and a compensation circuit. The detection circuit is configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold. The compensation circuit is configured to pull down the voltage of the bit line if the detection signal indicates that the voltage of the bit line is below the predetermined threshold. | 05-14-2015 |
20150138904 | MEMORY CIRCUIT AND METHOD OF OPERATING THE MEMORY CIRCUIT - A memory circuit includes a memory cell, a data line configured to be coupled with the memory cell, a node, a precharge circuit, a first transistor of a first type, and a second transistor of the first type. The precharge circuit is configured to charge the node toward a predetermined voltage level. The first transistor of the first type has a drain coupled with the node and a source coupled with the data line, and the first transistor has a first threshold voltage. The second transistor of the first type has a drain coupled with the node and a source coupled with the data line, and the second transistor having a second threshold voltage different from the first threshold voltage. | 05-21-2015 |
20150302914 | SEMICONDUCTOR DEVICE - A semiconductor device is equipped with memory cells which are provided at the intersections of word lines and local bit lines, hierarchical switches which are respectively connected between the local bit lines and a global bit line, and a hierarchical sense amplifier which amplifies a potential difference generated between signal nodes, with the signal nodes being respectively connected to the local bit lines. According to the present invention, because the hierarchical sense amplifier is a differential type circuit, a stable sensing operation can be performed. In addition, because one hierarchical sense amplifier can be assigned to multiple local bit lines, the number of hierarchical sense amplifiers can be reduced. | 10-22-2015 |
20150357013 | TRACKING SCHEME FOR FLOATING BITLINE PRECHARGE - A memory and a method for operating the memory are provided. The memory includes a bitline and at least one memory cell coupled to the bitline. A bitline precharge circuit is configured to precharge the bitline for a memory access and to deactivate to float the bitline in a standby state. A reference circuit is configured to charge a load circuit to a voltage in the standby state. In one example, the load circuit includes a dummy bitline having a substantially same or greater electrical characteristic of the bitline. The reference circuit includes a dummy bitline precharge circuit configured to charge the dummy bitline to the voltage in the standby state. | 12-10-2015 |
20150364164 | PRECHARGE CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME - A semiconductor apparatus includes a memory region configured to store data transmitted through a first data line and a second data line; and a precharge block configured to precharge the second data line to a level of a first voltage and precharge the first data line to a level of a second voltage higher than the level of the first voltage, based on a write signal. | 12-17-2015 |
20150364165 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a first memory bank configured to store data transmitted through a first data line; and a precharge block configured to precharge the first data line to a level of a first voltage or a second voltage. | 12-17-2015 |
20150364167 | INTEGRATED CIRCUIT AND PRECHARGE/ACTIVE FLAG GENERATION CIRCUIT - An integrated circuit includes a first stage including first logic gates each of which performs a first logic operation on a corresponding signal among first to N | 12-17-2015 |
20160071556 | APPARATUSES INCLUDING A MEMORY ARRAY WITH SEPARATE GLOBAL READ AND WRITE LINES AND/OR SENSE AMPLIFIER REGION COLUMN SELECT LINE AND RELATED METHODS - Apparatuses and methods related to memory arrays with separate global read and write lines and/or sense amplifier region column select lines are disclosed. An example apparatus includes first and second memory sections, and further includes a sense amplifier region. A memory section includes a word line extending in a first direction and a digit line extending in a second direction, and the sense amplifier region is disposed between the first and second memory sections. The sense amplifier region includes a sense amplifier coupled to the digit line, a local input/output (LIO) line, a column select circuit coupled to the sense amplifier, and a column select line. The column select line extends in the first direction and is configured to provide a column select signal to the column select circuit. Capacitance of a LIO line may be reduced by coupling fewer sense amplifiers of a group to the LIO line. | 03-10-2016 |
20160078920 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor device including a plurality of first diffusion layers that are formed over a semiconductor layer and disposed at predetermined intervals in a first direction, a plurality of second diffusion layers that are formed over the semiconductor layer, isolated from the first diffusion layers in a second direction orthogonal to the first direction, and disposed at the predetermined intervals in the first direction, a plurality of first regions that have a predetermined width in the first direction for separating the first diffusion layers from each other, a plurality of second regions that align with the first regions in the second direction and have the predetermined width for separating the second diffusion layers from each other, and a plurality of contacts that are formed over the first diffusion layers and over the second diffusion layers. | 03-17-2016 |
20160104518 | Memory Device With Timing Overlap Mode - In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes. | 04-14-2016 |
20160118104 | VOLATILE MEMORY SELF-DEFRESH - Embodiments of the inventive concept include a volatile memory device including a memory cell array, the memory cell array including multiple rows and/or banks to store data. The memory device can include an address decoder coupled to the memory cell array. The memory device can include a control logic section coupled to the address decoder. The control logic section can include a defresh logic section configured to intentionally violate, by an activate command, a row precharge time (T | 04-28-2016 |
20160155490 | MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE MEMORY DEVICE | 06-02-2016 |
20160180903 | MEMORY OPERATION LATENCY CONTROL | 06-23-2016 |
20160180917 | Techniques to Reduce Memory Cell Refreshes for a Memory Device | 06-23-2016 |
20160254044 | PRECHARGING AND REFRESHING BANKS IN MEMORY DEVICE WITH BANK GROUP ARCHITECTURE | 09-01-2016 |
20170236560 | SEMICONDUCTOR DEVICE WITH SINGLE ENDED MAIN I/O LINE | 08-17-2017 |
20180025773 | PRECHARGING AND REFRESHING BANKS IN MEMORY DEVICE WITH BANK GROUP ARCHITECTURE | 01-25-2018 |
20190147924 | INTRACYCLE BITLINE RESTORE IN HIGH PERFORMANCE MEMORY | 05-16-2019 |
20190147925 | MEMORY CIRCUITS PRECHARGING MEMORY CELL ARRAYS AND MEMORY DEVICES INCLUDING THE SAME | 05-16-2019 |
20190147944 | STATIC RANDOM-ACCESS MEMORY WITH VIRTUAL BANKING ARCHITECTURE, AND SYSTEM AND METHOD INCLUDING THE SAME | 05-16-2019 |