Class / Patent application number | Description | Number of patent applications / Date published |
365198000 | Transmission | 22 |
20080219068 | ZQ CALIBRATION CONTROLLER AND METHOD FOR ZQ CALIBRATION - A ZQ calibration circuit performs a ZQ calibration additionally in an initial operation of a semiconductor memory device. The ZQ calibration controller of the ZQ calibration circuit includes a first signal generator, a second signal generator, and a control unit. The first signal generator generates a pre-calibration signal during an initialization of the semiconductor memory device. The second signal generator generates ZQ calibration signals in response to a ZQ calibration command. The control unit outputs signals to control a ZQ calibration in response to the pre-calibration signal and the ZQ calibration signals. | 09-11-2008 |
20090116316 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE - Semiconductor device and semiconductor memory device include a plurality of internal circuits configured to perform test operations in response to their respective test mode signals and a plurality of test-off units configured to control the test operations of the internal circuits to be disabled in response to a test-off signal. | 05-07-2009 |
20090190421 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY SYSTEM FOR COMPENSATING CROSSTALK - A semiconductor memory device and a semiconductor memory system. The semiconductor memory device includes channels configured to transmit signals from a transmitter to a receiver, and a crosstalk compensator. The crosstalk compensator may be connected between the channels to compensate for crosstalk. The crosstalk compensator may comprise a capacitor connected in parallel between the channels, and a switching unit connected between the capacitor and one of the channels. The switching unit may control connections or disconnections between the capacitor and the channel. Therefore, the semiconductor memory device and the semiconductor memory system compensate for crosstalk occurring between transmitted signals that are out of phase with each other. | 07-30-2009 |
20090273995 | APPARATUS FOR REMOVING CROSSTALK IN SEMICONDUCTOR MEMORY DEVICE - An apparatus for removing crosstalk in a semiconductor memory device includes pads for receiving externally provided signals, transmission lines for delivering the signals received by each of the pads to corresponding elements in the apparatus, and capacitors, coupled between adjacent ones of the lines, for adjusting the transmission delay of the signals depending on a signal transmission mode between the adjacent lines. | 11-05-2009 |
20100142297 | DATA DRIVER - A data driver is presented in which the data driver includes a termination/pull-up driver and a pull-down driver. The termination/pull-up driver is configured to perform a termination operation and a pull-up operation at the same time for a data output terminal during an active interval of a semiconductor memory. The pull-down driver is configured to be activated when the semiconductor memory performs a read operation, and configured to pull down the output terminal in response to a level of an input data. | 06-10-2010 |
20100202227 | REFERENCE VOLTAGE AND IMPEDANCE CALIBRATION IN A MULTI-MODE INTERFACE - A memory controller includes a transmit circuit coupled to an output node and a receive circuit coupled to an input node. The transmit circuit transmits first data to a memory device through the output node and the receive circuit is configured to receive second data from the memory device through the input node. The memory controller includes a calibration circuit and control logic coupled to the calibration circuit, where the calibration circuit and the control logic are configured to select a first reference voltage and a driver impedance for the transmit circuit and are configured to select a second reference voltage and a termination impedance for the receive circuit. The first reference voltage, the second reference voltage, the driver impedance and the termination impedance are selected from a set of pre-determined values, which are associated with different signaling modes for communication of the first data and the second data. | 08-12-2010 |
20100220537 | ACTIVE TERMINATION CIRCUIT AND METHOD FOR CONTROLLING THE IMPEDANCE OF EXTERNAL INTEGRATED CIRCUIT TERMINALS - An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively. | 09-02-2010 |
20100246296 | Write Driver and Semiconductor Memory Device Using the Same - A semiconductor memory device includes a first memory bank and a second memory bank and a common write driver configured to drive write data to an activated memory bank of the first memory bank and the second memory bank. The common write driver of the semiconductor memory device includes a common write control block configured to generate common drive control signals corresponding to write data, and a common write drive block configured to drive transmission lines of a first memory bank or transmission lines of a second memory bank that are selected by a bank selection signal in response to the common drive control signals. | 09-30-2010 |
20100277994 | Semiconductor Memory Device and Operating Method Thereof - A semiconductor memory device and an operating method thereof prevent the mal-operation of the semiconductor memory device induced by misrecognizing addresses or data as commands. The semiconductor memory device includes a plurality of input pads, a data information path, a command path, a transfer block configured to transmit signals coupled through the input pads to the data information path and the command path, a command decoding block configured to decode signals transmitted through the command path to verify an inputting of a command, and a transmission control block configured to generate a control signal for controlling the signal transmission from the transfer block to the command path according to the verified result of the command decoding block. | 11-04-2010 |
20100302886 | MAT COMPRESS CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME - A mat compress circuit includes a pre-control signal generator that generates a first pre-control signal and a second pre-control signal alternatively activated in response to an up/down bank selection address in a mat compression test, and a control signal transmitter that inverts and transfers the first and second pre-control signals in response to a switching signal activated when there is an input of a block selection address in the mat compression test. | 12-02-2010 |
20110116331 | METHOD FOR INITIALIZING MEMORY DEVICE - A method for initializing a memory device is provided. The method includes a step for transmitting at least N+1 clock cycles to the memory device, wherein the N is an amount of bits of output serial data of the memory device. During a clock cycle of the at least N+1 clock cycles, a first start/stop signal is transmitted to the memory device. During another clock cycle of the at least N+1 clock cycles, a second start/stop signal is transmitted to the memory device. | 05-19-2011 |
20110216613 | LOW POWER TERMINATION FOR MEMORY MODULES - An apparatus is provided that includes a memory controller to provide a first on-die termination (ODT) signal and a second ODT signal, a memory channel, a first memory module to couple to the memory channel, and a second memory module to couple to the memory channel. The first memory module may include a first memory having a first ODT circuit to receive the first ODT signal, and a second memory having a second ODT circuit to receive the first ODT signal. The first ODT signal may disable the ODT circuit of the first memory when the first memory is to be ACTIVE. | 09-08-2011 |
20110242916 | ON-DIE TERMINATION CIRCUIT, DATA OUTPUT BUFFER AND SEMICONDUCTOR MEMORY DEVICE - An on-die termination circuit includes a termination resistor unit connected to an external pin, and a termination control unit connected to the termination resistor unit. The termination resistor unit provides termination impedance to a transmission line connected to the external pin. The termination control unit varies the termination impedance in response to a plurality of bits of strength code associated with a data rate. | 10-06-2011 |
20110305097 | Semiconductor device and data processing system - A semiconductor device comprises transmission lines, inverting circuits, first, second and third switches, global sense amplifiers, and a control circuit. The first switch switches between the transmission line and the input of the inverting circuit, the second switch switches between the transmission line and the output of the transmission line, and the third switch switches between the adjacent transmission lines. The control circuit turns off the first and second switches so that the transmission lines are brought into a floating state in a state where signals of the transmission lines are held in the inverting circuits by the global sense amplifiers. After charge sharing of the transmission lines occurs by turning on the third switches within a predetermined period, the control circuit turns off the second switches so that the transmission lines are inverted and driven via the inverting circuits and the second switches. | 12-15-2011 |
20120250436 | IMPEDANCE MATCHING BETWEEN FPGA AND MEMORY MODULES - Embodiments of the present invention provide impedance matching between a Field Programmable Gate Array (FPGA) and memory modules in a semiconductor storage device (SSD) system architecture. Specifically, a set (at least one) of memory modules is coupled to an FPGA. A damping resistor is placed at the impedance mismatching point to reduce signal noise. | 10-04-2012 |
20130242680 | MEMORY MODULES - A memory module includes a command/address (CA) register, memory devices, and a module resistor unit mounted on a circuit board. The centrally disposed CA register drive the memory devices one or more internal CA signal(s) to arrangements of memory devices using multiple CA transmission lines, wherein the multiple internal CA transmission lines are commonly terminated in the module resistor unit. | 09-19-2013 |
20140140152 | SEMICONDUCTOR STORAGE DEVICE AND CONTROL METHOD THEREOF - According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips is configured to connect to a signal transmission path and is controlled individually by individual chip enable signals. The plurality of semiconductor chips each includes a termination circuit connected to the signal transmission path. When one of the semiconductor chips is selected to input or output data, the control unit activates the termination circuit provided in the semiconductor chip that is not selected based on a first instruction signal and the chip enable signal. | 05-22-2014 |
20140169112 | SEMICONDUCTOR MEMORY SYSTEM AND OPERATING METHOD THEREOF - A semiconductor memory system configured to exchange signals through channels may include a memory control device configured to have a plurality of channels, a plurality of memory devices configured to be connected to each of the plurality of channels, wherein the plurality of channels share at least one of the plurality of memory devices. | 06-19-2014 |
20140204692 | SEMICONDUCTOR MEMORY DEVICE AND METHOD WITH AUXILIARY I/O LINE ASSIST CIRCUIT AND FUNCTIONALITY - A semiconductor memory device includes an I/O line for transmitting read data that has been read from a memory cell, a plurality of driver circuits for driving the I/O line on the basis of the read data, a read circuit for receiving the read data transmitted through the I/O line, and an assist circuit for amplifying the read data transmitted through the I/O line. The assist circuit is disposed farther away from a prescribed drive circuit included in the plurality of drive circuits as viewed from the read circuit. The signal level can thereby rapidly change levels even in memories having relatively long I/O lines. | 07-24-2014 |
20150098285 | ON-DIE TERMINATION APPARATUSES AND METHODS - Apparatuses and methods are disclosed herein, including those, performed by a memory die, that operate to detect that a command on a bus connected to the memory die is addressed to another memory die responsive to a chip select signal, and to change the impedance of an on-die termination circuit of the memory die responsive to the detecting. | 04-09-2015 |
20150103609 | SEMICONDUCTOR DEVICES - A semiconductor device including a control signal generator and an internal refresh signal generator is provided. The control signal generator generates first and second control signals, one of which is selectively enabled in response to temperature code signals and mode set signals after a pulse of an internal refresh signal is outputted by the internal refresh signal generator. The temperature code signals are obtained from temperature signals. The internal refresh signal generator outputs a refresh command signal as the internal refresh signal when the first control signal is enabled. Further, the internal refresh signal generator outputs the refresh command signal as the internal refresh signal at a moment that the refresh command signal is inputted thereto by a predetermined number of times when the second control signal is enabled. | 04-16-2015 |
20150124541 | MEMORY CARD AND SD CARD - According to one embodiment, there are provided a memory which is provided on a circuit board, a controller which is provided on the circuit board and controls the memory, and a signal line which is formed on the circuit board and configured to perform data transmission between the controller and the memory, in which a width of the signal line in the place where the signal line is led out from the memory is large compared with a place disposed under the memory. | 05-07-2015 |