Entries |
Document | Title | Date |
20080198642 | SEMICONDUCTOR MEMORY DEVICE - A memory cell includes an antifuse device that is capable of having data written thereto by breakdown of a gate dielectric film by application of a high voltage. A data inversion portion generates, according to a relationship between the sense amplifier's determination and write data to be written to the memory cell, inverted write data obtained by inverting the write data. The data inversion portion also inverts, when data is read from the memory cell to which the inverted write data is written, the read data and reads it. | 08-21-2008 |
20080198643 | One-time programmable cell and memory device having the same - One-time programmable cell and memory device having the same includes a first metal oxide semiconductor (MOS) transistor configured to form a current path between a first node and a second node in response to a read-control signal, a second MOS transistor configured to form a current path between a third node and the second node in response to a write-control signal and an anti-fuse connected between the second node and a ground voltage terminal, wherein a voltage applied to the second node is output as an output signal. | 08-21-2008 |
20080225566 | Using eFuses to Store PLL Configuration Data - A mechanism for using electrical fuses (eFuses) to store phase-locked loop (PLL) configuration data are provided. With the mechanism, a portion of the eFuses present in the integrated circuit are reserved for the PLL configuration data. Upon power up, a power up controller and eFuse controller direct the sensing and serial transfer of the data in the portion of eFuses to the PLL under the reference clock. When the transfer is complete, the power up controller directs the PLL logic to load the configuration data and start. The mechanism of the present invention allows manufacturing to tailor the PLL configuration on a given device based on the characteristics of that device and its intended usage. Thus, the same PLL may be used in the same or different architectures to perform different operations based on the configuration data passed into the PLL from the eFuses. | 09-18-2008 |
20080232150 | Method and Structure for Implementing a Reprogrammable ROM - A method and structure implementing a reprogrammable read only memory (ROM) include a pair of fuse elements having different lengths and selectively arranged to define an initial bit state. A group of a plurality of the pairs of fuse elements defines a predetermined data pattern of ones and zeros, providing initial states stored in the reprogrammable ROM. The reprogrammable ROM is reprogrammed when needed by selectively blowing a selected fuse or selected fuses to change the data pattern stored in the ROM. | 09-25-2008 |
20080232151 | System and method to control one time programmable memory - Systems and methods to control one time programmable (OTP) memory are disclosed. A method may include determining a functionality for a hardware capability bus in an integrated circuit. The method may also include storing data in a first register of the integrated circuit based on the functionality. The method may also include disabling the functionality in the integrated circuit by setting at least one bit in a one time programmable memory bank in the integrated circuit based on the data. | 09-25-2008 |
20080232152 | Method and Structure for Implementing a Reprogrammable ROM - A method and structure for implementing a reprogrammable read only memory (ROM), and a design structure on which the subject circuit resides are provided. A pair of fuse elements having different lengths are selectively arranged to define an initial bit state. A group of a plurality of the pairs of fuse elements defines a predetermined data pattern of ones and zeros, providing initial states stored in the reprogrammable ROM. The reprogrammable ROM is reprogrammed when needed by selectively blowing a selected fuse or selected fuses to change the data pattern stored in the ROM. | 09-25-2008 |
20080298112 | Memory array including programmable poly fuses - According to one exemplary embodiment, a memory array includes a memory cell having a programmable poly fuse coupled between a designated program node and a ground node, where the programmable poly fuse includes a P type resistive poly segment forming a P-N junction with an adjacent N type resistive poly segment. In the programmable poly fuse, the P type resistive poly segment is coupled to the ground node and the N type resistive poly segment is coupled to the designated program node. The programmable poly fuse further includes a P side silicided poly line contiguous with the P type resistive poly segment and coupled to the ground node. The programmable poly fuse further includes an N side silicided poly line contiguous with the N type resistive poly segment and coupled to the designated program node. | 12-04-2008 |
20080316789 | Random Access Electrically Programmable E-Fuse Rom - A one-time-programmable-read-only-memory (OTPROM) is implemented in a two-dimensional array of aggressively scaled suicide migratable e-fuses. Word line selection is performed by decoding logic operating at V | 12-25-2008 |
20090003028 | Carbon nanotube fuse element - In one embodiment of the invention, a fuse element for a one time programmable memory may include carbon nanotubes coupled to a first transistor node and to a second transistor node. The carbon nanotubes may have a first resistance which may be changed upon programming the memory cell with low current levels. | 01-01-2009 |
20090040804 | FUSE CIRCUIT - A fuse circuit in accordance with one embodiment of the present invention includes a first power supply liner a second power supply liner a current source connected between the first power supply line and an output terminal, a first transistor having a drain or a collector connected to the output terminal, the first transistor having a current supply capability or a current draw capability larger than that of the current source for the output terminal, a second transistor having a gate or a base connected in common with the gate or the base of the first transistor, a first resistive element and a fuse connected in series between the source or the emitter of either one of the first or second transistor and the second power supply line, and a second resistive element connected between the source or the emitter of the other one of the first or second transistor and the second power supply line. | 02-12-2009 |
20090052220 | ONE-TIME PROGRAMMABLE NON-VOLATILE MEMORY - An apparatus includes a semiconductor substrate, elongated diffused well regions, and elongated conductors. The semiconductor substrate has a first electrical conductivity type. The elongated diffused well regions are in the semiconductor substrate. The diffused well regions have a second electrical conductivity type opposite the first electrical conductivity type. Each of the elongated electrical conductors crosses the diffused well regions at respective locations of one-time programmable memory cells. Each of the memory cells includes a antifuse structure between the respective diffused well region and the respective electrical conductor. Each of the memory cells has a first state in which the antifuse structure has a first electrical resistance and a second state in which the antifuse structure has a second electrical resistance lower than the first electrical resistance. In the second state, each of the memory cells includes a rectifying junction between the respective diffused well region and the respective electrical conductor. | 02-26-2009 |
20090052221 | SEMICONDUCTOR DEVICE INCLUDING ANTIFUSE ELEMENT - An element isolation region exists at a side opposite to a diffusion layer region as seen from a channel region, without another electrode to which the same potential as one applied to the diffusion layer region is applied interposed between the channel region and the element isolation region. The electric field applied to the gate insulating film is not uniform and the magnitude of the electric field is increased when approaching closer to the diffusion layer region. Therefore, breakdown is likely to occur at parts closer to the diffusion layer region. | 02-26-2009 |
20090059645 | One time programmable memory - A one-time programmable memory. The one-time programmable memory has an antifuse and a read circuit configured to read the antifuse. An isolation transistor couples the antifuse to the read circuit. The read circuit and the isolation transistor have different power domains. | 03-05-2009 |
20090067211 | Electronic Fuse System and Methods - An electronic fuse system and method are disclosed employing a fuse ROM having one or more blocks of memory. Each block of memory comprises a plurality of words with at least one word of the plurality of words containing security bits associated with a respective block. An electronic fuse controller is in communication with the fuse ROM and one or more external devices that are configured to request one or more words that reside in the fuse ROM from the electronic fuse controller. At least one security register includes indication bits that provide an indication whether security bits have been obtained for a respective block of memory of the fuse ROM after a power down and power up cycle. The electronic fuse controller provides the requested word if an indication bit associated with the block of memory is set. | 03-12-2009 |
20090080232 | AREA EFFICIENT PROGRAMMABLE READ ONLY MEMORY (PROM) ARRAY - A programmable ROM (PROM) architecture includes cascode NMOS transistors with a fuse bit cell that is arrayed, with sleep transistors located in each column of the array that in a standby mode shut down the entire fuse array. A fuse redundancy scheme may be used to repair a defective fuse row. | 03-26-2009 |
20090086526 | APPARATUS, EMBEDDED MEMORY, ADDRESS DECODER, METHOD OF READING OUT DATA AND METHOD OF CONFIGURING A MEMORY - Embodiments of the invention relate generally to an apparatus, to an embedded memory, to an address decoder, to a method of reading out data and to a method of configuring a memory. In an embodiment of the invention an apparatus is provided. The apparatus may include a plurality of read-only memory (ROM) cells and an address decoder to access a ROM cell of the plurality of ROM cells, the address decoder further being fuse-programmable to divert an access to the ROM cell to a different memory cell. | 04-02-2009 |
20090109722 | REPROGRAMMABLE ELECTRICAL FUSE - The present invention provides a reprogrammable electrically blowable fuse and associated design structure. The electrically blowable fuse is programmed using an electro-migration effect and is reprogrammed using a reverse electro-migration effect. The state (i.e., “opened” or “closed”) of the electrically blowable fuse is determined by a sensing system which compares a resistance of the electrically blowable fuse to a reference resistance. | 04-30-2009 |
20090109723 | Quad SRAM Based One Time Programmable Memory - A quad SRAM based one time programmable memory cell is provided. Prior to programming, the memory cell operates as an SRAM memory cell. After programming, the memory cell operates as a one-time programmable non-volatile memory cell. The memory cell includes a storage element coupled at a first side to a first upper fuse and a first lower fuse and coupled at a second side to a second upper fuse and a second lower fuse. When the first upper fuse and second lower fuse are programmed, the storage element outputs a first value. When the second upper fuse and first lower fuse are programmed, the storage element outputs a second value. After programming the upper fuse acts as a pull-up fuse and the lower fuse acts as a pull-down fuse hold the state of the cell. | 04-30-2009 |
20090109724 | Differential Latch-Based One Time Programmable Memory - A differential latch-based one time programmable memory cell is provided. The differential latch-based one time programmable memory cell includes a differential latching amplifier having a first set of fuse devices coupled to the first input and a second set of fuse devices coupled to the second input. Only one set of fuse devices can be programmed in a memory cell. If one or more fuse devices in a set of fuse devices are programmed, the side having the programmed fuse will present a lower voltage at its input to the differential latching amplifier. Differential latching amplifier outputs a “0” or a “1” depending on the side having the programmed fuse. | 04-30-2009 |
20090109725 | Data storage in circuit elements with changed resistance - A method of storing data in an array of circuit elements, said method comprising injecting a current into selected circuit elements, said current causing a persistent change in a resistance of said selected circuit elements from a first resistance to a second higher resistance indicative of a binary data bit, wherein said current does not break an electrical circuit in which said circuit element is disposed. | 04-30-2009 |
20090116274 | DIODE-LESS ARRAY FOR ONE-TIME PROGRAMMABLE MEMORY - A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor. | 05-07-2009 |
20090122589 | ELECTRICAL FUSE SELF TEST AND REPAIR - A circuit for testing and repairing a fuse device having a plurality of fuse units and being able to serially input and output data is disclosed, the circuit comprises a first multiplexer configured to select either a true or an inverted data for being stored in the fuse device, a second multiplexer configured to select either a true or an inverted data being read out from the fuse device, a storage unit configured to store information of faulty fuse units, and an indication bit being programmed to reflect a comparison between the data intended to be stored in the fuse device and the stored faulty unit information, wherein when the indication bit is at a first state, the first and second multiplexers select the true data, and when the indication bit is at a second state, the first and second multiplexers select the inverted data. | 05-14-2009 |
20090135640 | ELECTROMIGRATION-PROGRAMMABLE SEMICONDUCTOR DEVICE WITH BIDIRECTIONAL RESISTANCE CHANGE - An electromigration-programmable semiconductor device may be programmed to increase the resistance or to decrease the resistance by selecting the amount of current passed through the electromigration-programmable semiconductor device. The electromigration-programmable semiconductor device comprises an anode, a cathode, and a link, each having a semiconductor portion and a metal semiconductor alloy portion. The metal semiconductor alloy portion of the link comprises two disjoined sub-portions with a gap therebetween. A low programming current fills the gap by electromigrating a small amount of metal semiconductor alloy from the cathode, A high programming current forms a large metal-semiconductor-alloy-deleted area in the cathode to increase the resistance. A tri-state programming is achieved by selecting the programming current level. | 05-28-2009 |
20090141533 | METAL GATE COMPATIBLE ELECTRICAL ANTIFUSE - A metal layer and a semiconductor layer are sequentially deposited on a substrate. The semiconductor layer and the metal layer are lithographically patterned to form a stack of a semiconductor portion and a metal gate portion, which is preferably performed concurrently with formation of at least one metal gate stack. In one embodiment, the size of the semiconductor portion is reduced and a metal semiconductor alloy portion is formed on the semiconductor portion by metallization. In a first electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the metal semiconductor alloy portion and the metal gate portion. In another embodiment, two disjoined metal semiconductor alloy portions are formed on the semiconductor portion. In a second electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the two previously disjoined metal semiconductor alloy portions. | 06-04-2009 |
20090141534 | DETECTION APPARATUS AND METHOD FOR SEQUENTIALLY PROGRAMMING MEMORY - A detection apparatus for sequentially programming a memory is provided. The detection apparatus comprises a current sensor and a programming controller. The current sensor is coupled to a programming source and a memory cell. The current sensor detects change of a programming current between the programming source and the memory cell and generates a control signal according to the detection result. The programming controller is coupled to the current sensor. The programming controller receives the control signal and generates a programming state signal. | 06-04-2009 |
20090141535 | METHODS INVOLVING MEMORY WITH HIGH DIELECTRIC CONSTANT ANTIFUSES ADAPTED FOR USE AT LOW VOLTAGE - Methods involve using a memory array having memory cells comprising a diode and an antifuse, in which the antifuse is made smaller and programmed at lower voltage by using an antifuse material having a higher dielectric constant and a higher acceleration factor than those of silicon dioxide, and in which the diode is made of a material having a lower band gap than that of silicon. Such memory arrays can be made to have long operating lifetimes by using the high acceleration factor and lower band gap materials. Antifuse materials having dielectric constants between 5 and 27, for example, hafnium silicon oxynitride or hafnium silicon oxide, are particularly effective. Diode materials with band gaps lower than that of silicon, such as germanium or a silicon-germanium alloy, are particularly effective. | 06-04-2009 |
20090154217 | HIGH SPEED OTP SENSING SCHEME - A high speed sensing scheme for a non-volatile memory array is disclosed. The memory array includes non volatile memory cells arranged in a complementary bitline configuration includes precharge circuits for precharging the bitlines to a first voltage level such as VSS, a reference circuits for applying a reference charge on the reference bitlines of the complementary bitline pairs, and bitline sense amplifiers for sensing a voltage differential between the complementary bitline pairs. A voltage on the data bitline being changed when a programmed non-volatile memory cell connected to an activated wordline couples the wordline voltage to the data bitline. | 06-18-2009 |
20090201713 | Unit cell of nonvolatile memory device and nonvolatile memory device having the same - A One-Time Programmable (OTP) unit cell and a nonvolatile memory device having the same are disclosed. A unit cell of a nonvolatile memory device includes: an anti-fuse connected between an output terminal and a ground voltage terminal; a first switching unit connected to the output terminal to transfer a write voltage to the output terminal; and a second switching unit connected to the output terminal to transfer a read voltage to the output terminal. | 08-13-2009 |
20090219747 | METHOD OF PROGRAMMING A MEMORY HAVING ELECTRICALLY PROGRAMMABLE FUSES - An array of memory cells is arranged in a plurality of columns and rows, each of the memory cells comprising a programmable fuse connected to a predetermined bit line and in series with a select transistor. The select transistor has a first current electrode connected to a reference voltage terminal, a control electrode connected to a predetermined word line, and a second current electrode connected to the programmable fuse. The select transistor further has a semiconductor body adjacent to which the first current electrode and the second current electrode are located. These electrodes are separated by a channel. A signal terminal that is connected to the semiconductor body receives an input signal to forward bias the channel to the first current electrode during programming of the programmable fuse to increase a programming current of the programmable fuse. | 09-03-2009 |
20090231900 | Fuse devices and methods of operating the same - A fuse device includes a fuse unit, which includes a cathode, an anode, and a fuse link coupling the cathode and the anode. A transistor includes at least a portion of the fuse unit to be used as an element of the transistor. | 09-17-2009 |
20090231901 | SEMICONDUCTOR INTEGRATED CIRCUIT FOR SUPPORTING A TEST MODE - A semiconductor integrated circuit for supporting a test mode includes a program region including at least one One Time Programmable Cell Array, and a program region control unit configured to activate the program region in response to an enabled fuse signal of a fuse corresponding to the program region, and to activate the program region in response to a test mode signal of the program region. | 09-17-2009 |
20090237974 | Programmable memory cell - A disclosed embodiment is a programmable memory cell comprising an elevated ground node having a voltage greater than a common ground node by an amount substantially equal to a voltage drop across a trigger point adjustment element. In one embodiment, the trigger point adjustment element can be a diode. The trigger voltage of the programmable memory cell is raised closer to a supply voltage when current passes through the trigger point adjustment element during a write operation. The programmable memory cell can comprise a pair of cross-coupled inverters, and first and second programmable antifuses that can be coupled to each inverter in the pair of cross-coupled inverters. Since the trigger voltage of the programmable memory cell is raised closer to the supply voltage, a programmed antifuse can easily reach below the trigger voltage and result in a successful write operation even when the supply voltage is a low voltage. | 09-24-2009 |
20090237975 | One-time programmable memory cell - A disclosed embodiment is a programmable memory cell having improved IV characteristics comprising a thick oxide spacer transistor interposed between a programmable thin oxide antifuse and a thick oxide access transistor. The spacer transistor separates a rupture site formed during programming the programmable antifuse from the access transistor, so as to result in the improved IV characteristics. The programmable antifuse is proximate to one side of the spacer transistor, while the access transistor is proximate to an opposite side of the spacer transistor. The source region of the access transistor is coupled to ground, and the drain region of the access transistor also serves as the source region of the spacer transistor. The access transistor is coupled to a row line, while the spacer transistor and the programmable antifuse are coupled to a column line. The rupture site is formed during programming by applying a programming voltage to the programmable antifuse. | 09-24-2009 |
20090251943 | TEST CIRCUIT FOR AN UNPROGRAMMED OTP MEMORY ARRAY - Circuits for testing unprogrammed OTP memories to ensure that wordline and bitline connections, column decoders, wordline drivers, correctness of decoding, sensing and multiplexing operate properly. The OTP testing system includes one or both of column test circuitry and row test circuitry. The column test circuitry charges all the bitlines to a voltage level similar to that provided by a programmed OTP memory cell during a read operation, in response to activation of a test wordline. The bitline voltages can be sensed, thereby allowing for testing of the column decoding and sense amplifier circuits. The row test circuitry charges a test bitline to a voltage level similar to that provided by a programmed OTP memory cell during a read operation, in response to activation of a wordline of the OTP memory array. This test bitline voltage can be sensed, thereby allowing for testing of the row decoding and driver circuits. | 10-08-2009 |
20090262566 | MASK PROGRAMMABLE ANTI-FUSE ARCHITECTURE - A memory array having both mask programmable and one-time programmable memory cells connected to the wordlines and the bitlines. All memory cells of the memory array are configured as one-time programmable memory cells. Any number of these one-time programmable memory cells are convertible into mask programmable memory cells through mask programming, such as diffusion mask programming or contact/via mask programming. Manufacturing of such a hybrid memory array is simplified because both types of memory cells are constructed of the same materials, therefore only one common set of manufacturing process steps is required. Inadvertent user programming of the mask programmable memory cells is inhibited by a programming lock circuit. | 10-22-2009 |
20090262567 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device including one-time programmable (OTP) unit cell is provided. The nonvolatile memory device includes: a unit cell; a detecting unit configured to detect data from the unit cell; and a read voltage varying unit configured to vary an input voltage and supply a varied read voltage to the unit cell. | 10-22-2009 |
20090316466 | METHOD, APPARATUS AND SYSTEM, PROVIDING A ONE-TIME PROGRAMMABLE MEMORY DEVICE - Disclosed are apparatus, system and methods of programming and readout of a one-time programmable memory devise having an array of memory cells, where the cells include an anti-fuse element and an in-cell amplifier transistor. Circuitry configured for programming and correlated double sampling readout of the cells is also disclosed. | 12-24-2009 |
20090323388 | Buried Bit Line Anti-Fuse One-Time-Programmable Nonvolatile Memory - An anti-fuse one-time-programmable (OTP) nonvolatile memory cell has a P well substrate with two P.sup.− doped regions. Another N.sup.+ doped region, functioning as a bit line, is positioned adjacent and between the two P.sup.− doped regions on the substrate. An anti-fuse is defined over the N.sup.+ doped region. Two insulator regions are deposited over the two P.sup.− doped regions. An impurity doped polysilicon layer is defined over the two insulator regions and the anti-fuse. A polycide layer is defined over the impurity doped polysilicon layer. The polycide layer and the polysilicon layer function as a word line. A programmed region, i.e., a link, functioning as a diode, is formed on the anti-fuse after the anti-fuse OTP nonvolatile memory cell is programmed. The array structure of anti-fuse OTP nonvolatile memory cells and methods for programming, reading, and fabricating such a cell are also disclosed. | 12-31-2009 |
20100014340 | Quad SRAM Based One Time Programmable Memory - A differential latch-based one time programmable memory cell is provided. The differential latch-based one time programmable memory cell includes a differential latching amplifier having a first set of fuse devices coupled to the first input and a second set of fuse devices coupled to the second input. Only one set of fuse devices can be programmed in a memory cell. If one or more fuse devices in a set of fuse devices are programmed, the side having the programmed fuse will present a lower voltage at its input to the differential latching amplifier. Differential latching amplifier outputs a “0” or a “1” depending on the side having the programmed fuse. | 01-21-2010 |
20100046269 | Programmable read only memory - An array of memory cells is disclosed. The memory cell includes a fuse and at least one transistor. The transistor is used to control the programming or sensing of the fuse. A program voltage is applied to a stack of first and second conductive layers. A first portion of the stack couples the program voltage to a terminal of the transistor in a cell. A second portion of the stack couples the program voltage to a terminal of the transistor in another cell. | 02-25-2010 |
20100061136 | Semiconductor Memory Device and Semiconductor Device - An anti-fuse memory device includes a plurality of word lines, a plurality of bit lines, and a memory cell provided with respect to an intersecting portion of any of the plurality of word lines and any of the plurality of bit lines. Memory cell includes a PIN diode and an anti-fuse. An anode of the PIN diode is electrically connected to any of the bit lines. A cathode of the PIN diode is electrically connected to a first terminal of the anti-fuse. A second terminal of the anti-fuse is electrically connected to any of the word lines. The anti-fuse includes a silicon layer and an insulating layer which are interposed between electrodes. | 03-11-2010 |
20100091545 | ELECTICALLY PROGRAMMABLE FUSE BIT - One-time programmable (OTP) nonvolatile fuse memory cells are disclosed that do not require decoding or addressing for reading their data content. Each fuse memory cell has its content latched at its output and available at all times and can be used, for example, for code storage memories, serial configuration memories, and as individual fuse bits for ID (identification), trimming, and other post-fabrication System-on-Chip (SoC) customization needs. Means are also provided for temporary data storage for design testing, etc. In alternative embodiments, using two differentially programmed fuses in a single memory cell, the selection and programming circuitry are merged. | 04-15-2010 |
20100110750 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - The row decoder receives writing instruction signal and reading instruction signal to selectively activate one of the word lines according to an input state of row address signals. The data buffer receives a data input signal when the writing instruction signal is received, and drives corresponding one of the bit lines and amplifies a minute reading signal transmitted to one of the bit lines to output a data output signal when the reading instruction signal is received. | 05-06-2010 |
20100118584 | MEMORY DEVICE USING ANTIFUSES - Herein described is a method of implementing one or more native NMOS antifuses in an integrated circuit. Also described is a method for programming one or more native NMOS antifuses used within a memory device. The method further comprises verifying one or more states of the one or more native NMOS antifuses after the programming has been performed. In a representative embodiment, the one or more native NMOS antifuses are implemented by blocking the implantation of a dopant into a substrate of an integrated circuit. In a representative embodiment, an integrated circuit incorporates the use of one or more native NMOS antifuses. In a representative embodiment, the integrated circuit comprises a memory device, such as a one time programmable memory. | 05-13-2010 |
20100128511 | High density prom - The invention shows how diodes in a modern semiconductor process can be used as a very compact switch element in a Programmable Read Only Memory (PROM) using common integrated circuit fuse elements such as polysilicon and metal. This compact switch element allows very dense PROM arrays to be realized since diodes have the highest conduction density of any semiconductor device. The high conduction density is used to provide the relatively high current needed to blow the fuse element open. Since MOSFETs are typically used as fuse array switch elements, a relatively large area is required for the MOSFET to reach the current needed to blow the fuse element. Since diodes are two terminal switch elements unlike MOSFETs which are three terminal devices, methods are outlined on how to both read and write the arrays using this two terminal switch. | 05-27-2010 |
20100157648 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH FUSE ELEMENTS AND CONTROL METHOD THEREFORE - A semiconductor integrated circuit device includes a first block, a second block, and a control section. The first block includes a first fuse, a first switching configured to write data to the first fuse, a first holding portion capable of holding a first instruction, and a first instruction portion configured to turn on the first switching when a second instruction is given thereto with the first instruction. The second block includes a second fuse, a second switching configured to write data to the second fuse, a second holding portion capable of holding the first instruction, and a second instruction portion configured to turn on the second switching when the second instruction is given thereto with the first instruction. The control section issues the second instruction at a point in time when the first instruction is held in the first and second holding portions. | 06-24-2010 |
20100165699 | ANTIFUSE PROGRAMMABLE MEMORY ARRAY - Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, such as PROM, OTPROM, and other such programmable non-volatile memories. The circuitry employs an antifuse scheme that includes an array of memory bitcells, each containing a program device and an antifuse element configured with current path isolation well and for storing the memory cell state. The bitcell configuration, which can be used in conjunction with column/row select circuitry, power selector circuitry, and/or readout circuitry, allows for high-density memory array circuit designs and layouts. | 07-01-2010 |
20100177548 | MULTILEVEL ONE-TIME PROGRAMMABLE MEMORY DEVICE - A multilevel one-time programmable memory device includes a plurality of memory cells, wherein each of the plurality of memory cells includes: a first electrode to which a first voltage is applied, a second electrode to which a second voltage is applied and a plurality of fuse lines performing a fusing operation according to a voltage difference between the first electrode and the second electrode. The plurality of fuse lines are connected to each other between the first electrode and the second electrode. In addition, at least one of the first electrode and the second electrode is formed such that the first electrode and the second electrode have different valid line lengths from each other therebetween so that the plurality of fuse lines have different resistances from each other. | 07-15-2010 |
20100177549 | Silicide-silicon oxide-semiconductor antifuse device and method of making - An antifuse contains a first silicide layer, a grown silicon oxide antifuse layer on a first surface of the first silicide layer, and a first semiconductor layer having a first surface in contact with the antifuse layer. | 07-15-2010 |
20100182818 | Non-volatile semiconductor memory device and method of writing data therein - A device includes a memory cell array and a control circuit, the memory cell array inclusing word-lines, bit-lines, and memory cells arranged at the intersections of the word-lines and the bit-lines, each memory cell inclusing an electrically programmable antifuse element. The control circuit may perform, as a first step, applying a programming voltage to one of the word-lines while applying a ground voltage to bit-lines each connected to respective selected memory cells, and as a second step, after the first step, keeping one of the one word-lines at the programming voltage while concurrently reading the electrical states of the selected memory cells, and according to the read electrical states, applying the ground voltage again to a bit-line connected to an unprogrammed selected memory cell after the first step, and applying a voltage higher than the ground voltage to a bit-line connected to a programmed selected memory cell after the first step. | 07-22-2010 |
20100182819 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprising: a memory cell array in which two bit lines are provided to each one bit of input data, and memory cells each including an anti-fuse element are arranged at an intersection point between one of the two bit lines and an even address word line, and an intersection point between the other one of the two bit lines and an odd address word line, respectively; a plurality of booster circuits which are arranged in a plurality of memory banks, respectively, and each of which generates a write voltage and a read voltage to be supplied to a corresponding one of the anti-fuse elements of the respective memory banks, each of the memory banks obtained by dividing the memory cell array; a booster circuit controller to issue an instruction to generate the write voltage and the read voltage to the plurality of booster circuits; a word line selector to activate a different word line at the time of writing from one to be activated at the time of reading, with respect to the same address value of an address signal; a write bit line selector to select bit lines one by one from the memory banks, respectively, at the time of writing, the bit lines performing writing simultaneously; and a read bit line selector to select a bit line at the time of reading, the bit line outputting data. | 07-22-2010 |
20100188881 | Method and Device for Correcting and Obtaining Reference Voltage - The present invention discloses a method for adjusting a reference voltage, including: decoding a default code configured in a reference voltage register in a chip to obtain an actual reference voltage; comparing the actual reference voltage with a benchmark value to obtain a deviation value between the two; configuring an adjustment code according to the deviation value; and, burning the adjustment code into a nonvolatile storage medium. The present invention also discloses an apparatus for adjusting a reference voltage. According to the method and apparatus for adjusting a reference voltage provided by embodiments of the present invention, the reference voltage need not be adjusted according to an external power supply's different application schemes. Thus, adjustment on the reference voltage of the chip is standardized and costs of the chip's application schemes are saved. Embodiments of the present invention further provide a method and apparatus for obtaining a reference voltage, which makes it not necessary to configure a dedicated reference voltage pin in the chip for introducing an external reference voltage, and thus stability of the circuit's working is improved and costs of the chip's applications are decreased. | 07-29-2010 |
20100202184 | One-Time Programmable Fuse with Ultra Low Programming Current - A method of operating a FinFET fuse includes providing the FinFET fuse including a drain, a gate, a source, and a channel between the drain and the source; and applying a program voltage to one of the source and the drain of the FinFET fuse to cause a punch-through in the channel of the FinFET fuse. The method further includes determining a program state of the FinFET fuse. | 08-12-2010 |
20100214816 | SEMICONDUCTOR DEVICES SUPPORTING MULTIPLE FUSE PROGRAMMING MODES - Semiconductor devices include a plurality of fuses and a plurality of program circuits, respective ones of which are configured to program respective ones of the plurality of fuses. The devices further include a shift register configured to activate at least two of the program circuits. In some embodiments, the shift register includes a first shift register configured to generate first select signals and a second shift register configured to generate second select signals corresponding to data to be programmed to the plurality of fuses. Respective ones of the program circuits may be configured to program respective ones of the fuses responsive to respective pairs of the first select signals and the second select signals. | 08-26-2010 |
20100220511 | LOW POWER ANTIFUSE SENSING SCHEME WITH IMPROVED RELIABILITY - Generally, a method and circuit for improving the retention and reliability of unprogrammed anti-fuse memory cells. This is achieved by minimizing the tunneling current through the unprogrammed anti-fuse memory cells which can cause eventual gate oxide breakdown. The amount of time a read voltage is applied to the anti-fuse memory cells is reduced by pulsing a read voltage applied to a wordline connected to the unprogrammed anti-fuse memory cells, thereby reducing the tunneling current. Further tunneling current can be reduced by decoupling the unprogrammed anti-fuse memory cells from a sense amplifier that can drive the corresponding bitline to VSS. | 09-02-2010 |
20100232203 | ELECTRICAL ANTI-FUSE AND RELATED APPLICATIONS - A first terminal and a second terminal of a FinFET transistor are used as two terminals of an anti-fuse. To program the anti-fuse, a gate of the FinFET transistor is controlled, and a voltage having a predetermined amplitude and a predetermined duration is applied to the first terminal to cause the first terminal to be electrically shorted to the second terminal. | 09-16-2010 |
20100246237 | ANTI-FUSE ELEMENT - Programmable anti-fuse circuitry including at least one anti-fuse cell having a first anti-fuse device coupled between a supply voltage and a first node and a second anti-fuse device coupled between the first node and a ground voltage, and control logic coupled to the first node and arranged to generate a programming voltage having one of at least a first voltage level for breaking-down the first anti-fuse device but not the second anti-fuse device and coupling the first node to the supply voltage; and a second voltage level for breaking-down the second anti-fuse device but not the first anti-fuse device and coupling the first node to the ground voltage. | 09-30-2010 |
20100265754 | SEMICONDUCTOR MEMORY DEVICE AND DATA PROCESSING DEVICE - When writing into an antifuse memory element finishes, a value of resistance of the memory element rapidly decreases; accordingly, an output voltage of a boosting circuit which produces a writing voltage rapidly decreases. By detecting a change in the output voltage of the boosting circuit to control a writing command, the writing operation can be stopped immediately after the memory element is shorted. Thus, unnecessary current consumption caused by continuing a writing operation on the shorted memory element can be suppressed. | 10-21-2010 |
20100296328 | BURIED BIT LINE ANTI-FUSE ONE-TIME-PROGRAMMABLE NONVOLATILE MEMORY - An anti-fuse one-time-programmable (OTP) nonvolatile memory cell has a P well substrate with two P.sup.-doped regions. Another N.sup.+doped region, functioning as a bit line, is positioned adjacent and between the two P.sup.-doped regions on the substrate. An anti-fuse is defined over the N.sup.+doped region. Two insulator regions are deposited over the two P.sup.-doped regions. An impurity doped polysilicon layer is defined over the two insulator regions and the anti-fuse. A polycide layer is defined over the impurity doped polysilicon layer. The polycide layer and the polysilicon layer function as a word line. A programmed region, i.e., a link, functioning as a diode, is formed on the anti-fuse after the anti-fuse OTP nonvolatile memory cell is programmed. The array structure of anti-fuse OTP nonvolatile memory cells and methods for programming, reading, and fabricating such a cell are also disclosed. | 11-25-2010 |
20100302833 | Semiconductor device having nonvolatile memory element and manufacturing method thereof - To provide a semiconductor device including a pair of antifuse elements at either a high level or a low level, an OR circuit that outputs different logic information for a case that at least one of the antifuse elements is at a high level and a case that both of the antifuse elements are at a low level, and an exclusive OR circuit that outputs different logic information for a case that the logic states are different from each other and a case that they are same as each other. | 12-02-2010 |
20100309709 | UNIT CELL OF NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY DEVICE WITH THE SAME - Disclosed are a unit cell capable of improving a reliability by enhancing a data sensing margin in a read operation, and a nonvolatile memory device with the same. The unit cell of a nonvolatile memory device includes: an antifuse having a first terminal between an input terminal and an output terminal; and a first switching unit coupled between a second terminal of the antifuse and a ground voltage terminal. | 12-09-2010 |
20100328987 | E-FUSE APPARATUS FOR CONTROLLING REFERENCE VOLTAGE REQUIRED FOR PROGRAMMING/READING E-FUSE MACRO IN AN INTEGRATED CIRCUIT VIA SWITCH DEVICE IN THE SAME INTEGRATED CIRCUIT - An electrically programmable fuse (e-fuse) apparatus includes an e-fuse macro and a switch device. The e-fuse macro is disposed in an integrated circuit, and has a plurality of e-fuse units. The switch device is disposed in the integrated circuit, and has an output node coupled to the e-fuse units and a first input node coupled to a first power source which supplies a first reference voltage acting as a programming voltage of the e-fuse macro. The switch device connects the first power source to the e-fuse units when the e-fuse macro is operated under a programming mode. | 12-30-2010 |
20110058402 | Semiconductor device having nonvolatile memory elements - A bit memory circuit of an antifuse element set includes two antifuse elements of which logical states are changed from an insulation state to a conductive state when a program voltage is applied. 1-bit data is represented by the logical states of the two antifuse elements. The two antifuse elements are collectively controlled by one decoder circuit. When writing data, the decoder circuit simultaneously performs insulation-breakdown on the two antifuse elements by simultaneously connecting the two antifuse elements to program voltage lines, respectively. | 03-10-2011 |
20110080764 | ONE-TIME PROGRAMABLE CELL CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME, AND DATA JUDGING METHOD THEREOF - Provided is a semiconductor integrated circuit including: an anti-fuse element that electrically connects a first node and a first power supply terminal when data is written and electrically disconnect the first node and the first power supply terminal when data is not written; a first switch circuit that is connected between the first node and a first data line applied with a predetermine first voltage, and enters an off state from an on state according to a first control signal; and a detection part that detects write data of the anti-fuse element according to whether a voltage of the first node is substantially the same as the first voltage or substantially the same as a supply voltage of the first power supply terminal when the first switch circuit enters the off state. | 04-07-2011 |
20110080765 | PROGRAMMABLE ANTIFUSE TRANSISTOR AND METHOD FOR PROGRAMMING THEREOF - Programmable antifuse transistor, in particular n-channel MOS transistor, and a method for programming at least one such antifuse transistor, includes at least one gate with a gate terminal, source with a source terminal, drain with a drain terminal, and substrate with a substrate terminal, configured so that active circuits/circuit elements do not have to be located at a distance from the antifuse, minimizing area requirements, without additional process steps the level of the potential difference between source terminal and substrate terminal is less than about 0.5 volts, drain terminal and source terminal lie at different potentials. By adjusting drain-source voltage and/or the gate-source voltage a flow of charge carriers occurs between source and drain, causing semiconductor material between source and drain to be thermally heated and to locally melt, forming at least one permanently conducting channel between source and drain. | 04-07-2011 |
20110103127 | AND-TYPE ONE TIME PROGRAMMABLE MEMORY CELL - An AND-type anti-fuse memory cell, and a memory array consisting of AND-type anti-fuse memory cells. Chains of AND type anti-fuse cells are connected in series with each other, and with a bitline contact, in order to minimize the area occupied by the memory array. Each AND type anti-fuse cell includes an access transistor serially connectable to the bitline or the access transistors of other AND type anti-fuse cells, and an anti-fuse device. The channel region of the access transistor is connected to the channel region of the anti-fuse device, and both channel regions are covered by the same wordline. The wordline is driven to a programming voltage level for programming the anti-fuse device, or to a read voltage level for reading the anti-fuse device. | 05-05-2011 |
20110116299 | SEMICONDUCTOR DEVICE - To provide a semiconductor device capable of reducing the line width of a fuse. | 05-19-2011 |
20110122672 | Non-volatile semiconductor memory device - A non-volatile semiconductor memory device having a memory cell in which operating potentials are few and the scale of the peripheral circuitry is reduced includes a select transistor having a source/drain on both sides of a channel of a semiconductor substrate and having a gate electrode disposed on the channel via a thick gate insulating film; an element isolation region formed on the semiconductor substrate in an area adjacent to the select transistor; an antifuse adjacent to the element isolation region, having a lower electrode formed on the semiconductor substrate and having an upper electrode disposed on the semiconductor substrate in an area between the element isolation region and lower electrode via a thin gate insulating film; and a connection contact electrically connecting the source and upper electrode and contacting the source and the upper electrode. | 05-26-2011 |
20110199809 | SECURITY CIRCUIT HAVING AN ELECTRICAL FUSE ROM - A security circuit includes an electrical fuse read only memory (ROM) including a plurality of electrical fuse units. The electrical fuse units are arranged to correspond to bit values of an initial security key before the electrical fuse ROM is programmed. | 08-18-2011 |
20110216572 | ELECTRICALLY PROGRAMMABLE FUSE BIT - One-time programmable (OTP) nonvolatile fuse memory cells are disclosed that do not require decoding or addressing for reading their data content. Each fuse memory cell has its content latched at its output and available at all times and can be used, for example, for code storage memories, serial configuration memories, and as individual fuse bits for ID (identification), trimming, and other post-fabrication System-on-Chip (SoC) customization needs. Means are also provided for temporary data storage for design testing, etc. In alternative embodiments, using two differentially programmed fuses in a single memory cell, the selection and programming circuitry are merged. | 09-08-2011 |
20110235388 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - According to an embodiment of the invention, a nonvolatile semiconductor storage device includes a first memory cell and a second memory cell. A first fuse element in which data can be electrically written only once is provided in the first memory cell. A second fuse element in which data can be electrically written only once is provided in the second memory cell to repair a defect of the first memory cell. | 09-29-2011 |
20110267869 | CIRCUIT FOR VERIFYING THE WRITE ENABLE OF A ONE TIME PROGRAMMABLE MEMORY - A memory system including a one time programmable (OTP) memory is provided. The memory system further includes a write enable verification circuit including an asymmetric inverter stage and a symmetric inverter stage coupled at a node. The write enable verification circuit is configured to receive a write enable signal. When the write enable signal changes from a first voltage level to a second voltage level, a voltage at the node changes at a first rate and wherein when the write enable signal changes from the second voltage level to the first voltage level, the voltage at the node changes at a second rate higher than the first rate. The write enable verification circuit is further configured to generate a verified write enable signal for enabling programming of the OTP memory. | 11-03-2011 |
20110292711 | DATA ENCODING SCHEME TO REDUCE SENSE CURRENT - Techniques for encoding and decoding fuse data to reduce sense current are disclosed. An embodiment to encode fuse sense data includes inverting each of the bits of the fuse data and using an individual fuse as a flag bit to record the data inversion. The states of the respective fuses may represent different logic states. A fuse may be blown to indicate a logic one and likewise, an unblown fuse may indicate a logic zero. A blown fuse and an unblown fuse may have different current consumption. An unblown fuse may consume more sensing current compared to a blown fuse. Another embodiment to decode the encoded fuse data includes embedded logic circuits and a separate fuse as a flag bit. Encoding and decoding fuse data may reduce fuse sensing current. | 12-01-2011 |
20110317468 | Non-Volatile Memory with Split Write and Read Bitlines - Read and write operations of a non-volatile memory (NVM) bitcell have different optimum parameters resulting in a conflict during design of the NVM bitcell. A single bitline in the NVM bitcell prevents optimum read performance. Read performance may be improved by splitting the read path and the write path in a NVM bitcell between two bitlines. A read bitline of the NVM bitcell has a low capacitance for improved read operation speed and decreased power consumption. A write bitline of the NVM bitcell has a low resistance to handle large currents present during write operations. A memory element of the NVM bitcell may be a fuse, anti-fuse, eFUSE, or magnetic tunnel junction. Read performance may be further enhanced with differential sensing read operations. | 12-29-2011 |
20120008363 | Diode-Less Array for One-Time Programmable Memory - A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor. | 01-12-2012 |
20120020139 | Apparatus and Method for Testing One-Time-Programmable Memory - An apparatus and method of testing one-time-programmable memory limits current through a one-time-programmable memory to less than a threshold amplitude, where the memory has a fuse configured to blow upon receipt of a signal having the threshold amplitude. The method also uses blow signal assertion circuitry to attempt to assert a blow signal to the fuse. When not defective, blow signal assertion circuitry is configured to permit the low amplitude signal to flow through the fuse when the fuse is not blown and the blow signal is asserted. The method then produces an output signal having a success value if the limited current flows through the fuse, and a failure value if the current does not flow through the fuse. | 01-26-2012 |
20120039105 | SEMICONDUCTOR DEVICE - Both decreasing access time and power consumption and improving storage bit count per one word line are compatibly attained. A memory cell array | 02-16-2012 |
20120044737 | CIRCUIT AND SYSTEM OF USING POLYSILICON DIODE AS PROGRAM SELECTOR FOR ONE-TIME PROGRAMMABLE DEVICES - Polysilicon diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The OTP device has an OTP element coupled to a diode in a memory cell. The diode can be constructed by P+/N+ implants on a polysilicon as a program selector. By applying a high voltage to an OTP element coupled to the P-terminal of a diode and switching the N-terminal of a diode to a low voltage for suitable duration of time, a current flows through the OTP element may change the resistance state. On the polysilicon diode, the spacing and doping level of a gap between the P- and N-implants can be controlled for different breakdown voltages and leakage currents. The Silicide Block Layer (SBL) can be used to block silicide formation on the top of polysilicon to prevent shorting. If the OTP element is a polysilicon electrical fuse, the fuse element can be merged with the polysilicon diode in one piece to save area. | 02-23-2012 |
20120044738 | ONE-TIME PROGRAMMABLE MEMORIES USING POLYSILICON DIODES AS PROGRAM SELECTORS - Polysilicon diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, using electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse etc. as OTP element The diode can be constructed by P+/N+ implants on a polysilicon as a program selector. The OTP device has an OTP element coupled to a polysilicon diode. The OTP devices can be used to construct a two-dimensional OTP memory with the N-terminals of the diodes in a row connected as a wordline and the OTP elements in a column connected as a bitline. By applying a high voltage between a selected bitline and a selected wordline to turn on a diode in a selected cell for suitable duration of time, a current flows through an OTP element may change the resistance state. The cell data in the OTP memory can also be read by turning on a selected wordline and to couple a selected bitline to a sense amplifier. The wordlines may have high-resistivity local wordlines coupled to low-resistivity global wordlines through conductive contact(s) or via(s). | 02-23-2012 |
20120044739 | CIRCUIT AND SYSTEM OF USING JUNCTION DIODE AS PROGRAM SELECTOR FOR ONE-TIME PROGRAMMABLE DEVICES - Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The OTP device has an OTP element coupled to a diode in a memory cell. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. By applying a high voltage to the P terminal of a diode and switching the N terminal of a diode to a low voltage for suitable duration of time, a current flows through an OTP element in series with the program selector may change the resistance state. The P+ active region of the diode can be isolated from the N+ active region in the N well by using dummy MOS gate, SBL, or STI/LOCOS isolations. If the resistive element is an interconnect fuse based on CMOS gate material, the resistive element can be coupled to the P+ active region by an abutted contact such that the element, active region, and metal are connected in a single rectangular contact. | 02-23-2012 |
20120044740 | ONE-TIME PROGRAMMABLE MEMORIES USING JUNCTION DIODES AS PROGRAM SELECTORS - Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. The OTP device has an OTP element coupled to the diode. The OTP device can be used to construct a two-dimensional OTP memory with the N terminals of the diodes in a row connected as a wordline and the OTP elements in a column connected as a bitline. By applying a high voltage between a selected bitline and a selected wordline to turn on a diode in a selected cell for suitable duration of time, a current flows through an OTP element in series with the program selector may change the resistance state. The cell data in the OTP memory can also be read by turning on a selected wordline and to couple a selected bitline to a sense amplifier. The wordlines may have high-resistivity local wordlines coupled to low-resistivity global wordlines through conductive contact(s) or via(s). | 02-23-2012 |
20120092916 | Built-In Self Test for One-Time-Programmable Memory - An apparatus and method of testing one-time-programmable memory provides one-time-programmable memory having one or more memory locations for storing data and corresponding programming circuitry for each memory location. In addition, each programming circuitry has a circuit element configured to permanently change state to store the data in the memory. The method also reads each memory location to verify that the memory location is unprogrammed and activates the programming circuitry for each memory location, which applies a test current to the programming circuitry. The test current is less than a threshold current needed to permanently change the state of the circuit element. The method then determines whether the programming circuitry is functioning properly. | 04-19-2012 |
20120195091 | Method and System for Split Threshold Voltage Programmable Bitcells - A memory device includes an antifuse. The antifuse is configured to program a bit cell of the memory device. The antifuse is configured with a PMOS device | 08-02-2012 |
20120224406 | Circuit and System of Using Junction Diode as Program Selector for One-Time Programmable Devices - Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The OTP device has at least one OTP element coupled to at least one diode in a memory cell. The diode can be constructed by P+ and N+ active regions in a CMOS N well, or on an isolated active region as the P and N terminals of the diode. The isolation between P+ and the N+ active regions of the diode in a cell or between cells can be provided by dummy MOS gate, SBL, or STI/LOCOS isolations. The OTP element can be polysilicon, silicided polysilicon, silicide, metal, metal alloy, local interconnect, thermally isolated active region, CMOS gate, or combination thereof. | 09-06-2012 |
20120243288 | METHOD FOR LEAKAGE REDUCTION IN MEMORY CIRCUITS - An apparatus includes a bit cell of a programmable memory circuit. The bit cell includes a programmable device. The bit cell includes a first device having a first type. The first device is configured to conduct a first current between a first node and a second node in response to a first value of a signal on the word line and a signal on a bit line. The programmable device is configured to be programmed in response to a first level of the first current. The bit cell includes a circuit coupled to the second node. The circuit is configured to reduce a leakage current through the first device in response to a second value of the signal on the word line and based on a feedback signal. In at least one embodiment of the apparatus, the feedback signal is based on a signal on the bit line. | 09-27-2012 |
20120243289 | ELECTRIC FUSE, SEMICONDUCTOR DEVICE, AND INFORMATION WRITING METHOD OF ELECTRIC FUSE - An electric fuse includes: a filament having a first conductive layer and a second conductive layer formed on the first conductive layer, wherein at least three discernible resistive states are generated in the filament by changing of a combination of a state of the first conductive layer and a state of the second conductive layer. | 09-27-2012 |
20120243290 | MULTI-LEVEL ELECTRICAL FUSE USING ONE PROGRAMMING DEVICE - A method for programming a multi-level electrical fuse system comprises providing a fuse box with an electrical fuse and providing one of at least two fuse writing voltages to the electrical fuse to program the electrical fuse to one of at least two resistance states. The fuse box comprises at least one electrical fuse, a programming device serially coupled to the electrical fuse, and a variable power supply coupled to the fuse box and configured to generate two or more voltage levels. | 09-27-2012 |
20120257435 | NON-SALICIDE POLYSILICON FUSE - The embodiments of methods and structures disclosed herein provide mechanisms of forming and programming a non-salicided polysilicon fuse. The non-salicided polysilicon fuse and a programming transistor form a one-time programmable (OTP) memory cell, which can be programmed with a low programming voltage. | 10-11-2012 |
20120275208 | RELIABLE ELECTRICAL FUSE WITH LOCALIZED PROGRAMMING AND METHOD OF MAKING THE SAME - An electrical fuse has an anode contact on a surface of a semiconductor substrate. The electrical fuse has a cathode contact on the surface of the semiconductor substrate spaced from the anode contact. The electrical fuse has a link within the substrate electrically interconnecting the anode contact and the cathode contact. The link comprises a semiconductor layer and a silicide layer. The silicide layer extends beyond the anode contact. An opposite end of the silicide layer extends beyond the cathode contact. A silicon germanium region is embedded in the semiconductor layer under the silicide layer, between the anode contact and the cathode contact. | 11-01-2012 |
20120281450 | ELECTRICALLY PROGRAMMABLE FUSE MODULE IN SEMICONDUCTOR DEVICE - A semiconductor device has an e-fuse module and a programming current generator. The e-fuse module includes an array of electrically programmable e-fuse elements. The programming current generator has a set of reference transistor elements, a selector for actuating the reference transistor elements to generate a selected reference current, and a current mirror for applying a programming current that is a function of the selected reference current to a selected e-fuse element of the array to program the resistance of the e-fuse element. | 11-08-2012 |
20120314472 | Multiple-Bit Programmable Resistive Memory Using Diode as Program Selector - A method and system for multiple-bit programmable resistive cells having a multiple-bit programmable resistive element and using diode as program selector are disclosed. The first and second terminals of the diode having a first and second types of dopants can be fabricated from source/drain of MOS in a well for MOS devices or fabricated on the same polysilicon structure. If a multiple-bit programmable resistive cell has 2 | 12-13-2012 |
20120314473 | Multiple-State One-Time Programmable (OTP) Memory to Function as Multi-Time Programmable (MTP) Memory - A circuit, method, and system for using multiple-state One-Time Programmable (OTP) memory to function as a multiple-bit programmable (MTP) memory are disclosed. The OTP memory can have N(N>2) distinct resistance states, that can be differentiated by at least N−1 reference resistances, can be functionally equivalent programmed N−1 times. The multiple-state OTP memory can have a plural of multiple-state OTP cells that can be selectively programmed to a resistance state. The reference resistance can be set to determine a state of the from the programmed multiple-state OTP cells. | 12-13-2012 |
20120320656 | Programmable Resistive Memory Unit with Data and Reference Cells - A method and system of a programmable resistive memory having a plurality of programmable resistive memory units is disclosed. At least one of the programmable resistive memory units has at least one data cell and at least one reference cell. The data cell can have one programmable resistive element coupled to at least one diode as a program selector and also coupled to a bitline (BL). The reference cell can have a reference resistive element coupled to at least one reference diode as reference program selector and also coupled to a reference bitline (BLR). In one embodiment, the reference resistive element can have substantially the same material, structure, or shape of the programmable resistive element. In one embodiment, the reference diode can have the same material, structure, or shape of the diode serving as the program selector diode. | 12-20-2012 |
20120320657 | Programmable Resistive Memory Unit with Multiple Cells to Improve Yield and Reliability - A method and system for a programmable resistive memory to improve yield and reliability has a plurality of programmable resistive units. Each programmable resistive unit can have at least one programmable resistive cell. Each programmable resistive cell can have a programmable resistive element with a first end coupled to a first supply voltage line and a second end coupled to at least one diode serving as program selector. Each diode can have at least first and second terminals with first and second types of dopants, with the second terminal being coupled to a second supply voltage line. The first and second terminals of the diode can be fabricated from source/drain of MOS in a well for MOS devices or fabricated on the same polysilicon structure. | 12-20-2012 |
20130039117 | ELECTRICAL FUSE BIT CELL - An electrical fuse (eFuse) bit cell includes a program transistor, a read transistor, and an eFuse. The program transistor has a first program terminal, a second program terminal, and a third program terminal. The read transistor has a first read terminal, a second read terminal, and a third read terminal. The eFuse has a first end and a second end. The first end, the first program terminal, and the second read terminal are coupled together. The read transistor is configured to be off and the program transistor is configured to be on when the eFuse bit cell is in a program mode. The program transistor is configured to be off and the read transistor is configured to be on when the eFuse bit cell is in a read mode. | 02-14-2013 |
20130058150 | OTP MEMORY - The present invention provides an OTP memory having higher confidentiality. A memory cell has a memory transistor forming a current path between first and second nodes, a selection transistor forming a current path between third and fourth nodes, the third node being coupled to the gate of the memory transistor via a line, and a capacitor coupled to the first node. By applying high voltage which does not break but deteriorates a gate oxide film and increases gate leak current to a memory transistor, data is written. Data can be read by the presence/absence of leak of charges accumulated in the capacitor. Since the position of deterioration in the gate oxide film cannot be discriminated by a physical analysis, confidentiality is high. | 03-07-2013 |
20130058151 | NON-VOLATILE MEMORY WITH SPLIT WRITE AND READ BITLINES - Read and write operations of a non-volatile memory (NVM) bitcell have different optimum parameters resulting in a conflict during design of the NVM bitcell. A single bitline in the NVM bitcell prevents optimum read performance. Read performance may be improved by splitting the read path and the write path in a NVM bitcell between two bitlines. A read bitline of the NVM bitcell has a low capacitance for improved read operation speed and decreased power consumption. A write bitline of the NVM bitcell has a low resistance to handle large currents present during write operations. A memory element of the NVM bitcell may be a fuse, anti-fuse, eFUSE, or magnetic tunnel junction. Read performance may be further enhanced with differential sensing read operations. | 03-07-2013 |
20130107603 | CIRCUIT AND METHOD FOR GENERATING A READ SIGNAL | 05-02-2013 |
20130170276 | ONE-TIME PROGRAMMABLE FUSE READ - This document discusses, among other things, a reference voltage generator circuit coupled to a plurality of fuse read circuits. The reference voltage generator circuit can be configured to mirror a reference current to produce a reference voltage and a gate bias voltage. The plurality of fuse read circuits can each be coupled to the reference voltage generator circuit and can also be coupled to a fuse of a plurality of fuses. Each fuse read circuit of the plurality of fuse read circuits can be configured to mirror the reference current using the gate bias voltage to produce a fuse read voltage across each fuse coupled to the plurality of fuse read circuits. Each fuse read circuit of the plurality of fuse read circuits can compare the fuse read voltage of each fuse and the reference voltage and can indicate a state of each fuse coupled to each fuse read circuit using the comparison. | 07-04-2013 |
20130176765 | ONE-TIME PROGRAMABLE CELL CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME, AND DATA JUDGING METHOD THEREOF - Provided is a semiconductor integrated circuit including: an anti-fuse element that electrically connects a first node and a first power supply terminal when data is written and electrically disconnect the first node and the first power supply terminal when data is not written; a first switch circuit that is connected between the first node and a first data line applied with a predetermine first voltage, and enters an off state from an on state according to a first control signal; and a detection part that detects write data of the anti-fuse element according to whether a voltage of the first node is substantially the same as the first voltage or substantially the same as a supply voltage of the first power supply terminal when the first switch circuit enters the off state. | 07-11-2013 |
20130201745 | Circuit and System of a Low Density One-Time Programmable Memory - A low density One-Time Programmable (OTP) memory is disclosed to achieve low gate count and low overhead in the peripheral circuits to save the cost. A maximum-length Linear Feedback Shift Register (LFSR) can be used to generate 2 | 08-08-2013 |
20130201746 | CIRCUIT AND SYSTEM FOR TESTING A ONE-TIME PROGRAMMABLE (OTP) MEMORY - Circuits, systems and techniques for testing a One-Time Programmable (OTP) memory are disclosed. An extra OTP bit can be provided as a test sample to be programmed. The programmed extra OTP bit can be read with any virgin cells in the OTP memory alternatively to generate a stream of logic 0 and logic 1 data so that every row or column path can be tested and the outcome can be observed in a pseudo-checkerboard pattern or other predetermined pattern. By carefully setting control signals, checkerboard-like pattern can be generated without actual programming any OTP cells in the memory array. | 08-08-2013 |
20130201747 | PERMANENT SOLID STATE MEMORY USING CARBON-BASED OR METALLIC FUSES - A permanent solid state memory device is disclosed. Recording data in the permanent solid state memory device forms voids in a data layer between a first wire array and a second wire array. Wires of the first wire array extend transversely to wires in the second wire array. The material is made of a carbon allotrope such that when current is passed through the carbon allotrope, the carbon is quickly oxidized (burned) leaving a complete gap (void) where the fuse once was. One of the advantages of this method is that the fuse material is fully oxidized in the particular “neck region of the bowtie”, such that there is no material left over from which dendrites can grow. In other embodiments, the data layer is a metal or metal oxide selected from the following metals: Tungsten (W), Rhenium (Rh), Osmium (Os), Iridium (Ir), Molybdenum (Mo), Ruthenium (Ru), Rhodium (Rh), Chromium (Cr), and Manganese (Mn). | 08-08-2013 |
20130208525 | SOFT BREAKDOWN MODE, LOW VOLTAGE, LOW POWER ANTIFUSE-BASED NON-VOLATILE MEMORY CELL - A non-volatile memory cell uses two transistors only, a bit select and a sense device. Each cell further comprises an antifuse device implemented, for example, with a field-effect transistor operated to behave like an antifuse when the cell is selected and a modest programming voltage under 5.5 volts and under 5-μA is applied. Only a soft breakdown is needed in the thin gate oxide because a local sense transistor is used during read operations to detect the programming and amplify it for column sense amplifiers. Reading also only requires low voltages of about one volt. | 08-15-2013 |
20130223124 | VARIABLE RESISTIVE MEMORY DEVICE AND METHOD OF FABRICATING AND DRIVING THE SAME - Provided are a variable resistive memory device, and methods of fabricating and driving the same. The variable resistive memory device includes a plurality of memory cells arranged in a first direction and in a second direction different from the first direction, each of the plurality of memory cells comprising a variable resistor and a selection device serially connected to the variable resistor. A common wiring is electrically connected to first ends of the plurality of memory cells to apply a common reference voltage. Each wiring line of a plurality of wiring lines is electrically connected to second ends of the plurality of memory cells arranged n the plurality of rows oriented in the first direction. A plurality of selection lines are respectively connected to the selection devices of the plurality of memory cells to select any one of the plurality of memory cells via the plurality of wiring lines. | 08-29-2013 |
20130235643 | SEMICONDUCTOR DEVICE HAVING A FUSE - A semiconductor device comprises an active region including a core circuit forming region and a buffer forming region, and a fuse element forming region arranged on a corner of the active region and to be able to be electrically fused. It is possible to arrange the fuse element without forming the fuse in the core circuit forming region by arranging the fuse element forming region at the corner of the active region. | 09-12-2013 |
20130250647 | Multi-Time Programmable Memory - Embodiments extend the capability of fuse elements, anti-fuse elements, and combinations thereof to enable multi-time programmable memory elements. Accordingly, embodiments significantly reduce area requirements and control circuitry complexity of memory elements. Embodiments can be used in non-volatile memory storage, for example, and are suitable for use in system on chip (SoC) products. | 09-26-2013 |
20130258748 | FUSE DATA READING CIRCUIT HAVING MULTIPLE READING MODES AND RELATED DEVICES, SYSTEMS AND METHODS - A fuse data reading circuit is configured to read fuse data in multi-reading modes. The fuse data may be stored in a fuse array that includes a plurality of fuse cells configured to store fuse data. The fuse data reading circuit may include a sensing unit configured to sense the fuse data stored in the fuse cells of the fuse array, and a controller configured to control an operation of reading the fuse data stored in the fuse cells. The controller sets different sensing conditions for sensing the fuse data according to an operation period during the fuse data reading operation to read the fuse data. Methods include operations and use of the fuse data reading circuit. | 10-03-2013 |
20130265815 | METHOD OF READING DATA STORED IN FUSE DEVICE AND APPARATUSES USING THE SAME - A method for reading data stored in a fuse device included in a memory device including a memory cell array is provided. The method comprises reading trimming data of the fuse device, wherein the trimming data is related to trimming a level of voltage or a level of current used for an operation of the memory device; and after the reading the trimming data, reading defective cell address data of the fuse device, wherein the defective cell address data is related to defective cells in the memory cell array. | 10-10-2013 |
20130272050 | NON-VOLATILE MEMORY, SEMICONDUCTOR DEVICE AND READING METHOD - There is provided a non-volatile memory circuit including: plural storage element sections each including a zener zap device and a switch section that connects an anode of the zener zap device to an output terminal during data reading; and wherein cathodes of respective zener zap devices of the plural storage element sections are commonly connected so as to be connected to a power supply employed in the writing or to a power supply employed in the reading, wherein the output terminals of the plural storage element sections are commonly connected to an input terminal of a detector, an anode of each of the storage element sections being connected to a ground voltage during data writing, and wherein the switch section is switched ON during data reading so as to connect the anode of the storage element section through the output terminal to the input terminal of the detector. | 10-17-2013 |
20130272051 | NON-VOLATILE MEMORY AND SEMICONDUCTOR DEVICE - There is provided a non-volatile memory including: plural zener zap devices, each including a cathode region and an anode region formed in a well; and a metal wiring line that is formed above the plural zener zap devices, that is commonly connected to each of the cathode regions, and that supplies a write voltage to each of the zener zap devices. | 10-17-2013 |
20130286710 | ONE-TIME PROGRAMMABLE MEMORY, INTEGRATED CIRCUIT INCLUDING SAME, AND METHOD THEREFOR - A one-time programmable memory includes a first one-time programmable memory cell including a fuse core having an input terminal for receiving a trim signal, an output terminal for providing a sense signal, and a fuse. The fuse core conducts current through the fuse in response to the trim signal. The one-time programmable memory cell also includes a sense circuit having an input terminal coupled to the output terminal of the fuse core, and an output terminal for providing a termination signal, and a logic circuit having a first input terminal for receiving a program enable signal, a second input terminal for receiving a data signal, a third input terminal coupled to the output terminal of the sense circuit for receiving the termination signal, and an output terminal coupled to the input terminal of the fuse core for providing the trim signal. | 10-31-2013 |
20130294140 | ANTI-FUSE CIRCUIT IN WHICH ANTI-FUSE CELL DATA IS MONITORED, AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - An anti-fuse circuit in which anti-fuse program data may be monitored outside of the anti-fuse circuit and a semiconductor device including the anti-fuse circuit are disclosed. The anti-fuse circuit includes an anti-fuse array, a data storage circuit, and a first selecting circuit. The anti-fuse array includes one or more anti-fuse blocks including a first anti-fuse block having a plurality of anti-fuse cells and the anti-fuse array is configured to store anti-fuse program data. The data storage circuit is configured to receive and store the anti-fuse program data from the anti-fuse array through one or more data buses. The first selecting circuit is configured to output anti-fuse program data of a selected anti-fuse block of the one or more anti-fuse blocks in response to a first selection signal. | 11-07-2013 |
20130294141 | MEMORY DEVICE INCLUDING ANTIFUSE MEMORY CELL ARRAY AND MEMORY SYSTEM INCLUDING THE MEMORY DEVICE - A memory device includes a memory cell array, a column decoder, and a row decoder. The row decoder includes a first word line driver and a second word line driver. The first word line driver is configured to electrically coupled to a first set of antifuse memory cells coupled to a first word line. The second word line driver is configured to electrically coupled to a second set of antifuse memory cells coupled to a second word line. The first set of antifuse memory cells are arranged in first and third rows of the memory cell array, and the second set of antifuse memory cells are arranged in second and fourth rows of the memory cell array. The second row is arranged between the first and third rows. | 11-07-2013 |
20130294142 | METHOD FOR CONTROLLING THE BREAKDOWN OF AN ANTIFUSE MEMORY CELL - A method for controlling the breakdown of an antifuse memory cell formed on a semiconductor substrate, including the steps of: applying a programming voltage; detecting a breakdown time; and interrupting the application of the programming voltage at a time following the breakdown time by a post-breakdown time. | 11-07-2013 |
20130294143 | Built-In Self Test for One-Time-Programmable Memory - An apparatus and method of testing one-time-programmable memory provides one-time-programmable memory having one or more memory locations for storing data and corresponding programming circuitry for each memory location. In addition, each programming circuitry has a circuit element configured to permanently change state to store the data in the memory. The method also reads each memory location to verify that the memory location is unprogrammed and activates the programming circuitry for each memory location, which applies a test current to the programming circuitry. The test current is less than a threshold current needed to permanently change the state of the circuit element. The method then determines whether the programming circuitry is functioning properly. | 11-07-2013 |
20130308364 | POWER UP DETECTION SYSTEM FOR A MEMORY DEVICE - A power up detection method for a memory device and a memory device are disclosed. In a first phase, a test word is read from a read-only memory (ROM) row of a memory array of the memory device, and the test word is compared to predetermined ROM row data. If the test word matches the predetermined ROM row data, a second phase may be performed. In the second phase, first user data is read from a user-programmed row of the memory array at a first time. Second user data is read from the user-programmed row of the memory array at a second time different from the first time. The first user data is compared to the second user data. Successful power up of the memory device is determined when the first user data matches the second user data. | 11-21-2013 |
20130308365 | CIRCUIT AND METHOD FOR REDUCING WRITE DISTURB IN A NON-VOLATILE MEMORY DEVICE - An active precharge circuit for a non-volatile memory array which minimizes write disturb to non-selected memory cells during programming is disclosed. In a programming cycle, all bitlines are pre-charged to a program inhibit voltage level and held at the program inhibit voltage level with current or voltage sources coupled to each of the bitlines in a precharge operation and a following programming operation. In the programming operation, a bitline connected to a memory cell to be programmed is driven to a programming level, such as VSS, while the active precharge circuit is enabled to enable programming thereof. Because the other non-selected bitlines are held at the program inhibit voltage level, they will not be inadvertently programmed when the programming voltage is supplied by the word line. | 11-21-2013 |
20130308366 | Circuit and System of Using Junction Diode as Program Selector for One-Time Programmable Devices - Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The OTP device has an OTP element coupled to a diode in a memory cell. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. By applying a high voltage to the P terminal of a diode and switching the N terminal of a diode to a low voltage for suitable duration of time, a current flows through an OTP element in series with the program selector may change the resistance state. The P+ active region of the diode can be isolated from the N+ active region in the N well by using dummy MOS gate, SBL, or STI/LOCOS isolations. If the resistive element is an interconnect fuse based on CMOS gate material, the resistive element can be coupled to the P+ active region by an abutted contact such that the element, active region, and metal are connected in a single rectangular contact. | 11-21-2013 |
20130322149 | MEMORY DEVICE, METHOD OF OPERATING THE SAME, AND ELECTRONIC DEVICE HAVING THE MEMORY DEVICE - A memory device includes a memory cell array and a fuse device. The fuse device includes a fuse cell array and a fuse control circuit. The fuse cell array includes a first fuse cell sub-array which stores first data associated with operation of the fuse control circuit, and a second fuse cell sub-array which stores second data associated with operation of the memory device. The fuse control circuit is electrically coupled to the first and second fuse cell sub-arrays, and is configured to read the first and second data from the first and second fuse cell sub-arrays, respectively. | 12-05-2013 |
20140003120 | STATE SENSING SYSTEM FOR EFUSE MEMORY | 01-02-2014 |
20140016394 | CCIRCUIT AND SYSTEM OF USING JUNCTION DIODE AS PROGRAM SELECTOR FOR METAL FUSES FOR ONE-TIME PROGRAMMABLE DEVICES - Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices. An OTP device can have at least one OTP element coupled to at least one diode in a memory cell. With a metal fuse is used by the OTP element, at least one contact and/or a plurality of vias can be built (possibly with use of one or more jumpers) in the program path to generate more Joule heat to assist with programming. The jumpers are conductive and can be formed of metal, metal gate, local interconnect, polymetal, etc. The metal fuse can also have an extended area that is longer than required by design rules for enhanced programmability. The OTP element can be polysilicon, silicided polysilicon, silicide, polymetal, metal, metal alloy, local interconnect, thermally isolated active region, CMOS gate, or combination thereof. | 01-16-2014 |
20140050006 | DIODE-LESS ARRAY FOR ONE-TIME PROGRAMMABLE MEMORY - A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor. | 02-20-2014 |
20140063894 | E-FUSE ARRAY CIRCUIT AND PROGRAMMING METHOD OF THE SAME - A program method for an e-fuse array circuit includes receiving an address and a multi-bit program data, programming the multi-bit program data in e-fuses designated by the address, reading a multi-bit read data from the e-fuses, and comparing bits of the multi-bit program data with bits of the multi-bit read data, wherein if the bits of the multi-bit program data are identical to the bits of the multi-bit read data, a program operation is terminated; and if the bits of the multi-bit read data are not identical to the bits of the multi-bit program data, then the programming of the multi-bit program data, the reading of the multi-bit read data, and the comparing of the bits are performed again. | 03-06-2014 |
20140098591 | ANTIFUSE OTP MEMORY CELL WITH PERFORMANCE IMPROVEMENT PREVENTION AND OPERATING METHOD OF MEMORY - Provided is an OTP memory cell including a first antifuse unit, a second antifuse unit, a select transistor, and a well region. The first and the second antifuse unit respectively include an antifuse layer and an antifuse gate disposed on a substrate in sequence. The select transistor includes a select gate, a gate dielectric layer, a first doped region, and a second doped region. The select gate is disposed on the substrate. The gate dielectric layer is disposed between the select gate and the substrate. The first and the second doped region are respectively disposed in the substrate at two sides of the select gate, wherein the second doped region is disposed in the substrate at the periphery of the first and the second antifuse unit. The well region is disposed in the substrate below the first and the second antifuse unit and is connected to the second doped region. | 04-10-2014 |
20140126266 | ONE-TIME PROGRAMMABLE MEMORIES USING POLYSILICON DIODES AS PROGRAM SELECTORS - Polysilicon diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, using electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse etc. as OTP element The diode can be constructed by P+/N+ implants on a polysilicon as a program selector. The OTP device can have an OTP element coupled to a polysilicon diode. The OTP devices can be used to construct a two-dimensional OTP memory with the N-terminals of the diodes in a row connected as a wordline and the OTP elements in a column connected as a bitline. | 05-08-2014 |
20140160830 | Programmable Resistive Device and Memory Using Diode as Selector - Building programmable resistive devices in contact holes at the crossover of a plurality of conductor lines in more than two vertical layers is disclosed. There are plurality of first conductor lines and another plurality of second conductor lines that can be substantially perpendicular to each other, though in two different vertical layers. A diode and/or a programmable resistive element can be fabricated in the contact hole between the first and second conductor lines. The programmable resistive element can be coupled to another programmable resistive device or shared between two programmable devices whose diodes conducting currents in opposite directions and/or coupled to a common conductor line. The programmable resistive memory can be configured to be programmable by applying voltages to conduct current flowing through the programmable resistive element to change its resistance for a different logic state. | 06-12-2014 |
20140169059 | FUSE REPAIR DEVICE - A fuse repair device may include a first fuse circuit configured to store a first portion out of a failed address, a second fuse circuit configured to store a multipurpose information or a second portion of the failed address, an enable control circuit configured to provide a first enable signal to enable the second fuse unit based on a first control signal, a switch control circuit configured to provide a second enable signal to enable the second fuse unit based on a second control signal, a repair control signal generation circuit configured to compare data stored in the first fuse circuit and the second fuse circuit with an input address, and generate a repair control signal based on the first enable signal and the second enable signal, and a multipurpose control signal generation circuit configured to generate a multipurpose control signal to control operations different from a repair operation. | 06-19-2014 |
20140177313 | SEMICONDUCTOR DEVICE AND METHOD OF OPERATION - A semiconductor device and method of operation having reduced read time of fuse array information during boot-up operation. When fuse array information is read, only repaired fuse-set information is read such that a read time of the semiconductor memory device is reduced, resulting in an increased read margin. | 06-26-2014 |
20140177314 | SEMICONDUCTOR MEMORY DEVICES AND SEMICONDUCTOR SYSTEM HAVING PARAMETERS, AND METHODS OF TESTING THE SAME - A semiconductor memory device may be effectively evaluated by a test that compares the phase of an internally generated control signal with the phase of an internally generated clock signal. Specifically, if the phase of the internal data strobe signal IDQS is synchronized with the phase of the internal clock signal ICLK through the test, the data strobe signal DQS may also be synchronized with the external clock signal CLK. Thus, the test may prevent certain critical parameters, for example, AC parameter tDQSCK, from being out of an allowable range over PVT (process, voltage, and temperature variation). The test helps ensure that the semiconductor memory device will operate properly in read mode. | 06-26-2014 |
20140185356 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF DRIVING THE SAME - A semiconductor integrated circuit includes a fuse circuit comprising a fuse configured to generate a fuse state signal corresponding to a rupture state of the fuse in response to an enable signal, a fuse state decision unit configured to determine whether or not the fuse state signal is normal based on a test signal, and generate an output enable signal according to a determination result, and a driving unit configured to output the fuse state signal in response to the output enable signal. | 07-03-2014 |
20140204649 | MEMORY ELEMENT, SEMICONDUCTOR DEVICE, AND WRITING METHOD - A memory element includes: an electrical fuse provided to be inserted between a first input node and a second input node; and an antifuse provided to be inserted between the second input node and a third input node. The third input node is configured to be a node to which a voltage is allowed to be applied separately from a voltage to be applied to the first input node. | 07-24-2014 |
20140219000 | OTP CELL ARRAY INCLUDING PROTECTED AREA, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND METHOD OF PROGRAMMING THE SAME - A method of programming a memory device including a one-time programmable (OTP) cell array configured to include at least one of a protected area and a programmable area are disclosed. The method includes receiving a fuse-program command to initiate a fuse-programming operation; checking whether the programmable area exists in the OTP cell array, terminating the fuse-programming operation when the OTP cell array does not include the programmable area, performing a fuse-programming operation on the programmable area when the OTP cell array includes the programmable area thereby programming fuses to create a fuse-programmed area; setting the fuse-programmed area of the OTP cell array as the protected area. | 08-07-2014 |
20140241031 | DIELECTRIC-BASED MEMORY CELLS HAVING MULTI-LEVEL ONE-TIME PROGRAMMABLE AND BI-LEVEL REWRITEABLE OPERATING MODES AND METHODS OF FORMING THE SAME - In some aspects, a memory cell is provided that includes a steering element and a memory element. The memory element includes a first conductive material layer, a first dielectric material layer disposed above the first conductive material layer, a second conductive material layer disposed above the first dielectric material layer, a second dielectric material layer disposed above the second conductive material layer, and a third conductive material layer disposed above the second dielectric material layer. One or both of the first conductive material layer and the second conductive material layer comprise a stack of a metal material layer and a highly doped semiconductor material layer. Numerous other aspects are provided. | 08-28-2014 |
20140247640 | MEMORY ARCHITECTURE AND CELL DESIGN EMPLOYING TWO ACCESS TRANSISTORS - Some embodiments include an improved memory array architecture and memory cell design. In one of such embodiments, a memory cell may comprise a memory element to store a logic state and two access transistors coupled to the memory element to access the logic state of the memory element. Other embodiments are described. | 09-04-2014 |
20140254233 | Redundant Fuse Coding - In accordance with some embodiments, fuse information may be written into a fuse array in a way that provides sufficient redundancy, making it harder for malicious parties to attack the fuse array. | 09-11-2014 |
20140254234 | RANDOM FUSE SENSING - In accordance with some embodiments, the way in which the fuses are sensed and, particularly, their order may be made more random so that it is much more difficult to simply exercise the device and determine all the values of the storage elements within the fuse array. One result is a more secure storage device. | 09-11-2014 |
20140268983 | OTPROM ARRAY WITH LEAKAGE CURRENT CANCELATION FOR ENHANCED EFUSE SENSING - Disclosed herein are memory cell arrays and methods for operating memory cell arrays. In one embodiment, a memory cell array includes a plurality of bitcells, a first bitline, a second bitline, a first wordline and a second wordline. The bitcells are arranged into rows and columns and each include a first transistor, a second transistor, and a fuse with a first end and a second end. The second transistor is selectively operable to couple the first end of the fuse to a ground. The first bitline is coupled to the first transistor of each of the bitcells of one column. The second bitline is coupled to the second end of the fuse of each of the bitcells of the column. The first transistor of each of the bitcells of the column is selectively operable to couple the first end of the fuse to the first bitline. | 09-18-2014 |
20140268984 | SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS - Provided is a semiconductor device that includes: a storage element including a first terminal, a second terminal, and a third terminal, and in which a resistance state between the second terminal and the third terminal is changed from a high resistance state to a low resistance state based on a stress current that flows between the first terminal and the second terminal; and a fuse connected to the first terminal, and configured to change from a conductive state to a non-conductive state based on the stress current. | 09-18-2014 |
20140293673 | NONVOLATILE MEMORY CELL STRUCTURE AND METHOD FOR PROGRAMMING AND READING THE SAME - A nonvolatile memory cell structure includes a doping well disposed in a substrate, an antifuse gate disposed on the doping well, a drain disposed in the substrate, an optional select gate disposed on the doping well and an optional shallow trench isolation disposed inside the doping well. | 10-02-2014 |
20140340954 | Low-Pin-Count Non-Volatile Memory Interface with Soft Programming Capability - A low-pin-count non-volatile (NVM) memory with no more than two control signals that can at least program NVM cells, load data to be programmed into output registers, or read the NVM cells. At least one of the NVM cells has at least one NVM element coupled to at least one selector and to a first supply voltage line. The selector is coupled to a second supply voltage line and having a select signal. At least one of the selected NVM cells can be coupled to at least one output register. No more than two control signals can be used to select the at least one NVM cells in the NVM sequentially for programming the data into the at least one NVM cells or loading data into the at least one output registers controlled by the pulse of the first signal and voltage level and/or timing of the second signal. Programming into the NVM cells, or loading data into output registers, can be determined by the voltage levels of the first to the second supply voltage lines. Reading at least one of the NVM cells can be activated by a third signal or by detecting ramping of the first or the second supply voltage line. | 11-20-2014 |
20140347909 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE - A semiconductor device includes a fuse array having a plurality of fuse sets suitable for outputting a plurality of fuse status signals having different levels according to whether fuses of the plurality of fuse sets are cut or not, a code counter suitable for counting selection codes in a preset order in response to an enable signal and an operation clock, and storage blocks suitable for receiving and storing the plurality of fuse status signals in a preset order in response to the selection codes. | 11-27-2014 |
20140369105 | GENERATING OUTPUT SIGNAL DURING READ OPERATION - A circuit includes a fuse cell, a sense circuit and an output control circuit. The fuse cell includes an electrical fuse. The sense circuit is electrically coupled to the fuse cell and configured for generating a sense signal indicative of a programmed condition of the electrical fuse, at an output of the sense circuit. The output control circuit is electrically coupled to the output of the sense circuit, and the output control circuit is configured for latching the sense signal indicative of the electrical fuse having been programmed, during a read operation of the fuse cell. | 12-18-2014 |
20140369106 | SEMICONDUCTOR DEVICE WITH FUSE ARRAY AND OPERATING METHOD THEREOF - A semiconductor device includes a fuse array for storing normal fuse data and pattern data through a programming operation, a boot-up control unit suitable for generating an enable signal for enabling an output of the pattern data, and a pattern detection unit suitable for detecting a pattern of the pattern data in response to the enable signal, and generating a detection signal. The fuse array outputs the normal fuse data in response to the detection signal. | 12-18-2014 |
20150009742 | SEMICONDUCTOR MEMORY DEVICE HAVING IMPROVED FUSE SENSING RELIABILITY IN SLOW POWER-UP OPERATION AND METHOD FOR READING FUSE BLOCK THEREBY - Provided is a semiconductor memory device with improved fuse sensing reliability during a slow power-up operation. The semiconductor memory device may include a memory cell array including a normal memory cell array and a spare memory cell array; an anti-fuse circuit supplied with a first voltage and configured to store fail address information associated with a defective memory cell in the normal memory cell array and configured to sense the fail address information in response to a clock signal applied during a power-up period; and a fuse read circuit including a clock generator supplied with a second voltage, the fuse read circuit configured to detect respective levels of the first and second voltages during the power-up period to generate the clock signal and to read the sensed fail address information from the anti-fuse circuit in response to the clock signal. | 01-08-2015 |
20150009743 | Low-Pin-Count Non-Volatile Memory Interface for 3D IC - A low-pin-count non-volatile (NVM) memory to be provided in an integrated circuit for a 3D IC to repair defects, trim devices, or adjust parameters is presented here. At least one die in a 3D IC can be built with at least one low-pin-count OTP memory. The low-pin-count OTP memory can be built with a serial interface such as I2C-like or SPI-like of interface. The pins of the low-pin-count OTP in at least one dies can be coupled together to have only one set of low-pin-count bus for external access. With proper device ID, each dies in a 3D IC can be accessed individually for soft programming, programming, erasing, or reading. This technique can improve the manufacture yield, device, circuit, or logic performance or to store configuration parameters for customization after 3D IC are built. | 01-08-2015 |
20150016174 | INTEGRATED CIRCUITS WITH PROGRAMMABLE ELECTRICAL CONNECTIONS AND METHODS FOR FABRICATING THE SAME - Methods and apparatus are provided for an integrated circuit with a programmable electrical connection. The apparatus includes an inactive area with a memory line passing over the inactive area. The memory line includes a programmable layer. An interlayer dielectric is positioned over the memory line and the inactive area, and an extending member extends through the interlayer dielectric. The extending member is electrically connected to the programmable layer of the memory line at a point above the inactive area. | 01-15-2015 |
20150023088 | APPARATUSES AND METHODS FOR SENSING FUSE STATES - Apparatuses and methods for sensing fuse states are disclosed herein. An apparatus may include an array having a plurality of sense lines. A plurality of cells may be coupled to a sense line of the plurality of sense lines. A fuse sense circuit may coupled to the sense line of the plurality of sense lines and configured to receive a sense voltage from a cell of the plurality of cells. The sense voltage may be based, at least in part, on a state of a fuse corresponding to the cell of the plurality of cells. The fuse sense circuit may further be configured to compare the sense voltage to a reference voltage to provide a fuse state control signal indicative of the state of the fuse. | 01-22-2015 |
20150029776 | SEMICONDUCTOR DEVICE HAVING A REDUCED AREA AND ENHANCED YIELD - A device includes a first power supply line supplying a first voltage, first, second, and third nodes, a selection circuit connected between the first power supply line and the first node, a first anti-fuse connected between the first node and the second node, and a second anti-fuse connected between the first node and the third node. The second node and the third node are not connected to each other. | 01-29-2015 |
20150029777 | Circuit and System of Using Junction Diode of MOS as Program Selector for Programmable Resistive Devices - A programmable resistive device cell using at least one MOS device as selector can be programmed or read by turning on a source junction diode of the MOS or a channel of the MOS. A programmable resistive device cell can include at least one programmable resistive element and at least one MOS device. The programmable resistive element can be coupled to a first supply voltage line. The MOS can have a source coupled to the programmable resistive element, a bulk coupled to a drain, a drain coupled to a second supply voltage line, and a gate coupled to a third supply voltage line. The programmable resistive element can be configured to be programmable or readable by applying voltages to the first, second, and/or third supply voltage lines to turn on the source junction of the MOS and/or to turn on the channel of the MOS. | 01-29-2015 |
20150036411 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a nonvolatile device array including write-once nonvolatile devices arranged in rows and columns, row select lines, a row control circuit connected to the row select lines, column select lines, a column control circuit connected to the column select lines, a flip-flop circuit provided at least on a side of the nonvolatile device array opposite to the row control circuit or on a side of the nonvolatile device array opposite to the column control circuit, and an inactivation unit configured to inactivate the row select lines or the column select lines based on a first control signal. | 02-05-2015 |
20150043265 | N-WELL SWITCHING CIRCUIT - A thin gate-oxide dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit is configured to bias the switched n-well to prevent voltage damage to the dual-mode PMOS transistor without the use of native transistors. | 02-12-2015 |
20150055395 | EXTENDED FUSE REPROGRAMMABILITY MECHANISM - An apparatus includes a semiconductor fuse array, disposed on a die, into which is programmed configuration data. The semiconductor fuse array has a first plurality of semiconductor fuses and a second plurality of semiconductor fuses. The first plurality of semiconductor fuses is configured to store the configuration data in an encoded and compressed format. The second plurality of semiconductor fuses is configured to store first fuse correction data that indicates locations and values corresponding to a first one or more fuses within the first plurality of fuses whose states are to be changed from that which was previously stored. | 02-26-2015 |
20150062996 | EMBEDDED SELECTOR-LESS ONE-TIME PROGRAMMABLE NON-VOLATILE MEMORY - An OTP anti-fuse memory array without additional selectors and a manufacturing method are provided. Embodiments include forming wells of a first polarity in a substrate, forming a bitline of the first polarity in each well, and forming plural metal gates across each bitline, wherein no source/drain regions are formed between the metal gates. | 03-05-2015 |
20150062997 | FUSE INFORMATION STORAGE CIRCUIT OF SEMICONDUCTOR APPARATUS - A test mode decoder configured to decode a test mode signal inputted a plurality of times and to generate preliminary fuse information, a count latch configured to count the preliminary fuse information in response to a count clock signal and to generate fuse information, and a fuse array block configured to store the fuse information can be included. | 03-05-2015 |
20150062998 | PROGRAMMABLE MEMORY - A programmable memory is provided. The programmable memory has a select transistor that includes a gate, a source, and a drain. An anti-fuse device is connected to a drain region of the select transistor. The anti-fuse device includes a dielectric layer on an upper substrate of the drain region, a polysilicon layer on the dielectric layer, and an anti-fuse electrode line in contact with the drain region. The dielectric layer breaks down and the anti-fuse device is programmed when the select transistor is turned on and a high voltage is applied through the anti-fuse line. | 03-05-2015 |
20150062999 | MEMORY DEVICE, MEMORY MODULE INCLUDING THE MEMORY DEVICE, METHOD OF FABRICATING THE MEMORY MODULE, AND METHOD OF REPAIRING THE MEMORY MODULE - A memory module is provided. A plurality of DRAMs is mounted on a PCB. At least one DRAM has an operating parameter different from other DRAMs according to a position where the at least one DRAM is mounted on the PCB. | 03-05-2015 |
20150063000 | SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME - A semiconductor device comprises a bit determination circuit to count the number of bits at a first level in an input address signal formed of a plurality of bits and to output a result indicating whether or not a value of the count exceeds a predetermined determination threshold value, as a bit determination result signal, and a selection control circuit to select a non-volatile program element to be cut off, based on the bit determination result signal and the address signal. Additional apparatus and methods are described. | 03-05-2015 |
20150063001 | SEMICONDUCTOR DEVICE - Disclosed herein is a semiconductor device that includes a plurality of memory cells assigned with addresses that are different from each other, a redundant memory cell replacing a defective memory cell among the memory cells, a fuse circuit storing an address of the defective memory cell, an access control circuit accessing the redundant memory cell when the address of the defective memory cell stored in the fuse circuit is supplied, and a roll call circuit outputting the address of the defective memory cell to outside the semiconductor device in a serial manner. | 03-05-2015 |
20150070963 | MEMORY PROGRAMMING METHOD AND APPARATUS - The memory programming apparatus includes a memory reader configured to read a read data in a plurality of cells related with an address of a programmable memory; and a memory writer configured to record a write data on the plurality of cells to compare the write data with the read data, to generate a re-writing pattern, and to correct at least one mismatch cell among the plurality of cells. Accordingly, it may be possible to reduce a programming processing time and to increase a yield rate. | 03-12-2015 |
20150085557 | MEMORY HAVING ONE TIME PROGRAMMABLE (OTP) ELEMENTS AND A METHOD OF PROGRAMMING THE MEMORY - A method of programming a memory includes selecting a logic state for programming a first bitcell of the memory. A first one-time-programmable (OTP) element of the first bitcell is programmed using a first set of conditions intended to achieve a first target resistance in accordance with the selected logic state which results in a first degree of programming of the first OTP element. A second OTP element of the first bitcell is programmed using a second set of conditions different from the first set of conditions intended to achieve a second target resistance in accordance with the selected logic state which results in a second degree of programming of the second OTP element, wherein the first and second degrees of programming are visually indistinguishable. | 03-26-2015 |
20150103579 | MEMORY DEVICE, WRITING METHOD, AND READING METHOD - A memory device includes a memory cell which has one cell selection section and a storage section which is connected in series with respect to the cell selection section and which is selected as an access target for writing or reading by the cell selection section, in which the storage section is provided with a plurality of memory elements which are able to be written one time only and where information is held by changing resistance values in a non-written state and a written state. | 04-16-2015 |
20150109848 | MECHANISMS FOR BUILT-IN SELF TEST AND REPAIR FOR MEMORY DEVICES - A method of storing repair data of a memory array in a one-time programming memory (OTPM) includes performing a first test and repair of the memory array using a built-in self-test-and-repair (BISTR) module to determine first repair data. The method includes loading the first repair data in a repair memory and in a duplicated repair memory of the BISTR module. The method includes performing a second test and repair to determine second repair data. The method includes storing the second repair data in the repair memory of the BISTR module and in the repair memory of the memory array. The method includes processing the repair data in the repair memory and the duplicated repair memory of the BISTR module. The method includes storing the output of the logic gate in the repair memory of the memory array. The method includes storing content of the repair memory in the OTPM. | 04-23-2015 |
20150117083 | MEMORY DEVICE - A memory device including: a memory cell array including normal memory cells and spare memory cells arranged in rows and columns including normal columns including the normal memory cells and at least one spare column including spare memory cells, a segment match determining circuit configured to compare a segment address with row address information corresponding to a failed segment and to generate a load control signal, and a column match determining circuit configured to compare column address information corresponding to a failed column in response to the load control signal with a column address and to generate a column address replacement control signal, wherein the memory cells connected to fail columns of the fail segment are replaced with memory cells connected to columns of the spare memory cells in response to the column address replacement control signal. | 04-30-2015 |
20150138866 | SEMICONDUCTOR MEMORY - According to an embodiment, a semiconductor memory includes word lines, a plurality of sets of a pair of bit lines, memory cells, a writing/reading circuit, and a word line selection circuit. In a state where inverted data of program data has been written to the memory cells, a stress is applied and the program data is programmed to the memory cells. The writing/reading circuit writes the inverted data of the same program data to a unit memory cell group made of memory cells connected to a set of a pair of bit lines at a time of programming, and reads data from the unit memory cell group by detecting a signal level of the pair of bit lines at a time of reading. The word line selection circuit simultaneously selects and drives two or more word lines of the word lines connected to the unit memory cell group. | 05-21-2015 |
20150146471 | ANTI-FUSE ARRAY OF SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - An anti-fuse array includes: a plurality of first transistors having a matrix structure over a semiconductor substrate; a plurality of second transistors respectively disposed adjacent to first ends of the plurality of first transistors along a first direction of the matrix structure; and a plurality of third transistors respectively disposed at second ends of the plurality of first transistors along a second direction. | 05-28-2015 |
20150294732 | Circuit and System of Using Junction Diode as Program Selector for One-Time Programmable Devices with Heat Sink - Junction diodes fabricated in standard CMOS logic processes can be used as program selectors with at least one heat sink or heater to assist programming for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The heat sink can be at least one thin oxide area, extended OTP element area, or other conductors coupled to the OTP element to assist programming. A heater can be at least one high resistance area such as an unsilicided polysilicon, unsilicided active region, contact, via, or combined in serial, or interconnect to generate heat to assist programming. The OTP device has at least one OTP element coupled to at least one diode in a memory cell. The diode can be constructed by P+ and N+ active regions in a CMOS N well, or on an isolated active region as the P and N terminals of the diode. The isolation between P+ and the N+ active regions of the diode in a cell or between cells can be provided by dummy MOS gate, SBL, or STI/LOCOS isolations. The OTP element can be polysilicon, silicided polysilicon, silicide, polymetal, metal, metal alloy, local interconnect, metal-0, thermally isolated active region, CMOS gate, or combination thereof. | 10-15-2015 |
20150294736 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM - A semiconductor device includes a nonvolatile memory block suitable for outputting data stored in a plurality of nonvolatile memory cells included therein based on first control information, and programming data in the nonvolatile memory cells based on second control information; a control block suitable for generating the first control information based on an initialization signal, wherein the control block sequentially generates the second control information and the first control information when a program mode is activated; and a test control block suitable for deactivating the nonvolatile memory block and determining whether at least one control signal among a plurality of control signals included in the first and second control information is normally generated, in a test operation on the program mode. | 10-15-2015 |
20150302932 | MEMORY DEVICE, SEMICONDUCTOR UNIT AND METHOD OF OPERATING THE SAME, AND ELECTRONIC APPARATUS - A semiconductor unit with memory devices, each of the memory devices includes: a first semiconductor layer; second and third semiconductor layers; a first dielectric film and a first conductive film; first, second, and third electrodes electrically connected to the second semiconductor layer, the third semiconductor layer, and the first conductive film, respectively, the third electrode being electrically connected to the first electrode. In the memory devices, when a voltage equal to or higher than a predetermined threshold value is applied between the first and second electrodes, a filament that is a conductive path electrically linking the second and third semiconductor layers is formed in the region between the second and third semiconductor layers, and thereby, writing operation of information is performed. | 10-22-2015 |
20150310924 | READ-ONLY MEMORY - A configuration for a bit-1 read-only memory (ROM) cell is provided. The bit-1 ROM cell comprises a first circuit connected to a second circuit. The first circuit comprises a first transistor and the second circuit comprises a second transistor. The second circuit is configured to receive a YMUX signal. The second circuit is connected to a word-line bar. The second circuit is configured to maintain a disconnection or connection between the first transistor and the word-line bar based upon the YMUX signal. The first circuit is located on a different physical layer than the second circuit. | 10-29-2015 |
20150310925 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - A semiconductor memory device includes a fuse array block including a plurality of fuses programmed with state information, an operation direction control block suitable for controlling a program operation direction and a boot-up operation direction of the fuse array block, and a fuse information loading block suitable for loading the state information which is programmed in the plurality of fuses of the fuse array block through the boot-up operation. | 10-29-2015 |
20150310926 | SEMICONDUCTOR DEVICE INCLUDING FUSE CIRCUIT - Disclosed here is a semiconductor device that comprises a plurality of input nodes configured to be supplied with input signals, a decoder coupled to the input nodes, the decoder configured to decode the input signals and output decoded signals, and a plurality of fuse circuits provided correspondingly with the decoded signals and configured to be programmed responsive to the decoded signals, respectively. | 10-29-2015 |
20150310927 | LOW-PIN-COUNT NON-VOLATILE MEMORY INTERFACE WITH SOFT PROGRAMMING CAPABILITY - A low-pin-count non-volatile (NVM) memory with no more than two control signals that can at least program NVM cells, load data to be programmed into output registers, or read the NVM cells. At least one of the NVM cells has at least one NVM element coupled to at least one selector and to a first supply voltage line. The selector is coupled to a second supply voltage line and having a select signal. No more than two control signals can be used to select the at least one NVM cells in the NVM sequentially for programming the data into the at least one NVM cells or loading data into the at least one output registers. Programming into the NVM cells, or loading data into output registers, can be determined by the voltage levels of the first to the second supply voltage lines. | 10-29-2015 |
20150310939 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR REPAIR SYSTEM INCLUDING THE SAME, AND METHOD FOR OPERATING THE SEMICONDUCTOR DEVICE - A semiconductor device includes: a plurality of fuse arrays each including a plurality of fuses; a selection block which selects one fuse array among the fuse arrays in response to values of a group of bits of a repair code; a code alignment block which aligns disposition of bits other than the group of bits of the repair code, wherein the alignment disposition is changed based on the fuse array selected in the selection block; and an operation block which controls an operation of the fuse array selected in the selection block in response to a repair command and an output code of the code alignment block. | 10-29-2015 |
20150318050 | MEMORY ARRAY AND OPERATION METHOD FOR MEMORY DEVICE - A method for operating a memory is disclosed. The memory has an array of memory cells arranged in a plurality of rows and columns. Each row includes a label storage unit. The method includes receiving a first to-be-programmed data set to be stored into a target row and determining whether a condition is satisfied. When the condition is satisfied, performing a first operation on the first to-be-programmed data set to obtain a second to-be-programmed data set, programming the second to-be-programmed data set into the target row of memory cells, and setting the value of the label storage, unit to be a first labeling value. When the condition is not satisfied, performing a second operation on the first to-be-programmed data set to program the first to-be-programmed data set into the target row of memory cells, and setting the value of the label storage unit to be a second labeling value. | 11-05-2015 |
20150325310 | DIELECTRIC-BASED MEMORY CELLS HAVING MULTI-LEVEL ONE-TIME PROGRAMMABLE AND BI-LEVEL REWRITEABLE OPERATING MODES AND METHODS OF FORMING THE SAME - A method of programming a memory cell is provided. The memory cell includes a memory element having a first conductive material layer, a first dielectric material layer above the first conductive material layer, a second conductive material layer above the first dielectric material layer, a second dielectric material layer above the second conductive material layer, and a third conductive material layer above the second dielectric material layer. One or both of the first and second conductive material layers comprises a stack of a metal material layer and a highly doped semiconductor material layer. The memory cell has a first memory state upon fabrication corresponding to a first read current. The method includes applying a first programming pulse to the memory cell with a first current limit. The first programming pulse programs the memory cell to a second memory state that corresponds to a second read current greater than the first read current. | 11-12-2015 |
20150325316 | REPAIR CIRCUIT AND FUSE CIRCUIT - A repair circuit includes first and second fuse circuits, a determination circuit and an output circuit. The first fuse circuit includes a first fuse and is configured to generate a first master signal indicating whether the first fuse has been programmed. The second fuse circuit includes second fuses and is configured to generate a first address indicating whether each of the second fuses has been programmed. The determination circuit is configured to generate a detection signal based on the first master signal and the first address. The detection signal indicates whether a negative program operation has been performed on the second fuse circuit. The output circuit is configured to generate a second master signal based on the first master signal and the detection signal and generate a repair address corresponding to a defective input address based on the first address and the detection signal. | 11-12-2015 |
20150340077 | APPARATUSES AND METHODS FOR CONTROLLING REFRESH OPERATIONS - An apparatus includes a first word line, a second word line and a control. The second word line is contiguous to the first word line. The control circuit includes a first defective address storing circuit and a first detection circuit. The first defective address storing circuit stores first enable information along with first defective address. The first enable information indicates whether or not the second word line is functional. The first detection circuit provides a first signal when the first word line is accessed. The first signal indicates whether or not the second word line is functional. The control circuit activates the second word line when the first signal indicates that the second word line is functional and does not activate the second word line when the first signal indicates that the second word line is not functional. | 11-26-2015 |
20150348645 | RELIABLE READOUT OF FUSE DATA IN AN INTEGRATED CIRCUIT - An integrated circuit includes fuse readout logic and first and second sets of fuses. One of the sets includes one or more primary fuses whose burn states represent respective bit values, and the other of the sets includes one or more secondary fuses whose burn states are indicative of the bit values stored in the primary fuses. The fuse readout logic is configured to read the bit values by sensing the burn states of the primary fuses, and to conditionally correct the read bit values by sensing the burn states of one or more of the secondary fuses. | 12-03-2015 |
20150357051 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a memory cell array region having a plurality of normal cell lines and a plurality of repair cell lines; a plurality of normal cell line selection units suitable for selecting the plurality of normal cell lines, respectively, in response to a local address; a plurality of repair cell line selection units suitable for selecting the plurality of repair cell lines, respectively, in place of normal cell line selection units corresponding to fail information of the local address; a fuse driving unit comprising a fuse array in which the fail information is programmed, suitable for disabling the normal cell line selection units corresponding to the fail information, and enabling normal cell line selection units unrelated to the fail information; and an address determination unit suitable for controlling the plurality of repair cell line selection units based on the fail information. | 12-10-2015 |
20150357052 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a memory cell array region having a plurality of normal cell lines and a plurality of repair cell lines; a plurality of normal cell line selection units suitable for selecting the plurality of normal cell lines, respectively, in response to a local address; a plurality of repair cell line selection units suitable for selecting the plurality of repair cell lines, respectively, in place of normal cell line selection units corresponding to fail information of the local address; a fuse driving unit comprising a fuse array in which the fail information is programmed, suitable for disabling the normal cell line selection units corresponding to the fail information, and enabling normal cell line selection units unrelated to the fail information; and an address determination unit suitable for controlling the plurality of repair cell line selection units based on the fail information. | 12-10-2015 |
20150364209 | METHOD FOR CONTROLLING THE BREAKDOWN OF AN ANTIFUSE MEMORY CELL - A method for controlling the breakdown of an antifuse memory cell formed on a semiconductor substrate, including the steps of: applying a programming voltage; detecting a breakdown time; and interrupting the application of the programming voltage at a time following the breakdown time by a post-breakdown time. | 12-17-2015 |
20150364210 | SEMICONDUCTOR DEVICE WITH FUSE ARRAY AND METHOD FOR OPERATING THE SAME - A semiconductor device includes a fuse array including verification fuses and normal fuses, a determination block suitable for reading data programmed in the verification fuses based on a read reference voltage and during a boot-up preparation section, determining whether or not a read value is the same as a predetermined value, and a level control block suitable for adjusting a level of the read reference voltage based on a determined result during the boot-up preparation section. | 12-17-2015 |
20150380103 | ONE-TIME PROGRAMMABLE MEMORY CELL AND CIRCUIT - An OTP memory cell and an OTP memory circuit. The OTP memory cell having a memory module, a write module, a read module, and a load module. Data may be written into the memory module once the write module is active; and data may be read out of the memory module once the read module is active. The OTP memory cell may also have a first latch module and a second latch module. | 12-31-2015 |
20150380104 | LATCH CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A latch circuit includes a write driving unit configured to output fuse data as boot-up data according to a fuse set select signal in a boot-up operation; and a latch set configured to latch the boot-up data when a latch select signal is activated in the boot-up operation, and output data latched as the latch select signal is activated as a repair column address in a normal operation. | 12-31-2015 |
20150380105 | SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME - The semiconductor system includes a controller and a semiconductor device. The controller outputs commands and receives an output datum to discriminate whether at least one of a plurality of fuse cells abnormally operates. The semiconductor device compares logic levels of a plurality of fuse data generated from the plurality of fuse cells with each other, thereby generating a flag signal enabled when at least one of the logic levels of the plurality of fuse data is different from the other logic levels while a boot-up operation is executed according to a combination of the commands. In addition, the semiconductor device outputs the flag signal as the output datum while a read operation is executed according to a combination of the commands. | 12-31-2015 |
20160005494 | E-FUSE TEST DEVICE AND SEMICONDUCTOR DEVICE INCLUDINGTHE SAME - An e-fuse test device is provided. The e-fuse test device may include a first transistor, and a fuse array connected to a source/drain terminal of the first transistor. The fuse array may include n fuse groups, each of the fuse groups may include one end, the other end, and m first fuse elements connected in series to each other between the one end and the other end, the one end of each of the fuse groups may be connected to each other, and the other end of each of the fuse groups may be connected to the source/drain terminal of the first transistor, and the n and m are natural numbers that are equal to or larger than two. | 01-07-2016 |
20160005496 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - A semiconductor memory device includes a memory cell array including a plurality of word lines; a repair fuse section programmed with one or more repair-target addresses and fuse enable information; an address generation section suitable for generating test addresses during a test operation, corresponding to the word lines based on the repair-target addresses and the fuse enable information; and a word line control section suitable for selectively activating the word lines based on the test addresses. | 01-07-2016 |
20160012908 | E-FUSE ARRAY CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS HAVING THE SAME | 01-14-2016 |
20160012909 | DATA STORAGE CIRCUIT AND SYSTEM INCLUDING THE SAME | 01-14-2016 |
20160013193 | ONE TIME PROGRAMMING MEMORY CELL, ARRAY STRUCTURE AND OPERATING METHOD THEREOF | 01-14-2016 |
20160027531 | APPARATUSES AND METHODS FOR TARGETED REFRESHING OF MEMORY - Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory. | 01-28-2016 |
20160035434 | MEMORY ARRAY, MEMORY DEVICE, AND METHODS FOR READING AND OPERATING THE SAME - The present invention provides a memory. The memory includes a plurality of memory cells arranged as an array with a plurality of rows and a plurality of column. A memory cell is connected to at least one redundant memory cell in a same row for storing same data as the memory cell; and a column of memory cells correspond to one redundant column of redundant memory cells wherein each redundant memory cell in the redundant column stores same data as the memory cell in a same row. | 02-04-2016 |
20160035435 | MEMORY CIRCUIT - A memory circuit includes: a control part configured to output a control signal; a fuse circuit which is driven by the control signal and is configured to output a fuse signal whose signal level is determined based on a state of a first fuse element; and a holding circuit configured to update and hold a signal based on the fuse signal in response to the control signal output from the control part and output the held signal as an output signal. | 02-04-2016 |
20160035438 | MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A memory device includes a non-volatile memory circuit suitable for storing system hard repair data, a temporary memory circuit suitable for storing system soft repair data, a system register circuit suitable for receiving and storing the system hard repair data or the system soft repair data during a boot-up operation, and a memory bank suitable for performing a repair operation based on first data stored in the system register circuit. | 02-04-2016 |
20160035439 | MEMORY ARRAY, MEMORY DEVICE, AND METHODS FOR READING AND OPERATING THE SAME - The present disclosure provides a memory. The memory includes an array of memory cells arranged as a plurality of rows by a plurality of columns. A memory cell is connected to at least one redundant memory cell in series in a same row for storing same data as the memory cell; and a column of memory cells correspond to at least one redundant column of redundant memory cells wherein each redundant memory cell in the at least one redundant column stores same data as the memory cell in a same row. | 02-04-2016 |
20160042804 | ELECTRONIC APPARATUS AND ELECTRONIC FUSE THEREOF - An electronic apparatus and an electronic fuse (e-fuse) thereof are provided. The e-fuse includes a transistor and a voltage selector. A first end of the transistor receives a power voltage, and a second end of the transistor is coupled to a reference ground voltage. The voltage selector receives a programming voltage and a read voltage, and outputs the programming voltage or the read voltage to a control end of the transistor according to a control signal. Wherein, the control signal is used to indicate the e-fuse being operated in a programming mode or a read mode. When the e-fuse is operated in the programming mode, the programming voltage is provided to the control end of the transistor for damaging a gate oxide layer of the transistor. | 02-11-2016 |
20160042805 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes a fuse portion including a first fuse set having a plurality of first fuses assigned for a first mode and a second fuse set having a plurality of second fuses assigned for a second mode, and a program portion suitable for programming an available fuse among the first fuses included in the first fuse set or programming the second fuses included in the second fuse set in response to a repair control signal in the second mode. | 02-11-2016 |
20160042813 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR TESTING REDUNDANCY WORD LINE - A semiconductor memory device includes a plurality of redundancy cells suitable for repairing a defective cell of a plurality of normal cells, a defective redundancy cell information storing circuit block suitable for detecting whether the redundancy cells are defective and storing information on a redundancy cell that is detected to be defective, and a defective redundancy cell rupture circuit block suitable for performing a disable rupture operation on the redundancy cell that is detected to be defective. | 02-11-2016 |
20160049207 | CONFIGURATION FUSE DATA MANAGEMENT IN A PARTIAL POWER-ON STATE - In an embodiment, an apparatus may include a plurality of circuit blocks, a plurality of fuses and circuitry. The circuitry may be configured to determine a state for each of the plurality of fuses in response to transitioning from an off mode to a first operating mode. A first number of circuit blocks may be enabled in the first operating mode. The circuitry may also be configured to initialize the first number of circuit blocks dependent upon the states of one or more of the plurality of fuses and to transition from the first operating mode to a second operating mode. A second number of circuit blocks, less than the first number, may be enabled in the second operating mode. The circuitry may also be configured to store data representing the states of a subset of the plurality of fuses into a first memory enabled in the second operating mode. | 02-18-2016 |
20160055920 | SEMICONDUCTOR MEMORY DEVICE AND MEMORY MODULE HAVING RECONFIGURATION REJECTING FUNCTION - A semiconductor memory device and a memory module have a reconfiguration rejecting function. The semiconductor memory device may include a memory cell array, a test information storing unit, and a control unit. The control unit may include a control signal storing unit and may reject programming of the test information storing unit according to a control signal stored in the control signal storing unit. | 02-25-2016 |
20160056163 | NON-VOLATILE MEMORY AND SEMICONDUCTOR DEVICE - There is provided a non-volatile memory including: plural zener zap devices, each including a cathode region and an anode region formed in a well; and a metal wiring line that is formed above the plural zener zap devices, that is commonly connected to each of the cathode regions, and that supplies a write voltage to each of the zener zap devices. | 02-25-2016 |
20160064058 | CONFIGURATION AND TESTING FOR MAGNETORESISTIVE MEMORY - Techniques and circuits for testing and configuring magnetic memory devices are presented. Registers and nonvolatile storage is included on the memory devices for storing values used to control testing of the memory devices as well as for configuring parameters related to both testing and normal operation. Examples include adjustment of bias voltages, sense amplifier offset values, and timing parameters to improve the efficiency of testing operations as well as improve reliability and speed of normal operation. | 03-03-2016 |
20160071582 | Method and System of programmable resistive devices with Read Capability Using a Low Supply Voltage - A Programmable Resistive Device (PRD) memory that can be read under low voltage is disclosed. The PRD includes at least one Programmable Resistive Element (PRE) having one end coupled to a first supply voltage line and the other end coupled to at least one selector and at least one read selector. The read selector includes at least one read source line (SLR) and/or one read enable (ENR) coupled to a second and/or a third supply voltage lines, respectively. The read selector includes at least one MOS device built by core logic device. The PRE in the at least one PRD cells can be configured to be readable by applying voltages to the first, second, and/or the third voltage supply lines to thereby sense the PRE resistance to a logic state. The programmable resistive element can have at least one element in an OTP, MTP, floating gate device, anti-fuse, or emerging memory such as PCRAM, RRAM, or MRAM, etc. | 03-10-2016 |
20160071613 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING FUSE BLOCK - A semiconductor integrated circuit device includes a plurality of column repair address lines configured to cross and a plurality of mat select lines; a fuse set unit including a plurality of latch units electrically coupled with the plurality of column repair address lines and the plurality of mat select lines; a fuse driving unit configured to provide fuse data to the latch units through the plurality of column repair address lines; and an equalizer configured to equalize the fuse data to a same level in response to a select signal of the fuse set unit and a boot-up signal of the fuse set unit. | 03-10-2016 |
20160078962 | ANTI-FUSE TYPE ONE-TIME PROGRAMMABLE MEMORY CELL AND ANTI-FUSE TYPE ONE-TIME PROGRAMMABLE MEMORY CELL ARRAYS - An anti-fuse type OTP memory cell includes a first anti-fuse transistor having a first channel width, a first selection transistor sharing a first active region with the first anti-fuse transistor and having a second channel width that is greater than the first channel width, a second anti-fuse transistor sharing a program gate with the first anti-fuse transistor and having a third channel width, and a second selection transistor sharing a second active region with the second anti-fuse transistor and having a fourth channel width that is greater than the third channel width. | 03-17-2016 |
20160078963 | PROGRAMMING OF ANTIFUSE CELLS - For programming an antifuse memory, the power consumption of the memory is assessed during programming mode. The power consumption is compared with a threshold. When the threshold is exceeded, indicative of successful programming of the antifuse memory cell, the programming mode is terminated. | 03-17-2016 |
20160078964 | METHOD FOR TESTING REDUNDANCY AREA IN SEMICONDUCTOR MEMORY DEVICE - A method tests a redundancy area of a semiconductor memory device. The method includes receiving a redundancy address to select a redundancy area including spare memory cells to repair normal memory cells, checking the redundancy address based on repair use information to determine whether the redundancy area is an actually repaired area, enabling the redundancy area when the redundancy area is the actually repaired area, and outputting data read from the enabled redundancy area to practically perform a redundancy area test. | 03-17-2016 |
20160078968 | MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A memory device includes: a non-volatile memory circuit suitable for storing hard repair data; a data bus suitable for transmitting the hard repair data during a boot-up operation, and transmitting soft repair data during a soft repair mode; a plurality of registers suitable for storing repair data transmitted through the data bus and activated when the transmitted repair data is stored; a control circuit suitable for selecting a register to store the transmitted repair data among the plurality of the registers, and during the soft repair mode, deactivating a register that stores the same data as the transmitted repair data; and a memory bank suitable for performing a repair operation based on the data stored in a register that is activated among the plurality of the registers. | 03-17-2016 |
20160078969 | EFFICIENT CODING FOR MEMORY REDUNDANCY - A system may be provided that provides redundancy for a plurality of embedded memories such as SRAMs. The system may include one or more decoders, each capable of decoding a selection address to identify a defective one of the embedded memories. | 03-17-2016 |
20160086649 | SMART REFRESH DEVICE - A smart refresh device includes an address control block configured to determine whether a specific row address is a row hammer address, and invert a first row hammer address and perform an addition/subtraction of an address; a repair control block configured to determine whether the row hammer address is a repaired address and output a stored repair address as a second repair control signal; a repair address storage block configured to store an output address of the address control block and output a stored address as a latch address; a fuse block configured to output a repair signal representing information on a repair address to the repair control block, and output a decoding signal according to the latch address; and an operator configured to add and subtract the decoding signal according to an addition signal and a subtraction signal. | 03-24-2016 |
20160093403 | METHOD AND APPARATUS FOR IN-SYSTEM REPAIR OF MEMORY IN BURST REFRESH - In a repair of a random access memory (RAM), an error information is received, a fail address of the RAM identified, and a one-time programming applied to a portion of the redundancy circuit while a content of the RAM is valid. Optionally, the RAM is a dynamic access RAM (DRAM), a refresh burst is applied to the DRAM, followed by a non-refresh interval, and the one-time programming is performed during the non-refresh interval. | 03-31-2016 |
20160099074 | FUSE CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME - A fuse circuit includes an E-fuse array including a plurality of E-fuse elements configured to store fuse data; a latch block including a plurality of latch groups configured to latch the fuse data read from the E-fuse array; and a control block configured to output latch reset signals corresponding to the plurality of latch groups in response to an apparatus reset signal and a clock signal, wherein the control block sequentially enables the latch reset signals. | 04-07-2016 |
20160099075 | FUSE ARRAY CIRCUIT AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A fuse array circuit includes a power generation block suitable for generating a driving power to be level-shifted at least once in a read operation period, a word line driving block suitable for driving a word line by using the driving power, and a fuse array suitable for outputting information programmed in a fuse that is activated by the driven word line through a bit line. | 04-07-2016 |
20160099077 | TEST SYSTEM SIMULTANEOUSLY TESTING SEMICONDUCTOR DEVICES - Individual memory chips are simultaneously tested by a tester using selectively enabled stress modules that apply a corresponding stress test to memory cells, wherein each stress test is associated with a corresponding failure attribute for the memory cells. Built-in self-test (BIST)/built-in self-stress (BISS) circuitry is provided in each stress module and may configured to selectively apply one or more stress test(s) during the simultaneous testing of a plurality of memory chips. | 04-07-2016 |
20160099079 | REPAIR CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME - A repair circuit includes a fuse set latch array including a plurality of fuse set latches, and configured to store fuse informations in target fuse latches selected among the plurality of fuse set latches in response to fuse latch select signals; a fuse information control unit configured to generate the fuse latch select signals by using boot-up source signals generated by differently combining boot-up mode region select informations according to a region determination signal; and a repair processing unit configured to compare an address inputted from an exterior and the fuse informations, and access a normal memory cell corresponding to the external address or a redundant memory cell. | 04-07-2016 |
20160104542 | MEMORY CELL CAPABLE OF OPERATING UNDER LOW VOLTAGE CONDITIONS - A memory cell includes a programming selection transistor, a following gate transistor, an antifuse element, and a reading circuit. A charging current formed by the antifuse element may trigger the reading circuit to form a stable read current during a reading operation of the memory cell so that the time for reading data from the memory cell can be shortened. A discharging process may be operated in the beginning of the reading operation of the memory cell so that the window of time for reading data from the memory cell can be widened. | 04-14-2016 |
20160111168 | MEMORY CIRCUIT HAVING NON-VOLATILE MEMORY CELL AND METHODS OF USING - One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first anti-fuse device, a first select device connected in series with the first anti-fuse device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell. The NVM cell may have two NV elements that are separately programmable and are separately selectable via separate access transistors to drive the VM input node. | 04-21-2016 |
20160111171 | MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A memory device may include an address latch circuit that latches an address received from an exterior of the memory device, a repair signal generation circuit that generates a soft repair signal, a selection information generation circuit that generates first selection information by using first bits of a latched address latched by the address latch circuit, first to N | 04-21-2016 |
20160111172 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a plurality of repair fuse circuits configured to each program a repair target address; and an enable signal generation circuit configured to generate at least one enable signal in response to a source signal and provide the enable signal to each of the repair fuse circuits in common. Since the semiconductor device may iteratively generate a rupture enable signal through a feedback scheme, the area occupied by a circuit, such as a shift register or a D flip-flop may be saved. | 04-21-2016 |
20160118139 | SEMICONDUCTOR DEVICES - A semiconductor device may include a fuse controller and a fuse array. The fuse controller may be configured to generate internal address signals according to a level combination of repair data and may generate first and second voltage control signals in response to a rupture control signal that is enabled to rupture a predetermined fuse set for selecting a failed redundancy word line, in a test mode. The fuse array may include a plurality of fuse sets including the predetermined fuse set. Each of the plurality of fuse sets may be selected according to a level combination of the internal address signals, and the fuse array ruptures the predetermined fuse set for selecting the failed redundancy word line in response to the first and second voltage control signals to output fuse data. | 04-28-2016 |
20160125953 | OTP CELL WITH REVERSED MTJ CONNECTION - A one time programming (OTP) apparatus unit cell includes magnetic tunnel junctions (MTJs) with reversed connections for placing the MTJ in an anti-parallel resistance state during programming. Increased MTJ resistance in its anti-parallel resistance state causes a higher programming voltage which reduces programming time and programming current. | 05-05-2016 |
20160133335 | SEMICONDUCTOR DEVICE CAPABLE OF RESCUING DEFECTIVE CHARACTERISTICS OCCURRING AFTER PACKAGING - A memory device capable of rescuing defective characteristics that occur after packaging includes a memory cell array including a plurality of memory cells and an antifuse circuit unit including at least one antifuse. The antifuse circuit unit stores a defective cell address of the memory cell array in the at least one antifuse and reads the defective cell address to an external source. The antifuse circuit unit stores a defective characteristic code in the at least one antifuse, wherein the defective characteristic code is related to at least one of a timing parameter spec., a refresh spec., an input/output (I/O) trigger voltage spec., and a data training spec. of the memory device, and outputs the defective characteristic code to an external source. | 05-12-2016 |
20160141295 | ONE TIME PROGRAMMABLE MEMORY CELL AND METHOD FOR PROGRAMMING AND READING A MEMORY ARRAY COMPRISING THE SAME - A one time programmable (OTP) memory cell includes a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor has a first gate terminal, a first drain terminal and a first source terminal. The following gate transistor has a second gate terminal, a second drain terminal and a second source terminal coupled to the first drain terminal. The antifuse varactor has a third gate terminal, a third drain terminal, and a third source terminal coupled to the second drain terminal. The select gate transistor, the following gate transistor, and the antifuse varactor are formed on a substrate structure. | 05-19-2016 |
20160148705 | ONE-TIME PROGRAMMABLE (OTP) MEMORY CELL AND OTP MEMORY DEVICE FOR MULTI-BIT PROGRAM - A one-time programmable (OTP) memory device includes a memory cell array including a plurality of OTP memory cells, the plurality of OTP memory cells being connected to a plurality of bitlines, a plurality of voltage wordlines and a plurality of read wordlines, respectively; and a switching circuit configured to, in a program mode, detect program states of the plurality of OTP memory cells to block currents from flowing through the plurality of OTP memory cells from the voltage wordlines to the bitlines based on the detected program states. | 05-26-2016 |
20160163399 | NON-VOLATILE MEMORY, SEMICONDUCTOR DEVICE AND READING METHOD - There is provided a non-volatile memory circuit including: plural storage element sections each including a zener zap device and a switch section that connects an anode of the zener zap device to an output terminal during data reading; and wherein cathodes of respective zener zap devices of the plural storage element sections are commonly connected so as to be connected to a power supply employed in the writing or to a power supply employed in the reading, wherein the output terminals of the plural storage element sections are commonly connected to an input terminal of a detector, an anode of each of the storage element sections being connected to a ground voltage during data writing, and wherein the switch section is switched ON during data reading so as to connect the anode of the storage element section through the output terminal to the input terminal of the detector. | 06-09-2016 |
20160172053 | OTP MEMORY CAPABLE OF PERFORMING MULTI-PROGRAMMING AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME | 06-16-2016 |
20160180961 | IMPLEMENTING HIDDEN SECURITY KEY IN EFUSES | 06-23-2016 |
20160180962 | IMPLEMENTING HIDDEN SECURITY KEY IN EFUSES | 06-23-2016 |
20160180963 | CIRCUIT AND METHOD FOR REDUCING WRITE DISTURB IN A NON-VOLATILE MEMORY DEVICE | 06-23-2016 |
20160180969 | POST PACKAGE REPAIR DEVICE | 06-23-2016 |
20160181260 | FUSE CELL CIRCUIT, FUSE CELL ARRAY AND MEMORY DEVICE INCLUDING THE SAME | 06-23-2016 |
20160189793 | USE OF IN-FIELD PROGRAMMABLE FUSES IN THE PCH DYE - A processor has a limited set of guard bands that the processor uses, and when a certain amount of stress is accumulated as indicated by the cumulative stress counters (S | 06-30-2016 |
20160189800 | SEMICONDUCTOR DEVICE INCLUDING REDUNDANCY CELL ARRAY - Provided is a semiconductor device and a manufacturing method thereof. The semiconductor device may include a first cell array, a first fuse circuit, a first spare cell array, a second spare cell array, and a redundancy select controller. The first fuse circuit may be configured to store a first failed address corresponding to one or more defective memory cells in the first cell array. Each of the first and second spare cell arrays may include a plurality of spare memory cells configured to replace first and second defective memory cells in the first cell array, respectively. For replacing the first and second defective memory cells, the redundancy select controller may be configured to selectively assign the first fuse circuit to either one or both of the first and second spare cell arrays. | 06-30-2016 |
20160196880 | FUSE ELEMENT PROGRAMMING CIRCUIT AND METHOD | 07-07-2016 |
20160196881 | REPAIR INFORMATION STORAGE CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME | 07-07-2016 |
20160254043 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME | 09-01-2016 |
20160379719 | SEMICONDUCTOR DEVICE AND METHOD FOR WRITING THERETO - A semiconductor device ( | 12-29-2016 |
20160379720 | Write Enhancement for One Time Programmable (OTP) Semiconductors - A method of programming one-time programmable (OTP) memory cells in an array is described. Each memory cell has a MOSFET programming element and a MOSFET pass transistor, the MOSFET pass transistor having a gate electrode over a channel region between two source/drain regions, and the MOSFET programming element having a gate electrode over a channel region contiguous to a source/drain region either part of, or connected to, one of the two source/drains associated with the MOSFET pass transistor. The other source/drain region of the MOSFET pass transistor is coupled to a bit line. The memory cell is programmed by setting a first voltage of a first polarity on the gate electrode of the pass transistor to electrically connect the source/drain regions of the pass transistor; setting a second voltage of the first polarity on the gate electrode of the programming element; and setting a third voltage of a second polarity on the bit line. The voltage across an oxide layer between the gate electrode and channel region of the programming element ruptures the oxide layer and effectively programs the programming element. | 12-29-2016 |
20170236571 | IMPLEMENTING EFUSE VISUAL SECURITY OF STORED DATA USING EDRAM | 08-17-2017 |
20180025785 | ONE-TIME PROGRAMMABLE MEMORY DEVICE | 01-25-2018 |
20190147967 | PROGRAMMING DEVICE ARRANGED TO OBTAIN AND STORE A RANDOM BIT STRING IN A MEMORY DEVICE | 05-16-2019 |
20190147968 | ELECTRONIC DEVICE WITH A FUSE READ MECHANISM | 05-16-2019 |