Class / Patent application number | Description | Number of patent applications / Date published |
365185270 | Substrate bias | 28 |
20080266979 | METHODS OF BIASING A MULTI-LEVEL-CELL MEMORY - Methods are described for double-side-bias of multi-level-cell memory devices comprising a NAND array that comprises a plurality of charge trapping memory cells. A memory device is programmed by a double-side-bias electron injection technique and is erased by a double-side-bias hole injection technique. Each charge trapping memory cell includes 2 | 10-30-2008 |
20080266980 | METHODS FOR CONDUCTING DOUBLE-SIDE-BIASING OPERATIONS OF NAND MEMORY ARRAYS - Methods are described for double-side-biasing of a NAND memory array device comprising a plurality of charge trapping memory cells for programming and erasing the NAND memory array device. A double-side-biasing method applies a bias voltage simultaneously on a first junction (a source region) and a second junction (a drain region) so that a left bit and a right bit in a charge trapping memory cell can be programmed in parallel or erased in parallel. Random (or selective) bit program and random (or selective) bit erase can be achieved by using a double-side-biasing method on a NAND memory array device for both data and code application. A first type of double-side-biasing method is to program the NAND array with a double-side-bias electron injection. A second type of double-side-biasing method is to erase the NAND array with a double-side-bias hole injection. | 10-30-2008 |
20090003081 | Non-volatile memory and method of manufacturing same - The number of process steps for manufacturing a non-volatile memory is reduced while the performance of the non-volatile memory is improved. The non-volatile memory has a memory cell in which first, second and third P-type diffusion regions are formed in an N-type well, a select gate is formed via a select-gate insulating film over a channel between the first and second P-type diffusion regions, and a floating gate is formed via a floating-gate insulating film over a channel between the second and third P-type diffusion regions. The non-volatile memory has a peripheral circuit in which fourth and fifth P-type diffusion regions are formed in an N-type well, and a peripheral-circuit gate is formed via a peripheral-circuit gate insulating film over a channel between the fourth and fifth P-type diffusion regions. The film thickness of the floating-gate insulating film is greater than that of the select-gate insulating film and peripheral-circuit gate insulating film. | 01-01-2009 |
20090180332 | OPERATION METHOD OF NITRIDE-BASED FLASH MEMORY AND METHOD OF REDUCING COUPLING INTERFERENCE - A method for operating a nitride-based flash memory is provided. The operation method includes pre-performing an interference reduction operation (IRO) before the routine programming operating step. Through bias arrangement of the target memory cell, charges are injected into the charge trapping layer mainly above the junction regions of the memory cell before programming so as to reset the influences caused by coupling interference issues. The operation method of this present invention not only reduces coupling interference but also afford a wider operation window. | 07-16-2009 |
20090185429 | Non-volatile memory with single floating gate and method for operating the same - A non-volatile memory with single floating gate and the method for operating the same are proposed. The non-volatile memory is formed by embedding a FET structure in a semiconductor substrate. The FET comprises a single floating gate, a dielectric, and two ion-doped regions in the semiconductor at two sides of the dielectric. The memory cell of the proposed nonvolatile memory with single floating gate can perform many times of operations such as write, erase and read by means of a reverse bias. | 07-23-2009 |
20100002524 | FLOTOX-TYPE EEPROM - In designing a FLOTOX EEPROM of a dual cell type, a consideration should be given to the layout of cells for microminiaturization of the FLOTOX EEPROM. The FLOTOX EEPROM of the dual cell type includes two paired floating gates ( | 01-07-2010 |
20100067310 | MOS TRANSISTOR WITH A SETTABLE THRESHOLD - A MOS transistor comprising a conductive extension of its source region, insulated from its substrate, and partially extending under its channel. | 03-18-2010 |
20100220533 | NON-DIFFUSION JUNCTION SPLIT-GATE NONVOLATILE MEMORY CELLS AND ARRAYS, METHODS OF PROGRAMMING, ERASING, AND READING THEREOF, AND METHODS OF MANUFACTURE - Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of floating gates are spaced apart from one another and each insulated from the channel region. A plurality of control gates are spaced apart from one another and insulated from the channel region, with each control gate being located between a first floating gate and a second floating gate and capacitively coupled thereto to form a subcell. A plurality of spaced-apart assist gates are insulated from the channel region, with each assist gate being located between and insulated from adjacent subcells. The channel is formed of three regions, two beneath adjacent control gate elements as well as a third region between the first two and beneath an associated assist gate. | 09-02-2010 |
20100265773 | 3D MEMORY ARRAY ARRANGED FOR FN TUNNELING PROGRAM AND ERASE - A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory. | 10-21-2010 |
20110051525 | POWER SAVING METHOD AND CIRCUIT THEREOF FOR A SEMICONDUCTOR MEMORY - A power saving method for a semiconductor memory is provided. The power saving method for a semiconductor memory including the steps of receiving a plurality of address codes, each of which has a first part code and a second part code; and activating a first boost process when the first part code of a currently received address code is different from the first part code of a last received address code, otherwise a second boost process is activated. | 03-03-2011 |
20110116323 | SEMICONDUCTOR DEVICE, METHOD OF CONTROLLING THE SAME, AND METHOD OF MANUFACTURING THE SAME - The present invention provides a system comprising a semiconductor device, a method of controlling the semiconductor device in the system, and a method of manufacturing the semiconductor device in the system. The semiconductor device includes: a semiconductor region located in a semiconductor layer formed on an isolating layer; an ONO film on the semiconductor region; bit lines on either side of the semiconductor region, which are located in the semiconductor layer, and are in contact with the isolating layer; a device isolating region on two different sides of the semiconductor region from the sides on which the bit lines are located, the device isolating region being in contact with the isolating layer; and a first voltage applying unit that is coupled to the semiconductor region. In this semiconductor device, the semiconductor region is surrounded by the bit lines and the device isolating region, and is electrically isolated from other semiconductor regions. | 05-19-2011 |
20110182123 | FLASH MEMORY AND MANUFACTURING METHOD AND OPERATING METHOD THEREOF - A flash memory and a manufacturing method and an operating method thereof are provided. The flash memory includes a substrate, a charge-trapping structure, a first gate, a second gate, a third gate, a first doped region and a second doped region. The substrate has a protrusion portion. The charge-trapping structure is disposed over the substrate. The first gate and the second gate are disposed respectively over the charge-trapping structure at two sides of the protrusion portion. The top surfaces of the first gate and the second gate are lower than the top surface of the charge-trapping structure located on the top of the protrusion portion. The third gate is disposed over the charge-trapping structure located on the top of the protrusion portion. The first doped region and the second doped region are disposed respectively in the substrate at two sides of the protrusion portion. | 07-28-2011 |
20110305092 | NON-VOLATILE MEMORY DEVICE WITH CONTROLLED DISCHARGE - An electrically programmable non-volatile memory device being integrated on a chip of semiconductor material is proposed. The memory device includes a plurality of sectors of memory cells each one being formed in a respective well of the chip; each sector includes a plurality word lines each one for accessing a corresponding block of memory cells of the sector; the memory device includes a first biasing line of the wells and a second biasing line of the word lines, biasing circuitry for providing a first bias voltage to the first biasing line and a second bias voltage to the second biasing line, selection circuitry for selectively connecting the first biasing line to the well of at least one selected sector and for selectively connecting the second biasing line to at least one selected word line of each selected sector, first charge transfer circuitry for bringing the first biasing line from the first bias voltage to a target voltage according to a pilot transient trend, the target voltage being between the first bias voltage and the second bias voltage, second charge transfer circuitry for bringing the second biasing line from the second bias voltage to the target voltage. The second charge transfer circuitry includes circuitry for binding the second biasing line to bring itself from the second bias voltage to the target voltage according to a transient trend being scaled with respect to the pilot transient trend. | 12-15-2011 |
20120002484 | OPERATION METHODS FOR MEMORY CELL AND ARRAY FOR REDUCING PUNCH THROUGH LEAKAGE - A method for programming a first memory cell in a memory array. In a specific embodiment, each memory cell has a drain, a source, a channel, and a control gate overlying a charge storage material and the channel. The source of the first memory cell is coupled to the drain of a second memory cell. A voltage is applied to the drain of the first memory cell, and the source of the second memory cell is grounded. The method includes floating the drain of the second memory cell and the source of the first memory cell and turning on the channels of the first and second memory cells, effectively forming an extended channel region. Hot carriers are injected to the charge storage material of the first cell to program the first memory cell. The extended channel lowers electrical fields and reduces punch through leakage in unselected memory cells. | 01-05-2012 |
20120039131 | LOW-VOLTAGE EEPROM ARRAY - A low-voltage EEPROM array, which has a plurality of parallel bit lines, parallel word lines and parallel common source lines is disclosed. The bit lines include a first bit line. The word lines include a first word line and a second word line. The common source lines include a first common source line and a second common source line. The low-voltage EEPROM array also has a plurality of sub-memory arrays. Each sub-memory array includes a first memory cell and a second memory cell. The first memory cell connects with the first bit line, the first common source line and the first word line. The second memory cell connects with the first bit line, the second common source line and the second word line. The first and second memory cells are symmetrical and arranged between the first and second common source lines. | 02-16-2012 |
20120113726 | FLASH MEMORY AND FABRICATION METHOD AND OPERATION METHOD FOR THE SAME - The present invention discloses a flash memory and the fabrication method and the operation method for the same. The flash memory comprises two memory cells of vertical channels, wherein a lightly-doped N type (or P type) silicon is used as a substrate; a P+ region (or an N+ region) is provided on each of the both ends of the silicon surface, and two channel regions perpendicular to the surface are provided therebetween; an N+ region (or a P+ region) shared by two channels is provided over the channels; a tunneling oxide layer, a polysilicon floating gate, a block oxide layer and a polysilicon control gate are provided sequentially on the outer sides of each channel from inside to outside; and the polysilicon floating gate and the polysilicon control gate are isolated from the P+ region by a sidewall oxide layer. The whole device is a two-bit TFET type flash memory with vertical channels which has better compatibility with prior-art standard CMOS process. As compared with a conventional MOSFET-based flash memory, the flash memory according to the present invention possesses various advantages such as high programming efficiency, low power consumption, effective inhibition of punch-through effect, and high density, etc. | 05-10-2012 |
20120176845 | TECHNIQUES FOR CONTROLLING A DIRECT INJECTION SEMICONDUCTOR MEMORY DEVICE - Techniques for controlling a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for controlling a direct injection semiconductor memory device comprising applying a first voltage potential to a first region via a bit line, applying a second voltage potential to a second region of the memory device via a source line, applying a control voltage potential to a body region of the memory device via a word line that is spaced apart and capacitively coupled to the body region, and applying a third voltage potential to a third region of the memory device via a carrier injection line in order to bias at least one of the first region, the second region, the third region, and the body region to perform one or more operations. | 07-12-2012 |
20120224433 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - A semiconductor device includes a differential circuit and a power supply circuit that provides a power supply to the differential circuit. Current to be supplied to the differential circuit by the power supply circuit is controlled, based on logics of a burn-in mode signal and an activation control signal for the differential circuit. | 09-06-2012 |
20120224434 | Interleaving Charge Pumps for Programmable Memories - Systems and methods, including computer software for performing operations enable interleaving of charging operations in a charging pump. A first charge pump is charged to a predetermined level, and a first operation is performed using a charge stored in the first charge pump after it reaches the predetermined level. A second charge pump is charged during a time that overlaps with performing the first operation. A second operation is performed using a charge stored in the second charge pump as a result of charging the second charge pump. | 09-06-2012 |
20120243336 | NONVOLATILE PROGRAMMABLE LOGIC SWITCH - An aspect of the present embodiment, there is provided a nonvolatile programmable logic switch including a first memory cell transistor, a second memory cell transistor, a pass transistor and a first substrate electrode applying a substrate voltage to the pass transistor, wherein a writing voltage is applied to the first wiring, a first voltage is applied to one of a second wiring and a third wiring and a second voltage which is lower than the first voltage is applied to the other of the second wiring and the third wiring, and the first substrate voltage which is higher than the second voltage and lower than the first voltage is applied to a well of the pass transistor, when data is written into the first memory cell transistor or the second memory cell transistor. | 09-27-2012 |
20120250421 | CHARGE PUMP CIRCUIT USING LOW VOLTAGE TRANSISTORS - The charge pump circuit has a plurality of cascaded charge pump stages, each provided with a first pump capacitor connected to a first internal node and receiving a first high voltage phase signal, and a second pump capacitor connected to a second internal node and receiving a second high voltage phase signal, complementary with respect to the first. A first transfer transistor is coupled between the first internal node and an intermediate node, and a second transfer transistor is coupled between the second internal node and the intermediate node. The first and second high voltage phase signals have a voltage dynamics higher than a maximum voltage sustainable by the first and second transfer transistors. A protection stage is set between the first internal node and second internal node and respectively, the first transfer transistor and second transfer transistor, for protecting the same transfer transistors from overvoltages. | 10-04-2012 |
20120250422 | Interleaving Charge Pumps for Programmable Memories - Systems and methods, including computer software for performing operations enable interleaving of charging operations in a charging pump. A first charge pump is charged to a predetermined level, and a first operation is performed using a charge stored in the first charge pump after it reaches the predetermined level. A second charge pump is charged during a time that overlaps with performing the first operation. A second operation is performed using a charge stored in the second charge pump as a result of charging the second charge pump. | 10-04-2012 |
20130028028 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A plurality of element isolation insulating films are formed in a semiconductor substrate in a memory cell array and have a first direction as a long direction. A plurality of element formation regions are formed isolated by the element isolation insulating films. A memory string is formed in each of the element formation regions. A plurality of element formation region groups are each configured by the element formation regions. In a memory cell array, in a second direction orthogonal to the first direction, a spacing between the element formation region groups is configured larger than a spacing between the element formation regions in each of the element formation region groups. A control circuit executes a write operation on the memory cell array on an element formation region group basis. | 01-31-2013 |
20130250699 | TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE - Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region and a second region. The apparatus may also include a body region disposed between the first region and the second region and capacitively coupled to a plurality of word lines, wherein each of the plurality of word lines is capacitively coupled to different portions of the body region. | 09-26-2013 |
20140029354 | NON-VOLATILE MEMORY CELL WITH HIGH BIT DENSITY - A non-volatile memory cell with high bit density is disclosed. Embodiments include: providing a transistor having a wordline gate structure over a substrate, first and second floating gate structures proximate opposite sides of the wordline gate structure, and first and second diffusion regions in the substrate, wherein the wordline gate structure, the first floating gate structure, and the second floating gate structure are laterally between the first and second diffusion regions; and providing a capacitor having first, second, and third control gate structures over the substrate, a third floating gate structure between the first and second control gate structures, a fourth floating gate structure between the second and third control gate structures, and third and fourth diffusion regions in the substrate, wherein the first, second, and third control gate structures are laterally between the third and fourth diffusion regions. | 01-30-2014 |
20140169103 | METHODS OF FORMING AND PROGRAMMING MEMORY DEVICES WITH ISOLATION STRUCTURES - Methods of programming and forming memory devices. Methods of programming include biasing a control gate of a selected memory cell of the memory device to a first voltage, the control gate being over a first conductive region having a first conductivity type and the first conductive region being over a second conductive region having a second conductivity type different than the first conductivity type; biasing the second conductive region to a second voltage to forward bias the junction from the second conductive region to the first conductive region; and injecting electrons into a charge-storage node of the selected memory cell from the second conductive region. The first conductive region and the second conductive region are contained within a dielectric isolation structure in which at least the selected memory cell is contained. | 06-19-2014 |
20140307511 | Non-volatile Memory Cell With Self Aligned Floating And Erase Gates, And Method Of Making Same - A memory device, and method of making the same, in which a trench is formed into a substrate of semiconductor material. The source region is formed under the trench, and the channel region between the source and drain regions includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the surface of the substrate. The floating gate is disposed in the trench, and is insulated from the channel region first portion for controlling its conductivity. A control gate is disposed over and insulated from the channel region second portion, for controlling its conductivity. An erase gate is disposed at least partially over and insulated from the floating gate. An electrically conductive coupling gate is disposed in the trench, adjacent to and insulated from the floating gate, and over and insulated from the source region. | 10-16-2014 |
20150325307 | METHOD FOR SETTING A FLASH MEMORY FOR HTOL TESTING - A method for setting voltages in a flash memory for high temperature operating life (HTOL) testing is provided. The flash memory includes a substrate, a source, and a control gate. The method includes adjusting the voltages that are applied to the source, the control gate, and the substrate, such that there is no voltage difference between the control gate and the source, and no voltage difference between the control gate and the substrate. Specifically, adjusting the voltages includes setting the voltage that is applied to the source to a ground voltage, setting the voltage that is applied to the control gate to the ground voltage, and setting the voltage that is applied to the substrate to a power supply voltage. | 11-12-2015 |