Entries |
Document | Title | Date |
20080212370 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE, NONVOLATILE SEMICONDUCTOR STORAGE SYSTEM AND METHOD OF MANAGING OF DEFECTIVE COLUMN IN NONVOLATILE SEMICONDUCTOR STORAGE SYSTEM - A nonvolatile semiconductor storage device is disclosed, which includes a memory cell array in which nonvolatile memory cells are arranged, a first data holding circuit which temporarily holds a collective processing unit of read or write data to be simultaneously read from or written to the memory cells, a circuit which takes out the data held in the first data holding circuit from the device, and a second data holding circuit in which data is automatically set at a time when power supply is turned on and in which the data is changeable based on a command input to the device, wherein the collective processing unit is equal to a sum of the number of units used within the device and the maximum number of units continuously output from the device to outside or input to the device from outside. | 09-04-2008 |
20080212371 | NON-VOLATILE MEMORY COPY BACK - Data move operations in a memory device are described that enable identification of data errors. During a write operation, identified errors are flagged and used to provide an error status during the data move operation. Results of the error detection can be accessed by a memory controller for data repair operations by the controller. | 09-04-2008 |
20080239808 | Flash Memory Refresh Techniques Triggered by Controlled Scrub Data Reads - The quality of data stored in individual blocks of memory cells of a flash memory system is monitored by a scrub read of only a small portion of a block, performed after data are read from less than all of a block in response to a read command from a host or memory controller. The small portion is selected for the scrub read because of its greater vulnerability than other portions of the block to being disturbed as a result of the commanded partial block data read. This then determines, as the result of reading a small amount of data, whether at least some of the data in the block was disturbed by the command data read to a degree that makes it desirable to refresh the data of the block. | 10-02-2008 |
20080239809 | FLASH MEMORY DEVICE AND METHOD FOR PROVIDING INITIALIZATION DATA - A flash memory device includes a cell array and a decision unit. The cell array includes multiple regions corresponding to multiple input/output lines. Initialization data are repeatedly stored in each of the regions. The decision unit determines whether the stored data are valid based on values of bits of the stored data read from each region. | 10-02-2008 |
20080266956 | FLASH MEMORY DEVICE AND METHOD OF CONTROLLING FLASH MEMORY DEVICE - A flash memory device includes multiple memory blocks, a decoder configured to select at least one of the memory blocks in response to block select signals, and a controller configured to generate the block select signals in response to a block address. When the block address corresponds to a bad block, the controller generates the block select signals to cause the decoder to interrupt selection of a memory block corresponding to the block address. | 10-30-2008 |
20080266957 | Method for Column Redundancy Using Data Latches in Solid-State Memories - A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in the user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A defective location latching redundancy scheme assumes the column circuits including data latches for defective columns to be still useable. The data latches for the defective columns are used to buffer corresponding redundant data that are normally accessible from their data latches in the redundant portion. In this way both the user and redundant data are available from the user data latches, and streaming data into or out of the data bus is simplified and performance improved. | 10-30-2008 |
20080279004 | Charge-Trapping Memory Device and Methods for its Manufacturing and Operation - A method for leveling bit errors in a charge-trapping memory device is disclosed. The memory device has a first and a second sector of memory cells. The first sector is validated by counting a number of bit failures occurring in memory cells of the first sector, the bit failures caused by accessing memory cells of the second sector. Data stored in the first sector is backed up if the validating indicates a likelihood of a forthcoming failure in the first sector. | 11-13-2008 |
20080285347 | NON-VOLATILE MEMORY DEVICES AND SYSTEMS INCLUDING BAD BLOCKS ADDRESS RE-MAPPED AND METHODS OF OPERATING THE SAME - A method of operating a non-volatile memory device included in a memory card can be provided by re-mapping addresses of bad blocks in a first non-volatile MAT in a memory card and re-mapping addresses of bad blocks in a second non-volatile MAT in the memory card, the second non-volatile MAT including blocks that are address mapped with blocks in the first non-volatile MAT. Also a method of scanning a non-volatile memory device for bad blocks can be provided by sequentially scanning blocks in a non-volatile memory device for data indicating that a respective block is a bad block starting at a starting block address that is above a lowermost block address of the non-volatile memory device, wherein the starting block address is based on a yield for the non-volatile memory device. | 11-20-2008 |
20080291729 | Non-Volatile Memory With High Reliability - A non-volatile memory (NVM) system includes a set of NVM cells, each including: a NVM transistor; an access transistor coupling the NVM transistor to a corresponding bit line; and a source select transistor coupling the NVM transistor to a common source. The NVM cells are written by a two-phase operation that includes an erase phase and a program phase. A common set of bit line voltages are applied to the bit lines during both the erase and programming phases. The access transistors are turned on and the source select transistors are turned off during the erase and programming phases. A first control voltage is applied to the control gates of the NVM transistors during the erase phase, and a second control voltage is applied to the control gates of the NVM transistors during the program phase. Under these conditions, the average required number of Fowler-Nordheim tunneling operations is reduced. | 11-27-2008 |
20080298126 | NON-VOLATILE SEMICONDUCTOR MEMORY AND METHOD FOR REPLACING DEFECTIVE BLOCKS THEREOF - A non-volatile semiconductor memory includes a memory cell array. The memory cell array includes a plurality of banks, redundant blocks, and special blocks storing management data. Each bank includes a plurality of normal blocks, which include a plurality of electrically rewritable memory cells, the normal block being a minimum unit which is independently erased, and the redundant block configured to replace the normal block and being incapable of replacing the special block. A defective block automatic replacement sequence control circuit controls the replacement operation of the defective block FBLK with the redundant block RBLK in a defective block automatic replacement sequence. | 12-04-2008 |
20080316822 | MEMORY SYSTEM THAT DETECTS BIT ERRORS DUE TO READ DISTURBANCE AND METHODS THEREOF - Methods and memory systems are provided that can detect bit errors due to read disturbances. A main page of a flash memory in a memory system is read. A bit error in data that is read from the main page is detected and corrected. In parallel with reading the main page, a bit error is detected in data that is read from a dummy page of the flash memory. | 12-25-2008 |
20090003064 | FLASH MEMORY DEVICE AND METHOD OF PROGRAMMING FLASH MEMORY DEVICE - A flash memory device and a method of programming the same include a memory cell array, a pass/fail check circuit and a control logic circuit. The memory cell array includes multiple memory cells arranged in rows and columns. The pass/fail check circuit verifies whether data bits selected by a column address during a column scan operation have program data values. The control logic circuit detects fail data bits from the selected data bits and stores the column address in response to the verification result of the pass/fail check circuit. The control logic circuit also compares a number of the fail data bits with a reference value and controls generation of the column address according to the comparison result. | 01-01-2009 |
20090027966 | FLASH MEMORY DEVICE - A bad block address of a flash memory device is stored through a fuse circuit and then compared with an input address in order to disable bad blocks. The flash memory device includes a bad block information unit for storing an address of a bad block, a comparator for comparing an input address including a memory block address and the address of the bad block stored in the bad block information unit, and for outputting a first control signal according to the comparison result, and an address counter for outputting a second control signal to enable or disable a memory block corresponding to the memory block address in response to the first control signal. | 01-29-2009 |
20090034332 | SEMICONDUCTOR MEMORY DEVICE - A reference cell outputs a reference current of a data reading current of a memory cell. A trimming data in accordance with the reference current is memorized in a non-volatile memory cell. A standard current generator outputs a standard current whose current quantity is adjusted in accordance with the trimming data. A current comparator compares the standard current to the reference current. The output of the reference current from the reference cell is adjusted through a reference cell adjuster based on a result of the comparison by the current comparator. | 02-05-2009 |
20090040825 | NOVEL ROW REDUNDANCY SCHEME IN A MULTICHIP INTEGRATED MEMORY - Column redundancy is provided outside of a FLASH memory chip using a separate companion controller chip. The companion chip initially receives and stores fuse address information from the FLASH memory chip for defective memory cells in the FLASH memory. In a read mode of operation, the companion control chip detects receipt of a defective address from the FLASH memory and stores in a redundant shift register redundant data that is downloaded from the FLASH memory chip. The redundant data is used to provide correct FLASH memory data to an external user that interfaces with the companion control chip. In a program mode of operation, the companion control chip provides redundant bits that are stored in redundant columns in the FLASH memory chip. The companion control chip provides flexibility by readily providing a number of different redundancy schemes for bits, nibbles, or bytes without requiring additional logic circuits in the FLASH memory chip itself. Data is transferred between the FLASH memory chip and the companion control chip a byte at a time. | 02-12-2009 |
20090040826 | FLASH MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A flash memory device is disclosed. The flash memory device includes a memory cell array configured to have memory cells for storing data, and store initial data in a part of the memory cells, a page buffer circuit configured to have page buffers for providing data to be programmed in the memory cell or reading data from the memory cell, a controller configured to control the page buffer circuit so that the initial data stored in the memory cell array are read when operation of the flash memory device is started, discriminate error of the read initial data, and amend the error of the initial data, and an initial data latching circuit for latching the initial data of which the error is amended by the controller. | 02-12-2009 |
20090040827 | Flash memory device for remapping bad blocks and bad block remapping method - Provided are a flash memory device and a bad block remapping method thereof. The flash memory device includes: an address storage block detecting whether a block address provided from the outside is identical to an already stored block address, and then generating a repair signal according to a detection result; and an encoder converting the repair signal into a block select signal in order to select the normal memory block. | 02-12-2009 |
20090046512 | Reliability System for Use with Non-Volatile Memory Devices - A system and method which provides a non-volatile memory management system with the ability to monitor the health of a corresponding non-volatile memory and to safeguard data stored within the non-volatile memory when data integrity is at risk. The monitoring and safeguarding is provided via a crisis reliability mode module which monitors the health of a corresponding non-volatile memory and to enters a crisis reliability mode of operation when data integrity within the non-volatile memory is at risk. | 02-19-2009 |
20090052247 | FUSE CIRCUIT AND FLASH MEMORY DEVICE HAVING THE SAME - A fuse circuit in a flash memory device is disclosed. The fuse circuit includes a plurality of memory cells turned on/off by a first voltage in accordance with program state, a switching circuit configured to switch in response to a control signal, thereby transmitting a verifying signal for verifying program of the memory cell to the memory cell, and a cell controller configured to output the verifying signal for controlling program, verification and erase of the memory cells and the control signal. | 02-26-2009 |
20090052248 | FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL - A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included. | 02-26-2009 |
20090052249 | SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY BLOCK CONFIGURATION - A memory array including memory mats is arranged in a U shape when seen in two dimensions, and a logic circuit and an analog circuit are arranged in a region unoccupied by the memory array. This facilitates transmission of power supply voltage and signals between the peripheral circuit including the analog and logic circuits and the pad band including power supply and data pads. The analog circuit is positioned close to the power supply pad, so that voltage drop due to the resistance of power supply interconnection is restricted. It is also possible to separate a charge pumping power supply interconnection and a peripheral circuit power supply interconnection in the vicinity of the power supply pad. | 02-26-2009 |
20090080255 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A memory cell array including at least one memory cell, an address storage section containing address information, an address judging circuit for judging whether an input address matches the address information in the address storage section and outputting a result of the judgment, and a write or erase voltage generation circuit for generating a write or erase voltage to be applied to the memory cell are provided. The write or erase voltage generation circuit receives the output result from the address judging circuit and changes a write or erase voltage. | 03-26-2009 |
20090086541 | COLUMN REDUNDANCY RAM FOR DYNAMIC BIT REPLACEMENT IN FLASH MEMORY - A column redundancy system for a non-volatile memory includes a separate companion controller chip that includes a column redundancy RAM memory array for storing addresses of defective non-volatile memory cells. Column redundancy match logic provides a match output signal corresponding to a match of a particular user input address for the non-volatile memory with the address of a defective non-volatile memory cell, the collection of said addresses stored in the column redundancy RAM memory array. Column redundancy replacement logic, in response to a match output, dynamically substitutes correct data associated with a defective non-volatile memory cell into an I/O program or read data bit stream of the non-volatile memory chip. | 04-02-2009 |
20090091978 | WEAR LEVELING METHOD AND CONTROLLER USING THE SAME - A wear leveling method under limited system resources is provided, the wear levelling method is suitable for a non-volatile memory, the non-volatile memory is substantially divided into a plurality of blocks, and the blocks are at least grouped into a data area, a spare area and a substitution-transient area. The blocks within the data area may be divided into a plurality of lately-used blocks and a plurality of lately-unused blocks. The method includes only recording erase times of the lately-used blocks and blocks within the spare area and selecting a block used for the substitution-transient area is selected from the spare area according to a judgment condition of erase times of another block within the spare area plus a first threshold value. The method also includes performing a wear leveling procedure. Wherein, the selected block and the other block are selected in a random mode or a sequential mode. | 04-09-2009 |
20090091979 | RELIABLE DATA STORAGE IN ANALOG MEMORY CELLS IN THE PRESENCE OF TEMPERATURE VARIATIONS - A method for data storage includes programming a first group of analog memory cells at a first time at a known first temperature, so as to cause the analog memory cells in the first group to assume respective first analog storage values. Respective second analog storage values are read from the analog memory cells in the first group at a second time at which the analog memory cells are at a second temperature. A shift is estimated between the first analog storage values and the second analog storage values, and a memory access parameter is adjusted responsively to the estimated shift. A second group of the analog memory cells is accessed at the second temperature using the adjusted memory access parameter. | 04-09-2009 |
20090129163 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR INCREASING A LIFETIME OF A PLURALITY OF BLOCKS OF MEMORY - A system, method, and computer program product are provided for increasing a lifetime of a plurality of blocks of memory. In operation, at least one factor that affects a lifetime of a plurality of blocks of memory is identified. Additionally, the plurality of blocks to write is selected, based on the at least one factor. | 05-21-2009 |
20090135650 | COMPENSATION OF BACK PATTERN EFFECT IN A MEMORY DEVICE - In one or more of the disclosed embodiments, a read operation is compensated for back pattern effect. A bit line current is generated by a read operation that biases the word lines. As part of a back pattern effect measurement phase, at predetermined time intervals an indication of the discharge status of the bit line is stored in a latch of a set of N latches coupled to each bit line. At the end of the measurement phase, the set of latches contains a multiple bit word that is an indication of the back pattern effect experienced by that particular series string of memory cells. This back pattern effect indication is used in subsequent read operations to adjust the timing of the operation. | 05-28-2009 |
20090147581 | NAND FLASH MEMORY AND MEMORY SYSTEM - A NAND flash memory comprising blocks which are units of writing and deletion of data, the block comprising: memory cells from which data corresponding to values of held threshold voltages can be read by applying a reading voltage to control gates of the memory cells; source-side selection gate transistors connected between a common source line and the memory cells; drain-side selection gate transistors connected between a bit line and the memory cells; and monitor cells which are configured as the memory cells and have a threshold voltage set according to monitor data, and from which data corresponding to values of held threshold voltages can be read by applying a decision voltage to control gates of the monitor cells. | 06-11-2009 |
20090154242 | FLASH MEMORY WITH OPTIMIZED WRITE SECTOR SPARES - In certain exemplary embodiments, a memory device with optimized write sectors has a plurality P of memory write sectors and N memory spare sectors Cumulatively, the memory write sectors correspond to the specified storage capacity of the memory. The number N of spares is approximately equal to the number of write sectors expected to be decommissioned within an operational lifetime of the memory, which can be determined by empirical measurement. A method, by way of non-limiting example, of making memory includes specifying a plurality P of write sectors which define a specified storage capacity of a memory device, determining a number N of spare sectors, and making a memory device with about P write sectors and about N spare sectors. The number N can be determined, by way of example, by summing the infant mortality with the random failure of write sectors. One exemplary tool to determine infant mortality and random failure is to empirically create a cycle-based bathtub curve having infant mortality, random failure, and wear out regions. | 06-18-2009 |
20090161428 | LOAD BALANCING BY USING CLOCK GEARS - An electronic device is capable of monitoring internal components to predict changes in processing power needs. When a prediction is made, a clock control circuit can be instructed to increase the clock signal frequency in response to a predicted increase in processing power needs, or decrease the clock signal frequency in response to a predicted decrease in processing power needs. The control circuit can further balance other clock signal frequencies in order to satisfy constraints such as a power supply constraint. | 06-25-2009 |
20090161429 | DYNAMIC COLUMN REDUNDANCY REPLACEMENT - A dynamic column redundancy replacement system for programming and reading a non-volatile memory system includes an input data replacement logic block and an output data replacement logic block. A column redundancy match logic block compares a user address to latched fuse addresses of bad columns and identifies address matches to facilitate the replacement of bits from defective memory cells with replacement redundancy bits. For a program mode of operation, a multi-bit data program redundancy register stores actual redundant input data information and a FIFO register masks internal operations of the memory controller logic while a user is sending data. For a read mode of operation, actual redundant output information is stored in a multi-bit data read redundancy register such that, if a match is found, data from the shift register is replaced with redundant data bits and sent to the data output terminal to provide dynamic replacement of data bits from defective non-volatile memory cells. | 06-25-2009 |
20090161430 | BIT MAP CONTROL OF ERASE BLOCK DEFECT LIST IN A MEMORY - Systems and methods that facilitate bad block management in a memory device that comprises nonvolatile memory are presented. One or more memory blocks of a memory device are each associated with one or more additional, dedicated bits that facilitate indicating whether the associated memory block is defective. These additional bits, called bad block bits, can be stored in a hardware-based storage mechanism within the memory device. Once a defect is detected in a memory block, at least one of the associated bad block bits can be set to indicate that the memory block is defective. If at least one of the bad block bits associated with a memory block indicates a memory block is defective, access to the memory block can be prevented. | 06-25-2009 |
20090161431 | BUILT-IN SELF-REPAIR METHOD FOR NAND FLASH MEMORY AND SYSTEM THEREOF - A built-in self-test system applied to NAND flash memory comprises a built-in self-test circuit, a built-in redundancy-analysis circuit, a content addressable memory, a spare memory, a page-mode processor and an address generator. The built-in self-test circuit is configured to test for defective data in a NAND flash memory. The built-in redundancy-analysis circuit is connected to the built-in self-test circuit. The content addressable memory is connected to the built-in redundancy-analysis circuit for storing the address of the defective data. The spare memory is electrically connected to the content addressable memory. The page-mode processor is configured to generate a page address signal and a compensation signal according to an address signal of the NAND flash memory. The address generator is configured to generate a current address signal according to the page address signal and compensation signal to the content addressable memory. | 06-25-2009 |
20090168522 | SEMICONDUCTOR MEMORY DEVICE WITH IMPROVED ECC EFFICIENCY - Memory cells store k bits of data (k is a natural number not less than 2) into a single cell. A number n of data storage circuits store externally supplied k bits of data to write data into the memory cells. A control circuit inputs the data on a first page, a second page, . . . , a k-th page to every h (h≦n) of the data storage circuits and then writes the data in the n data storage circuits into the memory cells. | 07-02-2009 |
20090168523 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device includes: a memory cell array; a bad block position data register area defined in the memory cell array to store bad block position data; an address decoder circuit configured to select a block in the cell array; and bad block flag latches disposed in the address decoder circuit, bad block flags being set in the bad block flag latches in accordance with the bad block position data read out the bad block position data register area, wherein the bad block position data in the bad block position data register area are defined by such a bit position assignment scheme that one bit is assigned to one block under the condition that block positions in the cell array and column positions in one page are set in one-to-one correspondence. | 07-02-2009 |
20090168524 | WEAR LEVEL ESTIMATION IN ANALOG MEMORY CELLS - A method for operating a memory includes applying at least one pulse to a group of analog memory cells, so as to cause the memory cells in the group to assume respective storage values. After applying the pulse, the respective storage values are read from the memory cells in the group. One or more statistical properties of the read storage values are computed. A wear level of the group of the memory cells is estimated responsively to the statistical properties. | 07-02-2009 |
20090185421 | Charge-Trap Flash Memory Device with Reduced Erasure Stress and Related Programming and Erasing Methods Thereof - Operation methods of charge-trap flash memory devices having an unused memory cell for data storage and a normal memory cell used for data storage are discussed. The operation method may include selecting the unused memory cell, and programming the unused memory cell to have a predetermined threshold voltage. The charge-trap flash memory device may thus be provided with improved reliability by interrupting erasure stress to unused memory cells. | 07-23-2009 |
20090196101 | MEMORY MODULE - The present invention provides a reliable memory module. The memory module including a plurality of memory devices arranged on a circuit board and controlled by an external memory controller includes a buffer having a function of detecting and correcting an error and a nonvolatile storage area that stores contents of the error. | 08-06-2009 |
20090201731 | Method and Apparatus for Accessing Memory With Read Error By Changing Comparison - In response to a disagreement between a previously generated check code associated with previously programmed data bits and a more recently generated check code generated in response to a read command, the comparison process is changed, between i) a value representing accessed data and ii) a reference applied to such accesses to distinguish between logical levels. For example, the read bias arrangement and/or a read reference of a memory integrated circuit is changed. | 08-13-2009 |
20090201732 | System and method for purging a flash storage device - A flash storage device includes flash storage units that are purged in response to a condition or command. A flash controller interface receives a command for purging the flash storage device and provides a purge command to flash controllers in the flash storage device. Alternatively, the flash storage device detects a condition in response to which the flash controller interface provides a purge command to the flash controllers. Each flash controller independently erases a flash storage unit in response to receiving the purge command such that the flash storage units are erased substantially in parallel with each other. | 08-13-2009 |
20090231917 | FLASH MEMORY DEVICE AND METHOD FOR PROGRAMMING FLASH MEMORY DEVICE HAVING LEAKAGE BIT LINES - Provided is a method for programming a flash memory device. The method includes receiving writing data, detecting leakage bit lines of the flash memory device, and updating the received writing data in order for data corresponding to the leakage bit lines to be modified as program-inhibit data. A programming operation is performed on the flash memory device after updating the writing data. | 09-17-2009 |
20090244973 | Memory Read-Out - A memory system having a plurality of memory cells for storing payload data and redundancy data. The memory system having a read-out circuit configured to read-out a status of the plurality of memory cells, the read-out status having payload data, redundancy data and associated reliability information. Moreover, the memory system has a data processor configured to derive the payload data from the read-out status using the reliability information. | 10-01-2009 |
20090244974 | MEMORY SYSTEM AND DATA WRITING METHOD - A data writing method is disclosed. In a memory system comprising a NAND flash memory and a controller which controls the memory, the memory system storing data provided from a host to the NAND flash memory, the data writing method comprises a steps of specifying a column address in which a column failure which has occurred in the NAND flash memory by the controller, and a step of, during writing into the NAND flash memory, writing data of a first logic level into a memory cell which corresponds to the specified column address regardless of write data provided from the controller. | 10-01-2009 |
20090268520 | LEAKAGE COMPENSATION DURING PROGRAM AND READ OPERATIONS - Methods of operating a memory and a memory are disclosed, such as an analog non-volatile memory device and process that reduces the effects of charge leakage from data cache capacitors, maintaining stored charge levels as data. In one embodiment, data values are compensated for leakage that is uniform across the data cache by charging a reference capacitor or initiating another leakage model and uniformly adjusting the ground of the data capacitors by the effect amount or by adjusting an amplifier offset or gain. In another embodiment, held data values are compensated for charge leakage effects that are non-uniform due to data values being sequentially transferred into the data cache by scaling a ground node or adjustment of amplifier offset/gain of each capacitor in the data cache against the leakage reference and the order in which data was transferred into the data cache. | 10-29-2009 |
20090290418 | METHOD OF VERIFYING A PROGRAM OPERATION IN A NON-VOLATILE MEMORY DEVICE - A method of verifying a program operation in a non-volatile memory device includes performing a program operation, verifying whether or not each of a plurality of program target memory cells is programmed to a voltage higher than a verifying voltage, counting a number of fail status bits in response to determining that a fail status memory cell is not programmed with a voltage higher than the verifying voltage based on the verified result, and setting data so that a plurality of page buffers each output a pass signal when the number of the fail status bits is smaller than a number of error correction code (ECC) processing bits. | 11-26-2009 |
20090316483 | Flash memory device and system including the same - The invention provides an operation method of a memory system including a flash memory device. The method includes programming at least one page included in a selected memory block of the flash memory device; and determining the selected memory block or the flash memory device to be invalid, according to whether a loop number of the programmed page is out of a reference loop range. | 12-24-2009 |
20090323417 | SEMICONDUCTOR MEMORY REPAIRING A DEFECTIVE BIT AND SEMICONDUCTOR MEMORY SYSTEM - A semiconductor memory has a plurality of blocks, and each of the blocks comprises a plurality of pages, and further, each of the pages has a plurality of memory cells. A block having defective bits less than N (N is an integer number more than 0) in all pages of the block stores a first data showing a normal block. A block including at least one page having defective bits more than N and including no page having defective bits more than M (M is an integer number of M>N) stores a second data showing a psedo-pass block as a pseudo-normal block. A block including at least one page having defective bits more than M stores a third data showing a defective block. | 12-31-2009 |
20090323418 | Use of Alternative Value in Cell Detection - A system and method, including computer software, allows reading data from a flash memory cell. Voltages from a group of memory cells are detected. The group of memory cells have associated metadata for error detection, and each memory cell stores a voltage representing a data value selected from multiple possible data values. Each possible data value corresponds to one range of multiple non-overlapping ranges of analog voltages. Memory cells having uncertain data values are identified based on the detected voltages. Alternative data values for the memory cells having the uncertain data values are determined, and a combination of alternative data values is selected. An error detection test is performed using the metadata associated with the multiple memory cells and the selected combination of alternative data values. | 12-31-2009 |
20100002512 | DISABLING FAULTY FLASH MEMORY DIES - Articles and associated methods and systems relate to disabling defective flash memory dies in a device containing multiple flash memory dies. Packages containing multiple flash memory dies may be labeled to indicate a flash memory data storage capacity based on the flash memory dies that are not disabled. Various disabling methods may be applied at the die level, package level, and/or board level. | 01-07-2010 |
20100020609 | FLASH MEMORY DEVICE WITH REDUNDANT COLUMNS - Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of columns. Each of the columns includes a bit line and a plurality of memory cells on the bit line. The plurality of columns include a plurality of groups of regular columns and a plurality of groups of redundant columns. The apparatus also includes a plurality of data latches. Each of the data latches is configured to store data read from a respective one group of regular columns. The apparatus further includes a plurality of redundant data latches. Each of the redundant data latches is configured to store data read from a respective one group of redundant columns. The apparatus also includes a multiplexer configured to selectively output data from the plurality of data latches and the plurality of redundant data latches. | 01-28-2010 |
20100020610 | Integrated Circuits Having a Controller to Control a Read Operation and Methods for Operating the Same - In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a memory cell block having a plurality of memory cells, a storage portion configured to store information about a quality characteristic of the memory cells of the memory cell block, and a controller configured to control a read operation, and to change the information about the quality characteristic depending on a quality of a read operation. | 01-28-2010 |
20100020611 | FLASH MEMORY SYSTEMS AND OPERATING METHODS USING ADAPTIVE READ VOLTAGE LEVELS - Some embodiments of the present invention provide methods of operating nonvolatile memory devices. Reference data is stored in a plurality of memory cells. The reference data is read, and a threshold voltage distribution of the plurality of memory cells is determined responsive to reading the reference data. A read voltage of the nonvolatile memory device is modified based on the determined threshold voltage distribution. The nonvolatile memory device may include a main region configured to stored data and a dummy region configured to store the reference data, and the methods may further include reading data from the main region using the modified read voltage. | 01-28-2010 |
20100020612 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - When a voltage level detector detects that a supply voltage reaches a recovery voltage level that requires a recovery operation, a signal generator generates a recovery operation instructing signal for instructing the recovery operation. The recovery operation instructing signal is invalidated if a certain operation mode is executed and validated in other cases. | 01-28-2010 |
20100020613 | STARTING PROGRAM VOLTAGE SHIFT WITH CYCLING OF NON-VOLATILE MEMORY - A system is disclosed for programming non-volatile storage that improves performance by setting the starting programming voltage to a first level for fresh parts and adjusting the starting programming voltage as the memory is cycled. For example, the system programs a set of non-volatile storage elements during a first period using an increasing program signal with a first initial value and subsequently programs the set of non-volatile storage elements during a second period using an increasing program signal with a second initial value, where the second period is subsequent to the first period and the second initial value is different than the first initial value. | 01-28-2010 |
20100027335 | Memory device and wear leveling method - The memory device selects any one of a first memory cell and a second memory cell based on a number of times that the first memory cell is erased, an elapsed time after the first memory cell is erased, a number of times that the second memory cell is erased, and an elapsed time after the second memory cell is erased, and program data in the selected memory cell. The memory device may improve distribution of threshold voltage of memory cells and endurance of the memory cells. | 02-04-2010 |
20100027336 | Non-volatile memory device and associated programming method using error checking and correction (ECC) - A programming method for a non-volatile memory device includes performing a programming operation to program memory cells, when the programmed memory cells are determined to include memory cells that failed to be programmed and when a current program loop is a maximum program loop, determining whether a number of the memory cells that failed to be programmed corresponds to a number of memory cells that can successfully undergo ECC (error checking and correction), when the number of the memory cells that failed to be programmed is less than the number of the memory cells that can successfully undergo ECC, reading data so as to determine whether a number of error bits of the memory cells that failed to be programmed can successfully undergo ECC, and, when the memory cells that failed to be programmed can successfully undergo ECC, ending a programming operation. | 02-04-2010 |
20100046292 | Non-volatile memory device and bad block remapping method - A non-volatile memory device and a bad block remapping method use some of main blocks as remapping blocks to replace a bad block in a main cell block and selects remapping blocks using existing block address signals. Thus, separate bussing of remapping block address signals is not needed. The bad block remapping includes comparing an external block address input from an external source to a stored bad block address, generating a bad block flag signal when the external block address is identical to the stored bad block address, generating a remapping block address selecting the remapping blocks in response to a remapping address corresponding to the bad block address, selecting one of the external block address and the remapping block address in response to the bad block flag signal to create a selected address, and outputting a row address signal in accordance with the selected address. | 02-25-2010 |
20100091568 | Nonvolatile Memory and Method With Reduced Program Verify by Ignoring Fastest and/or Slowest Programming Bits - A group of non-volatile memory cells are programmed in a programming pass by a series of incremental programming pulses where each pulse is followed by a program-verify and possibly program-inhibition step. Performance is improved during the programming pass by delayed starting and prematurely terminating the various verify levels that demarcate the multiple memory states. This amounts to skipping the verifying and inhibiting steps of the fastest and slowest programming (fringe) cells of the group. A reference pulse is established when the fastest cells have all been program-verified relative to a first verify level. The starting of what verify level at what pulse will then be delayed relative to the reference pulse. Verifying stops for a given verify level when only a predetermined number of cells remain unverified relative to that given level. Any errors arising from over- or under-programming of the fringe cells are corrected by an error correction code. | 04-15-2010 |
20100103737 | Read Compensation Circuits and Apparatus Using Same - A read compensation circuit is provided. The read compensation circuit corrects a read error occurring in an erased cell based on a pattern of programmed cells adjacent to the erased cell. The read compensation circuit also transmit program state information of a memory cell stored in a page buffer to another page buffer through a bit line, thereby allowing page buffers to easily detect and correct errors occurring in memory cells. | 04-29-2010 |
20100110791 | EEPROM MEMORY PROTECTED AGAINST THE EFFECTS OF BREAKDOWN OF MOS TRANSISTORS - The disclosure relates to an electrically erasable and programmable memory, comprising memory cells arranged in bit lines and word lines transverse to bit lines, wherein each memory cell may be in a programmed or erased state, the memory comprising memory cell selection circuits configured to memorize and read data bits in two memory cells belonging to different bit lines and different word lines, and to avoid a memory cell from being written or read by mistake in another state than a default state after a gate oxide breakdown of a transistor of the memory, and a read circuit to determine a data bit to be read in the memory according to the states of the two memory cells memorizing the data bit. | 05-06-2010 |
20100142275 | CONTINUOUS ADDRESS SPACE IN NON-VOLATILE-MEMORIES (NVM) USING EFFICIENT MANAGEMENT METHODS FOR ARRAY DEFICIENCIES - The invention provides a method of managing bad block in a data storage device having an OTP memory die in order to present a continues address space toward the user, by using some of the OTP memory space for the management and maintaining address replacement table. Fast and efficient programming and reading algorithms are presented. | 06-10-2010 |
20100172179 | Spare Block Management of Non-Volatile Memories - Techniques for the management of spare blocks in re-programmable non-volatile memory system, such as a flash EEPROM system, are presented. In one set of techniques, for a memory partitioned into two sections (for example a binary section and a multi-state section), where blocks of one section are more prone to error, spare blocks can be transferred from the more error prone partition to the less error prone partition. In another set of techniques for a memory partitioned into two sections, blocks which fail in the more error prone partition are transferred to serve as spare blocks in the other partition. In a complementary set of techniques, a 1-bit time stamp is maintained for free blocks to determine whether the block has been written recently. Other techniques allow for spare blocks to be managed by way of a logical to physical conversion table by assigning them logical addresses that exceed the logical address space of which a host is aware. | 07-08-2010 |
20100177564 | METHOD FOR DETECTING FLASH PROGRAM FAILURES - One or more techniques are provided for programming a flash memory device. In one embodiment, the memory device is programmed such that a data pattern written to a page in the memory device has encoded therein an expected count value corresponding to the number of times a first binary value occurs in the data pattern. The data pattern includes the program data and the expected count value, and is written to the page in a single operation. The expected count value may be stored in a count field in the management area of the page. During a page read operation, the expected count value is compared to the actual count of the number of bits having the first binary value in the data area of the page. If the expected count is equal to the actual count, then the program data is determined to be valid. | 07-15-2010 |
20100177565 | METHOD OF OPERATING A FLASH MEMORY DEVICE - A flash memory device is disclosed. The flash memory device includes a memory cell array configured to have memory cells for storing data, and store initial data in a part of the memory cells, a page buffer circuit configured to have page buffers for providing data to be programmed in the memory cell or reading data from the memory cell, a controller configured to control the page buffer circuit so that the initial data stored in the memory cell array are read when operation of the flash memory device is started, discriminate error of the read initial data, and amend the error of the initial data, and an initial data latching circuit for latching the initial data of which the error is amended by the controller. | 07-15-2010 |
20100182833 | MEMORY AND BOUNDARY SEARCHING METHOD THEREOF - A memory and a boundary searching method thereof are provided therein. When searching a boundary of a threshold voltage distribution of the memory, data errors resulted from tail bits of the memory would be corrected. Therefore, a sensing window could be broader, and the boundary of the threshold voltage distribution could be determined precisely. | 07-22-2010 |
20100195393 | Data storage system with refresh in place - A data storage system for refreshing in place data stored in a non-volatile re-writeable memory is disclosed. Data from a location memory can be read into a temporary storage location; the data at the memory location can be erased; the read data error corrected if necessary; and then the read data can be programmed and rewritten back to the same memory location it was read from. One or more layers of the non-volatile re-writeable memory can be fabricated BEOL as two-terminal cross-point memory arrays that are fabricated over a substrate including active circuitry fabricated FEOL. A portion of the active circuitry can be electrically coupled with the one or more layers of two-terminal cross-point memory arrays to perform data operations on the arrays, such as refresh in place operations or a read operation that triggers a refresh in place operation. The arrays can include a plurality of two-terminal memory cells. | 08-05-2010 |
20100202203 | Data restoration method for a non-volatile memory - A method and apparatus for selectively restoring data in a non-volatile memory array based on failure type. Weakened data and erroneous data are identified by performing two readings of a specific memory section. Alternatively, an error correction code is used after a first reading of data to identify erroneous data. The manner in which data is restored will depend on whether the data changed because of an erase failure or a program failure. If only a program failure occurred then the data will be reprogrammed without an intervening erase step. If the data experienced an erase failure, then the data will be erased prior to being programmed with correct data. | 08-12-2010 |
20100208521 | Nonvolatile memory device, method of operating nonvolatile memory device and memory system including nonvolatile memory device - The method of operating the nonvolatile memory device may include performing a read operation on a first address region, comparing a read time of the first address region with a reference time, and storing read data from the read from the first address region in a second address region based on the comparison result. | 08-19-2010 |
20100226178 | APPARATUS AND METHODS FOR CORRECTING OVER-ERASED FLASH MEMORY CELLS - A method and flash memory device that correct over-erased memory cells are described. The device includes flash memory cells, erase circuitry, measuring circuitry, and a pulse generator. The method includes performing an erase operation on a first plurality of memory cells, measuring at least one memory cell of a second plurality of memory cells, and if an over-erased memory cell is detected in measuring the second plurality of cells, applying one or more programming pulses to the one or more over-erased cells, the one or more programming pulses cumulatively sufficient to correct a cell in a maximum over-erased state. Also described is a method that registers over-erased cells for programming and applies one or more programming pulses to the registered over-erased cells, the one or more programming pulses cumulatively sufficient to correct a cell in a maximum over-erased state. | 09-09-2010 |
20100232223 | Defective block handling method for a multiple data channel flash memory storege device - The block groups of a multiple data channel flash memory storage device are detected for defective blocks. The block group containing any defective blocks is divided into subgroups, each of which contains only defective blocks or only good blocks. The subgroups containing only good blocks are selected to establish a new block group having the same amount of blocks as that of the original block groups. | 09-16-2010 |
20100259982 | FLASH MEMORY DEVICE AND METHOD OF CONTROLLING FLASH MEMORY DEVICE - A flash memory device includes multiple memory blocks, a decoder configured to select at least one of the memory blocks in response to block select signals, a controller configured to generate the block select signals in response to a block address and to generate a flag signal when the block address corresponds to a bad block, and an output buffer configured to output fixed data in response to the flag signal indicating that the block address corresponds to the bad block. When the block address corresponds to a bad block, the controller generates the block select signals to cause the decoder to interrupt selection of a memory block corresponding to the block address. | 10-14-2010 |
20100284222 | FUSE CIRCUIT AND FLASH MEMORY DEVICE HAVING THE SAME - A flash memory device includes a main cell array configured to have main memory cells for storing data and a redundancy cell array configured to have redundancy memory cells for repairing a failed memory cell of the main cell array. A page buffer circuit is configured to perform a program operation, a verifying operation and a read operation on the main cell array and the redundancy cell array. A repair circuit includes fuse circuits having fuse memory cells each of which is programmed in response to address information. The repair circuit is operated in response to a program state of the fuse memory cells and output a repair signal. A data input/output controller is configured to control input/output of data to/from the main memory cell or the redundancy memory cell in accordance with the repair signal outputted by the repair circuit. | 11-11-2010 |
20100302850 | Storage device and method for reading the same - The storage device includes a storage unit configured to store data, an error controlling unit configured to correct an error of the data read out from the storage unit according to at least one read level, and a read level controlling unit configured to control the at least one read level when the error is uncorrectable. The read level controlling unit is configured to measure a distribution of memory cells of the storage unit, configured to filter the measured distribution, and configured to reset the at least one read level based on the filtered distribution. | 12-02-2010 |
20110002169 | Bad Column Management with Bit Information in Non-Volatile Memory Systems - Column based defect management techniques are presented. Each column of the memory has an associated isolation latch or register whose value indicates whether the column is defective, but in addition to this information, for columns marked as defective, additional information is used to indicate whether the column as a whole is to be treated as defective, or whether just individual bits of the column are defective. The defective elements can then be re-mapped to a redundant element at either the appropriate bit or column level based on the data. When a column is bad, but only on the bit level, the good bits can still be used for data, although this may be done at a penalty of under programming for some bits, as is described further below. A self contained Built In Self Test (BIST) flow constructed to collect the bit information through a set of column tests is also described. Based on this information, the bad bits can be extracted and re-grouped into bytes by the controller or on the memory to more efficiently use the column redundancy area. | 01-06-2011 |
20110002170 | SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY BLOCK CONFIGURATION - A memory array including memory mats is arranged in a U shape when seen in two dimensions, and a logic circuit and an analog circuit are arranged in a region unoccupied by the memory array. This facilitates transmission of power supply voltage and signals between the peripheral circuit including the analog and logic circuits and the pad band including power supply and data pads. The analog circuit is positioned close to the power supply pad, so that voltage drop due to the resistance of power supply interconnection is restricted. It is also possible to separate a charge pumping power supply interconnection and a peripheral circuit power supply interconnection in the vicinity of the power supply pad. | 01-06-2011 |
20110013453 | NONVOLATILE MEMORY DEVICE INCLUDING CIRCUIT FORMED OF THIN FILM TRANSISTORS - A transistor is arranged for electrically isolating a sense amplifier formed of a thin film transistor from a data line electrically coupled to the sense amplifier. When a write driver drives the data line, a control signal is applied to isolate the data line from the sense amplifier. | 01-20-2011 |
20110019474 | FLASH MEMORY DEVICE WITH REDUNDANT COLUMNS - Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of columns. Each of the columns includes a bit line and a plurality of memory cells on the bit line. The plurality of columns include a plurality of groups of regular columns and a plurality of groups of redundant columns. The apparatus also includes a plurality of data latches. Each of the data latches is configured to store data read from a respective one group of regular columns. The apparatus further includes a plurality of redundant data latches. Each of the redundant data latches is configured to store data read from a respective one group of redundant columns. The apparatus also includes a multiplexer configured to selectively output data from the plurality of data latches and the plurality of redundant data latches. | 01-27-2011 |
20110026326 | MEMORY SYSTEM INCLUDING FLASH MEMORY AND METHOD OF OPERATING THE SAME - A method for operating a memory system including a flash memory device having a plurality of memory blocks includes determining whether a read error generated during a read operation of the flash memory device is caused by read disturbance and replacing a memory block which includes the read error, with a spare memory block if the read error is caused by read disturbance. | 02-03-2011 |
20110051513 | METHODS, DEVICES, AND SYSTEMS FOR DEALING WITH THRESHOLD VOLTAGE CHANGE IN MEMORY DEVICES - The present disclosure includes methods, devices, and systems for dealing with threshold voltage change in memory devices. A number of embodiments include an array of memory cells and control circuitry having sense circuitry coupled to the array. The control circuitry is configured to determine changes in threshold voltages (Vts) associated with the memory cells without using a reference cell, and adjust the sense circuitry based on the determined changes and without using a reference cell. | 03-03-2011 |
20110051514 | NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM INCORPORATING SAME, AND METHOD OF OPERATING SAME - A nonvolatile memory device performs a program operation comprising applying a program pulse to selected memory cells, detecting a number of fail bits among the selected memory cells, the fail bits comprising failed program bits and disturbed inhibit bits, and determining a program completion status of the program operation based on the number of detected fail bits. | 03-03-2011 |
20110058420 | Storage Apparatus, Substrate, Liquid Container, System, and Control Method of the Storage Apparatus - A storage apparatus including a nonvolatile storage section and a control section controlling the nonvolatile storage section, wherein the control section has a detection circuit detecting floating state in at least one of power supply terminal connected to host side power supply terminal to which a power supply voltage is supplied from the host device, and ground terminal connected to host side ground terminal to which a ground voltage is supplied from the host device and a mask process section performing a mask process of the system clock that is used to control the nonvolatile storage section, wherein the mask process section masks the system clock if the floating state is detected by the detection circuit. | 03-10-2011 |
20110063909 | NONVOLATILE SEMICONDUCTOR MEMORY AND METHOD OF TESTING THE SAME - A memory cell array and a peripheral circuit are provided. The memory cell array has a plurality of blocks which are erasing units respectively. Each of the blocks includes a plurality of memory cells. A block control unit operates according to input signals from outside and controls operation of the blocks. A ready/busy control circuit outputs a busy signal during a period of operation implementation for a block selected from the blocks, in response to an output from the block control unit. The ready/busy control circuit outputs a ready signal out of the period of the operation implementation for the selected block. A registration control unit registers the selected block as a bad block, in the case that the ready/busy control circuit outputs a busy signal when the registration control unit receives a bad block identification command. | 03-17-2011 |
20110069549 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE, NONVOLATILE SEMICONDUCTOR STORAGE SYSTEM AND METHOD OF MANAGING OF DEFECTIVE COLUMN IN NONVOLATILE SEMICONDUCTOR STORAGE SYSTEM - A nonvolatile semiconductor storage device is disclosed, which includes a memory cell array in which nonvolatile memory cells are arranged, a first data holding circuit which temporarily holds a collective processing unit of read or write data to be simultaneously read from or written to the memory cells, a circuit which takes out the data held in the first data holding circuit from the device, and a second data holding circuit in which data is automatically set at a time when power supply is turned on and in which the data is changeable based on a command input to the device, wherein the collective processing unit is equal to a sum of the number of units used within the device and the maximum number of units continuously output from the device to outside or input to the device from outside. | 03-24-2011 |
20110096601 | Non-Volatile Memory And Method With Accelerated Post-Write Read To Manage Errors - Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. An error management provides reading and checking the copy after copying to the second portion. If the copy has excessive error bits, it is repeated in a different location either in the second or first portion. The reading and checking of the copy is accelerated by reading only a sample of it. The sample is selected from a subset of the copy having its own ECC and estimated to represent a worst error rate among the copy it is sampling. One embodiment has the sample taken from one bit of each multi-bit memory cell of a group. | 04-28-2011 |
20110103146 | MEMORY DEVICE OF THE ELECTRICALLY ERASABLE AND PROGRAMMABLE TYPE, HAVING TWO CELLS PER BIT - The memory device includes a memory cell unit of the electrically erasable and programmable non-volatile type including two memory cells respectively connected to two bit lines via two bit line select transistors. The common terminal between the bit line select transistor and the floating-gate transistor of each memory cell of the memory cell unit is connected to the control gate of the floating-gate transistor of the other memory cell of the memory cell unit. | 05-05-2011 |
20110141812 | Method and Apparatus for Restoring Data in a Non-Volatile Memory - A method and apparatus for selectively restoring data in a non-volatile memory array based on failure type. Weakened data and erroneous data are identified by performing two readings of a specific memory section. Alternatively, an error correction code is used after a first reading of data to identify erroneous data. The manner in which data is restored will depend on whether the data changed because of an erase failure or a program failure. If only a program failure occurred then the data will be reprogrammed without an intervening erase step. If the data experienced an erase failure, then the data will be erased prior to being programmed with correct data. | 06-16-2011 |
20110157985 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory region including memory cells configured to store data, a redundant region including memory cells configured to store data, and a control unit. The control unit is responsive to an erase command to execute, prior to an erase operation corresponding to the erase command, an error detection operation on data read from the memory region to detect whether the memory region is a defective memory region to be replaced by the redundant region | 06-30-2011 |
20110157986 | MEMORY AND OPERATING METHOD THEREOF - A memory and an operating method thereof are provided therein. When searching a boundary of a threshold voltage distribution of the memory, data errors resulted from tail bits of the memory would be corrected. Therefore, a sensing window could be broader, and the boundary of the threshold voltage distribution could be determined precisely. | 06-30-2011 |
20110157987 | Non-Volatile Memory With Redundancy Data Buffered in Remote Buffer Circuits - A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in column circuits of user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A remote redundancy scheme has the redundant data available from a central buffer accessible by any number of column circuits. Redundant data buffer circuits enable bus exchange with data from the user data latches except for defective locations when data are taken from the central buffer. In this way only addressing for the user portion is used for bus exchange. Also, accessibility to the redundant data will not be restricted by the locations of the column circuits relative to the redundant data latches and the buffered redundant data can be accessed at a finer granularity than that imposed by the column circuits. | 06-30-2011 |
20110164450 | Integrated circuits and methods to compensate for defective non-volatile embedded memory in one or more layers of vertically stacked non-volatile embedded memory - Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods to compensate for defective memory in third dimension memory technology. In a specific embodiment, an integrated circuit is configured to compensate for defective memory cells. For example, the integrated circuit can include a memory having memory cells that are disposed in multiple layers of memory. It can also include a memory reclamation circuit configured to substitute a subset of the memory cells for one or more defective memory cells. At least one memory cell in the subset of the memory cells resides in a different plane in the memory than at least one of the one or more defective memory cells. | 07-07-2011 |
20110170349 | DRIFT COMPENSATION IN A FLASH MEMORY - A plurality of memory cells are managed by obtaining values of one or more environmental parameters of the cells and adjusting values of one or more reference voltages of the cells accordingly. Alternatively, a statistic of at least some of the cells, relative to a single reference parameter that corresponds to a control parameter of the cells, is measured, and the value of the reference voltage is adjusted accordingly. Examples of environmental parameters include program-erase cycle count, data retention time and temperature. Examples of reference voltages include read reference voltages and program verify reference voltages. Examples of statistics include the fraction of cells whose threshold voltages exceed initial lower bounds or initial medians. | 07-14-2011 |
20110182121 | DATA RECOVERY FOR NON-VOLATILE MEMORY BASED ON COUNT OF DATA STATE-SPECIFIC FAILS - An error detection and data recovery operation for a non-volatile memory system. Even after a programming operation for a set of storage elements is successfully completed, the data of some storage elements may be corrupted. For example, erased state storage element may be disturbed by programming of other storage elements. To allow recovery of data in such situations, associated data latches can be configured to allow the erased state storage elements to be distinguished from other data states once programming is completed. Furthermore, a single read operation can be performed after programming is completed. Logical operations are performed using results from the read operation, and values in the data latches, to identify erased state storage elements which have strayed to another data state. If the number of errors exceeds a threshold, a full recovery operation is initiated in which read operations are performed for the remaining states. | 07-28-2011 |
20110205796 | NONVOLATILE MEMORY DEVICE AND SYSTEM PERFORMING REPAIR OPERATION FOR DEFECTIVE MEMORY CELL - A nonvolatile memory device comprises a main memory cell array, a redundancy memory cell array, and a controller. The main memory cell array comprises a plurality of bit lines each connected to a plurality of strings arranged perpendicular to a substrate. The redundancy memory cell array comprises a plurality of redundancy bit lines each connected to a plurality of redundancy strings arranged perpendicular to the substrate. The controller is configured to control one of the redundancy bit lines to repair strings in the main memory cell array. | 08-25-2011 |
20110211393 | FLASH MEMORY DEVICE AND SET-UP DATA INITIALIZATION METHOD - A flash memory device includes a memory cell array having a set-up data region configured to store set-up data, wherein the set-up data includes first data and second data. The second data is stored in an empty cell area of the set-up data region. The flash memory also includes a page buffer and decoder configured to read the set-up data from the set-up data region, and a status detector receiving the set-up data from the page buffer and decoder and configured to discriminate the first data from the second data and generate a Pass/Fail status signal. | 09-01-2011 |
20110216591 | PROGRAMMING RATE IDENTIFICATION AND CONTROL IN A SOLID STATE MEMORY - Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes determining a rate of programming (i.e., rate of movement of the respective threshold voltage) of the memory cells and biasing the corresponding bit line with a programming rate control voltage that is greater than the bit line enable voltage and less than the inhibit voltage. This voltage can be adjusted to change the speed of programming. A capacitor coupled to the bit line stores the programming rate control voltage in order to maintain the proper bit line bias for the duration of the programming operation or until it is desired to change the programming rate. | 09-08-2011 |
20110228604 | PRELOADING DATA INTO A FLASH STORAGE DEVICE - Programmer's data is initially stored in a memory device of the storage device by using an MBC storage scheme. After the storage device is embedded in a host device, the programmer's data is internally read from the memory device by using conventional read reference voltages, and the number of erroneous data bits in the programmer's data is calculated. If the programmer's data includes an uncorrectable number of erroneous data bits, the programmer's data is iteratively reread by using unconventional read reference voltages with decreased levels. The iteration process, which includes decreasing the level of the read reference voltages and recalculating the number of erroneous data bits, is terminated when the number of erroneous data bits in the programmer's is less than or equals a predetermined number of erroneous data bits, after which the storage device restores the programmer's data and conventionally rewrites it into the memory device. | 09-22-2011 |
20110228605 | NONVOLATILE MEMORY - A nonvolatile memory includes a memory cell array comprising an object block which includes a first data bit region capable of storing input data and a first flag bit region capable of storing first flag information, a redundant block which includes a second data bit region capable of storing input data and a second flag bit region capable of storing second flag information, and a special block including a special bit region capable of storing an object block address of the object block. The nonvolatile memory includes an object block retention part which retains the object block address. The nonvolatile memory includes an object block flag storage part which stores the first flag information therein. The nonvolatile memory includes a redundant block flag storage part which stores the second flag information. The nonvolatile memory includes a coincidence detection circuit which detects whether a block address which is input coincides with the object block address retained in the object block retention part. The nonvolatile memory includes a block changeover circuit which controls selection of one of the object block and the redundant block on the basis of the first and second flag information when the coincidence detection circuit has detected that the input block address coincides with the object block address. | 09-22-2011 |
20110235415 | READ METHOD FOR NONVOLATILE MEMORY DEVICE, AND DATA STORAGE SYSTEM USING THE SAME - Provided is a method for reading data from a nonvolatile memory device. In the method, a read method includes a first read step including reading a first memory cell of the nonvolatile memory device by applying a first set of read voltages to the first memory cell. The read method further includes a second read step including reading the first memory cell by applying a second set of read voltages and none of the voltages in the first set to the first memory cell when it is determined that the first read step results in an error and cannot be corrected with error correction. The second read step is performed by using data resulting from the first read step. | 09-29-2011 |
20110255338 | Flash memory device and system including the same - The invention provides an operation method of a memory system including a flash memory device. The method includes programming at least one page included in a selected memory block of the flash memory device; and determining the selected memory block or the flash memory device to be invalid, according to whether a loop number of the programmed page is out of a reference loop range. | 10-20-2011 |
20110286271 | MEMORY SYSTEMS AND METHODS FOR READING DATA STORED IN A MEMORY CELL OF A MEMORY DEVICE - A memory system is provided. A memory device includes multiple memory cells for storing data. A controller is coupled to the memory device for accessing the memory device. When reading the data stored in a memory cell, the controller receives a digital signal representing content of the data stored in the memory cell, and detects a level of a voltage or conducted current of the memory cell according to the digital signal to obtain the content of the data. | 11-24-2011 |
20110305086 | SEMICONDUCTOR MEMORY DEVICE - A memory includes stacking chips. The chip includes a pad commonly connected to the chips and receiving an enable signal that enables access to each chip. The chip includes a chip address memory that can store a chip address. The chip includes a determining part comparing a select address to the chip address for determining whether they match each other. The chip includes a control-signal setting part setting the control signal inputted to the chip itself to be valid or invalid depending on a determination made by the determining part. The chip includes a chip-address setting part determining whether the chip address is stored in the chip address memory depending on number of fail bits. The device includes a memory controller allocating respectively different ones of the chip addresses to the chips based on the number of fail bits. | 12-15-2011 |
20110317488 | DATA READING METHOD AND CONTROL CIRCUIT AND MEMORY CONTROLLER USING THE SAME - A data reading method for a flash memory module is provided. The method includes applying a bit-data-read voltage to get read data from memory cells of the flash memory module. The method also includes setting a minus-adjustment-bit-data-read voltage and a plus-adjustment-bit-data-read voltage corresponding to the bit-data-read voltage based on an error-distribution estimated value and applying the minus-adjustment-bit-data-read voltage and the plus-adjustment-bit-data-read voltage to obtain soft values corresponding to the read data from the memory cells. The method further includes calculating a soft-information estimated value corresponding to each bit of the read data according to the soft-values. Accordingly, the method can effectively obtain soft information. | 12-29-2011 |
20120002471 | Memory Bit Redundant Vias - An integrated circuit containing a memory array with memory bits and a differential sense amplifier for reading the logic state of the memory bits. The integrated circuit also contains redundant vias which are in the via path that couples a bitline to Vss. Moreover, an integrated circuit containing a FLASH memory bit with redundant vias in the via path from the bitline to Vss. | 01-05-2012 |
20120002472 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device according to an embodiment includes: a data write portion configured to repeat a write loop until data write is complete, the write loop including a program operation of applying a selected word-line with a program voltage necessary for program and a verify operation of applying the selected word-line with a verify voltage necessary for verify, the program voltage being changed for each write loop by a predetermined step width, the data write being performed in units of a page including a plurality of memory cells selected by the selected word-line; and an endurance determination portion configured to determine the endurance of the memory cells of the page, the data write portion supplies the selected word-line with a program voltage of a step width depending on the endurance. | 01-05-2012 |
20120063227 | SYSTEM AND METHOD FOR ADJUSTING READ VOLTAGE THRESHOLDS IN MEMORIES - A system and method for adjusting read threshold voltage values, for example, in a read circuit internal to a memory device. The quality of an associated read result may be estimated for each read threshold voltage value used to read memory cells. Only read results estimated to have sufficient quality may be allowed to pass to storage. The read threshold voltage value may be adjusted for subsequent read operations, for example, if the associated read result is estimated to have insufficient quality. The read threshold voltage value may be iteratively adjusted, for example, until a read result is estimated to have sufficient quality. | 03-15-2012 |
20120069657 | MEMORY DEVICE AND SELF INTERLEAVING METHOD THEREOF - A memory device includes a memory cell array, a self interleaver configured to interleave and load data on the fly into a buffer circuit using an interleaving scheme, and a control logic configured to control programming of the interleaved data in the memory cell array. | 03-22-2012 |
20120069658 | METHODS, DEVICES, AND SYSTEMS FOR DEALING WITH THRESHOLD VOLTAGE CHANGE IN MEMORY DEVICES - The present disclosure includes methods, devices, and systems for dealing with threshold voltage change in memory devices. A number of embodiments include an array of memory cells and control circuitry having sense circuitry coupled to the array. The control circuitry is configured to determine changes in threshold voltages (Vts) associated with the memory cells without using a reference cell, and adjust the sense circuitry based on the determined changes and without using a reference cell. | 03-22-2012 |
20120069659 | MEMORY WITH INTERLEAVED READ AND REDUNDANT COLUMNS - Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of columns. Each of the columns includes a bit line and a plurality of memory cells on the bit line. The plurality of columns include a plurality of groups of regular columns and a plurality of groups of redundant columns. The apparatus also includes a plurality of data latches. Each of the data latches is configured to store data read from a respective one group of regular columns. The apparatus further includes a plurality of redundant data latches. Each of the redundant data latches is configured to store data read from a respective one group of redundant columns. The apparatus also includes a multiplexer configured to selectively output data from the plurality of data latches and the plurality of redundant data latches. | 03-22-2012 |
20120081959 | MEMORY SYSTEM AND PROGRAMMING METHOD THEREOF - Provided are a non-volatile memory system and a programming method thereof. The programming method of the non-volatile memory system includes adjusting a program-verify-voltage of a selected memory cell referring to program data to be written in an interfering cell configured to provide interference for the selected memory cell and programming the selected memory cell depending on the adjusted program-verify-voltage. | 04-05-2012 |
20120092927 | MEMORY SYSTEM - A memory system includes a NAND flash memory having a page buffer capable of holding a page of data and a cell array having a plurality of pages. The system also includes a plurality of memory portions electrically connected to the NAND flash memory via a data bus, and a controller for controlling the NAND flash memory and the plurality of memory portions. A width of the data bus is less than a size of the page of data. When any one of a write operation and a read operation is performed on the NAND flash memory, the controller exchanges data held in the page buffer and data held in one memory portion of the plurality of memory portions. | 04-19-2012 |
20120113719 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE, NONVOLATILE SEMICONDUCTOR STORAGE SYSTEM AND METHOD OF MANAGING OF DEFECTIVE COLUMN IN NONVOLATILE SEMICONDUCTOR STORAGE SYSTEM - A nonvolatile semiconductor storage device is disclosed, which includes a memory cell array in which nonvolatile memory cells are arranged, a first data holding circuit which temporarily holds a collective processing unit of read or write data to be simultaneously read from or written to the memory cells, a circuit which takes out the data held in the first data holding circuit from the device, and a second data holding circuit in which data is automatically set at a time when power supply is turned on and in which the data is changeable based on a command input to the device, wherein the collective processing unit is equal to a sum of the number of units used within the device and the maximum number of units continuously output from the device to outside or input to the device from outside. | 05-10-2012 |
20120155172 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a first memory and a second memory, a data path between the first memory and the second memory, a register configured to store first data transferred through the data path in a first direction, and a comparison circuit configured to compare second data transferred through the data path in a second direction with the first data stored in the register so as to detect a fault location. | 06-21-2012 |
20120155173 | Universal Timing Waveforms Sets to Improve Random Access Read and Write Speed of Memories - Methods of increasing the speed of random read and write operations of a memory device are provided for improving the performance of volatile and non-volatile memory devices. In contrast to the conventional approach that latches the current memory address right before the currently accessed memory data are outputted, the methods latch the next memory address before the currently accessed memory data are read out. The flow, timing waveforms and control sequences of applying the methods to parallel NOR flash, parallel pSRAM, serial SQI NOR flash and NAND flash are described in detail. The NOR flash device designed with the method can be integrated with a NAND flash device on a same die in a combo flash device packaged in either an ONFI compatible NAND flash package or other standard NAND flash package. | 06-21-2012 |
20120155174 | Use of Alternative Value in Cell Detection - A system and method, including computer software, allows reading data from a flash memory cell. Voltages from a group of memory cells are detected. The group of memory cells have associated metadata for error detection, and each memory cell stores a voltage representing a data value selected from multiple possible data values. Each possible data value corresponds to one range of multiple non-overlapping ranges of analog voltages. Memory cells having uncertain data values are identified based on the detected voltages. Alternative data values for the memory cells having the uncertain data values are determined, and a combination of alternative data values is selected. An error detection test is performed using the metadata associated with the multiple memory cells and the selected combination of alternative data values. | 06-21-2012 |
20120206964 | PROGRAMMING RATE IDENTIFICATION AND CONTROL IN A SOLID STATE MEMORY - Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes determining a rate of programming (i.e., rate of movement of the respective threshold voltage) of the memory cells and biasing the corresponding bit line with a programming rate control voltage that is greater than the bit line enable voltage and less than the inhibit voltage. This voltage can be adjusted to change the speed of programming. A capacitor coupled to the bit line stores the programming rate control voltage in order to maintain the proper bit line bias for the duration of the programming operation or until it is desired to change the programming rate. | 08-16-2012 |
20120213003 | NON-VOLATILE MEMORY DEVICE AND RELATED READ METHOD - A nonvolatile memory device comprises a memory cell array, a page buffer, and a bit line connection signal controller. The memory cell array comprises a plurality of word lines and bit lines arranged in rows and columns, and a plurality of memory cells connected to the respective word lines and bit lines. The page buffer connects a selected bit line among the plurality of bit lines to the page buffer, applies a precharge voltage to the selected bit line, and senses a voltage of the selected bit line after developing of the selected bit line according to a bit line connection signal, during a read operation. The bit line connection signal controller changes the bit line connection signal according to a control signal, during the read operation. | 08-23-2012 |
20120224425 | Using Temperature Sensors with a Memory Device - In one implementation, a method for performing memory operations includes receiving, at a memory device, a request to read data from one or more non-volatile memory cells; and retrieving stored temperature information associated with the non-volatile memory cells, wherein the temperature information is associated with a temperature at approximately at a time when the data was written to the non-volatile memory cells. The method can further include reading, by the memory device, the data from the non-volatile memory cells. The method can also include processing the read data based on, at least, the retrieved temperature information; and providing the processed data. | 09-06-2012 |
20120250410 | SEMICONDUCTOR INTEGRATED CIRCUIT AND DATA READ METHOD - A semiconductor integrated circuit includes a memory cell area comprising a main cell and a spare cell, and a memory controller configured to set an offset value using a program verify level which is set during a program operation, and set a read level using the offset value during a read operation. | 10-04-2012 |
20120250411 | NONVOLATILE SEMICONDUCTOR MEMORY - According to one embodiment, a nonvolatile semiconductor memory includes a memory cell array including memory cells of a first unit in which read and write are parallelly performed, n (n is a natural number of not less than 2) sense amplifiers, n detection circuits corresponding to the n sense amplifiers, an accumulator configured to divide the first unit data read from the memory cell array into z (z is a natural number) second unit data and accumulate a fail bit for which the write is incomplete for the second unit data, and a control circuit configured to control an operation of detecting the fail bit after the write. | 10-04-2012 |
20120275222 | NONVOLATILE MEMORY APPARATUS AND VERIFICATION METHOD THEREOF - A nonvolatile memory apparatus includes: a memory cell array including a plurality of unit memory cells; a page buffer unit configured to read data from a selected memory cell of the memory cell array and store the read data; a controller configured to generate a reference current generation signal, a first current control signal, and a second current control signal, which correspond to the number of fail bits to be sensed and a deviation in cell current amounts flowing through the unit memory cells during a read operation, in response to a verification command; and a fail bit sensing unit configured to receive the reference current generation signal, the first current control signal, and the second current control signal from the controller in response to the verification command, and control at least one of a reference current amount and a data read current amount of the page buffer unit. | 11-01-2012 |
20120314498 | Method for Detecting Flash Program Failures - One or more techniques are provided for programming a flash memory device. In one embodiment, the memory device is programmed such that a data pattern written to a page in the memory device has encoded therein an expected count value corresponding to the number of times a first binary value occurs in the data pattern. The data pattern includes the program data and the expected count value, and is written to the page in a single operation. The expected count value may be stored in a count field in the management area of the page. During a page read operation, the expected count value is compared to the actual count of the number of bits having the first binary value in the data area of the page. If the expected count is equal to the actual count, then the program data is determined to be valid. | 12-13-2012 |
20120320676 | SEMICONDUCTOR SYSTEM, NONVOLATILE MEMORY APPARATUS, AND AN ASSOCIATED READ METHOD - A semiconductor system includes a host configured to output a command, a control signal, an address signal, and data; and a nonvolatile memory apparatus configured to receive at least one of the command, the control signal, the address signal, and the data from the host, to provide a process result to the host, and to determine data levels of memory cells included in an overlap section of memory cell threshold voltage distributions based on an initial read bias voltage. | 12-20-2012 |
20130003459 | Read Error Recovery for Solid-State Memory Based on Cumulative Background Charges - A read error is determined that affects a page of solid-state, non-volatile memory. The page is associated with a selected word line that crosses a plurality of NAND strings coupled to respective grounds and bit lines. Word lines of the memory are ordered from a lower end proximate the ground to a higher end proximate the bit lines. Cumulative background charges each associated with one of the memory cells of the page are determined. The cumulative background charges are based on charge levels of respective cells of a plural subset of the word lines that are lower in order than the selected word line. A recovery operation is performed on the page using the cumulative background charges. | 01-03-2013 |
20130010538 | MEMORY DEVICE AND METHOD FOR REPAIRING A SEMICONDUCTOR MEMORY - A block repair device is used in a Dynamic Random Access Memory (DRAM) having a primary array with a defective cell and a redundant array with a redundant row. The block repair device stores a block repair configuration that determines the dimensions (e.g., the number of rows and columns spanned) of a repair block. Routing circuitry is configured by the stored block repair configuration to output some row and column address bits from received row and column addresses in a selected ratio. Comparison circuitry compares the row and column address bits output by the routing circuitry with the address of the defective cell that defines the repair block. When a match occurs, the comparison circuitry implements a block repair by activating the redundant row and by causing data to be written to or read from the activated redundant row instead of the primary array. | 01-10-2013 |
20130039129 | MEMORY DEVICES AND CONFIGURATION METHODS FOR A MEMORY DEVICE - Memory devices and methods of operating memory devices are disclosed. In one such method, different blocks of memory cells have different configurations of user data space and overhead data space. In at least one method, overhead data is distributed within more than one block of memory cells. In another method, blocks are reconfigurable responsive to particular operating modes and/or desired levels of reliability of user data stored in a memory device. | 02-14-2013 |
20130051143 | MEMORY CELL COUPLING COMPENSATION - Methods for memory cell coupling compensation and apparatuses configured to perform the same are described. One or more methods for memory cell coupling compensation includes determining a state of a memory cell using a voltage that is changed in accordance with a first memory cell coupling compensation voltage, performing an error check on the state of the memory cell, and determining the state of the memory cell using a voltage that is changed in accordance with a second memory cell coupling compensation voltage in response to the error check failing. | 02-28-2013 |
20130058164 | MEMORY APPARATUS, SYSTEMS, AND METHODS - Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed aggressor memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation. Additional apparatus, systems, and methods are provided. | 03-07-2013 |
20130107626 | METHODS FOR SEGMENTED PROGRAMMING AND MEMORY DEVICES | 05-02-2013 |
20130128665 | NON-VOLATILE STORAGE WITH BROKEN WORD LINE SCREEN AND DATA RECOVERY - Data, normally read using a page-by page read process, can be recovered from memory cells connected to a broken word line by performing a sequential read process. To determine whether a word line is broken, both a page-by page read process and a sequential read process are performed. The results of both read processes are compared. If the number of mismatches between the two read processes is greater than a threshold, it is concluded that there is a broken word line. | 05-23-2013 |
20130141975 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING THE SAME - A semiconductor memory device capable of reducing the size of a NAND flash memory device includes a latch unit configured to store a bad block address, a comparator configured to compare the bad block address with an access address so as to output a bad-block detection signal, and a bad block controller configured to sequentially output a plurality of bad block pulses corresponding to the bad-block detection signal during a predetermined period in response to a plurality of bad-block flag signals that are sequentially activated. | 06-06-2013 |
20130163330 | MITIGATING VARIATIONS ARISING FROM SIMULTANEOUS MULTI-STATE SENSING - Methods and devices for mitigating sensing variations that may arise from simultaneous multi-threshold (SMT) sensing are provided. During SMT sensing, two or more different bias conditions may be used to simultaneously sense two different threshold voltages. However, there may be variances in the threshold voltage shift of memory cells when read with a different bias condition than was used to verify. In one embodiment each programmed state is read using both (or all) bias conditions that were used during SMT verify. In other words, two (or more) different sense operations are used to read each memory cell. The data from these different sense operations may be used to compute initialization values (e.g., LLRs, LRs, probabilities) for an ECC decoder. In one embodiment, this technique is only performed when a normal read fails. | 06-27-2013 |
20130170295 | SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF - A semiconductor memory device includes an information generation unit configured to convert positions of threshold voltages of memory cells in threshold voltage distributions based on determination voltages included in an overlapping portion between the threshold voltage distributions to generate a plurality of position information codes, and an error correction unit configured to sequentially receive the plurality of position information codes and perform an error correction operation for data of the memory cells. | 07-04-2013 |
20130170296 | MEMORY CONTROLLER FOR MULTI-LEVEL MEMORY DEVICE AND ERROR CORRECTING METHOD - Disclosed is an error correcting method of a memory controller which controls a nonvolatile memory device. The error correcting method includes judging whether first read data read from the nonvolatile memory device is correctable; reading second read data from the nonvolatile memory device when the first read data is uncorrectable; and correcting an error of the first read data based on error information of the second read data and error information of the first read data. | 07-04-2013 |
20130170297 | NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - According to example embodiments, a nonvolatile memory device includes a first and a second NAND string. The first NAND string includes a first string selection transistor, a first local ground and a first global ground selection transistor, and first memory cells stacked in a direction perpendicular to a substrate. The second NAND string includes a second string selection transistor, a second local ground and a second global ground selection transistor, and second memory cells stacked in the direction perpendicular to the substrate. The device includes a selection line driver including path transistors configured to select and provide at least one operation voltage to the first and second string selection transistors, the first and second local and global ground selection transistors. The first and second string selection transistors are electrically isolated from each other, and the first and second global ground selection transistors are electrically connected. | 07-04-2013 |
20130176783 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND WRITE-IN METHOD THEREOF - TASK: to minimize variations of the threshold voltage distribution after programming and obtain a high-speed rewriting characteristic. MEANS FOR SOLVING THE PROBLEM: A non-volatile semiconductor memory device includes a non-volatile memory cell array and a control circuit for controlling writing-in to the memory cell array, wherein before or after an erasing process where data of written-in memory cells is erased, the control circuit detects a programming speed when writing-in to the memory cell array, determines a programming start voltage corresponding to the programming speed for every block or every word line, stores the determined programming start voltage in the memory cell array and reads-out the programming start voltage from the memory cell array to write-in predetermined data. | 07-11-2013 |
20130242655 | Techniques for Accessing Column Selecting Shift Register with Skipped Entries in Non-Volatile Memories - Techniques are present for locating an initial physical location in a looping shift register with random skips on each loop. Here the shift register is for accessing columns in a non-volatile memory, where defective columns of the array are skipped. A look-up table provides for the initial skip of each loop, providing the number of skips from preceding loop to provide a physical address is close to the actual physical address. A new structure of shift registers then enables an automatic shift mode within the loop. The new structure has an additional register and logic gates that count how many skipped entry before the current pointer and shift the current pointer accordingly. | 09-19-2013 |
20130242656 | HOST EQUIPMENT, MEMORY CONTROLER, AND MEMORY DEVICE - A memory controller includes a processor that includes a monitoring module, a control module, and a parity generating module. The monitoring module receives a data sequence and checks the data sequence for a designated pattern. The control module determines page size of data sequences that include the designated pattern and arranges an idle area for each page based on the total data quantity and the size of the data sequence, where the data quantity of the data stored in each page is uniform. The parity generating module generates the extended parity in the idle area based on a portion of the data stored in each page and the management information of the page. In each page, the control module stores a portion of the data and the extended parity in the idle area. | 09-19-2013 |
20130242657 | USE OF EMERGING NON-VOLATILE MEMORY ELEMENTS WITH FLASH MEMORY - Memory devices and methods of operating memory devices are provided, such as those that involve a memory architecture that replaces typical static and/or dynamic components with emerging non-volatile memory (NV) elements. The emerging NV memory elements can replace conventional latches, can serve as a high speed interface between a flash memory array and external devices and can also be used as high performance cache memory for a flash memory array. | 09-19-2013 |
20130258774 | READING MEMORY CELL HISTORY DURING PROGRAM OPERATION FOR ADVAPTIVE PROGRAMMING - Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a memory device. | 10-03-2013 |
20130279254 | SEMICONDUCTOR MEMORY STORAGE APPARATUS HAVING CHARGE STORAGE LAYER AND CONTROL GATE - According to one embodiment, a semiconductor memory storage apparatus includes an array, a sense amplifier, and a controller. The array includes a memory cell. The sense amplifier includes a first latch and a second latch. The first latch and the second latch are capable of storing a data read out from the memory cell. The controller performs a first operation, a second operation, and a third operation. In the first operation, the controller transfers an inverted data in the first latch to the first node and transfers the data in the second latch. In the second operation, the controller transfers the data in the first latch to the first node and transfers an inverted data in the second latch. | 10-24-2013 |
20130286736 | DETERMINING AND USING SOFT DATA IN MEMORY DEVICES AND SYSTEMS - The present disclosure includes methods, devices, and systems for determining and using soft data in memory devices and systems. One or more embodiments include an array of memory cells and control circuitry coupled to the array. The control circuitry is configured to perform a number of sense operations on the memory cells using a number of sensing voltages to determine soft data associated with a target state of the memory cells, and adjust a sensing voltage used to determine the target state based, at least partially, on the determined soft data. | 10-31-2013 |
20130294162 | Column Redundancy Circuitry for Non-Volatile Memory - In a non-volatile memory circuit, techniques are presented so that bad columns can be ignored and/or replaced during memory data input and output operations. A column redundant circuit for this purpose reduces circuit size and improves performance. User data is grouped in an interleaved manner so that data belonging to consecutive logical address will be distributed into different physical locations. For example, all column data can be physically grouped into, say, 5 divisions and user data can be written into or accessed from one division after another consecutively. Each division has its own clock control. The column redundancy block can generate bad column locations' information and send it to control logic to switch the user clock to a different division clock, thereby skipping bad columns. By controlling the clocks for different columns, the user can directly access good columns without touching bad columns. | 11-07-2013 |
20130301353 | Methods of Driving a Memory - Methods of driving a memory include erasing a plurality of memory cells of a memory device, testing whether the memory cells have been erased, and programming the memory cells without erasing the memory cells again if more than a predetermined percentage of the memory cells, but less than all of the memory cells, were successfully erased. | 11-14-2013 |
20130314992 | SEMICONDUCTOR MEMORY AND METHOD OF CONTROLLING THE SAME - According to one embodiment, a memory includes main and redundancy regions including cells, first units in the main region, second units in the redundancy region, a column control circuit configured to selects the first units using a first pointer corresponding to an address signal, and selects the second unit using a second pointer when defect address of the main region matches the address signal so that defect first unit is replaced with the second unit, a selection circuit configured to connects one of a first path for the main region and a second path for the redundancy region to a third path based on a comparison result between the address signal and the defect address. | 11-28-2013 |
20130314993 | PROGRAMMING RATE IDENTIFICATION AND CONTROL IN A SOLID STATE MEMORY - Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes determining a rate of programming (i.e., rate of movement of the respective threshold voltage) of the memory cells and biasing the corresponding bit line with a programming rate control voltage that is greater than the bit line enable voltage and less than the inhibit voltage. This voltage can be adjusted to change the speed of programming. A capacitor coupled to the bit line stores the programming rate control voltage in order to maintain the proper bit line bias for the duration of the programming operation or until it is desired to change the programming rate. | 11-28-2013 |
20130322174 | Threshold Voltage Adjustment For A Select Gate Transistor In A Stacked Non-Volatile Memory Device - In a 3D stacked non-volatile memory device, the threshold voltages are evaluated and adjusted for select gate, drain (SGD) transistors at drain ends of strings of series-connected memory cells. To optimize and tighten the threshold voltage distribution, the SGD transistors are read at lower and upper levels of an acceptable range. SGD transistors having a low threshold voltage are subject to programming, and SGD transistors having a high threshold voltage are subject to erasing, to bring the threshold voltage into the acceptable range. The evaluation and adjustment can be repeated such as after a specified number of program-erase cycles of an associated sub-block. The condition for repeating the evaluation and adjustment can be customized for different groups of SGD transistors. Aspects include programming SGD transistors with verify and inhibit, erasing SGD transistors with verify and inhibit, and both of the above. | 12-05-2013 |
20130329494 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device has memory cell arrays, with the memory cells arranged in a matrix configuration and divided into p areas in the column direction, a column redundancy area arranged in a portion of the memory cell array and having redundancy columns that can substitute for defective user data columns, and a column substituting register that holds the column substituting information for substituting the defective user data columns of the selected area with the redundancy columns. | 12-12-2013 |
20130329495 | SEMICONDUCTOR MEMORY AND SEMICONDUCTOR MEMORY CONTROL METHOD - According to one embodiment, a semiconductor memory includes memory cells, word lines connected to gate of memory cells arranged in a row direction, a control circuit which controls the operation of the memory cells. During k-level data writing to a selected cell, the control circuit applies the corrected unselect voltage in accordance with the result of the reading of data from the unselected cell connected to the adjacent word line to the adjacent word line and applies a read voltage to the selected word line to read (k−1)-level data from the selected cell, and the control circuit writes data to the selected cell in accordance with the read (k−1)-level and the k-level data to be written. | 12-12-2013 |
20130336059 | BLOCK LEVEL GRADING FOR RELIABILITY AND YIELD IMPROVEMENT - A system for grading blocks may be used to improve memory usage. Blocks of memory, such as on a flash card, may be graded on a sliding scale that may identify a level of “goodness” or a level of “badness” for each block rather than a binary good or bad identification. This grading system may utilize at least three tiers of grades which may improve efficiency by better utilizing each block based on the individual grades for each block. The block leveling grading system may be used for optimizing the competing needs of minimizing yield loss while minimizing testing defect escapes. | 12-19-2013 |
20130336060 | MEMORY DEVICE AND REDUNDANCY METHOD THEREOF - A memory device includes at least one memory, a controller controlling the at least one memory and a connect unit. The at least one memory includes a memory region comprising a plurality of memory cells, a redundant memory region comprising a plurality of memory cells and a redundancy information memory unit. The redundancy information memory unit stores redundancy information of the memory cells of the memory region. The controller includes a control unit. The control unit controls data read-out from the at least one memory and data to be written-in to the at least one memory according to the redundancy information stored in the redundancy information memory unit. | 12-19-2013 |
20140036589 | MEMORY CELL STATE IN A VALLEY BETWEEN ADJACENT DATA STATES - The present disclosure includes apparatuses and methods related to memory cell state in a valley between adjacent data states. A number of methods can include determining whether a state of a memory cell is in a valley between adjacent distributions of states associated with respective data states. The method can also include transmitting a signal indicative of a data state of the memory cell and whether the state of the memory cell is in the valley. | 02-06-2014 |
20140063944 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device and a method of operating the same are disclosed. The semiconductor memory device includes a memory cell block configured to have memory cell groups, a peripheral circuit configured to read data by supplying a read voltage to memory cells in the memory cell groups, a fail detection circuit configured to perform a pass/fail check operation of memory cell groups according to the data read by the peripheral circuit and a control circuit configured to control the peripheral circuit and the fail detection circuit to perform again the read operation about the memory cell groups using a compensation read voltage different from the read voltage in the event that it is determined that one or more memory cell group is failed according to the pass/fail check operation. | 03-06-2014 |
20140063945 | READ METHOD FOR NONVOLATILE MEMORY DEVICE, AND DATA STORAGE SYSTEM USING THE SAME - Provided is a method for reading data from a nonvolatile memory device. In the method, a read method includes a first read step including reading a first memory cell of the nonvolatile memory device by applying a first set of read voltages to the first memory cell. The read method further includes a second read step including reading the first memory cell by applying a second set of read voltages and none of the voltages in the first set to the first memory cell when it is determined that the first read step results in an error and cannot be corrected with error correction. The second read step is performed by using data resulting from the first read step. | 03-06-2014 |
20140092683 | ADJUSTABLE READ TIME FOR MEMORY - A method facilitates controlling a read time (tREAD) of an electronic memory device. The method includes implementing a first read time indicative of an array time for a read process for a memory array of the electronic memory device. The first read time relates to the time allocated to make data available at an I/O buffer of the electronic memory device for access by a controller. The method also includes implementing a second read time for the electronic memory device. The second read time has a total duration which is different from the first read time. In this way, different read times can be implemented for read operations at the same electronic memory device. The read times may be changed automatically based on one or more performance parameters (e.g., RBER, P/E count, etc.) of the electronic memory device. | 04-03-2014 |
20140104947 | NON-VOLATILE SEMICONDUCTOR MEMORY DATA READING METHOD THEREOF - A non-volatile semiconductor memory includes a memory array, a selecting device selecting a page according to addresses, a data storage device, storing page data, and an output device outputting the stored data. The data storage device includes a first data storage device receiving data from a selected page of the memory array, a second data storage device receiving data from the first data storage device, and a data transmission device configured between the first and the second data storage device. The data transmission device transmits data in a second part of the first data storage device to the second data storage device when data in a first part of the second data storage device is output, and transmits data in a first part of the first data storage device to the second data storage device when data in a second part of the second data storage device is output. | 04-17-2014 |
20140133228 | Key-Value Addressed Storage Drive Using NAND Flash Based Content Addressable Memory - A NAND Flash based content addressable memory (CAM) is used for a key-value addressed storage drive. The device can use a standard transport protocol such as PCI-E, SAS, SATA, eMMC, SCSI, and so on. A host writes a key-value pair to the drive, where the drive writes the keys along bit lines of a CAM NAND portion of the drive and stores the value in the drive. The drive then maintains a table linking the keys to location of the value. In a read process, the host provides a key to drive, which then broadcasts down the word lines of blocks storing the keys. Based on any matching bit lines, the tables can then be used to retrieve and supply the corresponding data to the host. | 05-15-2014 |
20140153332 | DETERMINING SOFT DATA FROM A HARD READ - Apparatuses and methods involving the determination of soft data from hard reads are provided. One example method can include determining, using a hard read, a state of a memory cell. Soft data is determined based, at least partially, on the determined state. | 06-05-2014 |
20140160845 | SETTING A DEFAULT READ SIGNAL BASED ON ERROR CORRECTION - The present disclosure includes apparatuses and methods related to setting a default read signal based on error correction. A number of methods can include reading a page of data from a group of memory cells with a first discrete read signal and error correcting at least one codeword of the page of data as read with the first discrete read signal. Methods can include reading a page of data from the group of memory cells with a second discrete read signal different than the first discrete read signal and error correcting at least one codeword of the page of data as read with the second discrete read signal. One of the first and the second discrete read signals can be set as a default read signal based at least in part on the respective error corrections. | 06-12-2014 |
20140169091 | MEMORY CONTROLLER, STORAGE DEVICE, AND MEMORY CONTROL METHOD - According to one embodiment, a memory controller controlling a NAND memory having D bits/cell, includes: a code encoder which generates a code word having correction capability of t symbols; a write control unit which controls writing of the code word to the NAND memory; and a code decoder which decodes the code word read from the NAND memory, wherein the write control unit dispersedly allocates 2×D pages stored in adjacent two word lines in a block of the NAND memory to 2×D/t or more code words. | 06-19-2014 |
20140169092 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first data bus having a first width, and a second data bus which is separate from the first data bus and which has a second width which is different from the first width. The semiconductor memory device further includes a data transfer unit configured for transferring data from memory cells connected to a plurality of bit lines. In a first operational mode, the data transfer unit connects a first number of bit lines from among the plurality of bit lines to the first data bus to transfer the data, the first number being equal to the first width. In a second operational mode, the data transfer unit connects a second number of bit lines from among the plurality of bit lines to the second data bus to transfer the data, the second number being equal to the second width. | 06-19-2014 |
20140185380 | SEMICONDUCTOR MEMORY DEVICE HAVING FAULTY CELLS - In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories. | 07-03-2014 |
20140204671 | SYSTEMS AND METHODS OF UPDATING READ VOLTAGES - A method includes, in a data storage device that includes a non-volatile memory, reading data from the non-volatile memory using a first read voltage. The method includes determining a first count of errors in the data having a first error type and a second count of errors in the data having a second error type. A value of the first read voltage is selectively updated based on a comparison of the first count to the second count. | 07-24-2014 |
20140219023 | Bad Column Management with Bit Information in Non-Volatile Memory Systems - Column based defect management techniques are presented. Each column of the memory has an associated isolation latch or register whose value indicates whether the column is defective, but in addition to this information, for columns marked as defective, additional information is used to indicate whether the column as a whole is to be treated as defective, or whether just individual bits of the column are defective. The defective elements can then be re-mapped to a redundant element at either the appropriate bit or column level based on the data. When a column is bad, but only on the bit level, the good bits can still be used for data, although this may be done at a penalty of under programming for some bits, as is described further below. A self contained Built In Self Test (BIST) flow constructed to collect the bit information through a set of column tests is also described. Based on this information, the bad bits can be extracted and re-grouped into bytes by the controller or on the memory to more efficiently use the column redundancy area. | 08-07-2014 |
20140233314 | MEMORY CELL COUPLING COMPENSATION - Methods for memory cell coupling compensation and apparatuses configured to perform the same are described. One or more methods for memory cell coupling compensation includes determining a state of a memory cell using a voltage that is changed in accordance with a first memory cell coupling compensation voltage, performing an error check on the state of the memory cell, and determining the state of the memory cell using a voltage that is changed in accordance with a second memory cell coupling compensation voltage in response to the error check failing. | 08-21-2014 |
20140241059 | METHOD AND DEVICE FOR STORING AND READING RELIABLE INFORMATION IN A NAND ARRAY - A method (and device) includes producing first data in a page region of a memory, the first data including a first number of memory sets, each of the memory sets having a second number of bits, where the first number is a positive number more than one and the second number is a positive number more than three. After the producing the first data in the page region of the memory, second data is produced in response to the produced first data, the second data having the first number of bits, each of the bits of the second data having a logic value that is determined by a majority of the bits included in a corresponding one of the memory sets. | 08-28-2014 |
20140269065 | NAND Flash Memory - Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR (“HPSF-NOR”) memory read commands so that the serial NAND flash memory may be used with controllers designed for HPSF-NOR memory. Serial NAND flash memory having these compatibilities is referred to herein as high-performance serial flash NAND (“SPSF-NAND”) memory. Since devices and systems which use HPSF-NOR memories and controllers often have extreme space limitations, HPSF-NAND may also be provided with the same physical attributes of low pin count and small package size of HPSF-NOR memory for further compatibility. HPSF-NAND memory is particularly suitable for code shadow applications, even while enjoying the low “cost per bit” and low per bit power consumption of a NAND memory array at higher densities. | 09-18-2014 |
20140269066 | METHODS FOR EXTENDING THE EFFECTIVE VOLTAGE WINDOW OF A MEMORY CELL - Methods for operating a non-volatile storage system in which cross-coupling effects are utilized to extend the effective threshold voltage window of a memory cell and to embed additional information within the extended threshold voltage window are described. In some cases, additional information may be embedded within a memory cell storing the highest programming state if the memory cell is in a high boosting environment by splitting the highest programming state into two substates and programming the memory cell to one of the two substates based on the additional information. A memory cell may be in a high boosting environment if its neighboring memory cells are in a high programmed state. Additional information may also be embedded within a memory cell storing the lowest programming state if the memory cell is in a low boosting environment. The additional information may include error correction information. | 09-18-2014 |
20140286097 | THERMALLY ASSISTED FLASH MEMORY WITH DIODE STRAPPING - A memory includes an array of memory cells including rows and columns. The memory includes circuitry coupled to the word lines applying a first bias voltage to a first set of spaced-apart locations on a word line or word lines in the array, while applying a second bias voltage different than the first bias voltage, to a second set of spaced-apart locations on the word line or word lines, locations in the first set of spaced-apart locations being interleaved among locations in the second set of spaced-apart locations, whereby current flow is induced between locations in the first and second sets of locations that cause heating of the word line or word lines. | 09-25-2014 |
20140301142 | SYSTEMS AND METHODS OF WRITE PRECOMPENSATION TO EXTEND LIFE OF A SOLID-STATE MEMORY - Write precomensation mechanisms for non-volatile solid-state memory are disclosed. In one embodiment, programming verify voltage levels are lowered from the default levels in the early life of the solid-state memory. As memory errors increase beyond an error threshold, programming verify voltage levels are increased by one or more voltage step sizes. This programming verify voltage level increase can be performed until default levels are reached or exceeded. As a result of lowered programming verify voltage levels in the early life of the solid-state memory device, solid-state memory experiences less wear and the operational life of the memory can be extended. Disclosed write precomensation mechanisms can be used for single-level cell (SLC) and multi-level cell (MLC) memory. | 10-09-2014 |
20140301143 | TECHNIQUES FOR CONTROLLING RECYCLING OF BLOCKS OF MEMORY - In operation, respective lifetime expectancy scores are calculated for each of a plurality of blocks of a memory based on a respective count percentage of free space of each of the blocks. The blocks are recycled based on at least some of the life expectancy scores. A total amount of the blocks that are re-written is minimized while equalizing lifetime expectancy score variation between the blocks. | 10-09-2014 |
20140321206 | READING MEMORY CELL HISTORY DURING PROGRAM OPERATION FOR ADAPTIVE PROGRAMMING - Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a memory device. | 10-30-2014 |
20140355344 | Adaptive Operation of Three Dimensional Memory - When data from a portion of a three dimensional NAND memory array is determined to be uncorrectable by Error Correction Code (ECC), a determination is made as to whether data is uncorrectable by ECC throughout some unit that is larger than the portion. If modified read conditions provide ECC correctable data, the modified read conditions are recorded for subsequent reads of the larger unit. | 12-04-2014 |
20140355345 | Adaptive Operation of Three Dimensional Memory - When data from a portion of a three dimensional NAND memory array is determined to be uncorrectable by Error Correction Code (ECC), a determination is made as to whether data is uncorrectable by ECC throughout some unit that is larger than the portion. If modified read conditions provide ECC correctable data, the modified read conditions are recorded for subsequent reads of the larger unit. | 12-04-2014 |
20150049546 | METHOD OF PROGRAMMING FUSE CELLS AND REPAIRING MEMORY DEVICE USING THE PROGRAMMED FUSE CELLS - A plurality of fuse cells includes a first fuse cell and a second fuse cell. Each of the first and second fuse cells includes a first anti-fuse and a second anti-fuse. A method of programming the fuse cells includes rupturing the first anti-fuse of the first fuse cell based on first data loaded to a program control circuit. The method includes rupturing the second anti-fuse of the first fuse cell before loading second data to the program control circuit. The second data is for rupturing the first anti-fuse of the second fuse cell or the second anti-fuse of the second fuse cell. | 02-19-2015 |
20150049547 | METHOD CONTROLLING READ SEQUENCE OF NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM PERFORMING SAME - To control a read sequence of a nonvolatile memory device, a plurality of read sequences are set and the read sequences respectively correspond to operating conditions different from each other. The read sequences are performed selectively based on sequence selection rates respectively corresponding to the read sequences. Read latencies of the respective read sequences are monitored and the sequence selection rates are adjusted based on monitoring results of the read latencies. | 02-19-2015 |
20150070993 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to an embodiment comprises: a memory string including a first memory cell and a second memory cell; a first word line connected to a gate of the first memory cell; a second word line connected to a gate of the second memory cell; and a peripheral circuit configured to control a write sequence and a read sequence, the peripheral circuit, during the write sequence or the read sequence on the first memory cell, executing a first operation on the condition that a positive first pass voltage is applied to the first word line and the second word line. | 03-12-2015 |
20150078085 | SEMICONDUCTOR DEVICE HAVING STACKED CHIPS - According to one embodiment, a semiconductor device includes chips and a first selection circuit. Each of the chips has at least first and second vias for transmitting at least first and second address signals, these chips are stacked to be electrically connected via the first and second vias. The first selection circuit is provided in each chip, includes a logic circuit that selects a chip based on at least the first and second address signals, and supplies a result of operating the first and second address signals to the subsequent chip. | 03-19-2015 |
20150138885 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE, AND SEMICONDUCTOR DEVICE - A non-volatile semiconductor storage device includes a memory cell array divided into blocks, each of which is a erasable unit, the blocks, the blocks including a first block which is determined to be a bad block and a second block which is determined to be a partial bad block, a storage unit configured to store address information of the first block and the second block, and a block decoder including a latch section which is configured to control selection and non-selection of the blocks, and to release data held by the latch section based on the stored address information of the second block. | 05-21-2015 |
20150325298 | MEMORY ACCESS TECHNIQUES FOR A MEMORY HAVING A THREE-DIMENSIONAL MEMORY CONFIGURATION - A data storage device includes a memory having a three-dimensional (3D) memory configuration. A method includes writing first data at a first physical page that is disposed within the memory at a first distance from a substrate of the memory. The first data is written at the first physical page using a first write technique. The method further includes writing second data at a second physical page that is disposed within the memory at a second distance from the substrate. The second distance is greater than the first distance. The second data is written at the second physical page using a second write technique that is different than the first write technique. | 11-12-2015 |
20160019982 | MEMORY SYSTEM AND METHOD OF CONTROLLING MEMORY SYSTEM - According to one embodiment, a controller includes a quality measuring unit, a block classifying unit, and a multi-plane setting unit. The quality measuring unit measures quality of a block. The block classifying unit classifies the block for every plane based on a measurement result of the quality. The multi-plane setting unit selects one block belonging to the same classification from each plane and combines the blocks to generate the multi-plane. | 01-21-2016 |
20160071618 | DETERMINING SOFT DATA FROM A HARD READ - Apparatuses and methods involving the determination of soft data from hard reads are provided. One example method can include determining, using a hard read, a state of a memory cell. Soft data is determined based, at least partially, on the determined state. | 03-10-2016 |
20160104545 | DATA STRUCTURE OF DEFECTIVE ADDRESS INFORMATION AND DEFECTIVE ADDRESS INFORMATION ENCODING METHOD FOR MEMORY ARRAY - A defective address information encoding method for a memory array is provided. A page of the memory array is divided into plural segments. Each segment contains 2 | 04-14-2016 |
20160118137 | REDUCTION OF POWER CONSUMPTION IN FLASH MEMORY - Technologies are generally described for systems, devices and methods effective to reduce power consumption in flash memory. In some examples, a bit error rate estimator module may estimate two or more bit error rates. The two or more bit error rates may be associated with application of respective voltages to read from a memory. A voltage setup module may be configured to be in communication with the bit error rate estimator module. The voltage setup module may be configured to select a voltage to read from the memory. The voltage may be selected based on the two or more bit error rates and based on an error correction level. The error correction level may be a tolerance level available to correct read errors from the memory. | 04-28-2016 |
20160163397 | INTRINSIC MEMORY BLOCK HEALTH MONITORING - A memory system or flash card may monitor the health of memory and the user data stored by detecting and storing a number of bits in error for each block. This detection can be used to determine where user data should be programmed and which blocks should be cycled. The erratic bits are detected after a programming and the listing for each block is updated. When the erratic bits exceed a threshold for a particular block, that block may be cycled or retired. | 06-09-2016 |
20160172061 | STORAGE MEDIUM MANAGEMENT DEVICE, STORAGE MEDIUM MANAGEMENT METHOD, STORAGE MEDIUM, AND STORAGE MEDIUM MANAGEMENT SYSTEM | 06-16-2016 |
20160180952 | END OF LIFE PREDICTION BASED ON MEMORY WEAR | 06-23-2016 |
20160180959 | MEMORY BLOCK CYCLING BASED ON MEMORY WEAR OR DATA RETENTION | 06-23-2016 |
20160189789 | Method of Operating a NAND Flash Memory Device - Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR (“HPSF-NOR”) memory read commands so that the serial NAND flash memory may be used with controllers designed for HPSF-NOR memory. Serial NAND flash memory having these compatibilities is referred to herein as high-performance serial flash NAND (“SPSF-NAND”) memory. Since devices and systems which use HPSF-NOR memories and controllers often have extreme space limitations, HPSF-NAND may also be provided with the same physical attributes of low pin count and small package size of HPSF-NOR memory for further compatibility. HPSF-NAND memory is particularly suitable for code shadow applications, even while enjoying the low “cost per bit” and low per bit power consumption of a NAND memory array at higher densities. | 06-30-2016 |
20220139484 | NONVOLATILE MEMORY DEVICE, CONTROLLER FOR CONTROLLING THE SAME, STORAGE DEVICE INCLUDING THE SAME, AND READING METHOD OF THE SAME - A nonvolatile memory device includes a plurality of memory blocks and a control logic circuit configured to perform a first page on-chip valley search (OVS) operation on memory cells connected to one wordline of a memory block selected in response to an address, among the plurality of memory blocks, in response to a first read command. The control logic circuit is further configured to change a read level of at least one state using detection information of the first page OVS operation, and to perform a second page read operation on the memory cells using the changed read level in response to a second read command. | 05-05-2022 |
20220139486 | STORAGE DEVICE INCLUDING NONVOLATILE MEMORY DEVICE, OPERATING METHOD OF STORAGE DEVICE, AND OPERATING METHOD OF ELECTRONIC DEVICE INCLUDING NONVOLATILE MEMORY DEVICE - Disclosed is a storage device which includes a nonvolatile memory device and a memory controller, and an operating method of the storage device includes sending, at the memory controller, a first read command and first offset information to the nonvolatile memory device, performing, at the nonvolatile memory device, first read operations based on the first read command and the first offset information, sending, at the nonvolatile memory device, a result of the first read operations as first data to the memory controller, sending, at the memory controller, a second read command, read voltage levels, and second offset information to the nonvolatile memory device, performing, at the nonvolatile memory device, second read operations based on the second read command, the read level information, and the second offset information, and sending, at the nonvolatile memory device, results of the second read operations as second data to the memory controller. | 05-05-2022 |