Class / Patent application number | Description | Number of patent applications / Date published |
341166000 | Intermediate conversion to time interval | 64 |
20080238754 | TIME CONTINUOUS PIPELINE ANALOG-TO-DIGITAL CONVERTER - A Sampled Pipeline Subranging Converter (SPSC) may include at least one stage—e.g. at least the input stage—operating in a time-continuous fashion. In the time continuous input stage, the analog input may be processed in two parallel paths. A lower path may comprise a track-and-hold (T/H) element, an Analog-to-Digital-Converter (ADC) and a Digital-to-Analog-Converter (DAC). The T/H element may be optional and may be present if required by the ADC. The signal entering the lower path may be sampled at the desired conversion rate. The time continuous stage(s) may additionally be configured with an upper path that includes a delay element configured to receive the analog input, a Low-Pass (LP) filter coupled to the delay element, and an anti alias filter. The output generated by the DAC may be subtracted from the output of the LP filter, and the resulting difference signal may be provided to the anti alias filter, which in turn may generate the residue (or error) output. The digital output of the time continuous converter may be calculated by combining the digital outputs of the various sections. | 10-02-2008 |
20080272952 | ROTARY CLOCK FLASH ANALOG TO DIGITAL CONVERTER SYSTEM AND METHOD - System and method for converting an analog voltage to a digital signal. The system includes an input voltage sampler, a ramp generator, a comparator, a time-to-digital converter (TDC), and a multiphase oscillator, preferably a rotary traveling wave oscillator, that provides the critical system timing. The phases of the multiphase oscillator define a sampling interval during which the input voltage is sampled and held and a conversion interval during which the ramp generator, comparator, and TDC operate to convert the sampled voltage to the digital signal. The TDC samples at times provided by the phases of the multiphase oscillator to form the bits of the digital signal. The sampler, ramp generator, and comparator can be constructed from multiple fragments, one of which is selectable for calibration while the rest of the fragments are joined for normal operation. Multiple converters can be interleaved to increase the sampling rate. | 11-06-2008 |
20090219187 | HIGH-SPEED TIME-TO-DIGITAL CONVERTER - Techniques for enabling a time-to-digital (TDC) to sample with sub-inverter delay resolution are disclosed. In an embodiment, the inputs to a differential D-Q flip-flop in the TDC are coupled to a single-ended signal and a delayed and inverted version of that signal to allow time interpolation of the signal. Further disclosed are techniques to balance the loads of a first delay line and a complementary delay line within the TDC. | 09-03-2009 |
20090243908 | METHOD AND SYSTEM FOR DECIMATING A PULSE WIDTH MODULATED (PWM) SIGNAL - A method and system of decimating a Pulse Width Modulated (PWM) signal ( | 10-01-2009 |
20090251349 | MULTIPLE OUTPUT TIME-TO-DIGITAL CONVERTER - A multiple output time-to-digital converter (TDC) and an Analog-to-Digital Converter (ADC) incorporating the multiple output TDC is dislosed. | 10-08-2009 |
20100013693 | A-D CONVERT APPARATUS - Provided is an AD conversion apparatus including a bit selecting section that sequentially selects conversion target bits of the output data, from an upper bit downward; a data control section that outputs comparison data determining a value of the conversion target bit, each time a conversion target bit is selected; a DA converting section that outputs an analog comparison signal corresponding to the comparison data; a timing generating section that outputs a comparison control signal ordering comparison initiation; a changing section that changes a timing of the comparison control signal according to a bit position of the conversion target bit, such that the timing of the comparison initiation indicated by the comparison control signal is later for higher conversion target bits; a comparing section that begins comparing the input signal to the comparison signal at the comparison initiation timing indicated by the comparison control signal having the timing changed by the changing section; and a completion detecting section that outputs a completion signal causing the bit selecting section to select a next conversion target bit, after the comparing section has output the comparison result. | 01-21-2010 |
20100090876 | CONTINUOUS SYNCHRONIZATION FOR MULTIPLE ADCS - A system, apparatus and method for continuous synchronization of multiple ADC circuits is described. The ADC circuits can be arranged in a master-slave configuration within the system so that the converter clock is subdivided into slower speeds for the data output clock or for the control of de-multiplexing the outputs onto a wider bus, while maintaining ADC-to-ADC synchronization resilient to perturbations from noise and other upset sources. The configuration of the ADCs in the master-slave configuration can be varied according to overall system requirements in any one of a sequential configuration, a parallel configuration or a tree type of configuration, as well as others. Digital and/or analog timing adjustments can be made to each of the ADC circuits. The master clocking signals can be generated by a master clock generator circuit, which is either internally implemented in an ADC circuit, or externally implemented as a separate master clock generator circuit. | 04-15-2010 |
20100097261 | DIGITIZER WITH VARIABLE SAMPLING CLOCK AND METHOD USING THE SAME - A digitizer comprising an analog to digital converter (ADC), a sampling frequency generator, and a controller. The ADC samples an IF signal to generate a digital signal. The sampling frequency generator is coupled to the ADC and provides a sampling clock of variable frequency to the ADC. The controller is coupled to the sampling frequency generator and determines frequency of the sampling clock. | 04-22-2010 |
20100182186 | VOLTAGE-TO-TIME CONVERTER, AND VOLTAGE-TO-DIGITAL CONVERTING DEVICE HAVING THE SAME - A voltage-to-digital converting device includes a first voltage-to-time converter outputting a first delay clock having a first time delay relative to a reference clock in response to an input voltage, and a second voltage-to-time converter outputting a second delay clock having a second time delay relative to the reference clock in response to a feedback voltage. The first and second time delays correspond respectively to the input and feedback voltages. A time-to-digital converting circuit receives the first and second delay clocks from the first and second voltage-to-time converters, compares phases of the first and second delay clocks, generates the feedback voltage based on result of phase comparison made thereby, and outputs a digital signal upon detecting that the phases of the first and second delay clocks are in-phase. | 07-22-2010 |
20100259435 | DELAY CIRCUIT - A delay circuit includes a MOSFET and bias voltage sources. The bias voltage sources apply a voltage difference between the drain and source of the MOSFET. The bias voltage source supplies a source voltage to a source electrode of the MOSFET. The bias voltage source supplies a drain voltage to a drain electrode of the MOSFET. An input signal to be delayed is propagated through the gate of the MOSFET in the gate width direction (y-axis direction). | 10-14-2010 |
20100271251 | Serial Interface, Apparatus Including the Same, and Method of Using the Same - An apparatus for transferring serial data (e.g., a serial interface using a single wire) generally includes a detector configured to detect a first level time period and a second level time period of an input signal, and a computing unit configured to compute a duty or duty cycle of the input signal and generate an output signal based on the duty or duty cycle. | 10-28-2010 |
20100283653 | VERNIER RING TIME-TO-DIGITAL CONVERTERS WITH COMPARATOR MATRIX - A time to digital converter (TDC) is able to be utilized for measuring a time interval between two signals with a very fine time resolution, which is defined as the difference in propagation delay per stage between two rings or chains of delay stages. The Vernier ring TDC, Vernier TDC with comparator matrix or Vernier ring TDCs with comparator matrix comprise two rings or chains of delay stages with slightly different propagation delays per stage and a plurality of comparators for comparing two signals propagation along two rings or chains and determining when the lag signal passes the lead signal. The lead and lag signal are initiated by two events and are each fed into a separate one the first stages of one of the specified rings or chains. The comparators are able to be organized in a comparator matrix in order to occupy less space and permit reuse. As a result, the input time interval (the time between the two initiating events) is able to be measured through the product of the time resolution and the number of stages through which the two signals propagated. | 11-11-2010 |
20100283654 | DIGITAL PHASE LOCKED LOOP WITH DITHERING - An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels. | 11-11-2010 |
20100328130 | TIME-TO-DIGITAL BASED ANALOG-TO-DIGITAL CONVERTER ARCHITECTURE - Apparatus and methods are provided relating to time-to-digital based analog-to-digital converter. An apparatus includes a time-to-digital converter based analog-to-digital converter for generating a first signal and a second signal having a timing relationship between a rising edge of the first signal and a rising edge of the second signal based on a sampled input analog voltage level, and converting the timing relationship into a corresponding time-to-digital representation. The time-to-digital representation is obtained without any voltage comparison and current comparison. | 12-30-2010 |
20110074617 | CHARGE-SHARING DIGITAL TO ANALOG CONVERTER AND SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER - In one embodiment, an analog to digital converter includes a comparator having a first input, a second input and an output, the first input being coupled to an analog signal, a successive approximation register having a serial input coupled to the output of the comparator, and being configured to generate a plurality of control signals and an N-bit digital value corresponding to the analog signal, and a digital to analog converter having an input coupled to the plurality of control signals, the digital to analog converter further comprising a first, a second, and a third capacitor and a plurality of switches controlled by the plurality of control signals and being configured to couple the first capacitor to the second capacitor and the third capacitor to the second capacitor mutually exclusively to share charge on the first capacitor and charge on the third capacitor with charge on the second capacitor and to generate an analog signal on the second capacitor, the second capacitor being coupled to the second input of the comparator. | 03-31-2011 |
20110074618 | METHOD AND SYSTEM FOR CONVERTING TIME INTERVALS - A method and a system for converting time intervals are provided. In one embodiment, the system comprises a first time-to-digital converter having a first resolution configured to convert a first time interval, a second time-to-digital converter having a second resolution configured to convert a second time interval, and a third time-to-digital converter having a third resolution and coupled to the first time-to-digital converter and the second time-to-digital converter, the third time-to-digital converter configured to convert a third time interval and a fourth time interval. | 03-31-2011 |
20110090108 | A/D CONVERSION CIRCUIT - An A/D conversion circuit includes: a pulse transit circuit into which either a power supply or current source and also a pulse signal is input, and through which the pulse signal transits; a transit position detection section that detects a transit position of the pulse signal within the pulse transit circuit, and outputs data in accordance with the transit position; and a digital data creation section that, based on the data output by the transit position detection section, creates digital data that corresponds to the size of the power supply or current source. The pulse transit circuit is formed by a plurality of inverter circuits that are joined together in series, and the plurality of inverter circuits are formed by identical logical elements in which delay times between input signals and output signals change in accordance with the size of the power supply or current source. In the pulse transit circuit, a start-up signal that causes the transiting of the pulse signal to commence is input into one of the plurality of inverter circuits, and the transit position detection section detects the transit position of the pulse signal within the pulse transit circuit based on the output signals from each one of the plurality of inverter circuits. | 04-21-2011 |
20110095927 | Sampling/Quantization Converters - Provided are, among other things, systems, methods and techniques for converting a continuous-time, continuously variable signal into a sampled and quantized signal. According to one representative embodiment, an apparatus includes multiple continuous-time quantization-noise-shaping circuits, each in a separate processing branch and having an adder that includes multiple inputs and an output; an input signal is coupled to one of the inputs of the adder; the output of the adder is coupled to one of the inputs of the adder through a first filter; and the output of a sampling/quantization circuit in the same processing branch is coupled to one of the inputs of the adder through a second filter, with the second filter having a different transfer function than the first filter. | 04-28-2011 |
20110095928 | A/D CONVERSION CIRCUIT AND SOLID STATE IMAGING DEVICE - A clock generating circuit in which a plurality of stages of inverting circuits are connected, a start signal that causes start of clock generation and an output signal from the inverting circuit of a predetermined stage are input to one of the inverting circuits, an element having impedance that changes in accordance with a magnitude of an object analog signal that is an object of conversion to a digital signal is provided between the adjacent inverting circuits, generates a clock of a frequency in accordance with the magnitude of the object analog signal. A counter counts the number of clocks generated by the clock generating circuit and outputs a count value. | 04-28-2011 |
20110133973 | TIME MEASUREMENT CIRCUIT - A time measurement circuit measures the time difference between edges of a first signal and a second signal. A sampling circuit acquires the logical level of the first signal at a timing of the edge of the second signal. When a sampling circuit enters a metastable state, an output signal thereof transits with a long time scale. A transition time measurement circuit measures a transition time (settling time) of the output signal of the sampling circuit in the metastable state. | 06-09-2011 |
20110210882 | ANALOG/DIGITAL CONVERSION CIRCUIT - An analog-to-digital converter may include an annular delay circuit that includes a plurality of delay units connected in an annular shape, each of the plurality of delay units delaying a pulse current that is input to each of the plurality of delay units, a current source that outputs an electric current, in accordance with an input analog signal, to selected delay units, which is selected from among the plurality of delay units, and a digital signal generation unit that generates a digital signal in accordance with a number of circulations per predetermined period of time of the pulse current circulating around the annular delay circuit. | 09-01-2011 |
20110260902 | TIME-TO-DIGITAL CONVERTER AND OPERATION METHOD THEREOF - A Time-to-Digital Converter (TDC) is provided. The TDC includes a first TDC unit for receiving a first input signal and a second input signal, delaying the first input signal on a specific time basis using each of first delay blocks, generating first phase-divided signals by performing first phase division on signals of input/output nodes for each of the first delay blocks on a predefined Phase-Interpolation (PI) delay time basis, and outputting the second input signal and a phase-divided signal closest to the second input signal, among the first phase-divided signals, a time amplifier for independently time-amplifying the second input signal and the phase-divided signal closest to the second input signal, and a second TDC unit for delaying a phase-divided signal closest to the time-amplified second input signal on a specific time basis using each of second delay blocks, and generating second phase-divided signals by performing second phase division on signals of input/output nodes for each of the second delay blocks on a predefined PI delay time basis. | 10-27-2011 |
20110279299 | SUB-EXPONENT TIME-TO-DIGITAL CONVERTER USING PHASE-DIFFERENCE ENHANCEMENT DEVICE - A time-to-digital converter includes a phase-difference enhancement section configured to receive first and second input signals having a reference phase difference Δt, and to output first and second output signals having an enhanced phase difference; and a comparison section configured to receive the first and second output signals, to compare a phase difference between the first and second output signals with a reference delay time τ, and to output a comparison signal. The time-to-digital converter has a high resolution. That is to say, the time-to-digital converter has a resolution less than the minimum phase delay time of a delay element, which is obtainable in a corresponding semiconductor process. | 11-17-2011 |
20120026028 | TIME-TO-DIGITAL CONVERTER AND OPERATING METHOD - Provided are a TDC having a pipeline or cyclic structure and an operating method thereof. The TDC includes a first stage block and a second stage block. The first stage block detects a first bit of a digital code for a time difference between first and second input signals. The second stage block detects a second bit of the digital code for a time difference between first and second output signals of the first stage block. The first stage block amplifies a time difference between first and second delay signals for the first and second input signals to generate the first and second output signals, and transfers the first and second output signals to the second stage block. | 02-02-2012 |
20120056769 | METHOD AND SYSTEM FOR TIME TO DIGITAL CONVERSION WITH CALIBRATION AND CORRECTION LOOPS - Methods and apparatuses for time to digital conversion (TDC) are disclosed. A timing circuit comprises a TDC circuit, a calibration module, and a correction module. The TDC circuit is configured to provide a timing signal indicative of a timing difference between edges of a periodic reference clock signal and a variable feedback signal. The TDC circuit is also configured to provide a delay signal that is variably delayed relative to the reference clock signal. The calibration module is configured to provide a calibration signal to increase and decrease a total delay of the TDC circuit based on a time delay of the calibration signal plus a time delay of a correction signal. The correction module, which is configured to receive the timing signal and provide the correction signal, minimizes harmonic spurs in a frequency response of the timing signal by operating at a frequency of the reference clock signal. | 03-08-2012 |
20120133540 | VOLTAGE-TIME CONVERTERS AND TIME-DOMAIN VOLTAGE COMPARATORS INCLUDING THE SAME - Provided is a time-domain voltage comparator including a voltage-time converter. The voltage-time converter includes a conversion unit and an output unit. The conversion unit includes a first MOS transistor which shifts a voltage level of the first detection node according to an external first voltage signal, and a second MOS transistor which shifts a voltage level of the second detection node according to an external second voltage signal. The output unit generates first and second output signals in response to voltages of the first and second detection nodes. The output unit determines a shifted time of the first output signal according to a voltage level of the first detection node and determines a shifted time of the second output signal according to a voltage level of the second detection node. | 05-31-2012 |
20120268303 | APPARATUS FOR DETECTION OF A LEADING EDGE OF A PHOTO SENSOR OUTPUT SIGNAL - A system and method for processing an analog signal output by a sensor. The system and method converting, using at least one analog-to-digital converter (ADC), the analog output signal to a digital signal, the digital signal including a plurality of samples at a predetermined resolution, detecting whether a trigger condition is met by analyzing the digital signal, detecting an event based on trigger information from the detecting whether a trigger condition is met, generating event information having time information included therein when the event is detected, defining one or more time windows based on the time information included in the event information, performing decimation on the digital signal based on the defined one or more time windows to generate a decimated signal, and outputting the decimated signal. | 10-25-2012 |
20120286987 | AD CONVERTER AND TD CONVERTER CONFIGURED WITHOUT OPERATIONAL AMPLIFIER AND CAPACITOR - An AD converter includes a VT converter circuit part which inputs an analog input voltage and a sampling clock, converts the analog input voltage to a corresponding delay time, and outputs time domain data. A ring oscillator circuit part of N stages inputs the time domain data, and an error propagation circuit part takes out delay information containing a quantization error from phase information of the ring oscillator circuit part of the previous stage, and propagate the delay information to the ring oscillator circuit part of a subsequent stage. A counter circuit part measures a number of waves of an output oscillation waveform of the ring oscillator circuit part of each stage, and an output signal generator part generates an output signal from an output counted value of each counter circuit part. A reset part resets each error propagation circuit part and each counter circuit part with a sampling clock. | 11-15-2012 |
20120313803 | TIME-TO-DIGITAL CONVERSION STAGE AND TIME-TO-DIGITAL CONVERTER INCLUDING THE SAME - In a time-to-digital conversion stage, a time-to-digital conversion circuit outputs an n-bit digital signal, which represents an integer value ranging from −(2 | 12-13-2012 |
20130033392 | SUCCESSIVE APPROXIMATION REGISTER ADC CIRCUITS AND METHODS - A non-binary successive approximation analogue to digital converter, for converting using successive conversion steps, is operable in first and second modes. The first and second modes have different noise properties and the converter is switched between the modes during the conversion process. | 02-07-2013 |
20130069812 | Time-Interleaved Analog-to-Digital Converter for Signals in any Nyquist Zone - Processing a signal by receiving an analog input signal located outside of a first Nyquist zone that is between 0 and fs/2; passing the analog input signal through an M-channel time-interleaved analog-to-digital converter (TI-ADC) to generate a TI-ADC output signal; and estimating and correcting a timing skew error in the TI-ADC output signal. Alternatively, an electronic circuit that includes an input for an analog input signal, an M-channel time-interleaved analog-to-digital converter (TI-ADC) and a timing skew error estimating and correcting circuitry. The analog input signal is located outside of a first Nyquist zone that is between 0 and fs/2. The TI-ADC receives the analog input signal and generates a TI-ADC output signal. The timing skew error estimating and correcting circuitry estimates and corrects a timing skew error in the TI-ADC output signal. | 03-21-2013 |
20130154867 | A/D CONVERTER - An A/D converter having high accuracy and high throughput irrespective of characteristic variations of analog circuits is provided. The A/D converter includes a voltage-to-time converter configured to synchronize with a sampling clock signal and convert an input analog voltage to a time difference between two signals, and a plurality of time-to-digital converters each configured to convert the time difference between the two signals to a digital value. The plurality of time-to-digital converters operate in an interleaved manner. | 06-20-2013 |
20130162458 | AD CONVERTER AND SOLID-STATE IMAGING APPARATUS USING THE SAME - There is a need to provide an AD converter capable of reducing occurrence of a noise. An AD converter includes an operational amplifier and a clip circuit. The operational amplifier receives ramp voltage and voltage for an analog signal and allows output terminal voltage to transition from an H level to an L level when a change in the ramp voltage reaches the voltage for the analog signal. The clip circuit fixes an output terminal of the operational amplifier to clipping voltage after output voltage for the operational amplifier reaches threshold voltage for a latch circuit. Therefore, the AD converter can limit a range of output voltage, as a source of noise, for the operational amplifier and eliminate an unnecessary change in the output voltage after the threshold voltage for the latch circuit is reached. | 06-27-2013 |
20130176158 | DISTANCE MEASURING DEVICE AND RECEIVING DEVICES THEREOF - Provided are a distance measuring device using an impulse signal and a receiving device thereof. The distance measuring device includes: a transmitting device transmitting an impulse signal; and a receiving device receiving the impulse signal and measuring a time interval (hereinafter, referred to as a delay time) between a transmitting timing and a receiving timing of the impulse signal, wherein the receiving device measures the delay time through a Time to Digital Converter (TDC) technique. According to the present invention, the distance measuring device measures the distance accurately and speedly. | 07-11-2013 |
20130214959 | LOW-POWER HIGH-RESOLUTION TIME-TO-DIGITAL CONVERTER - Disclosed is a low-power and high-resolution time-to-digital converter including: a coarse delay cell configured to delay a reference clock by a coarse delay time and output the reference clock; a rising-edge retimer configured to output a rising-edge retimed clock synchronized with the rising-edge of a DCO clock in response to the reference clock; a falling-edge retimer configured to output a falling-edge retimed clock synchronized with the falling-edge of the DCO clock; a firs sampler configured to latches output of the coarse delay cell in response to the rising-edge retimed clock and the falling-edge retimed clock; and a pseudo-thermometer code edge detector configured to detect a rising-edge fractional phase error between the reference clock and the rising-edge retimed clock as a coarse phase error from a signal output by the first sampler, and detect a falling-edge fractional phase error between the reference clock and the falling-edge retimed clock. | 08-22-2013 |
20130222170 | METHOD AND APPARATUS FOR CONVERSION OF TIME INTERVAL TO DIGITAL WORD - The solution according to the invention consisting in conversion of a time interval to a digital word of a number of bits equal to n by the use of the array (A) of binary-scaled capacitors (C. | 08-29-2013 |
20130300593 | COMPARISON CIRCUITS - A comparison circuit is provided and includes first and second comparators and a first time-to-digital comparator. The first comparator with a first offset voltage receives an input signal and generates a first comparison signal and a first inverse comparison signal. The second comparator receives the input signal and generates a second comparison signal and a second inverse comparison signal. The first offset voltage is larger than the second offset voltage. The first time-to-digital comparator receives the first comparison signal and the second inverse comparison signal and generates first and second determination signals according to the first comparison signal and the second inverse comparison signal. The first and second determination signals indicate whether a voltage of the input signal is larger than a first middle voltage. The first middle voltage is equal to a half of the sum of the first offset voltage and the second offset voltage. | 11-14-2013 |
20130307713 | TD CONVERTER AND AD CONVERTER WITH NO OPERATIONAL AMPLIFIER AND NO SWITCHED CAPACITOR - A TD converter is provided for digitally converting a delay time value into a digital value. In the TD converter, an oscillator circuit part inputs time domain data. A first-state counter circuit part measures a number of waves of an output oscillation waveform from the oscillator circuit part when time domain data is in a first state, and a second-state counter circuit part measures a number of waves of the output oscillation waveform from the oscillator circuit part when the time domain data is in a second state. An output signal generator part generates an output signal based on output count values of the first-state counter circuit part and the second-state counter circuit part, and a frequency control circuit controls the oscillator circuit part to always oscillate and to control an oscillation frequency of the oscillator circuit part. | 11-21-2013 |
20130335251 | TIME-TO-DIGITAL CONVERSION CIRCUIT AND TIME-TO-DIGITAL CONVERTER INCLUDING THE SAME - A time-to-digital conversion circuit for converting a time difference between two input signals to a 1-bit digital value, and adjusting the time difference between the two input signals to generate two output signals includes: a phase comparator configured to compare phases of the two input signals with each other to generate the digital value; a phase selector configured to output one of the two input signals which has a leading phase as a first signal, and the other of the two input signals which has a lagging phase as a second signal; and a delay unit configured to output the first signal with a delay, wherein the time-to-digital conversion circuit outputs the signal output from the delay unit and the second signal as the two output signals. | 12-19-2013 |
20140015703 | METHOD AND SYSTEM FOR GAIN CONTROL FOR TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTOR (ADC) - A system for processing signals may be configured to apply digital conversion to analog signals, and to apply, prior to the analog-to-digital conversion, a gain to at least a portion of the analog signals. The gain may be controlled and/or adjusted based on processing of digital output generated based on the analog-to-digital conversion. The system may comprise a plurality of sampling slices, which may be configured to provide the analog-to-digital conversion in interleaved (e.g., time-interleaved) manner. Each of the sampling slices may comprise a dedicated gain element, for applying gain to signals handled by the corresponding slice. The gain applied by the gain elements of the sampling slices may be controlled, independently, collectively, and/or in based on grouping into subsets. The gain may be controlled based on application of a particular gain control algorithm, which may be selected from a plurality of predefined algorithms. | 01-16-2014 |
20140055296 | TIME-TO-DIGITAL CONVERTING CIRCUIT AND DIGITAL-TO-TIME CONVERTING CIRCUIT - A time-to-digital converting circuit includes a first flip-flop and a second flip-flop. The time-to-digital converting circuit a first delay controlling circuit that outputs a first data signal obtained by controlling a delay time of the reference data signal input thereto via the first signal input terminal based on the first output signal and a first clock signal obtained by controlling a delay time of the reference clock signal input thereto via the second signal input terminal based on the first output signal. | 02-27-2014 |
20140104090 | TIME DIFFERENCE ADJUSTMENT CIRCUIT AND TIME-TO-DIGITAL CONVERTER INCLUDING THE SAME - A time difference adjustment circuit includes two flip-flop circuits, a delay circuit, and a reset circuit. The delay circuit includes first and second transistors of a first polarity and third and fourth transistors of a second polarity, wherein drains of the first and third transistors are coupled to each other, drains of the second and fourth transistors are coupled to each other, the drains of the first and third transistors and a gate of the fourth transistor are coupled to each other, an input signal is coupled to a gate of the first transistor, an output signal is supplied from the drains of the second and fourth transistors, and first and second reset signals are respectively coupled to gates of the second and third transistors. | 04-17-2014 |
20140152484 | OVERSAMPLING TIME-TO-DIGITAL CONVERTER - An oversampling time-to-digital converter includes an input pulse generation circuit generating two pulse signals, a reference pulse generation circuit generating two pulse signals, a swap circuit swapping two pulse signals, a multiplexer selecting an output of the input pulse generation circuit or the swap circuit, a time-to-current conversion circuit outputting two pulse currents in accordance with an output of the multiplexer, a current mirror circuit whose input and output terminals receive the two pulse currents, an integration circuit integrating a differential current between the pulse current connected to the output terminal of the current mirror circuit and an output current of the current mirror circuit, and a comparison circuit comparing an output signal of the integration circuit to a threshold voltage. An output signal of the comparison circuit is given to the swap circuit as a control signal. | 06-05-2014 |
20140203957 | CONTINUOUS TIME INPUT STAGE - A continuous time input stage including a first digital-to-analog converter (DAC) including a first DAC code input, a second DAC including a second DAC code input, a first set of switches coupled to the output of the first DAC, a second set of switches coupled to the output of the second DAC, and an amplifier configured to receive the output of either the first DAC or the second DAC. | 07-24-2014 |
20140266848 | BIPOLAR TIME-TO-DIGITAL CONVERTER - Representative implementations of devices and techniques provide bipolar time-to-digital conversion. For example, either a positive time duration or a negative time duration may be converted to a digital representation by a linear time-to-digital converter (TDC). A set of logic functions may be applied to the input of the TDC to provide start and/or stop signals for the TDC. Further, a correction component may be applied to an input or an output of the TDC to compensate for a delay offset of the TDC. | 09-18-2014 |
20140320329 | TIME-TO-DIGITAL CONVERTER - An edge detector includes flip-flops receiving phase signals of a ring oscillator, a resetter canceling the reset states of the flip-flops at the edge timing of an input signal, and a logical operator performing a logical operation on output signals of the flip-flops. A phase state detector detects a phase state of the ring oscillator occurring at the edge timing of the input signal based on the output signals of the flip-flops. A time-to-digital converter converts an edge interval between the input signal and an output signal of the logical operator into a digital value. A latch latches a value of a counter counting the number of cycles of an output signal of the ring oscillator, at the edge timing of the input signal. An operator calculates a digital value of a received signal from output signals of the latch, the phase state detector, and the time-to-digital converter. | 10-30-2014 |
20140347205 | TIME-TO-DIGITAL CONVERTER AND AN A/D CONVERTER INCLUDING THE SAME - A time-to-digital converter includes first and second phase distribution circuits and N time-to-digital conversion circuits. The first and second phase distribution circuits each includes a plurality of frequency dividers connected in a tree structure. The first and second phase distribution circuits each divides a signal received by the frequency dividers of root nodes into N signals. The first and second phase distribution circuits each outputs the N signals each having a different phase. The N time-to-digital conversion circuits each converts a phase difference between an i-th signal (where i is an integer from 0 to N-1) that is output from the first phase distribution circuit and another i-th signal that is output from the second phase distribution circuit into a digital value. | 11-27-2014 |
20140368372 | TIME TO DIGITAL CONVERTER - A time to digital converter includes: a first measurement unit measuring a time difference between a start signal and a stop signal as a first time unit by using a first delay line; a second measurement unit measuring a time difference between the stop signal and the start signal delayed by the first delay line as a second time unit by using a second delay line and a third delay line and comparing an output signal of one delay cell included in the second delay line with an output signal of at least two delay cells included in the third delay line; and an output unit outputting a final time difference between the start signal and the stop signal as a digital code on the basis of measurement results of the first measurement unit and the second measurement unit. | 12-18-2014 |
20150301505 | TIME-TO-DIGITAL CONVERTER - A time-to-digital converter (TDC) in which a chain of inverters with finite propagation delays form a delay line in which a level transition applied to one end of the delay line from an input line produces a series of progressively delayed level transitions of alternating polarity along the delay line. Each inverter has an associated pass gate, with the output of the inverter together with the output of the preceding delay line element driving the complementary gate inputs of the pass gate. The complementary gate inputs of each pass gate are coupled to the corresponding delay line outputs in an alternating manner so that, as the level transitions traverse the delay line, the pass gates are progressively enabled to couple the input line to corresponding output lines to produce a series of progressively delayed level transitions of like polarity on those output lines. | 10-22-2015 |
20160109860 | Device And Method For Determining Timing Of A Measured Signal - The invention is a device for determining timing of a measured signal, the device comprising a plurality of flip-flop units ( | 04-21-2016 |
20160124393 | EVENT DRIVEN SIGNAL CONVERTERS - In some implementations, a method comprises: generating, by an event system of an integrated circuit, a first event signal in response to a clock signal; distributing the first event signal to a first digital converter, where the first event signal triggers conversion of a first analog signal to a first digital value by the first digital converter; generating, by the event system, a second event signal in response to the clock signal; and distributing the second event signal to a second digital converter, where the second event signal triggers conversion of a second analog signal to a second digital value. | 05-05-2016 |
20160132024 | ANNULAR TIME-TO-DIGITAL CONVERTER AND METHOD THEREOF - An annular time-to-digital converter includes a pulse shaper that shapes an input start pulse and an input stop pulse to form fixed-width pulses for output. The annular time-to-digital converter also includes at least two differential comparing units that enable, during matching enabling, triggers of the differential comparing units to set setting ends to 1. A circle counter counts the number of times a pulse is propagated in a loop. A matching enabling logical device generates a matching enabling signal, and sends the generated matching enabling signal to comparing enabling ports of the differential comparing units. At least two in-loop position encoders find a position of a first matched unit according to matching signals sent by the differential comparing units. Result recording registers record the number of circles and in-loop positions when matching occurs. High resolution is realized using a differential chain, and wafer area is saved by the annular design. | 05-12-2016 |
20160195853 | DISCRETE-TIME ANALOG CIRCUIT, TRANSMITTING DEVICE, AND RECEIVING DEVICE | 07-07-2016 |
20180026617 | CIRCUIT DEVICE, ELECTRONIC DEVICE, PHYSICAL QUANTITY SENSOR, AND VEHICLE | 01-25-2018 |
20180026647 | COMPARATOR, CIRCUIT DEVICE, PHYSICAL QUANTITY SENSOR, ELECTRONIC DEVICE, AND VEHICLE | 01-25-2018 |
341167000 | Dual slope | 1 |
20130201049 | ORGANISM STATE QUANTITY MEASURING APPARATUS - An apparatus including a detecting unit that detects information indicating a state of an organism from the organism or an organism specimen extracted from the organism and outputs the detected information as a current, a current-voltage conversion circuit that converts the current output from the detecting unit into a voltage, a double-integration-type A/D conversion circuit having an integration capacitor that is charged based on a voltage output from the current-voltage conversion circuit and is thereafter discharged, and a counter that measures a charge time during which the integration capacitor is charged and a discharge time during which the integration capacitor is discharged, the A/D conversion circuit converting into digital quantities the charge time and the discharge time measured by the counter, and outputting the digital quantities, and an information processing unit that calculates a state quantity of the organism based on the digital quantities output from the A/D conversion circuit. | 08-08-2013 |
341169000 | Input signal compared with linear ramp | 7 |
20090167586 | SOLID-STATE IMAGING DEVICE, DRIVING METHOD THEREOF, AND CAMERA - It is an object of the present invention to provide a solid-state imaging device for enhancing accuracy of AD conversion and active switching of up-counting and down-counting in the asynchronous counter without limiting the AD conversion frequency. The solid-state imaging device according to the present invention includes an asynchronous counter having an up-counting mode in which up-counting is performed, a down-counting mode in which down-counting is performed, and a holding mode for switching operation settings between the up-counting and the down-counting while maintaining a count value held in the asynchronous counter. | 07-02-2009 |
20090256735 | ANALOG-TO-DIGITAL CONVERSION IN PIXEL ARRAYS - An analog-to-digital converter (ADC) generates an output digital value equivalent to the difference between two analog signal values. The ADC | 10-15-2009 |
20100033362 | Solid-state image sensing device, imaging method, and imaging apparatus - A solid-state image sensing device includes: a pixel unit that has plural pixels and outputs analog pixel signals; a ramp signal generator unit that generates a ramp signal having a predetermined initial voltage and a fixed gradient; and an analog-digital converter unit that compares the analog pixel signals output by the pixel unit to the ramp signal generated by the ramp signal generator unit and digitally converts the analog pixel signals based on a comparison time, wherein the analog-digital converter unit can perform operation in a digital addition mode of adding the analog pixel signals output from the plural pixels of the pixel unit among plural pixels and outputting the signals as digital pixel signals, and the ramp signal generator unit can set the initial voltage of the ramp signal to an arbitrary value after resetting a potential of the ramp signal in the digital addition mode. | 02-11-2010 |
20110095929 | ANALOG-TO-DIGITAL CONVERSION IN PIXEL ARRAYS - An analog-to-digital converter (ADC) generates an output digital value equivalent to the difference between two analog signal values. The ADC | 04-28-2011 |
20110193735 | HANDHELD ELECTRONIC DEVICE AND ASSOCIATED METHOD EMPLOYING A MULTIPLE-AXIS INPUT DEVICE AND REINITIATING A TEXT DISAMBIGUATION SESSION UPON RETURNING TO A DELIMITED WORD - A handheld electronic device includes a reduced QWERTY keyboard and is enabled with disambiguation software. The device provides output in the form of a default output and a number of variants. The output is based largely upon the frequency, i.e., the likelihood that a user intended a particular output, but various features of the device provide additional variants that are not based solely on frequency and rather are provided by various logic structures resident on the device. The device enables editing during text entry and also provides a learning function that allows the disambiguation function to adapt to provide a customized experience for the user. The disambiguation function can be selectively disabled and an alternate keystroke interpretation system provided. During text entry, a user is able to delimit a language entry session, such the entering of a word, by actuating a multiple-axis input device or another input device. The user can also reinitiate the language entry session by actuating a linguistic input member at a location abutting the delimited word. | 08-11-2011 |
20110205100 | ANALOG-TO-DIGITAL CONVERSION IN PIXEL ARRAYS - An analog-to-digital converter (ADC) generates an output digital value equivalent to the difference between two analog signal values. The ADC | 08-25-2011 |
20130063295 | A/D CONVERSION CIRCUIT AND IMAGING DEVICE - In an A/D conversion circuit and an imaging device, an upper counter acquires a first upper count value by performing counting using one output signal, which constitutes a first lower phase signal output from a delay circuit, as a count clock. After values of bits constituting the first upper count value are inverted, the upper counter acquires a second upper count value by performing counting using one output signal, which constitutes a second lower phase signal output from the delay circuit, as a count clock, and further performing counting based on an upper count clock output from a lower counter. A modification unit modifies a logic state of a count clock to a predetermined state when the count clock of the upper counter is switched. | 03-14-2013 |
341170000 | Input signal compared with nonlinear ramp | 1 |
20090212987 | VARIABLE QUANTIZATION ADC FOR IMAGE SENSORS - An A/D converter suitable for use in a system in which the signal power of noise increases with the signal power of the signal, such as an imaging system, utilizes a variable quantization system for converting analog signals into digital signals. The variable quantization is controlled so that at low signal levels the quantization is similar or identical to conventional A/D converters, while the quantization level is increased at higher signal levels. Thus, higher resolution is provided at low signal levels while lower resolution is produced at high signal levels. | 08-27-2009 |