Class / Patent application number | Description | Number of patent applications / Date published |
331002000 | Plural oscillators controlled | 31 |
20080224782 | Frequency jittering control circuit and method for using the same - A frequency jittering control circuit wherein by means of the characteristics of a PLL whose input switches between different frequencies, the output frequency of the PLL swings between the different frequencies to achieve the desired frequency jittering. | 09-18-2008 |
20080265998 | DUAL PLL LOOP FOR PHASE NOISE FILTERING - System for filtering an input frequency to produce an output frequency having low phase noise. A first PLL includes, in the feedback path, a frequency translation circuit which translates a frequency from a VCO in the first PLL by an offset frequency provided by the second PLL to provide either a sum or difference frequency. The first PLL locks its VCO to a crystal oscillator input frequency translated by the offset frequency due to the frequency translation circuit. A second PLL compares the input frequency to be filtered to the output of the first PLL VCO. The second PLL causes the first PLL VCO to lock to the input frequency by varying the offset frequency it provides to the frequency translation circuit. The bandwidth of the second PLL is significantly smaller than the bandwidth of the first PLL. The filtered output frequency is available from the first PLL VCO. | 10-30-2008 |
20080290953 | System and Method for Generating LO Frequencies with Phase Locking in 2 Steps - System and method for generating multiple local oscillator signals comprising a first-stage phase-locked loop (PLL) having an input to receive a first reference signal input and having an output to transmit a second reference signal, wherein the second reference signal is an integer or fractional multiple of the first reference signal; and a plurality of second-stage PLLs, each second-stage PLL having an input coupled to the output of the first-stage PLL and receiving the second reference signal, and each second-stage PLL having an output for transmitting a local oscillator signal, wherein each of the local oscillator signals is an integer multiple of the second reference signal. | 11-27-2008 |
20090021310 | SYSTEM AND METHOD FOR PHASE-LOCKED LOOP (PLL) FOR HIGH-SPEED MEMORY INTERFACE (HSMI) - A phase-locked loop (PLL) to provide clock generation for high-speed memory interface is presented as the innovate PLL (IPLL). The IPLL architecture is able to tolerate external long loop delay without deteriorating jitter performance. The IPLL comprises in part a common mode feedback circuit with a current mode approach, so as to minimize the effects of mismatch in charge-pump circuit, for instance. The voltage-controlled oscillator (VCO) of the IPLL is designed using a mutually interpolating technique generating a 50% duty clock output, beneficial to high-speed double data rate applications. The IPLL further comprises loop filter voltages that are directly connected to each VCO cell of the IPLL. Conventional voltage-to-current (V-I) converter between loop filter and VCO is hence not required. A tight distribution of VCO gain curves is therefore obtained for the present invention across process corners and varied temperatures. | 01-22-2009 |
20090033427 | OSCILLATOR, PLL OSCILLATOR, RADIO APPARATUS - An oscillator includes a plurality of oscillating units connected in parallel with each other, and a control unit which controls the number of parallel connections of the plurality of oscillating units based on an instruction signal indicating accuracy to be tolerated with respect to oscillation outputs of the oscillating units. | 02-05-2009 |
20090121792 | METHOD OF ESTABLISHING AN OSCILLATOR CLOCK SIGNAL - A hybrid numeric-analog clock synchronizer, for establishing a clock or carrier locked to a timing reference. The clock may include a framing component. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip. It may comprise a numeric time-locked loop (TLL) with an analog phase-locked loop (PLL). Moreover a high-performance number-controlled oscillator (NCO), for creating an event clock from a master clock according to a period control signal. It processes edge times rather than period values, allowing direct control of the spectrum and peak amplitude of the justification jitter. Moreover a combined clock-and-frame asynchrony detector, for measuring the phase or time offset between composite signals. It responds e.g. to event clocks and frame syncs, enabling frame locking with loop bandwidths greater than the frame rate. | 05-14-2009 |
20090167441 | Injection locking clock generator and clock synchronization circuit using the same - An injection locking clock generator can vary the free running frequency of an injection locking oscillator to broaden an operating frequency range of an oscillation signal injected to itself, thereby performing an injection locking with respect to all frequencies of an operating frequency range. The clock generator includes a main oscillator configured to generate oscillation signals of a frequency corresponding to a control voltage, and an injection locking oscillator configured to generate division signals synchronized with the oscillation signals by dividing the oscillation signals, wherein a free running frequency of the injection locking oscillator is set according to the frequency of the oscillation signals. | 07-02-2009 |
20090201092 | COMMUNICATION SYSTEM AND OSCILLATION SIGNAL PROVISION METHOD - An embodiment of a communication system is provided, in which a high frequency oscillator generates a first high frequency signal upon receipt of no disable signal. The first high frequency signal is commonly shared by at least two modules. Each module coupled to the high frequency oscillator operates in either busy or idle mode, wherein the module operates at the first high frequency signal when in busy mode, and asserts a request signal when in idle mode. A disablement unit, coupled to the first and second modules, asserts the disable signal to the high frequency oscillator when all of the request signals are asserted, thereby forcing the high frequency oscillator to cease the generation of the first high frequency signal. | 08-13-2009 |
20090212874 | OSCILLATOR DEVICE - An oscillator device having an oscillation system including an oscillator and a resilient supporting member, a driving member configured to supply a driving force to the oscillation system based on a driving signal, a detecting member configured to detect at least an oscillation amplitude of the oscillator, a driving amplitude control unit configured to control at least a driving amplitude of the driving signal, and a driving frequency control unit configured to control a driving frequency of the driving signal to be supplied to the driving member, wherein, in a state in which the driving amplitude control unit controls the driving amplitude of a driving signal so that the oscillation amplitude to be detected becomes equal to a target value, and on the basis of information including driving frequencies in different driving states being driven with driving signals of these driving frequencies as well as the controlled driving amplitude, the driving frequency control unit acquires, as a resonance frequency of the oscillation system, a driving frequency with which the driving amplitude of the driving signal becomes minimal. | 08-27-2009 |
20090295488 | Self-calibrated wide range LC tank voltage-controlled oscillator (VCO) system with expanded frequency tuning range and method for providing same - The present invention is a self-calibrating, dual-band, wide range LC tank Voltage Controlled Oscillator (VCO) system. The system may include a first Voltage-Controlled Oscillator (VCO) and a second Voltage-Controlled Oscillator (VCO). The system may further include a calibration engine. The calibration engine may be configured for being connectable to at least one of the first VCO or the second VCO. The calibration engine may further be configured for automatically establishing/providing a VCO fix capacitor band code setting and a gear control setting for selectively activating or inactivating the first VCO and/or the second VCO. The calibration engine may be further configured for automatically comparing a VCO control voltage of the system to an allowable control voltage range for the system and may be further configured for automatically adjusting the VCO fix capacitor band code setting and/or the gear control setting when the VCO control voltage falls outside of the allowable control voltage range. | 12-03-2009 |
20090315627 | PHASE-LOCKED LOOP CIRCUITRY WITH MULTIPLE VOLTAGE-CONTROLLED OSCILLATORS - Configurable phase-locked loop circuitry is provided. The phase-locked loop circuitry may include a buffer having a buffer output and a multiplexer having inputs and an output. The phase-locked loop circuitry may include multiple voltage-controlled oscillators. The phase-locked loop circuitry may be configured to switch a desired one of the voltage-controlled oscillators into use. Each voltage-controlled oscillator may be controlled by control signals applied to a control input for that voltage-controlled oscillator. The control input of each voltage-controlled oscillator may be connected to the buffer output. The output of each voltage-controlled oscillator may be connected to a respective one of the multiplexer inputs. Power-down transistors may be used to disable unused voltage-controlled oscillators to conserve power. The power-down transistors and the multiplexer may be controlled by signals from programmable elements. One or more of the voltage-controlled oscillators may be implemented using a separate integrated circuit connected using through-silicon vias. | 12-24-2009 |
20090322431 | SELF-BIASED BIPOLAR RING-OSCILLATOR PHASE-LOCKED LOOPS WITH WIDE TUNING RANGE - Self-biased bipolar ring-oscillator phase-locked loops with a wide tuning range are disclosed. In a particular example, an apparatus to provide a phase-locked loop is described, comprising a voltage-controlled oscillator (VCO) to provide an output clock signal having a frequency, a quantizer, a phase-frequency detector to generate an adjustment signal, and a charge pump to modify the control voltage. The example VCO includes several ring-oscillator stages, where each ring-oscillator stage includes several gain stages to provide several output currents based on a comparison of a control voltage and several corresponding threshold voltages. The example quantizer includes several comparators to generate digital signals based on the output currents. The example charge pump modifies the control voltage based on the digital signals and the adjustment signal, and includes several switching elements to increase or decrease current to the charge pump based on the digital signals. | 12-31-2009 |
20100201451 | METHOD AND SYSTEM FOR FREQUENCY CALIBRATION OF A VOLTAGE CONTROLLED RING OSCILLATOR - Aspects of a method and system for frequency calibration of a voltage controlled ring oscillator are provided. In this regard, an oscillating voltage may be generated via a voltage controlled ring oscillator comprising a plurality of delay cells. Each of the plurality of delay cells may comprise a MOSFET differential pair coupled to a plurality of variable resistors. A frequency of oscillation and amplitude of the generated oscillating voltage may be controlled by controlling a resistance of the plurality of variable resistors. The frequency of oscillation and amplitude may be controlled via one or more digital control words generated by a baseband processor, a DSP, and/or a memory. The digital control words may comprise a control word for finely tuning the frequency of oscillation and amplitude and a control word for coarsely tuning the frequency of oscillation and amplitude. | 08-12-2010 |
20110032040 | WIDE SPECTRUM RADIO TRANSMIT ARCHITECTURE - A communications device ( | 02-10-2011 |
20110102090 | Phase Locked Loop and Method Thereof - A phase locked loop (PLL) includes a clock generating circuit, a first phase detecting circuit, a first loop filter, a first VCO, a first mixer and a control circuit. The clock generating circuit generates a first clock signal. The first phase detecting circuit detects a phase difference between an input data signal and a feedback signal and generates a detection output signal according to the phase difference. The first loop filter, coupled to the first phase detecting circuit, generates a first VCO control signal according to the detection output signal. The first mixer, coupled to the first VCO and the clock generating circuit, mixes the output data signal and the first clock signal to generate the feedback data signal. The control circuit, coupled to the clock generating circuit and the first loop filter, for adjusting the first clock signal according to the first VCO control signal to calculate a gain of the first VCO. | 05-05-2011 |
20110215872 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: digitally controlled oscillators; a phase-data output unit; an integration processing unit; a filter unit; a multiplier (a first multiplier) that outputs, as an oscillator tuning word, a value obtained by multiplying an output signal subjected to time division from the filter unit with a predetermined coefficient; and an output selector (a tuning-word separating unit) that allocates the oscillator tuning word to the digitally controlled oscillators in synchronization with a reference frequency. | 09-08-2011 |
20110254631 | REFERENCE ASSISTED CONTROL SYSTEM AND METHOD THEREOF - A reference assisted control system and method thereof are disclosed. The method comprises: receiving a first input signal and a second control signal; generating a first intermediate signal in accordance with a difference between the first input signal and the first output signal; filtering the second control signal to generate a second intermediate signal; performing a weighted sum of the first intermediate signal and the second intermediate signal to generate the control signal; and outputting the first output signal in accordance with the control signal. | 10-20-2011 |
20110267146 | OPEN LOOP COARSE TUNING FOR A PLL - In many types of wireless applications (like wireless modems), it is important that the phase locked loops (PLLs) be able to synthesize clock frequencies in a wide tuning range. Because of the complexity of many conventional PLLs (which were deigned to cover wide tuning ranges), there was often a significant delay to achieve phase and frequency lock. Here, an open loop calibration system is provided to coarse tune a PLL very rapidly. Generally, this calibration system employs binary searches to coarsely adjust a voltage controlled oscillator (VCO) from a VCO bank to within a predetermined range around a target frequency. | 11-03-2011 |
20120105159 | MEMRISTIVE PROGRAMMABLE FREQUENCY SOURCE AND METHOD - A frequency source and a method of frequency generation employ a memristive negative differential resistance (M-NDR) voltage controlled oscillator (VCO). The frequency source includes a first M-NDR VCO of a plurality of memristive VCOs to provide a first signal having a first signal frequency. The frequency source further includes a second M-NDR VCO of the plurality to provide a second signal having a second signal frequency. The first and second M-NDR VCOs are interconnected with the plurality of memristive VCOs. The first and second M-NDR VCOs have independent programmable states and are connected to a common output of the frequency source. The method includes providing an M-NDR VCOs, where each M-NDR VCO includes an M-NDR device connected in parallel with a capacitance, and applying a bias voltage to activate a selected M-NDR VCO of the plurality to produce a frequency output. | 05-03-2012 |
20120112841 | CLOCK OSCILLATOR CIRCUIT AND SEMICONDUCTOR DEVICE - An object is to provide a method for preventing the occurrence of variations in time resolution by providing a calibration process to a TDC at the time of start up and further preventing the increase in circuit scale by reducing the redundancy of delay elements. A calibration of a multiphase oscillator TDC and a vernier TDC is carried out at the time of power-on. In the calibration, a timing input to be input to the vernier TDC is selected from output signals of DCCO based on a reference clock. Also, data is defined as an output signal which is adjacent to the output signal of DCCO mentioned above and proceeds in phase, and the delay therebetween is derived. By repeating it to all of the output signals, the one cycle of the output signal of DCCO is derived. | 05-10-2012 |
20120194277 | OSCILLATION DEVICE - To perform, in an oscillation device compensating an output frequency based on a detection result of ambient temperature, temperature compensation of the output frequency with high accuracy. First and second quartz-crystal oscillators are structured by using a common quartz-crystal piece, and when oscillation outputs of first and second oscillation circuits respectively connected to these quartz-crystal oscillators are set to f | 08-02-2012 |
20120218048 | OSCILLATION DEVICE - Provided is an oscillation device capable of obtaining a stable oscillation frequency by compensating for a change in oscillation frequency caused with an elapse of operating time of a quartz-crystal oscillator. A difference value ΔF between a frequency difference between first and second quartz-crystal oscillators after a predetermined period of time has elapsed from a reference time and a frequency difference between the first and second quartz-crystal oscillators at the reference time is determined. | 08-30-2012 |
20120262238 | PVT CONSISTENT PLL INCORPORATING MULTIPLE LCVCOS - In described embodiments, a wide toning-range (WTR) inductive-capacitive (LC) phase locked loop (PLL) provides for a large range of differing oscillation frequencies with a set of individual LC voltage controlled oscillator (VCO) paths. The output of each individual wide range LCVCO path is provided to a multiplexor (MUX), whose output is selected based on a control signal from, for example, a device controller. Each of the set of individual wide range LCVCO paths includes a switch that couples the LCVCO to a loop filter of a voltage tuning module, wherein each switch also receives the control signal to disable or enable the LCVCO path when providing the output signal from the MUX. Each switch is configured so as to minimize leakage current drawn by the LCVCO when disabled, and to reduce or eliminate effects of input capacitance of each dormant LCVCO to the loop dynamics of the PLL. | 10-18-2012 |
20120306580 | Correction of Low Accuracy Clock - An electronic device has two oscillators, for example a first highly accurate crystal oscillator and a second less accurate low power oscillator. In a normal mode of operation, time is counted based on an output from the crystal oscillator, but in a low power mode of operation, time is counted based on an output from the less accurate oscillator. During the low power mode of operation, a calibration process is performed repeatedly. During a first calibration time period the second oscillator is calibrated against the first oscillator to obtain a first calibration result, and a recalibration is performed during a second calibration time period to obtain a second calibration result. A correction factor is determined from the first and second calibration results, and the correction factor is applied when subsequently counting time based on the output from the second oscillator. | 12-06-2012 |
20130335148 | OSCILLATION FREQUENCY ADJUSTING CIRCUIT - According to one embodiment, a first oscillator has an oscillation frequency that is changed depending on a temperature. A second oscillator has different temperature characteristics from the first oscillator. An on-chip heater heats the first oscillator and the second oscillator. A counter counts a first oscillation signal of the first oscillator. An ADPLL generates a third oscillation signal on the basis of a second oscillation signal of the second oscillator and corrects the frequency of the third oscillation signal on the basis of a count value of the counter. | 12-19-2013 |
20140015615 | Digital Calibration for Multiphase Oscillators - A phase-locked loop circuit comprises a multi-phase oscillator having a plurality of coupled oscillators. A calibration module detects mismatches between frequency characteristics of the different oscillators in the phase-locked loop circuit during a calibration process. The calibration module then calibrates the various oscillators to compensate for the detected mismatch. Once calibrated, the phase-locked loop circuit can operate with little or no performance degradation despite the mismatch in frequency characteristics between the different oscillators. | 01-16-2014 |
20140184342 | SYSTEMS AND METHODS FOR FREQUENCY SYNTHESIS TO IMPROVE COEXISTENCE - A frequency synthesizer for a WLAN transceiver is disclosed that may be used to generate 5.4 GHz and 2.4 GHz signals. The frequency synthesizer may be configured to minimize VCO pulling by using VCO operating frequencies that are not integer multiples of the RF bands. Further, the frequency synthesizer may be configured to minimize interference with other frequency bands used by existing wireless systems. | 07-03-2014 |
20140285270 | Electronic Oscillation Circuit - An electronic oscillator circuit has a first oscillator, for supplying a first oscillation signal, a second oscillator, for supplying a second oscillation signal, a first controller for delivering the first control signal as a function of a phase difference between a first controller input and a second controller input of the first controller; a second controller for delivering the second control signal as a function of a phase difference between a first controller input of the second controller and a second controller input of the second controller; a resonator; at least a second resonance frequency, with a first phase shift dependent on the difference between the frequency of a second exciting signal and the second resonance frequency and processing means, for receiving the first oscillator signal and the second oscillator signal, determining their mutual proportion, looking up a frequency compensation factor in a prestored table and outputting a compensated oscillation signal. | 09-25-2014 |
20140312980 | CIRCUIT FOR MEASURING THE RESONANT FREQUENCY OF NANORESONATORS - In the field of nanoresonator oscillators or NEMS (nanoelectromechanical systems) oscillators, a circuit is proposed for measuring the oscillation frequency of a resonator, including a phase-locked loop with a frequency-controlled oscillator and a phase comparator. The resonator includes a vibration excitation input and a dynamic polarization input (using strain gauges). The frequency-controlled oscillator applies a polarization frequency f1 to the polarization input. A frequency generator supplies a fixed intermediate frequency FI; a mixer receives the frequencies f1 and FI for producing an excitation frequency f0 that is the sum or difference of f1 and FI. The phase comparator receives the frequency FI and the output signal of the resonator and produces a control signal that is sent to the frequency-controlled oscillator, indirectly locking the oscillation frequency onto the resonant frequency of the resonator. | 10-23-2014 |
20160072440 | Digital Calibration for Multiphase Oscillators - A phase-locked loop circuit comprises a multi-phase oscillator having a plurality of coupled oscillators. A calibration module detects mismatches between frequency characteristics of the different oscillators in the phase-locked loop circuit during a calibration process. The calibration module then calibrates the various oscillators to compensate for the detected mismatch. Once calibrated, the phase-locked loop circuit can operate with little or no performance degradation despite the mismatch in frequency characteristics between the different oscillators. | 03-10-2016 |
20160072512 | INCREASED SYNTHESIZER PERFORMANCE IN CARRIER AGGREGATION/MULTIPLE-INPUT, MULTIPLE-OUTPUT SYSTEMS - Certain aspects of the present disclosure provide methods and apparatus for using multiple voltage-controlled oscillators (VCOs) to increase frequency synthesizer performance, such as in stringent multiple-input, multiple-output (MIMO) modes. One example apparatus capable of generating oscillating signals generally includes a first VCO, a second VCO, and connection circuitry configured to connect the second VCO in parallel with the first VCO if a phase-locked loop (PLL) associated with the second VCO is idle. | 03-10-2016 |