Entries |
Document | Title | Date |
20080197911 | CIRCUIT WITH FUSE/ANTI-FUSE TRANSISTOR WITH SELECTIVELY DAMAGED GATE INSULATING LAYER - A semiconductor integrated circuit is disclosed which includes a main transistor and at least one of a fuse transistor or an anti-fuse transistor (“fuse/anti-fuse transistor”). Each transistor type includes an active region formed in a semiconductor substrate, a gate stack comprising a gate insulation layer and a gate electrode sequentially formed on the active region, and source/drain regions separated across the gate stack, but the gate insulation layer of the fuse/anti-fuse transistor is selectively damaged during fabrication. | 08-21-2008 |
20080204119 | DEVICE PROVIDING TRIM VALUES - Devices comprising trimmable electric units and methods for providing trim values to electric units are presented herein. One such device comprises a trimmable electric unit, at least one fuse to provide at least one first trim value, and a trim value provision unit to provide at least one second trim value, and a register. The register, which is connected to the electric unit, the at least one fuse, and the trim value provision unit, selectively stores the first and/or the second trim values and provides them to the electric unit. Optionally, a third trim value may be used. In the case of integrated circuits, provision of the trim values allows for on-chip debugging without waiting for creation of a test program used by automatic testing equipment at the wafer probe stage. | 08-28-2008 |
20080218247 | METHOD FOR AUTOMATICALLY ADJUSTING ELECTRICAL FUSE PROGRAMMING VOLTAGE - The present invention provides a circuit for determining the optimal gate voltage for programming transistors. The determination of the optimal voltage compensates for the variations in the programming current due to process variations in manufacturing or due to ambient conditions. By applying the optimal gate voltage thus determined to the programming transistors of electrical fuses, the optimal level of current is passed through the electrical fuses to enable high yielding and reliable electrical fuse programming. | 09-11-2008 |
20080218248 | Circuit for Adjusting Reference Voltage Using Fuse Trimming - A binary bidirectional trimming circuit is disclosed. The trimming circuit includes: a first resistor set having 4 resistors in parallel connected and a first fuse bridged two ends thereto provide one trimming step; a second resistor set having 2 resistors in series connected and a second fuse bridged two ends thereto provide eight trimming steps; a third resistor set having 2 resistors in parallel connected and a third fuse bridged two ends thereto provide two trimming steps; a fourth resistor set having 1 resistor and a fourth fuse bridged two ends thereto provide four trimming steps; a first loading resistor; and a second loading resistor. The first resistor set, second resistor set, first loading resistor, third resistor set, the fourth resistor set, and the second loading resistor are in series connected. The output terminal is located at the nodes of the third resistor set and the first loading resistor so that the trimming steps provided by the third resistor set and the fourth resistor set are opposite to that of the first resistor set and the second resistor set. | 09-11-2008 |
20080218249 | Semiconductor device and trimming method therefor - Provided is a semiconductor device including a divisional resistor having a fuse, and a divisional resistor for measuring relative accuracy which is obtained by eliminating the fuse from the divisional resistor having the fuse. Characteristic values of the divisional resistor for measuring relative accuracy are measured so as to obtain trimming data, and then the divisional resistor having the fuse is trimmed, to thereby obtain a semiconductor device with highly precise characteristics. | 09-11-2008 |
20080252361 | ELECTRICAL FUSES WITH REDUNDANCY - The present disclosure provides an electrical fuse cell with redundancy features and the method for operating the same. The fuse cell includes a first set of electrical fuses having at least one electrical fuse contained therein, and a second set of electrical fuses having at least one electrical fuse for providing redundancy to at least one fuse of the first set, wherein if one of the first set of electrical fuses is defective, at least one of the second set of the electrical fuses can be programmed to provide a redundancy function of the defective fuse. | 10-16-2008 |
20080265982 | METHOD OF IMPROVING FUSE STATE DETECTION AND YIELD IN SEMICONDUCTOR APPLICATIONS - Disclosed are embodiments of an apparatus incorporating a detection circuit adapted for determining the state of selected fuses and a programming circuit for blowing selected fuses on demand. Also, disclosed are embodiments of an associated method. The detection circuit comprises a plurality of fuses in identical signal and reference legs in order to increase the signal margin for detecting blown fuses and/or current sources configured to pass offset currents through the signal and reference legs in order to set the trip point for detecting blown fuses between the un-blown and the minimum blown resistances. Thus, the invention provides the flexibility of single-sided fuse state detection devices with even greater sensitivity than both single-sided and differential fuse state detection device. | 10-30-2008 |
20080284494 | FUSE DEVICE, METHOD FOR WRITING DATA, METHOD FOR READING DATA, AND METHOD FOR WRITING AND READING DATA - A fuse device includes a plurality of serially connected fuse elements whose number is n (n is an integer of two or more), a power source connected to one end of a first fuse element that is a top of the n serially connected fuse elements, and a plurality of program control transistors. Each of the program control transistors is connected to each of nodes between the fuse elements, and to an end of the n-th fuse element, respectively. | 11-20-2008 |
20090002058 | Automatic Bias Circuit for Sense Amplifier - The present invention discloses a bias circuit for a sense amplifier having a device under sensing, the device under sensing having an un-programmed state and a programmed state, the bias circuit comprises at least one first branch having at least one first device formed substantially the same as the device under sensing and remaining in the un-programmed state, and at least one second device formed also substantially the same as the device under sensing and being in the programmed state, wherein the at least one first device and the at least one second device are serially connected. A typical application of the present invention is an electrical fuse memory. | 01-01-2009 |
20090027107 | SEMICONDUCTOR DEVICE AND OFFSET VOLTAGE ADJUSTING METHOD - A semiconductor device includes a fuse section having a plurality of fuse circuits configured to generate switch control signals; and an offset adjusting section configured to adjust an offset voltage of a differential amplifier based on the switch control signals supplied from output nodes of the plurality of fuse circuits. Each of the plurality of fuse circuits includes a fuse connected between a first power supply voltage and a cut node; a current source connected between a second power supply voltage and the output node; and a first transistor connected between the output node and the cut node and having a gate connected to the second power supply voltage. | 01-29-2009 |
20090039946 | FUSE CIRCUIT - A fuse circuit includes a first power supply line, a second power supply line, a first current source connected between the first power supply line and an output terminal, a second current source connected between the second power supply line and the output terminal, the second current source having higher current supply capacity or current draw-out capacity than the first current source, and a fuse connected in series with the second current source between the second power supply line and the output terminal | 02-12-2009 |
20090045867 | FUSE CELL AND METHOD FOR PROGRAMMING THE SAME - The fuse cell architecture | 02-19-2009 |
20090051411 | Trimmer circuit and method - A trimmer circuit is so configured that an electronic device will break down to produce a high current to trim a fuse. The electronic device is selectively configured to have a breakdown voltage lower than an applied voltage, for the trigger of its breakdown to be controllable. In an embodiment, the electronic device is switched between two states having two breakdown voltages respectively, and the applied voltage is higher than one of the breakdown voltages and lower than the other one. | 02-26-2009 |
20090051412 | INTEGRATED CIRCUT, AND APPARATUS AND METHOD FOR PRODUCTION THEREOF - An integrated circuit includes a trimming signal creating section, disposed downstream of a trimming circuit in which a number of fuses are arranged in alignment, creating a trimming signal corresponding to the trimming value on the basis of a signal output from said trimming circuit and arranges blown object fuses such that every two of the blown object fuses are interposed at least one un-blown fuses in the trimming circuit. An efficient arrangement of blowing points in addition to the above arrangement of blown object fuses can reduce the area occupied by the trimming circuit. | 02-26-2009 |
20090058503 | Method to Bridge a Distance Between eFuse Banks That Contain Encoded Data - An eFuse system that includes a mechanism that bridges banks of eFuses and allows the banks of eFuses to be placed any distance from each other. The bridging of the eFuse banks is transparent to compression and encode programming algorithm and hardware decode mechanisms. Thus, by using the mechanism for bridging gaps between eFuse banks, an eFuse subsystem with several banks distributed on an integrated circuit chip appears to be a single large eFuse bank to the encode/decode mechanisms of the integrated circuit. Additionally, with this mechanism, eFuse banks can be easily added or deleted. | 03-05-2009 |
20090072886 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, REDUNDANCY SYSTEM, AND REDUNDANCY METHOD THEREOF - A semiconductor integrated circuit device including a fuse latch circuit including a fuse and a latch circuit for latching fuse data held in the fuse, a fuse counter circuit for counting the number of transfers of the fuse data, and a control circuit including a transmitter circuit for transmitting the fuse data to the outside, and a detour data path circuit which when the fuse data is not transferred, does not transfer the fuse data to the outside, and forms a detour data path for detouring the fuse data in the circuit itself. | 03-19-2009 |
20090115492 | FUSE-FETCHING CIRCUIT AND METHOD FOR USING THE SAME - A fuse-fetching circuit comprises a plurality of fuses, a plurality of first switches and a shift register. Each of the first switches includes a first data end, a second data end and a control end. The first data end is connected to the fuse, and the control end is controlled by a fuse-fetching signal. The shift register includes a plurality of registers, each of which includes a first latch, a first transmission gate, a second latch and a second transmission gate. The first latch is connected to the second data end of the first switch. | 05-07-2009 |
20090115493 | Electric fuse determination circuit and determination method - An electrical fuse determination circuit that can speedily and reliably incorporate an electrical fuse data and improve a reliability of electrical fuse device, includes a first electrical fuse device of which one end connects with a higher voltage, a second electrical fuse device of which one end connects with a lower voltage, a set portion that puts one of the first electrical fuse device and the second electrical fuse device in a conductive state, and a determination portion that determines a voltage level of a predetermined contact point connecting the other end of the first electrical fuse device and the other end of the second electrical fuse device. | 05-07-2009 |
20090128225 | STRUCTURE OF AN APPARATUS FOR PROGRAMMING AN ELECTRONICALLY PROGRAMMABLE SEMICONDUCTOR FUSE - A design structure for an apparatus for programming an electronically programmable semiconductor fuse. The apparatus applies a programming current to a fuse link as a series of multiple pulses. Application of the programming current as a series of multiple short pulses provides a level of programming current sufficiently high to ensure reliable and effective electromigration while avoiding exceeding temperature limits of the fuse link. | 05-21-2009 |
20090128226 | Fuse option circuit - A fuse option circuit including a fuse, a control switch, a latch, and a logical operational controller is provided. The latch stores a selected level. The logical operational controller outputs a selected result signal and feedbacks a control signal to the control switch. The level of the control signal determines whether the control switch is on or off. Therefore, the required level is input to the latch and the working mode having an ultra low current is selected. Furthermore, when the fuse is in an untrimmed state, the level of the selected result signal could be selected by a reset pulse signal of the latch in order to test a product. Afterward, it is determined whether the fuse is trimmed or not. When the fuse is in a trimmed state, the level of the selected result signal is established by a rising edge of the reset pulse signal. | 05-21-2009 |
20090134935 | ANTI-FUSE REPAIR CONTROL CIRCUIT FOR PREVENTING STRESS ON CIRCUIT PARTS - The present invention relates to an anti-fuse repair control circuit which regulates transmission of a power voltage and a back-bias voltage that are converted to repair an anti-fuse to a circuit part. As such, the present invention prevents the influence of a high power voltage or a low back-bias voltage on a circuit part such as a cell, a peripheral circuit, or a core region during an anti-fuse repair. The anti-fuse repair control circuit includes an anti-fuse repair enabling part providing an anti-fuse repair enabling signal corresponding to a repair of an anti-fuse; a power voltage control part controlling transmission of a power voltage to a first circuit part according to an enablement state of the anti-fuse repair enabling signal; and a back-bias voltage control part controlling transmission of a back-bias voltage to a second circuit part according to the enablement state of the anti-fuse repair enabling signal. | 05-28-2009 |
20090153228 | STRUCTURE FOR IMPROVING FUSE STATE DETECTION AND YIELD IN SEMICONDUCTOR APPLICATIONS - Disclosed is a design structure of an apparatus incorporating a detection circuit adapted for determining the state of selected fuses and a programming circuit for blowing selected fuses on demand. Also, disclosed are embodiments of an associated method. The detection circuit comprises a plurality of fuses in identical signal and reference legs in order to increase the signal margin for detecting blown fuses and/or current sources configured to pass offset currents through the signal and reference legs in order to set the trip point for detecting blown fuses between the un-blown and the minimum blown resistances. Thus, the invention provides the flexibility of single-sided fuse state detection devices with even greater sensitivity than both single-sided and differential fuse state detection device. | 06-18-2009 |
20090167415 | Skew signal generator and semiconductor memory device - A skew signal generator is provided which comprises a fuse signal generating unit for generating a plurality of fuse signals, and an encoder for generating skew signals including skew information of a wafer by encoding the fuse signals. | 07-02-2009 |
20090184750 | Programmable electronics - An electronic device with polarity reversal protected connections and irreversibly interruptible programming connections, wherein the interruption is performed through safety elements provided in the programming paths, behind which safety elements diodes are disposed which block towards ground in normal operation, so that an overload current can be passed through the safety elements and through the diodes to ground through intentional polarity reversal of the respective connections, whereby the safety elements are destroyed and the programming conductors are irreversibly interrupted. | 07-23-2009 |
20090212850 | Method and Circuit for Implementing Efuse Resistance Screening - A method and circuit for implementing eFuse resistance screening, and a design structure on which the subject circuit resides are provided. An eFuse is sensed using a first reference resistor. Responsive to the eFuse being sensed as blown with the first reference resistor, the eFuse is sensed using a second reference resistor having a higher resistance than the first reference resistor. Responsive to the eFuse being sensed as unblown with the second reference resistor, the eFuse is recorded as poorly blown. Reliability concerns are identified quickly and accurately without being required to measure the resistance of the eFuse. | 08-27-2009 |
20090231020 | Electrical fuse, semiconductor device and method of disconnecting electrical fuse - An electrical fuse including a polysilicon layer; a silicide layer formed over the polysilicon layer; and a first metal contact and a second metal contact arranged over the silicide layer, while being spaced from each other, the electrical fuse being configured so that the silicide layer, after disconnection, is excluded from a region right under the second metal contact, and from a region between the second metal contact and the first metal contact is provided. | 09-17-2009 |
20090251200 | MASTER FUSE MODULE - A master fuse module includes a base housing configured to be disposed on a battery, a fuse assembly connected to the base housing, and a cover disposed on the base housing. The fuse assembly includes a first generally planar portion including a first terminal, a second generally planar portion disposed generally perpendicular to the first generally planar portion, a plurality of second terminals, and a plurality of fuses. Each fuse includes a first portion in electrical communication with the first terminal and a second portion in electrical communication with one of the plurality of second terminals. A fuse element is in electrical communication between the first and second portions and provides overcurrent protection by melting when subjected to a predetermined current. A plurality of connectors connects the fuse assembly to the base housing. | 10-08-2009 |
20090251201 | Multi-level anti-fuse and methods of operating and fabricating the same - Provided may be a multi-level anti-fuse and methods of fabricating and operating the same. The multi-level anti-fuse may include at least three anti-fuses having a plurality of anti-fuses connected in parallel constituting a parallel connection structure and at least one anti-fuse connected to the parallel connection structure in series, wherein the parallel connection structure may have a smaller resistance than the resistance of the anti-fuse connected in series, the plurality of anti-fuses connected in parallel may include dielectric layers having different thicknesses from one another, and the breakdown voltages of each dielectric layer may be different from one another. | 10-08-2009 |
20090256624 | Antifuse and methods of operating and manufacturing the same - Provided are an antifuse and methods of operating and manufacturing the same. The antifuse may include first and second conductors separate from each other; a dielectric layer for an antifuse between the first and second conductors; and a diffusion layer between one of the first and second conductors and the dielectric layer. | 10-15-2009 |
20090295462 | Voltage Divider, Constant Voltage Circuit Using Same, And Trimming Method In The Voltage Divider Circuit - A voltage divider circuit generating a divided voltage by dividing an input voltage with a predetermined voltage division ratio, and outputting the divided voltage is disclosed. The voltage divider circuit includes a first resistor circuit including multiple resistors connected in series, the resistors being connected in parallel to corresponding fuses; and a second resistor circuit including multiple resistors connected in series, the resistors being connected in parallel to corresponding fuses, the second resistor circuit being connected in series to the first resistor circuit. The divided voltage is output from the connection of the first resistor circuit and the second resistor circuit, and the fuses of the first resistor circuit and the second resistor circuit are subjected to trimming so that the combined resistance of the first resistor circuit and the second resistor circuit is constant. | 12-03-2009 |
20100007406 | Electrical fuse devices and methods of operating the same - Provided are an electrical fuse device and a method of operating the same. The electrical fuse device may include a fuse, and a driving element connected to the fuse and including a resistance change layer having a resistance that changes according to an applied voltage. The resistance change layer may have a metal-insulator transition (MIT) characteristic. As the driving element is turned on, a programming current may be applied to the fuse connected to the driving element. | 01-14-2010 |
20100085107 | Trim fuse circuit capable of disposing trim conducting pads on scribe lines of wafer - A trim fuse circuit includes a metal fuse, a trim pad coupled to the first end of the metal fuse, a first transistor coupled to the first end of the metal fuse, a second transistor coupled to the second end of the metal fuse, an inverter coupled to the second end of the metal fuse, a switch coupled to the second end of the metal fuse, and a common trim pad coupled to the control end of the switch. The inverter outputs a data signal according to the status of the metal fuse. The trim pad can be disposed on the scribe line of a wafer. When the trim pad is cut and accordingly connects to the substrate of the wafer, the data signal is not affected. | 04-08-2010 |
20100090750 | TRIMMING CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS AND TRIMMING METHOD THEREOF - A trimming circuit for a semiconductor memory apparatus includes a trimming code generator configured to provide a trimming code signal group by performing one of addition and subtraction using a test mode signal and a fuse coding signal, and an internal voltage generator configured to provide trimmed voltage in response to the trimming code signal group as output voltage. | 04-15-2010 |
20100090751 | Electrical Fuse Structure and Method - An electrical fuse and a process of programming the same are presented. An electrical fuse comprises a lower level silicide layer on a non-doped or lightly-doped polysilicon layer, an upper level conductive layer, and a tungsten contact coupled between the lower level silicide layer and the upper level conductive layer. The tungsten contact and a neck portion of the silicide layer are the programmable portion of the electrical fuse. High post-programming resistance is achieved by a first programming phase that depletes silicide in the silicide layer, followed by a second programming phase that depletes tungsten in the tungsten contact. | 04-15-2010 |
20100127757 | EFUSE DEVICE - An exemplary embodiment of an efuse device is provided, operating in a write mode and a read mode and comprising a source line, a cell, a blow device, and a sensing circuit. The cell has a first terminal coupled to the source line and a second terminal. The blow device is coupled between the second terminal of the cell and a ground terminal. The blow device is turned on in the read mode. The sensing circuit is coupled to the first terminal of the cell and the ground terminal, and is arranged to determine a state of the cell. | 05-27-2010 |
20100134175 | Antifuse Circuit Having Protection Circuit - An antifuse circuit includes a protection circuit. The antifuse circuit receives a program voltage using a non-connection (NC) pin or ball of a semiconductor device. The protection circuit prevents an unintended voltage lower than the program voltage from being applied to the antifuse circuit. | 06-03-2010 |
20100164603 | Programmable fuse and anti-fuse elements and methods of changing conduction states of same - A programmable anti-fuse element includes a substrate ( | 07-01-2010 |
20100164604 | FUSE CIRCUIT AND LAYOUT DESIGNING METHOD THEREOF - A fuse circuit for sensing a fuse connected state and layout designing method thereof are disclosed. Embodiments include a fuse program control unit providing a fuse open voltage in response to a program signal, a fuse cell unit configured to use a contact resistor connecting a node supplied with the fuse open voltage and a node supplied with a fuse connection voltage as a fuse, the fuse cell unit outputting a state information of the contact resistor in response to the fuse open voltage, and a fuse sensing unit outputting a fuse data signal corresponding to the state information of the contact resistor in response to a read signal. Accordingly, embodiments reduce a layout size of the fuse circuit. | 07-01-2010 |
20100214008 | SEMICONDUCTOR DEVICE WITH TRANSISTOR-BASED FUSES AND RELATED PROGRAMMING METHOD - A method of programming a transistor-based fuse structure is provided. The fuse structure is realized in a semiconductor device having a semiconductor substrate, transistor devices formed on the semiconductor substrate, and the transistor-based fuse structure formed on the semiconductor substrate. The transistor-based fuse structure includes a plurality of transistor-based fuses, and the method begins by selecting, from the plurality of transistor-based fuses, a first target fuse to be programmed for operation in a low-resistance/high-current state, the first target fuse having a first source, a first gate, a first drain, and a first gate insulator layer between the first gate and the semiconductor substrate. The method applies a first set of program voltages to the first source, the first gate, and the first drain to cause breakdown of the first gate insulator layer such that current can flow from the first source to the first gate through the first gate insulator layer, and from the first gate to the first drain through the first gate insulator layer. | 08-26-2010 |
20100225381 | FUSE FOR USE IN HIGH-INTEGRATED SEMICONDUCTOR DEVICE - The invention relates to a semiconductor device comprising a fuse that is implemented as a bar type pattern that forms a straight line instead of a pattern that is difficult to secure a manufacturing margin. A fuse block including a plurality of fuses comprises a plurality of first connection parts, each including a blowing area, a plurality of second connection parts, wherein the plurality of the second connection parts and the plurality of the corresponding first connection parts respectively form part of the fuse, and a common connection unit configured to electrically connect the plurality of the first connection parts and the plurality of the second connection parts. | 09-09-2010 |
20100244933 | ELECTRIC FUSE CUTOFF CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE - An electric fuse cutoff control circuit controlling cutoff of a plurality of electric fuses including: a cutoff information storage circuit adapted to store cutoff information about whether or not each of the plurality of electric fuses is cut off; a cutoff information control circuit controlling the cutoff of the plurality of electric fuses based on an output signal of the cutoff information storage circuit; and a cutoff information renewal circuit receiving an output signal of the cutoff information control circuit and renewing the cutoff information set for the cutoff information storage circuit. | 09-30-2010 |
20100283531 | FUSE CIRCUITS - A fuse circuit includes a fuse having an intact state and a blown state. The fuse can be switched to the blown state by enabling a blowing current to flow through the fuse. The fuse is coupled between a first transistor and a second transistor in series. The first transistor and the second transistor are complementary transistors and operable for reducing an electrostatic discharge current flowing through the fuse. The first transistor and the second transistor are turned on to enable the blowing current to flow through the fuse. | 11-11-2010 |
20100295605 | FUSE CIRCUIT OF SEMICONDUCTOR DEVICE AND METHOD FOR MONITORING FUSE STATE THEREOF - A fuse circuit of a semiconductor device includes a plurality of fuse set units configured to compare an input address with address information programmed according to a fuse cutting state and a test control unit configured to enable one or more fuse set units selected based on a number of times that a selection signal is enabled in a test mode. | 11-25-2010 |
20100308896 | Fuse circuit and semiconductor device including the same - A fuse circuit may include a fuse section which generates a fuse control signal at an output terminal of the fuse circuit in response to a power-up signal according to a status of a fuse in the fuse section; and a current path break section which detects the status of the fuse in the fuse section prior to a trip period of the power-up signal and breaks an inrush current path created in the fuse section during the trip period based on the detected status. | 12-09-2010 |
20100321095 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, SEMICONDUCTOR CHIP AND SYSTEM - A semiconductor device ( | 12-23-2010 |
20110001551 | CIRCUIT STRUCTURE AND METHOD FOR PROGRAMMING AND RE-PROGRAMMING A LOW POWER, MULTIPLE STATES, ELECTRONIC FUSE (E-FUSE) - Disclosed are embodiments of an e-fuse programming/re-programming circuit. In one embodiment, the e-fuse has two short high atomic diffusion resistance conductor layers positioned on opposite sides and at a same end of a long low atomic diffusion resistance conductor layer. A voltage source is used to vary the polarity and, optionally, the magnitude of voltage applied to the terminals in order to control bi-directional flow of electrons within the long conductor layer and, thereby formation of opens and/or shorts at the long conductor layer-short conductor layer interfaces. The formation of such opens and/or shorts can be used to achieve different programming states. Other circuit structure embodiments incorporate e-fuses with additional conductor layers and additional terminals so as to allow for even more programming states. Also disclosed are embodiments of associated e-fuse programming and re-programming methods. | 01-06-2011 |
20110001552 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first transmission line and a second transmission line disposed at different layers; a contact fuse coupled with the first transmission line and the second transmission line; a power driver configured to apply an electric stress to the contact fuse; and a fuse state output unit configured to output a fuse state signal having a logic level corresponding to an electric connection state of the contact fuse. | 01-06-2011 |
20110006834 | SEMICONDUCTOR DEVICE AND METHOD OF MONITORING BLOWING OF FUSE IN SEMICONDUCTOR DEVICE - In some embodiments, a semiconductor device includes a fuse having a conductive portion configured to be blown when a current exceeding a rated value flows through the conductive portion, a first monitor wiring configured to monitor blowing of the conductive portion of the fuse, and a second monitor wiring configured to monitor blowing of the conductive portion of the fuse. The first monitor wiring and the second monitor wiring are connected to the conductive portion of the fuse so as to be away from a longitudinal center of the conductive portion. | 01-13-2011 |
20110012668 | PROGRAMMABLE EFUSE AND SENSE CIRCUIT - A circuit for electric fuses includes circuits for sensing status and programming that have separate paths for each operation. The circuit includes a plurality of electrically programmable fuses and, associated with each fuse, a switch for coupling a first terminal of the fuse to a ground supply for programming or to a comparator for sensing. The circuit uses a switched current source to supply current to the fuses for programming. The comparator senses a fuse status when a current source is switched through the fuse. The comparator compares a voltage across the fuse and associated switches to a comparison voltage across a comparison resistor and switches included for matching. | 01-20-2011 |
20110032025 | PROGRAMMABLE SEMICONDUCTOR DEVICE - A programmable device includes a substrate ( | 02-10-2011 |
20110063015 | SEMICONDUCTOR MEMORY DEVICE - The present invention provides a semiconductor memory device that includes: a fuse circuit having multiple fuse elements; and a fuse selection circuit connected to an internal address signal line that receives an address signal externally inputted. The fuse circuit is connected to the fuse selection circuit to receive an output from the fuse selection circuit, is supplied with an externally inputted trigger signal that permits nonvolatile recording of the fuse elements, and, in response to the output and the trigger signal, records the fuse element corresponding to the internal address signal line among the plurality of fuse elements while recording at least one of the plurality of fuse elements other than the fuse element thus recorded. | 03-17-2011 |
20110102067 | Fuse devices and methods of operating the same - A fuse device includes a fuse unit, which includes a cathode, an anode, and a fuse link coupling the cathode and the anode. A transistor includes at least a portion of the fuse unit to be used as an element of the transistor. | 05-05-2011 |
20110128068 | FUSE CIRCUIT AND OPERATION METHOD THEREOF - A fuse circuit includes a control signal generation unit configured to generate a control signal that is enabled after a moment when a power-up signal is enabled, a potential control unit configured to control potentials of both ends of a fuse in response to the control signal, and a fuse output unit configured to be initialized in response to the power-up signal and output a fuse signal in response to whether the fuse is cut or not. | 06-02-2011 |
20110156801 | TAMPER RESISTANT FUSE DESIGN - A tamper resistant fuse design is generally presented. In this regard, an apparatus is introduced comprising a plurality of fuses in an integrated circuit device to store values and a plurality of resistors in parallel to the fuses, wherein each fuse includes a parallel resistor to provide a potential dissipation path around the fuse. Other embodiments are also described and claimed. | 06-30-2011 |
20110199150 | FUSE SET AND SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS HAVING THE SAME - A fuse set includes a first row constituted by a plurality of fuses which are arranged with a first spacing; a second row including a plurality of fuses which are disposed to correspond to the fuses of the first row on the same plane, and separated from the fuses of the first row with a second spacing; and a connection part disposed between the first row and the second row and electrically connected with the plurality of fuses of the first row and the plurality of fuses of the second row, wherein the connection part and the pluralities of fuses of the first and second rows are disposed on different planes. | 08-18-2011 |
20110234303 | ELECTRIC FUSE CIRCUIT AND METHOD OF OPERATING THE SAME - A fuse circuit includes an electric fuse coupled to a first voltage source; a low resistance unit coupled to the electric fuse and having a junction which is capable of breaking down; and a switching unit coupled between the low resistance unit and a second voltage source. | 09-29-2011 |
20110241761 | FUSE CIRCUIT WITH ENSURED FUSE CUT STATUS - A fuse circuit includes a fuse information signal generation unit and an output driving unit. The fuse information signal generation unit is configured to precharge a fuse information signal in response to a precharge signal and drive the fuse information signal in response to a selection signal capable of cutting a fuse. The output driving unit configured to equally maintain potentials at both terminals of the fuse in response to a control signal. | 10-06-2011 |
20110241762 | FUSE CIRCUIT - A fuse circuit includes a fuse, a control pulse generation unit, and an equipotential element. The fuse is coupled between a power supply voltage terminal and a first node. The control pulse generation unit is configured to generate a control pulse including a pulse generated in a period in which a power-up period is ended. The equipotential element is configured to make the first node have the same potential as a power supply voltage in response to the control pulse. | 10-06-2011 |
20110248775 | ELECTRONIC FUSE SYSTEM - An electronic fuse system includes: a pad, an electronic fuse circuit, a first switch circuit, and a control circuit. The pad is used of receiving a reference voltage. The electronic fuse circuit is used of changing a voltage level when a current signal passes. The first switch circuit coupled between the pad and the electronic fuse circuit, for controlling the first switch circuit disabled or enabled according to a switch control signal. The control circuit, coupled to the first switch circuit, for transferring the switch control signal according a control signal and a lock signal. Wherein, when the lock signal is enabled, the control signal is unable to control the control circuit to turn on the first switch circuit. | 10-13-2011 |
20110267136 | SEMICONDUCTOR DEVICE AND METHOD OF CUTTING ELECTRICAL FUSE - A method of cutting an electrical fuse including a first conductor and a second conductor, the first conductor including a first cutting target region, the second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on a semiconductor substrate, the method includes flowing a current in the first conductor, causing material of the first conductor to flow outward near a coupling portion connecting the first conductor to the second conductor, and cutting the first cutting target region and the second cutting target region. | 11-03-2011 |
20110279171 | ELECTRICALLY PROGRAMMABLE FUSE CONTROLLER FOR INTEGRATED CIRCUIT IDENTIFICATION, METHOD OF OPERATION THEREOF AND INTEGRATED CIRCUIT INCORPORATING THE SAME - An electrically programmable fuse controller, a method of controlling a drive voltage of an integrated circuit (IC) and an IC incorporating the controller or the method. In one embodiment, the controller includes a VID eFuse controller configured to receive and write a voltage identifier to an associated eFuse and thereafter allow the voltage identifier to be read from the eFuse and employed to set a drive voltage of an integrated circuit associated with the VID eFuse controller. | 11-17-2011 |
20110291744 | FUSE CIRCUIT OF SEMICONDUCTOR APPARATUS - Various embodiments of a fuse circuit of a semiconductor apparatus are disclosed. In one exemplary embodiment, the fuse circuit may include a fuse whose electrical connection state can be changed by an electrical stress applied thereto and a plurality of self boosting units configured to perform self boosting operations under the control of a rupture enable signal. The self boosting units may also be configured to generate stress voltages and supply the generated stress voltages to the fuse. The fuse circuit may also include a precharge unit configured to supply a precharge voltage to the fuse in response to a precharge signal and a cross-coupled latching amplification unit configured to sense a change in a voltage level of the precharge voltage supplied to the fuse, with reference to a reference voltage, and output a fuse state signal. | 12-01-2011 |
20110316613 | MICROPROCESSOR APPARATUS AND METHOD FOR SECURING A PROGRAMMABLE FUSE ARRAY - An apparatus in an integrated circuit for precluding the use of extended JTAG operations. The apparatus has a JTAG control chain, a feature fuse, and an access controller. The JTAG control chain is configured to enable/disable the extended JTAG operations. The feature fuse is configured to indicate whether the extended JTAG features are to be disabled. The access controller is coupled to the feature fuse and the JTAG control chain. The access controller determines if the feature fuse is blown, and directs the JTAG control chain to disable the extended JTAG operations. | 12-29-2011 |
20110316614 | APPARATUS AND METHOD FOR TAMPER PROTECTION OF A MICROPROCESSOR FUSE ARRAY - An apparatus in an integrated circuit for precluding the use of extended JTAG operations. The apparatus has a JTAG control chain, a feature fuse, a level sensor, and an access controller. The JTAG control chain is configured to enable/disable the extended JTAG operations. The feature fuse is configured to indicate whether the extended JTAG features are to be disabled. The level sensor is configured to monitor an external voltage signal, and configured to indicate that the external voltage signal is at an illegal level. The access controller is coupled to the feature fuse, the level sensor, and the JTAG control chain, and is configured to determine if the feature fuse is blown, and is configured to direct the JTAG control chain to disable the extended JTAG operations if the external voltage signal is at an illegal level regardless of whether the feature fuse is blown. | 12-29-2011 |
20110316615 | INTEGRATED CIRCUIT - An integrated circuit, wherein a voltage-adjustable power supply circuit ( | 12-29-2011 |
20120019310 | TRIMMER CIRCUIT AND METHOD - A trimmer circuit is so configured that an electronic device will break down to produce a high current to trim a fuse. The electronic device is selectively configured to have a breakdown voltage lower than an applied voltage, for the trigger of its breakdown to be controllable. In an embodiment, the electronic device is switched between two states having two breakdown voltages respectively, and the applied voltage is higher than one of the breakdown voltages and lower than the other one. | 01-26-2012 |
20120068761 | Method and apparatus for protection of an anti-fuse element in a high-voltage integrated circuit - A soft clamp semiconductor device for preventing inadvertent programming of an unselected anti-fuse (AF) element comprises a MOSFET which includes a first well region disposed in a substrate. Source and drain regions are disposed in the first well region, the drain region being electrically coupled to the first capacitive plate of the AF element and the source region being electrically coupled to a second capacitive plate of the AF element. An insulated gate is disposed over a channel area of the first well region that separates the drain and source regions. A gate capacitance of the MOSFET is substantially less than a capacitance of the unselected AF element such that when a programming voltage is applied to the first capacitive plate, a current flows through the MOSFET that charges the second capacitive plate, thereby reducing a voltage build-up across the unselected AF element. | 03-22-2012 |
20120075006 | ZERO PIN SERIAL INTERFACE - A method for controlling performance of an integrated circuit using a zero-pin serial interface is provided. The method comprises identifying a desired performance characteristic of the circuit, and transmitting a first change mode signal to the circuit on a first pin to cause the circuit to enter an instruction reception mode, with the first pin performing differently during a normal operation mode. The method also comprises transmitting a performance adjusting instruction to the circuit on a second pin when the circuit is in the instruction reception mode, with the second pin performing differently during the normal operation mode, and transmitting a second change mode signal to the circuit on the first pin to cause the circuit to enter the normal operation mode. An output performance of the circuit is compared to the desired performance characteristic, with the output performance being the performance of the circuit during the normal operation mode. The circuit is set to permanently provide the output performance when the output performance is within a desired tolerance of the desired performance characteristic. | 03-29-2012 |
20120086500 | FUSE DETECTING APPARATUS - A fuse detecting apparatus including a detector, a calibrator and a logical operating unit is disclosed. The detector includes a detecting switch module and a detecting latch. The detecting switch module generates an initial detecting result according to a first and a second control signals and a status of the fuse. The detecting latch stores a voltage level of the initial detecting result or maintains its originally stored voltage level according to the initial detecting result for generating a pre-calibrating detecting signal. The calibrator includes a calibrating switch module and a calibrating latch. The calibrating switch module generates a calibrating result according to the first and the second control signals. The calibrating latch stores the calibrating result and generates a calibrating signal accordingly. The logical operating unit generates a calibrated detecting signal according to the pre-calibrating detecting signal and the calibrating signal. | 04-12-2012 |
20120092062 | SEMICONDUCTOR SYSTEM - A semiconductor system includes a controller; a semiconductor device comprising a plurality of stacked semiconductor chips stacked over the controller, and a plurality of through-silicon vias (TSVs) configured to commonly transfer a signal to the plurality of stacked semiconductor chips; and a defect information transfer TSV configured to transfer TSV defect information sequentially outputted from at least one of the semiconductor chips to the controller, wherein the controller comprises: a plurality of first repair fuse units configured to set first fuse information based on the TSV defect information; and a plurality of first TSV selection units configured to selectively drive the TSVs in response to the first fuse information. | 04-19-2012 |
20120105136 | FUSE LINK SYSTEM FOR DISPOSABLE COMPONENT - A fuse system for use with a disposable component of a device may include a disposable component having at least a first lockout circuit and a second lockout circuit. The first lockout circuit may include a first fuse link, and the second lockout circuit may include a second fuse link. The fuse system may include a computing device in communication with the first lockout circuit and the second lockout circuit, and a computer-readable storage medium in communication with the computing device. The computer-readable storage medium may include one or more programming instructions for deactivating the first fuse link at a first time, and deactivating the second fuse link at a second time. | 05-03-2012 |
20120119820 | Fuse Circuit - A fuse circuit comprises a fuse set and an enable circuit. The enable circuit is configured to receive a test mode enable signal and a power up signal to generate an enable signal and a voltage level to the fuse set for indicating whether an external supply voltage reaches a predetermined value and whether a test mode is enabled. In particular, an output signal of the fuse set is constant in the test mode, regardless of whether a fuse in the fuse set is blown or not. | 05-17-2012 |
20120146710 | Fuse Device - Implementations are presented herein that relate to a fuse device, an integrated circuit including a fuse device, a method of implementing a fuse device and a method of programming a fuse device. | 06-14-2012 |
20120161855 | APPARATUS AND METHOD FOR PROGRAMMING AN ELECTRONICALLY PROGRAMMABLE SEMICONDUCTOR FUSE - An apparatus for programming an electronically programmable semiconductor fuse applies a programming current to a fuse link as a series of multiple pulses. Application of the programming current as a series of multiple short pulses provides a level of programming current sufficiently high to ensure reliable and effective electromigration while avoiding exceeding temperature limits of the fuse link. | 06-28-2012 |
20120169402 | SEMICONDUCTOR DEVICE - A semiconductor device includes an electric fuse circuit and a program protective circuit. The electric fuse circuit includes a fuse element and a transistor connected together in series and placed between a program power supply and a grounding, and controlling sections. The program protective circuit is placed in parallel with the electric fuse circuit and between the program power supply and the grounding. When a surge voltage is applied between the program power supply and the grounding, the foregoing structure allows a part of a surge electric current can flow through the program protective circuit. | 07-05-2012 |
20120176180 | PASSIVE RESISTIVE-HEATER ADDRESSING NETWORK - There is described a passive heater-and-diode multiplexing network for selective addressing of thermally-coupled and electrically-disconnected fuses within a passive device network (resistor/capacitor/inductor) or within an application circuit. | 07-12-2012 |
20120194260 | SEMICONDUCTOR DEVICE HAVING PLURAL OPTICAL FUSES AND MANUFACTURING METHOD THEREOF - Such a device is disclosed that includes a first ladder fuse for which blowing points are arranged at a first coordinate and a second ladder fuse for which blowing points are arranged at a second coordinate. When adjustment data for adjusting circuit characteristics is within a first range, a trimming operation is performed on both the first and second ladder fuses, and when the adjustment data for adjusting the circuit characteristics is within a second range, the trimming operation is performed on the second ladder fuse without performing the trimming operation on the first ladder fuse. This configuration eliminates a necessity of irradiation on the first ladder fuse with a laser when the adjustment data is within the second range. | 08-02-2012 |
20120249220 | Trim Circuit for Power Supply Controller - A trim circuit for a power supply controller includes: a control circuit; at least a capacitance type programmable circuit connection; and a switching circuit, under control of the control circuit, the switching circuit selectively coupling the capacitance type programmable circuit connection to anyone of an operation voltage and a programming voltage, for determining a programming state of the capacitance type programmable circuit connection. | 10-04-2012 |
20120249221 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a fuse set; a terminal assigned to be applied with a first external signal in a normal operation; and a control unit configured to receive a second external signal through the terminal and apply the received second external signal to the fuse set in a fuse control operation. | 10-04-2012 |
20120262223 | SEMICONDUCTOR DEVICE - A semiconductor device includes a signal output unit, and a decision unit. The signal output unit includes m (≧2) pieces of fuses, a NAND gate, resistance elements, and an output terminal. The decision unit decides whether n or more pieces (m≧n≧2) of fuses are disconnected out of the m pieces of fuses included in the signal output unit, and outputs the result of a decision. When m=n=2, the decision unit is constituted of a NOR gate having two input terminals connected to a respective end of the fuses. Thus, a H-level potential signal is output at an output terminal of the NOR gate when the decision result is affirmative. On the other hand, when the decision result is negative, a L-level potential signal is output at the output terminal. | 10-18-2012 |
20120268195 | IMPLEMENTING eFUSE CIRCUIT WITH ENHANCED eFUSE BLOW OPERATION - A method and an eFuse circuit for implementing with enhanced eFuse blow operation without requiring a separate high current and high voltage supply to blow the eFuse, and a design structure on which the subject circuit resides are provided. The eFuse circuit includes an eFuse connected to a field effect transistor (FET) operatively controlled during a sense mode and a blow mode for sensing and blowing the eFuse. The eFuse circuit is placed over an independently voltage controlled silicon region. During a sense mode, the independently voltage controlled silicon region is grounded providing an increased threshold voltage of the FET. During a blow mode, the independently voltage controlled silicon region is charged to a voltage supply potential. The threshold voltage of the FET is reduced by the charged independently voltage controlled silicon region for providing enhanced FET blow function. | 10-25-2012 |
20120274391 | FUSE CIRCUIT FOR SEMICONDUCTOR DEVICE - A fuse circuit of a semiconductor device includes a transfer unit configured to selectively transfer a corresponding address signal in response to a first test mode signal, a fuse control unit configured to drive an output end with a first voltage in response to an output signal of the transfer unit, a fuse unit including a MOS transistor having a gate coupled to the output end, and a fuse enable unit configured to selectively supply a second voltage to a source/drain of the MOS transistor of the fuse unit in response to the first test mode signal, wherein the fuse circuit is programmed by causing a breakdown of the MOS transistor in response to a voltage difference between the first voltage and the second voltage that are applied to the gate and the source/drain of the MOS transistor of the fuse unit. | 11-01-2012 |
20120286848 | ELECTRONIC TRIMMING CIRCUIT - The trimming circuit includes a plurality of trimmable resistances that may be coupled among them, each resistance being connected in parallel to a respective fuse. The trimming circuit allows burning any number of fuses according to a fixed trimming sequence using only one or two dedicated pins because it includes an input diode-connected transistor and a plurality of trimming transistors of different sectional area, each connected to force current throughout a respective one of the shunt fuses and coupled to the input diode-connected transistor such to mirror the current flowing therethrough. The fuses of the trimming circuit may be burnt by applying a trimming voltage to the diode-connected input transistor with a voltage generator connected between a dedicated pin of the circuit and a terminal at a reference potential, such to force a current therethrough as long as the mirrored currents flowing throughout the fuses burn them. | 11-15-2012 |
20120286849 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE SYSTEM - A semiconductor apparatus includes: a plurality of electrical fuses; a rupture unit configured to rupture an electrical fuse in response to rupture information applicable to the plurality of electrical fuses, when a rupture enable signal is activated; a scan unit configured to output information on whether an each of the plurality of electrical fuses are ruptured or not, as scan information, when a scan enable signal is activated; and a shift register unit configured to receive an input signal in synchronization with a clock signal and store the input signal as the rupture information, and configured to receive the scan information and output the scan information as an output signal in synchronization with the clock signal. | 11-15-2012 |
20120293241 | ELECTRONIC TRIMMING CIRCUIT WITH REDUCED NUMBER OF DEDICATED TRIMMING PINS - An electronic trimming circuit carries out a trimming operation on portions of an integrated device. The circuit includes N trimmable interconnected resistances, each connected in parallel to a respective shunt fuse. N trimming transistors are each connected to a respective one of the shunt fuses to force therethrough substantially the whole current flowing in the respective trimming transistor. N bias networks are each functionally connected to a control terminal of a respective one of the trimming transistors to directly bias an active junction thereof. An externally driven heating device is thermally coupled with the active junctions of the trimming transistors adapted to raise the temperature thereof. | 11-22-2012 |
20120299639 | TRIMMING CIRCUIT AND METHOD FOR DRIVING TRIMMING CIRCUIT - A highly reliable trimming circuit is provided. A rewritable trimming circuit is provided. A method for driving a highly reliable trimming circuit is provided. A method for driving a rewritable trimming circuit is provided. The trimming circuit includes a storage node connected to a source electrode or a drain electrode of a transistor whose off-state leakage current is extremely low and a transistor whose gate electrode is connected to the storage node. The trimming state of an element or a circuit connected in parallel to a source electrode and a drain electrode of the transistor whose gate electrode is connected to the storage node is controlled using the transistor whose off-state leakage current is extremely low. | 11-29-2012 |
20120299640 | Integrated Circuit Die Stacks Having Initially Identical Dies Personalized With Fuses - Integrated circuit die stacks having a first die mounted upon a substrate, the first die manufactured to be initially identical to a second die with a plurality of through silicon vias (‘TSVs’), the first die personalized by blowing fuses on the first die, converting the TSVs previously connected through the blown fuses into pass-through vias (‘PTVs’), each PTV implementing a conductive pathway through the first die with no connection to any circuitry on the first die; and the second die, manufactured to be initially identical to the first die and later personalized by blowing fuses on the second die, the second die mounted upon the first die so that the PTVs in the first die connect signal lines from the substrate through the first die to TSVs in the second die. | 11-29-2012 |
20120313690 | Capacitive Discharge Fuse Programming Apparatus and Method - An apparatus for programming a fuse includes a programmable branch comprising a fusable element and a reverse-biased diode connected in series. The programmable branch is connected in parallel with a current boost capacitor. An electrical source or input supplies a current that is sufficient to charge the current boost capacitor to a breakdown voltage of the reverse-biased diode and subsequently melt the reverse-biased diode. Melting the reverse-biased diode may induce a reduction in voltage across the current boost capacitor and result in a current surge through the programmable branch that is sufficient to program (i.e. blow) the fusable element. A corresponding method for programming a fuse is also disclosed. | 12-13-2012 |
20130063202 | SECURE ANTI-FUSE WITH LOW VOLTAGE PROGRAMMING THROUGH LOCALIZED DIFFUSION HEATING - An antifuse has first and second semiconductor regions having one conductivity type and a third semiconductor region therebetween having an opposite conductivity type. A conductive region contacting the first region has a long dimension in a second direction transverse to the direction of a long dimension of a gate. An antifuse anode is spaced apart from the first region in the second direction and a contact is connected with the second region. Applying a programming voltage between the anode and the contact with gate bias sufficient to fully turn on field effect transistor operation of the antifuse heats the first region to drive a dopant outwardly, causing an edge of the first region to move closer to an edge of the second region and reduce electrical resistance between the first and second regions by an one or more orders of magnitude. | 03-14-2013 |
20130093502 | APPARATUS AND METHOD FOR GENERATING DIGITAL VALUE - Provided is an apparatus for generating a digital value that may generate a random digital value, and guarantee time invariance of the generated digital value. The apparatus may include a digital value generator to generate a random digital value using semiconductor process variation, and a digital value freezing unit that may be connected to the digital value generator and fixed to one of a first state and a second state based on the generated digital value, to freeze the digital value. | 04-18-2013 |
20130106496 | NANOWIRE EFUSES | 05-02-2013 |
20130106497 | METHODS FOR TRAPPING CHARGE IN A MICROELECTROMECHANICAL SYSTEM AND MICROELECTROMECHANICAL SYSTEM EMPLOYING SAME | 05-02-2013 |
20130135034 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING FUSE CIRCUIT AND DRIVING METHOD OF FUSE CIRCUIT - A semiconductor integrated circuit includes a fuse connected between a first node and a second node, a first driver configured to pull down a voltage of the first node in an initialization period in response to a fuse sensing signal, a second driver configured to pull up a voltage of the second node in an initial period of a fuse sensing period in response to the fuse sensing signal, a sensor configured to determine whether the fuse is blown or not in response to a voltage of the first node, and a third driver configured to drive the second node to a voltage level lower than a pull-up voltage level of the second driver after the initial period of the fuse sensing period in response to an output signal of the sensor and the fuse sensing signal. | 05-30-2013 |
20130135035 | ANTI-FUSE CONTROL CIRCUIT - An anti-fuse control circuit includes a first power supply voltage application unit, a second power supply voltage application unit and a control unit. The first power supply voltage application unit configured to selectively apply first power supply voltage to an output node in response to a power up signal. The second power supply voltage application unit configured to selectively apply second power supply voltage to the output node in response to a program signal. The control unit configured to control a connection between the output node and an anti-fuse in response to the power up signal when the program signal is inactivated. | 05-30-2013 |
20130147542 | FUSE CIRCUIT - A fuse circuit includes a programming fuse signal generation block configured to generate parity signals, logic levels of which are determined according to addresses selected among a plurality of addresses with a programming enable signal enabled, and generate programming fuse signals which are programmed in response to the programming enable signal, the plurality of addresses and the parity signals; a corrected pulse generation block configured to correct an error included in the programming fuse signals and generate corrected pulses; and a fuse unit configured to generate fuse signals which are reprogrammed according to the corrected pulses. | 06-13-2013 |
20130162329 | ANTI-FUSE CIRCUIT AND FUSE REPTURE METHOD THEREOF - An anti-fuse circuit includes a control block configured to generate a first control signal and a second control signal in response to a first test signal and a second test signal, and a fuse set block configured to perform a primary fuse rupture operation in response to the first control signal and to perform a secondary fuse rupture operation in response to the second control signal, the fuse set block activating a fuse signal if any one of the primary fuse rupture operation and the secondary fuse rupture operation succeeds. | 06-27-2013 |
20130169349 | ANTI-FUSE CIRCUIT - An anti-fuse circuit includes: a first fuse unit including a first anti-fuse which is determined to be short-circuited if the first anti-fuse in a programmed state and determined not to be short-circuited if the first anti-fuse in a non-programmed state, and configured to generate an output signal according to a state of the anti-fuse and a restoration signal; and a second fuse unit including a second anti-fuse, and configured to activate the restoration signal when the second anti-fuse is in the programmed state in case where the first anti-fuse is in the programmed state. | 07-04-2013 |
20130176073 | BACK-END ELECTRICALLY PROGRAMMABLE FUSE - A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current. | 07-11-2013 |
20130187706 | TAMPER RESISTANT ELECTRONIC SYSTEM UTILIZING ACCEPTABLE TAMPER THRESHOLD COUNT - A tamper resistant electronic device includes multiple eFuses that are individually blown in each instance the electronic device is tampered with. For example an eFuse is blown when the electronic device is subjected to a temperature that causes solder reflow. Since it is anticipated that the electronic device may be tampered with in an acceptable way and/or an acceptable number of instances, functionality of the electronic device is altered or disabled only after a threshold number of eFuses are blown. In certain implementations, the threshold number is the number of anticipated acceptable tamper events. Upon a tamper event an individual eFuse is blown. If the total number of blown eFuses is less than the threshold, a next eFuse is enabled so that it may be blown upon a next tamper event. | 07-25-2013 |
20130222048 | POWER DEVICE - A power device possesses a built-in fuse function and can continue to normally operate after a short circuit failure. The power device includes a plurality of output cells, a plurality of bonding wires provided corresponding to the output cells, and a control terminal driving circuit. Each of the output cells includes an output transistor. First side electrodes of the output transistors are commonly coupled to a first power source. Each of second side electrodes of the output transistors is coupled to an output terminal through the corresponding bonding wire. The control terminal driving circuit supplies a drive signal to the control terminals of the individual output transistors to control the output transistors. Each of the bonding wires is designed to be fused and cut if the output transistor included in the corresponding output cell fails and is shorted. | 08-29-2013 |
20130234783 | MOTOR DRIVE WITH CONFIGURABLE SIGNAL CONDITIONING APPARATUS AND METHOD - Motor drives, signal conditioning systems and configurable circuit boards are presented in which diode blocking circuits are provided for contemporaneous opening of programming fuses in multiple programmable impedance circuits using a single configuration input signal during manufacturing and for mitigating interference between impedance circuits during system operation. | 09-12-2013 |
20130257520 | SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME - A semiconductor device includes: a first driving voltage generation unit configured to generate a first driving voltage; a fuse unit coupled between an output node for receiving the first driving voltage and a fuse state sensing node; a driving unit configured to drive the fuse state sensing node with a second driving voltage in response to a control signal; a voltage level control unit configured to generate a voltage level control signal in response to a fuse state sensing signal that corresponds to a voltage level of the fuse state sensing node; and a second driving voltage generation unit configured to control and output a voltage level of the second driving voltage in response to the voltage level control signal. The semiconductor device repeatedly performs a rupture operation by monitoring a fuse state sensing signal. | 10-03-2013 |
20130265101 | ANTI-FUSE CIRCUIT - An anti-fuse circuit includes: an anti-fuse unit including an anti-fuse capable of being programmed in response to a rupture signal and configured to generate a fuse signal corresponding to a state of the anti-fuse; a dummy fuse unit including a dummy fuse and configured to generate a dummy fuse signal corresponding to a state of the dummy fuse; and a blocking unit configured to output the fuse signal as a fuse output signal in response to a state of the dummy fuse signal. | 10-10-2013 |
20130314149 | ANTI-FUSE CIRCUIT - An anti-fuse circuit includes: a rupture unit including an anti-fuse programmed in response to an input rupture signal during a program mode, and configured to generate an output rupture signal corresponding to a state of the anti-fuse to output the generated output rupture signal to a transmission node, a voltage clamp unit configured to generate a clamp voltage proportional to an external voltage level to generate the clamp voltage having a constant voltage level when the external voltage level rises to a predetermined level or more, and a fuse signal generation unit configured to reset the transmission node to the clamp voltage at the initial stage of the program mode to generate a fuse signal in response to the voltage level of the transmission node during an output mode. | 11-28-2013 |
20130314150 | Method for Detecting Electrical Energy Produced from a Thermoelectric Material contained in an Integrated Circuit - An integrated circuit includes active circuitry disposed at a surface of a semiconductor body and an interconnect region disposed above the semiconductor body. A thermoelectric material is disposed in an upper portion of the interconnect region away from the semiconductor body. The thermoelectric material is configured to deliver electrical energy when exposed to a temperature gradient. This material can be used, for example, in a method for detecting the repackaging of the integrated circuit after it has been originally packaged. | 11-28-2013 |
20130321066 | ELECTRONICALLY PROGRAMMABLE FUSE SECURITY ENCRYPTION - A semiconductor structure including a device configured to receive an input data-word. The device including a logic structure configured to generate an encrypted data-word by encrypting the input data-word through an encrypting operation. The device further including an eFuse storage device configured to store the encrypted data-word as eFuse data by blowing fuses in accordance with the encrypted data-word. | 12-05-2013 |
20140002178 | SEMICONDUCTOR PACKAGE WITH MECHANICAL FUSE | 01-02-2014 |
20140022004 | FUSE SENSING CIRCUITS - A fuse sensing circuit is disclosed. Embodiments include: providing a sense input terminal; providing a sense output terminal; and providing first and second capacitors that are configured to charge and discharge based on the sense input terminal, wherein the first and second capacitors are further configured to discharge current to a fuse unit cell, and the sense output terminal is configured to indicate a fuse state of the fuse unit cell based on the discharging of the first and second capacitors. Embodiments include the indicated fuse state being based on a discharge rate difference between the discharging of the first capacitor and the discharging of the second capacitor. | 01-23-2014 |
20140028381 | HIGH SPEED LOW POWER FUSE CIRCUIT - A fuse circuit having a fuse unit cell containing two fuses. In the program/write mode, only one of the fuses in the fuse unit cell will be blown. In read mode, since only one fuse is blown, the current that goes through the two fuses in the fuse unit cell will be very small. Hence, the read power consumption for the fuse circuit is also very small and its sensing speed is also very high. | 01-30-2014 |
20140218100 | A New E-fuse Structure Design in Electrical Programmable Redundancy for Embedded Memory Circuit - An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer. | 08-07-2014 |
20140240033 | On-Die Programming of Integrated Circuit Bond Pads - SoC and SiP designs are configured with an antifuse link within the die to allow on-die programming of bond wires connecting package lead fingers to the bond pads on the die. This permits alteration of the bond pad connections for the die, particularly for the ground voltage ground signal (VSS) connections on the bond pad, at the testing stage after the die package and the power supply have been installed on the PCB. On-die programming of antifuse link allows the VSS bond pad connections to be reconfigured, typically to eliminate long bond wire runs to reduce ground bounce and simultaneous switching output (SSO) noise, after assembly and field testing of the integrated circuit. Antifuse programming is completed by applying the programming voltage to the programming pad of the antifuse. | 08-28-2014 |
20140253220 | ELECTRONIC FUSE CELL AND ARRAY - Embodiments may include an eFuse cell. The eFuse cell may include an eFuse having a first end and a second end. A blowFET has a first source/drain area, a second source/drain area, and a first gate. The first source/drain area is coupled to the second end of the eFuse, the second source/drain area is coupled to ground, and the first gate is coupled to a first node. The eFuse cell includes a senseFET having a third source/drain area, a fourth source/drain area, and a second gate. The second gate is coupled to the first node, and the third source/drain area is coupled to a second node. The second node is coupled to an operation signal and the second end of the eFuse. The eFuse cell includes a select eFuse logic element having an input to receive a select eFuse signal and an output coupled to the first node. | 09-11-2014 |
20140253221 | On-Die Programmable Fuses - In one embodiment described herein, on-die programmable fuses may be used. On-die programmable fuses may be programmed by entities other than the chip manufacturer after the fuse array chip has been manufactured and shipped out. However, other non-volatile memories may also be used. | 09-11-2014 |
20140253222 | PREVENTING ELECTRONIC DEVICE COUNTERFEITS - Systems and methods for authenticating electronic devices may perform one or more operations including, but not limited to: receiving at least one code associated with an authorization to perform one or more manufacturing life-cycle operations for at least one electronic device; and blowing one or more fuses of the at least one electronic device according to the at least one code associated with an authorization to perform one or more manufacturing life-cycle operations for the at least one electronic device. | 09-11-2014 |
20140306750 | SEMICONDUCTOR DEVICE - A low cost, small scale semiconductor device including a trimming circuit having a fuse resistor is disclosed. By a trimming circuit being configured of a MOSFET, a protection circuit, and a fuse resistor, it is possible to carry out a change from an open circuit state to a short circuit state by fusing the fuse resistor. Also, by the protection circuit and fuse resistor configuring the trimming circuit being formed in a two layer structure, it is possible to reduce the size of the trimming circuit, and thus it is possible to provide a low cost, small scale semiconductor device having a trimming circuit that occupies a small area. | 10-16-2014 |
20140347120 | Controlled Transformation of Non-Transient Electronics - Systems and methods of the invention generally relate to altering the functionality of a non-transient electronic device. A container holding an agent is located proximal to a non-transient electronic device capable of performing at least one function. The agent is capable of rendering the device incapable of performing the at least one function. The container is configured to controllably release the agent to the electronic device in a variety of passive and active eventualities. | 11-27-2014 |
20140368261 | SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME - Semiconductor systems are provided. The semiconductor system includes a controller and a semiconductor device. The controller generates a power voltage signal. The semiconductor device generates a power-up signal in response to the power voltage signal, generates a first selection pulse, a second selection pulse and an initialization pulse signal, generates a first fuse signal for controlling an internal operation according to a cut state of a first fuse, and generates a second fuse signal for controlling the internal operation according to a cut state of a second fuse. | 12-18-2014 |
20150008976 | ANTI-FUSE AND METHOD FOR OPERATING THE SAME - An anti-fuse includes a single transistor formed over an active region of a semiconductor substrate and entering a fuse cut state by a threshold voltage being varied upon receiving a voltage applied thereto. The single transistor includes a device isolation film formed in the semiconductor substrate to define the active region, and a liner trap film formed between the device isolation film and the active region in such a manner that electrons are trapped in the liner trap film upon receiving the voltage. | 01-08-2015 |
20150102852 | Stressed Substrates For Transient Electronic Systems - A stressed substrate for transient electronic systems (i.e., electronic systems that visually disappear when triggered to do so) that includes one or more stress-engineered layers that store potential energy in the form of a significant internal stress. An associated trigger mechanism is also provided that, when triggered, causes an initial fracture in the stressed substrate, whereby the fracture energy nearly instantaneously travels throughout the stressed substrate, causing the stressed substrate to shatter into multiple small (e.g., micron-sized) pieces that are difficult to detect. The internal stress is incorporated into the stressed substrate through strategies similar to glass tempering (for example through heat or chemical treatment), or by depositing thin-film layers with large amounts of stress. Patterned fracture features are optionally provided to control the final fractured particle size. Electronic systems built on the substrate are entirely destroyed and dispersed during the transience event. | 04-16-2015 |
20150116028 | Fuse Circuit - A fuse circuit includes a plurality of fuses, a plurality of switches and a plurality of trimming components. The fuses are coupled in parallel to a first node and a second node. The first node is coupled to an operating voltage. The switches are coupled to the second node. The trimming components are respectively disposed between the switches and a ground voltage, and coupled to the second node via the switches, respectively. When one of the trimming components is activated, the activated trimming component allows a plurality of branch currents to be generated between the first node and the second node. The branch currents respectively flow through the fuses so that one of the fuses is blown out by the branch current flowing through the one of the fuses. | 04-30-2015 |
20150145590 | System And Method For On Demand, Vanishing, High Performance Electronic Systems - An integrated circuit system having an integrated circuit (IC) component which is able to have its functionality destroyed upon receiving a command signal. The system may involve a substrate with the IC component being supported on the substrate. A module may be disposed in proximity to the IC component. The module may have a cavity and a dissolving compound in a solid form disposed in the cavity. A heater component may be configured to heat the dissolving compound to a point of sublimation where the dissolving compound changes from a solid to a gaseous dissolving compound. A triggering mechanism may be used for initiating a dissolution process whereby the gaseous dissolving compound is allowed to attack the IC component and destroy a functionality of the IC component. | 05-28-2015 |
20150358021 | Thermally Tempered Glass Substrate Using CTE Mismatched Layers And Paste Mixtures For Transient Electronic Systems - A thermally tempered glass substrate for transient electronic systems (i.e., including electronic devices that visually disappear when triggered to do so) including two or more fused-together glass structures having different coefficient of thermal expansion (CTE) values disposed in an intermixed arrangement manner that generates and stores potential energy in the form of residual, self-equilibrating internal stresses. In alternative embodiments the substrate includes laminated glass sheets, or glass elements (e.g., beads or cylinders) disposed in a glass layer. A trigger device causes an initial fracture in the thermally tempered glass substrate, whereby the fracture energy nearly instantaneously travels throughout the thermally tempered glass substrate, causing the thermally tempered glass substrate to shatter into multiple small (e.g., micron-sized) pieces that are difficult to detect. Patterned fracture features are optionally provided to control the final fractured particle size. Electronic systems built on the substrate are entirely destroyed and dispersed during the transience event. | 12-10-2015 |
20160118138 | PROGRAMMING AN ELECTRICAL FUSE WITH A SILICON-CONTROLLED RECTIFIER - Circuits for programming an electrical fuse, methods for programming an electrical fuse, and methods for designing a silicon-controlled rectifier for use in programming an electrical fuse. A programming current for the electrical fuse is directed through the electrical fuse and the silicon-controlled rectifier. Upon reaching a programmed resistance value for the electrical fuse, the silicon-controlled rectifier switches from a low-impedance state to a high-impedance state that interrupts the programming current. | 04-28-2016 |
20160163658 | ACTIVATING REACTIONS IN INTEGRATED CIRCUITS THROUGH ELECTRICAL DISCHARGE - Embodiments of the present invention provide integrated circuits and methods for activating reactions in integrated circuits. In one embodiment, an integrated circuit is provided having reactive material capable of being activated by electrical discharge, without requiring a battery or similar external power source, to produce an exothermic reaction that erases and/or destroys one or more semiconductor devices on the integrated circuit. | 06-09-2016 |
20170236666 | PROTECTIVE ELEMENT AND PROTECTIVE CIRCUIT SUBSTRATE USING THE SAME | 08-17-2017 |
20170236667 | PROTECTIVE ELEMENT AND PROTECTIVE CIRCUIT SUBSTRATE USING THE SAME | 08-17-2017 |