Class / Patent application number | Description | Number of patent applications / Date published |
327336000 | By integrating | 64 |
20080265974 | Method and Apparatus for Characterizing Signals - Methods and corresponding computer systems for characterizing signals and applications thereof are provided that use a functional depending on signal waveforms. | 10-30-2008 |
20090085641 | CIRCUIT AND METHOD FOR INTEGRATING A VOLTAGE SIGNAL - A circuit arrangement having a signal input configured to be supplied with a voltage signal; a first operational transconductance amplifier (OTA) having a voltage input that may be coupled to the signal input; at least one second OTA having a voltage input that may be coupled to the signal input; and at least one output capacitor which may be coupled to an output of the first OTA and to an output of the at least one second OTA, wherein an identical potential is set at the outputs of the first OTA and of the at least one second OTA. | 04-02-2009 |
20090167406 | Read circuit, variable resistive element device, and imaging device - A read circuit includes: an integration circuit section configured to perform an integral operation and whose input is connected to an integration node; and a bias circuit connected between a connection node to which a variable resistive element is connected and the integration node. The bias circuit includes: an integration transistor whose source and drain are respectively connected to the connection node and the integration node; an operational amplifier whose output is connected to a gate of the integration transistor, to whose first input a bias voltage is supplied, and whose second input is connected to the source of the integration transistor; and a current switching circuit configured to provide or shut off a first current path. The first current path is a current path through which a current flowing between the drain and source of the integration transistor flows without passing through the connection node. | 07-02-2009 |
20100085103 | System and Method for Charge Integration - An arrangement for charge integration comprises an input ( | 04-08-2010 |
20100117710 | SWITCHED CHARGE STORAGE ELEMENT NETWORK - A switched charge storage element integrator in a continuous or discrete time circuit, the integrator including a differential input amplifier, a first 2-terminal charge storage element, a second 2-terminal charge storage element, and a plurality of controlled switches. The differential input amplifier is coupled to a capacitor and a resistor and configured as an inverting integrator. An inverting terminal of the amplifier is coupled to two controlled switches. A non-inverting terminal of the amplifier is coupled to a reference voltage. The first and second switched charge storage element blocks are alternatingly coupled to the inverting terminal INM of the amplifier XOPA during the active state of a second clock signal and a first clock signal, respectively, for making the supply noise continuous and eliminating its dependency on the clock phases, thereby zeroing its convolution with the clock signal. | 05-13-2010 |
20100156501 | Adjustable integrator using a single capacitance - An integrating amplifier on an IC, which comprises a feedback loop using an external device as an integrating capacitor, has added a second feedback loop that provides an additional current to the input of the amplifier, which current can be used to increase the input range of the charge that can be measured without needing another external capacitor or pad. | 06-24-2010 |
20100164594 | System and Method for Charge Integration - An arrangement for charge integration comprises a charge-generating circuit ( | 07-01-2010 |
20100176865 | GAIN CONTROL WITH MULTIPLE INTEGRATORS - A system according to one embodiment includes an analog input for receiving an analog signal; a variable gain amplifier coupled to the analog input; a first integrator coupled to the variable gain amplifier for controlling the gain of the analog signal; a second integrator generating control signals for controlling functions of the first integrator; a serializer for serializing the control signals; and a deserializer coupled to the serializer for deserializing the control signals and passing the deserialized control signals to the first integrator. | 07-15-2010 |
20100308889 | Crossing Input Signal Modulator - The invention relates to a pulse width modulator, more particularly to a cross-coupled pulse width modulator. A crossing input signal modulator according to the present invention comprises: a positive path block which includes a first integrator for performing the first-order integration of feedback signals in first input and output signals and then transmitting the first—order integrated signals to a second integrator, and a second integrator for performing the second-order integration of a signal from the first integrator and a second input signal and then transmitting the second-order integrated signals; and a negative path block which includes a third integrator for performing the first-order integration of feedback signals in the second input and output signals and integration of a signal from the third integrator and the first input signal and then transmitting the second-order integrated signals. This configuration allows cross-coupling of the inputs from two integrators to generate an accurate differential pulse width modulation (PWM) single, and enables optimization of the IC implementation by adopting a feedback system that features a simplified implementation and minimal application area. | 12-09-2010 |
20110068847 | EQUALIZER CIRCUIT AND RECEPTION APPARATUS - An equalizer circuit includes: a plurality of amplifiers that convert a voltage signal into a current; a plurality of capacitive loads that are charged and discharged in accordance with respective outputs of the plurality of amplifiers; a charge discharge circuit provided for each of the plurality of capacitive loads to charge or discharge one of the plurality of capacitive loads; and a reset circuit provided for each of the capacitive loads to initialize the charge stored in the one of the plurality of capacitive loads, wherein a current according to the voltage signal is integrated in different periods for each of the plurality of capacitive loads and the capacitive load is discharged through the current in a first period and the capacitive load is charged through the current in a second period following the first period. | 03-24-2011 |
20110084752 | Systems and Methods for Maintaining a Drive Signal to a Resonant Circuit at a Resonant Frequency - Systems and methods for maintaining a drive signal to a resonant circuit at a resonant frequency are provided. A system for maintaining a drive signal to a resonant circuit at a resonant frequency can include: an oscillator configured to provide an output to a phase comparator and a drive circuit, the drive circuit configured to provide a drive signal to a resonant circuit; a phase detector configured to receive a filtered version of the drive signal from the resonant circuit and provide a phase-indicating signal to the phase comparator; and the phase comparator, wherein the phase comparator is configured to provide a signal based on the phase difference between the oscillator output and the phase-indicating signal, wherein the signal from the phase comparator is used to control the frequency of the oscillator such that the phase difference converges to a fixed value. | 04-14-2011 |
20120126876 | GAIN CONTROL WITH MULTIPLE INTEGRATORS - A method according to one embodiment includes receiving an increment signal at a first integrator when a second integrator overflows; receiving a decrement signal at the first integrator when the second integrator underflows; and incrementing or decrementing a gain applied to an analog signal based on receipt of the increment or decrement signal. A system according to one embodiment includes a first integrator configured to cause incrementing of a gain applied to an analog signal based on receipt of an increment signal when a second integrator overflows, the first integrator being configured to cause decrementing of the gain applied to the analog signal based on receipt of a decrement signal when the second integrator underflows; and the second integrator. | 05-24-2012 |
20120169397 | Mixed Signal Integrator Incorporating Extended Integration Duration - A mixed-signal integrator, having an analog input and a digital output, is adapted to perform an integration operation partially in the analog domain and partially in the digital domain while eliminating the limitations of a conventional analog integrator. The integrator also digitizes a signal of interest without the use of a conventional sampling operation followed by a conventional analog-to-digital converter. The analog integrator portion generates an analog integration signal limited between low and high rail voltages defined by two comparators with corresponding threshold voltages. When either rail voltage is reached, the polarity of the input signal is reversed to prevent the integration result from exceeding that rail. Each such event is also tracked in digital logic, which provides a count whenever two consecutive such events correspond to the two different rails. At the end of the integration duration this count serves as the digital representation of the integration result. | 07-05-2012 |
20130169340 | CAPACITIVE TOUCH SENSOR INTERFACE - A technique includes charging and discharging a capacitive sensor of a display. The technique includes regulating currents that are associated with the charging and discharging based at least in part on a reference time interval and determining a capacitance sensed by the capacitive sensor based at least in part on the regulating. | 07-04-2013 |
20140125399 | CHARGE MEASUREMENT - An apparatus comprises a comparator that includes a first input, a second input and an output. The comparator is configured for measuring a difference in voltage between a source coupled to the first input and another source coupled to the second input, and providing information associated with the measured difference at the output. The apparatus also comprises a controllable current source coupled to the first input of the comparator and configured for supplying or drawing current. The apparatus also comprises a digital logic circuit that is configured for controlling an amount of current supplied or drawn by the controllable current source. The apparatus is configured for measuring a charge associated with an external source that is coupled to the first input of the comparator. | 05-08-2014 |
20140125400 | Detecting a Periodic Timing Reference in a Received Signal - An apparatus for detecting a periodic timing reference in a received signal comprises a correlator and an integrator. The correlator is configured to correlate the received signal with a template to produce a correlated signal indicating the presence of the periodic timing reference in the received signal. The integrator is configured to produce an accumulated signal by overlaying one or more delayed versions of the accumulated signal onto the correlated signal, and is further configured to delay the accumulated signals by integer multiples L of a period of the periodic timing reference, the integer multiples L being at least two. | 05-08-2014 |
20140240022 | CHARGE MEASUREMENT - An apparatus comprises a comparator that includes a first input, a second input and an output. The comparator is configured for measuring a difference in voltage between a source coupled to the first input and another source coupled to the second input, and providing information associated with the measured difference at the output. The apparatus also comprises a controllable current source coupled to the first input of the comparator and configured for supplying or drawing current. The apparatus also comprises a digital logic circuit that is configured for controlling an amount of current supplied or drawn by the controllable current source. The apparatus is configured for measuring a charge associated with an external source that is coupled to the first input of the comparator. | 08-28-2014 |
20140354343 | ANALOG INTEGRATOR SYSTEM AND METHOD - Systems and methods are disclosed to integrate signals. Some embodiments include an integrator comprising an active input; a passive input; a first integrator having a first integrator input and a first integrator output; a second integrator having a second integrator input and a second integrator output; a first plurality of switches coupled with the first integrator input, the second integrator input, the active input, and the passive input; a second plurality of switches coupled with the first integrator output and the second integrator output; and a controller. The controller may be configured to control the operation of the first plurality of switches to switch the active input between the first integrator input and the second integrator input, and control the operation of the first plurality of switches to switch the passive input between the first integrator input and the second integrator input. | 12-04-2014 |
20150054566 | CONVERSION OF ANALOG SIGNAL INTO MULTIPLE TIME-DOMAIN DATA STREAMS CORRESPONDING TO DIFFERENT PORTIONS OF FREQUENCY SPECTRUM AND RECOMBINATION OF THOSE STREAMS INTO SINGLE TIME-DOMAIN DATA STREAM - An electrical signal is processed by digitizing the electrical signal to produce a stream of digitized data in the time domain, wherein the stream has an original frequency spectrum, transmitting the stream to N signal paths (N>1), and down-converting and filtering the stream in each of the N signal paths to produce N streams of digitized data in the time domain, wherein the N streams have N frequency spectra, respectively, and the N frequency spectra cover N different portions of the original frequency spectrum, respectively. | 02-26-2015 |
20160042203 | CHARGE MEASUREMENT - An apparatus comprises a comparator that includes a first input, a second input and an output. The comparator is configured for measuring a difference in voltage between a source coupled to the first input and another source coupled to the second input, and providing information associated with the measured difference at the output. The apparatus also comprises a controllable current source coupled to the first input of the comparator and configured for supplying or drawing current. The apparatus also comprises a digital logic circuit that is configured for controlling an amount of current supplied or drawn by the controllable current source. The apparatus is configured for measuring a charge associated with an external source that is coupled to the first input of the comparator. | 02-11-2016 |
327337000 | Having switched capacitance | 28 |
20090128216 | SYSTEM AND METHOD FOR TIME-TO-VOLTAGE CONVERSION WITH LOCK-OUT LOGIC - An event time stamping system comprising a current source, an integrator comprising an input and an output, and configured to output a voltage proportional to the length of time the current source is coupled to the input, and one or more switches configured to couple the current source to the input of the integrator upon receipt of an event signal and configured to de-couple the current source from the input of the integrator upon receipt of a control trigger. The system further comprises a lock-out signal generator configured to generate a lock-out signal, and a controller coupled to the one or more switches, wherein the controller is configured to generate the control trigger based on the lock-out signal to ensure a minimum integration time. | 05-21-2009 |
20090167407 | Operational amplifier and integrating circuit - An operational amplifier in accordance with one embodiment of the present invention includes a differential amplifier circuit to perform differential amplification of an input signal with respect to a reference potential Vbias, an output circuit to output a signal amplified by the differential amplifier circuit, a phase compensation capacitance connected between the output of the differential amplifier circuit and the output of the output circuit to compensate the phase of the signal output from the output circuit, and a diode connected in parallel with the phase compensation capacitance. | 07-02-2009 |
20090273386 | APPARATUS FOR CURRENT-TO-VOLTAGE INTEGRATION FOR CURRENT-TO-DIGITAL CONVERTER - Methods and apparatus for improved current-to-voltage integrators reducing charge injection and kT/C errors from capacitor switching and intrinsic operational amplifier noise (i.e., offset, 1/f noise, thermal noise) during the reset cycle of the integrator, simultaneously reducing demands on the reference voltage source, using correlated double sampling to compensate for DC offset and low frequency op-amp noises, and “fake” integration and a capacitor divider to eliminate or significantly reduce kT/C noise and charge injection. | 11-05-2009 |
20090295453 | SIGNAL READING METHOD, SIGNAL READING CIRCUIT, AND IMAGE SENSOR - A signal reading method successively outputs a read signal by scanning a voltage value of an integrating capacitor in an image sensor in which a plurality of sensor parts are arranged in a two-dimensional array made up of rows and columns and each sensor part includes the integrating capacitor accumulating a charge obtained by integrating a photocurrent output from a sensor. A first integration of the photocurrent using the integrating capacitor and a first sampling and holding using a sample and hold capacitor are performed in a first time interval, during a time of one frame made up of the first through third time intervals. A second integration of the photocurrent using the integrating capacitor is performed in the second time interval, and processes in the first and second time intervals are performed in common with respect to all of the sensor parts simultaneously. A vertical scan is started by selecting the row in an order starting from a first row. | 12-03-2009 |
20090309645 | SWITCHED CAPACITOR APPARATUS PROVIDING INTEGRATION OF AN INPUT SIGNAL - An apparatus includes an operational amplifier, a switched capacitor network, an optical sensor, and a clock. The switched capacitor network is coupled to an input terminal of the operational amplifier and coupled to an output terminal of the operational amplifier. The optical sensor includes a sensor output coupled to the switched capacitor network. The clock is coupled to at least one switch of the switched capacitor network. The clock is configured to activate the at least one switch to provide an integrated output at the output terminal corresponding to the sensor output. | 12-17-2009 |
20100019826 | SWITCHED CAPACITOR CIRCUIT CAPABLE OF MINIMIZING CLOCK FEEDTHROUGH EFFECT AND HAVING LOW PHASE NOISE AND METHOD THEREOF - A switched capacitor circuit includes a positive side capacitor coupled to a first positive side node; a first positive side switch element for selectively coupling the first positive side node to a second node according to a first control signal; and a precharge circuit coupled to the first positive side node for precharging the first positive side node to a precharge voltage for a predetermined time when the first positive side switch element is switched off according to the first control signal, and then for charging the first positive side node to a charge voltage until the first positive side switch element is switched on according to the first control signal. By rapidly precharging the first positive side node, the clock feedthrough effect is eliminated and the locking period of the VCO is shortened. Afterwards by charging the first positive side node, the phase noise of the VCO is minimized. | 01-28-2010 |
20100134173 | INTEGRATOR-BASED COMMON-MODE STABILIZATION TECHNIQUE FOR PSEUDO-DIFFERENTIAL SWITCHED-CAPACITOR CIRCUITS - A pseudo-differential switched-capacitor circuit using integrator-based common-mode stabilization technique is disclosed. A pseudo-differential switched-capacitor circuit with the differential floating sampling (DFS) technique has a common-mode gain value of one (1). An integrator is electrically coupled to the differential positive/negative outputs of the DFS circuit, and the integrator feeds back integrator output to the DFS circuit by detecting common-mode voltage disturbance at the differential positive output (V | 06-03-2010 |
20110043270 | LOW POWER AND LOW NOISE SWITCHED CAPACITOR INTEGRATOR WITH FLEXIBLE INPUT COMMON MODE RANGE - An integrator is described that may include a level-shifting capacitor, a feedback capacitor, a pre-amplifier stage and a multi-path amplifier module. The integrator may have inputs for connected an input signal source to the level-shifting capacitor. The level-shifting capacitor is connected to an input of a pre-amplifier stage of an integration signal path and to the input. The level-shifting capacitor may level shift the voltage at the input of the circuit to a lower voltage at the input of the pre-amplifier stage. Thereby, the supply voltage to the pre-amplifier stage may be reduced as well as have limited power consumption, limited temperature rise, and reduced noise that may be attributed to any thermal effects. | 02-24-2011 |
20110175666 | SYSTEM AND A METHOD FOR GENERATING AN ERROR VOLTAGE - The invention allows for the realization of a precision current reference or a fully integrated crystal-less precision oscillator by providing a circuit that precisely controls the cyclic charging operation of a switched capacitor. The voltage across the switched capacitor is ramped up and stops at the end of the charge phase at precisely a desired voltage. By using an appropriate network of switches based around a transconductance amplifier, the error voltage between the desired voltage and the voltage across the switched capacitor is amplified by the transconductance amplifier to give an error current. The error current is integrated over time to give an integrated amplified error voltage. By using appropriate feedback, the error voltage can be minimised to give a precise output current whose value depends on a capacitance, a voltage and a frequency. In a different feedback configuration the circuit described can be used as part of a frequency locked loop to provide a precise crystal-less oscillator whose frequency depends on a resistance and a capacitance. The circuit is insensitive to amplifier offset and bandwidth, switch resistance, duty cycle and non-symmetrical ripple at the input of the amplifier. The circuit also comprises means to compensate for temperature variations and means to compensate for variations in resistance and capacitance commonly occurring in integrated circuits due to process variations. | 07-21-2011 |
20110193611 | SWITCHED CAPACITOR CIRCUIT - A switched capacitor circuit includes: an operational amplifier; a first capacitor; a first switch that charges the first capacitor by connecting the first capacitor between an inverting input terminal and an output terminal of the operational amplifier, and discharges the first capacitor by disconnecting the inverting input terminal and the output terminal of the operational amplifier in a predetermined period; and a first output terminal that outputs an output voltage of the switched capacitor circuit, wherein after a predetermined period from a time when the first switch connects the first capacitor between the inverting input terminal and the output terminal of the operational amplifier, the first output terminal and the output terminal of the operational amplifier are connected to each other. | 08-11-2011 |
20110221503 | SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING CONSTANT ADJUSTING CIRCUIT - A semiconductor integrated circuit includes an integrating circuit comprising a variable resistance, an integration capacitance and an amplifier; a switched capacitor connected with the amplifier in parallel to the variable resistance; and an adjusting circuit configured to adjust a resistance value of the variable resistance. The integrating circuit generates a control signal of a voltage based on a first time constant determined based on the resistance value of the variable resistance and a capacitance value of the integration capacitance, and a second time constant determined based on a capacitance value of the switched capacitor and the capacitance value of the integration capacitance. The adjusting circuit adjusts the resistance value of the variable resistance based on the control signal. | 09-15-2011 |
20110221504 | CONFIGURABLE SWITCHED CAPACITOR BLOCK - A configurable switched capacitor block includes a switched-capacitor (SC) sampling circuit, a fully differential amplifier, an SC feedback circuit, and a comparator. The SC sampling circuit is coupled to receive an input signal and to selectively generate a sampled signal to a differential input of the amplifier. The SC feedback circuit is coupled between the differential inputs and the differential outputs of the amplifier to selectively control a feedback of the amplifier. The comparator is coupled to the differential outputs of the amplifier to generate an output signal. The configurable switched capacitor block has multiple modes of operation which are selectable by programming the SC sampling circuit and the SC feedback circuit. | 09-15-2011 |
20110298520 | INTEGRATOR CIRCUIT WITH MULTIPLE TIME WINDOW FUNCTIONS - An integrator circuit with multiple time window functions for carrying out a plurality of integration operations in parallel, each integration operation being carried out in a coherent manner over a sequence of time windows including at least one such window. The circuit includes a plurality of integration paths each corresponding to an integration operation. The integration paths share a same voltage/current converter and a same first switching mechanism for switching a signal to be integrated at an input of the converter, each integration path further including at least one integration capacitor mounted in counter-reaction to a functional amplifier and receiving a resulting current via a second switching mechanism for selecting the path. | 12-08-2011 |
20120038408 | INTEGRATOR CIRCUIT - An integrator circuit is provided in the present invention, which utilizes a first capacitor and a first switching unit to sample an input signal and carries out distribution of charges between the first capacitor and a second capacitor. The second capacitor is larger than the first capacitor in capacitance. The integrator circuit transmits the charges stored in the second capacitor to a node of the first capacitor which is coupled to a ground previously. Accordingly, a direct current voltage level of the first capacitor may increase, facilitating an increase in a direct current voltage level at the second capacitor. Thereby, the accuracy and linearity of the integrator circuit may improve. | 02-16-2012 |
20120133417 | ANALOG CONVERSION OF PULSE WIDTH MODULATED SIGNALS - A method of converting a periodic pulse width modulated input signal into a voltage output signal wherein the input signal is in an active state for a first portion of each of successive time periods and in an inactive state for a second portion of each time period. A first and second input is supplied to an integrator circuit and a first capacitor is coupled between a first output of the integrator circuit and the first input and a second capacitor is coupled between a second output and the second input of the integrator circuit during a first time period of the pulse width modulated signal. A third capacitor is coupled between a first output of the integrator circuit and the first input and a fourth capacitor is coupled between a second output of the integrator circuit and the second input during a successive second time period of the pulse width modulated signal. Said coupled capacitors are charged during the active state of the first and second time periods and discharged during the inactive state of the first and second time periods. | 05-31-2012 |
20120139609 | Integrator - An integrator ( | 06-07-2012 |
20120139610 | Common Mode Voltage Control - A common mode control circuit ( | 06-07-2012 |
20120200332 | ELECTRICALLY TUNABLE CONTINUOUS-TIME CIRCUIT AND METHOD FOR COMPENSATING A POLYNOMIAL VOLTAGE-DEPENDENT CHARACTERISTIC OF CAPACITANCE - A capacitance compensation circuit includes an input terminal, a plurality of switches coupled to the input terminal, a plurality of varactors coupled to the plurality of switches, and a plurality of blocking capacitors coupled between the plurality of switches and the plurality of varactors. The capacitance compensation circuit further includes a plurality of adjustable biasing circuits to precisely compensate for linear and parabolic voltage dependent components of an input or other capacitor. Two such circuits can be used with a single input terminal to compensate for both increasing and decreasing voltage dependent characteristics of a target capacitor. | 08-09-2012 |
20120218020 | CALIBRATION FOR MIXED-SIGNAL INTEGRATOR ARCHITECTURE - A mixed signal correlator utilizes coherent detection within a capacitance measurement application. In some applications, the mixed signal correlator is used to measure capacitance of a touch screen display. An external capacitor whose capacitance is measured is kept small for improved sensitivity and can be used for a variety of applications having varied integration periods for measurement. The external capacitor is kept small and can be used for varied applications by adjusting the output voltage within a range that is less than the supply voltage, and maintaining a count of the adjustments to later reconstruct an actual output voltage for the integration period. An output is a weighted sum of an analog integrator output and a digital counter output. | 08-30-2012 |
20120293232 | 2-PHASE THRESHOLD DETECTOR BASED CIRCUITS - A switched capacitor circuit includes a threshold detector to generate a threshold detection signal when a difference between first and second input signals crosses a predetermined level. A coarse current source produces a coarse ramp. A series sampling capacitor samples a coarse output voltage when the threshold detector indicates a first threshold crossing. The sampling capacitor is connected in series with a fine current source producing a fine ramp. | 11-22-2012 |
20130106486 | Feedback in Noise Shaping Control Loop | 05-02-2013 |
20130127516 | Offset Cancellation for Sampled-Data Circuits - A comparator based circuit with effective offset cancellation includes first and second amplifiers and an offset capacitor operatively connected to the first and second amplifiers. An offset voltage source generates an offset voltage. A first switch connects the offset voltage source to ground during a first time period. The first amplifier generates an output voltage in response to the first switch connecting the offset voltage source to ground during the first time period. A second switch connects the offset capacitor to ground during a second time period. The first switch disconnects the offset voltage source from ground during a third time period, and the second switch disconnects the offset capacitor from ground during the third time period | 05-23-2013 |
20130257506 | Passive Integrator and Method - In accordance with an embodiment, a passive integrator includes a charge storage element coupled between first and second transistors, wherein the first transistor has a current carrying electrode coupled for receiving a signal and a current carrying electrode coupled to the charge storage element. The second transistor has a current carrying electrode coupled to the charge storage element and a second current carrying electrode coupled to another charge storage element. | 10-03-2013 |
20130300488 | Passive Offset and Overshoot Cancellation for Sampled-Data Circuits - A zero-crossing detector with effective offset cancellation includes a set of series connected capacitors and an amplifier having an input terminal. An offset capacitor is operatively connected between the amplifier and the set of series connected capacitors. A switch is operatively connected to the input terminal, and an offset sampling capacitor is operatively connected to the switch. The switch connects the offset sampling capacitor to the input terminal of the amplifier during a charge transfer phase. | 11-14-2013 |
20130335131 | System and Method for a Switched Capacitor Circuit - In an embodiment, a circuit includes a forward path circuit having an auto-zero switch coupled between an input of an amplifier and an output of the amplifier, a first chopping circuit having an input coupled to an input of the forward path circuit and an output coupled to the input of the amplifier, and a second chopping circuit having an input coupled to the output of the amplifier and an output coupled to an output of the forward path circuit. The circuit further includes a feedback circuit that has a feedback switch, a feedback capacitor including a first end coupled to an output of the amplifier, a third chopping circuit coupled between the input of the forward path circuit and a first end of a feedback switch, and a fourth chopping circuit coupled between a second end of the feedback switch and a second end of the feedback capacitor. | 12-19-2013 |
20140015589 | METHODS, DEVICES, AND SYSTEMS FOR SWITCHED CAPACITOR ARRAY CONTROL TO PROVIDE MONOTONIC CAPACITOR CHANGE DURING TUNING - The present subject matter relates to methods, devices, and systems for switched capacitor array control. For an array of two-state elements that can be independently positioned in either an active state or an inactive state, the methods, devices, and systems can determine a linear number D of elements in the active state needed to achieve a total combined activity corresponding to a desired behavior, compare a number A of elements in an active state to the linear number D of elements needed to achieve the desired behavior, activate a first number n of inactive elements, and deactivate a second number m of active elements, wherein the difference between the first number n and the second number m is equal to the difference between the linear number D of elements needed to achieve the desired behavior and the present number A of elements in an active state. | 01-16-2014 |
20140035653 | CAPACITANCE SENSING DEVICE AND TOUCHSCREEN - There are provided a capacitance sensing device and a touchscreen, the capacitance sensing device including a driving circuit unit allowing a capacitor to be charged and discharged; and an integrating circuit unit integrating charges stored in the capacitor, wherein the integrating circuit unit integrates the charges stored in the capacitor to thereby output a first voltage having a positive polarity and a second voltage having a negative polarity. | 02-06-2014 |
20140375374 | Capacitance to Digital Converter and Method - An integrator circuit includes a switched capacitor bridge including first and second inputs and first and second outputs. The switched capacitor bridge is configured to sample first and second reference voltages twice per unit time interval. The integrator circuit further includes an integrator coupled to the first and second outputs and configured to integrate charge dumped into the first and second outputs twice per unit time interval. | 12-25-2014 |
327339000 | With summing or counting | 5 |
20090231017 | Counter circuit - Reduction in power consumption of a counter circuit for continuous operation is demanded. Therefore, provided is a counter circuit including: a first counter of m bits for counting and storing a value of a predetermined bit width according to an input clock; a clock transmission control circuit for controlling whether to transmit the input clock based on a value output according to a counting result of the first counter; and a second counter of n bits for counting and storing another value of the predetermined bit width according to the input clock transmitted from the clock transmission control circuit. | 09-17-2009 |
20100176866 | Signal Preprocessing Device Comprising Band-Pass Filters For Structure-Borne Noise Sensors - A signal preprocessing device is disclosed, which is integrated into a structure-borne sound sensor or into an acceleration sensor for sensing structure-borne sound, or which is connected at the input end to at least one sensor of this type and is connected at the output end to at least one signal channel that is connected to at least one central electronic control unit, and wherein the signal preprocessing device has at least one filter module having at least two bandpass filters. | 07-15-2010 |
20120139611 | HIGH DYNAMIC RANGE COULOMB COUNTER WHICH SIMULTANEOUSLY MONITORS MULTIPLE SENSE RESISTORS - A circuit may include a source of electrical energy and a plurality of current loads. Each load may be of a different amount. For each current load, a resistance may be in series between the source and the current load. The resistance may be weighted inversely proportional to the amount of the current load with respect to the other resistances. For each resistance, an integrator may generate an integrated output representative of an integration of the current traveling through the resistance. A summer may generate a summed output which is representative of the sum of each of the integrated outputs, weighted inversely proportional to the resistance that is associated with the integrated output. | 06-07-2012 |
20120293233 | Broadband Analog Radio-Frequency Components - Broadband analog radio-frequency devices can be used to create building blocks for scalable analog signal processors that operate over bandwidths of | 11-22-2012 |
20130106487 | WIDEBAND SIGNAL PROCESSING | 05-02-2013 |
327341000 | With compensation | 2 |
20130057331 | AMPLIFICATION SYSTEMS AND METHODS WITH DISTORTION REDUCTIONS - System and method for integrating an input signal to generate an output signal. The system includes a first integrator configured to receive the input signal and generate an integrated signal based on at least information associated with the input signal, a second integrator configured to receive the integrated signal and generate the output signal based on at least information associated with the integrated signal, and a compensation capacitor coupled to the first integrator and the second integrator. The first integrator includes a first integration capacitor and a first operational amplifier including a first input terminal and a first output terminal, the first integration capacitor being coupled between the first input terminal and the first output terminal. The second integrator includes a second integration capacitor and a second operational amplifier including a second input terminal and a second output terminal. | 03-07-2013 |
20150145585 | Sample Rate Converter and Rate Estimator Thereof and Rate Estimation Method Thereof - A sample rate converter receives an input signal with an input sample rate, and generates an output signal with an output sample rate. The sample rate converter includes: a rate estimator, a polynomial interpolation calculation circuit, an up sampling filter, and a down sampling filter. The rate estimator includes: a subtractor, which generates an error signal according to an input clock signal and a second order rate signal; a first order integrator, which generates a first order rate signal according to the error signal; and a second order integrator, which generates the second order rate signal according to the first order rate signal. | 05-28-2015 |
327342000 | With transducer | 1 |
20130335132 | CIRCUIT SHARING TIME DELAY INTEGRATOR - The present invention discloses a circuit sharing time delay integrator structure. The major composing elements of this circuit sharing time delay integrator structure are: a sharing circuit, a first control block, a plurality of second control blocks and a timing set generated by a timing generator circuit. The sharing circuit can be an OP-AMP, an active load, or any of a variety of combinations used in signal accumulation applications. With the implementation of the present invention to applications of signal accumulations, the necessity of an adder circuitry is eliminated, the overall circuitry and hence the total amount of transistors required when producing the integrated circuit is massively reduced, and thus a great cost reduction and better timing and power efficiency can all be thereof achieved. | 12-19-2013 |
327343000 | With rectifier circuit | 1 |
20110193612 | METHODS OF CONTROLLING A SYNCHRONOUS RECTIFIER - Consistent with an example embodiment, there is a method of controlling a synchronous rectifier having an input signal having oscillations therein and a switch which is switchable between an open state and a closed state. The method comprises filtering the input signal to produce a filtered signal, comparing the filtered signal with a reference value, and opening the switch in response to the comparison, in which the filtering is active filtering. | 08-11-2011 |
327344000 | Including RC circuit | 2 |
20080278213 | HIGH OHMIC INTEGRATED RESISTOR WITH IMPROVED LINEARITY - An integrated circuit that includes a resistor module with improved linearity is disclosed. The resistor module includes a diffused resistor body of a first conductivity type; a first terminal and a second terminal, each making direct electrical contact with the diffused resistor body; a doped well of a second conductivity type substantially surrounding the diffused resistor body on all but one major surface of the diffused resistor body, the doped well having contact regions; a first amplifier connected to the first terminal and to one contact region of the doped well; and a second amplifier connected to the second terminal and to another contact region of the well, such that the first amplifier and the second amplifier are connected for power supply only to the first terminal and second terminal, respectively. The first and second amplifiers may be unity gain buffer amplifiers or inverting opamps. | 11-13-2008 |
20090189672 | Pseudo-differential active RC integrator - A pseudo-differential active RC integrator is described. The pseudo-differential active RC integrator includes a common-mode feedback sub-circuit to control the common-mode output signal of the integrator. The common-mode feedback subcircuit may be coupled to one or more virtual ground nodes of the pseudo-differential active RC integrator, and may include one or more transconductors. | 07-30-2009 |
327345000 | Having feedback | 5 |
20100244925 | DEVICE FOR CONTROLLING THE CURRENT THROUGH A PN JUNCTION - Device for controlling the current through a PN junction includes a voltage source connected in series to, in order, firstly a controllable current generator having an input connected to the voltage source, an output and a control input, thereafter a measurement resistor connected to the output, and finally a controlled output to which the PN junction is connected. The device further includes a control signal input, a differential amplifier and an integrating device, which includes a balanced integrator. The current through the output of the controllable current generator is proportional to the voltage difference between its input and its control input, and the reference voltage of the integrating device is constituted of the voltage of the voltage source. | 09-30-2010 |
20110068848 | MULTI-CHANNEL INTEGRATOR - A multi-channel integrator is provided. The multi-channel integrator includes an integrator and a plurality of channels. Each of the channels includes an input selector and a unit-gain amplifier. The input selector has a common terminal, a first selecting terminal and a second selecting terminal. The input selector selectively electrically connects the common terminal to the first selecting terminal or to the second selecting terminal. The first selecting terminal of the input selector is coupled to an input terminal of the integrator. An input terminal of the unit-gain amplifier is coupled to the second selecting terminal of the input selector. | 03-24-2011 |
20110187436 | INTEGRATION CIRCUIT - An integration circuit includes a first differential amplifier that reduces an input offset, which is an offset of a threshold voltage of a transistor that composes a differential pair, using a first clock signal as a clock signal for chopping, a first and a second input terminals that are connected to an inverting input terminal and a noninverting input terminal of the first differential amplifier circuit, and a first capacitance that is connected between the inverting input terminal of the first differential amplifier circuit and an output terminal of the first differential amplifier circuit. The integration circuit changes a frequency of the first clock signal input to the first differential amplifier circuit according to a potential difference between the first and the second input terminals. | 08-04-2011 |
20110227627 | PULSE WIDTH MODULATOR WITH TWO-WAY INTEGRATOR - An example two-way integrator includes a first current source, a second current source, a first offset current source, a second offset current source, a capacitor, a switching reference and a comparator. The capacitor integrates a sum of a first input current and a first offset current by charging with both the first current source and the first offset current source. The capacitor subsequently integrates a sum of the second input current and the second offset current by discharging with both the second current source and the second offset current source. The switching reference outputs a first reference voltage and a second reference voltage responsive to pulses of a pulse signal. The comparator is coupled to compare the switching reference with a voltage on the capacitor. | 09-22-2011 |
20120139612 | INTEGRATOR INPUT ERROR CORRECTION CIRCUIT AND CIRCUIT METHOD - A circuit includes a first amplifier and a second amplifier, wherein first amplifier is configured to receive an input current at a first input of the first amplifier, and an output of the first op-mp is configured to drive a first input of the second amplifier. The circuit further includes a pull-up current source selectively coupled to the first input of the second amplifier, and a pull-down current source selectively coupled to the first input of the second amplifier. If the absolute value of the input current is larger than a predefined threshold current: i) the pull-up current source is configured to drive current into the first input of the second amplifier for a first polarity of the input current, and ii) the pull-down current source is configured to sink current from the first input of the second amplifier for a second polarity of the input current. | 06-07-2012 |