Class / Patent application number | Description | Number of patent applications / Date published |
327233000 | Correction to specific phase shift | 19 |
20090167397 | Delay device for adjusting phase SMIA standard - A delay device for adjusting phase under a SMIA (Standard Mobile Imaging Architecture) standard is provided. More particularly, the delay device is used to adjust a phase of a clock signal, which carries data, under the SMIA standard. The delay device includes plural delay cells, which are disposed on a circuit board by means of APR (Automated Placement and Routing) method, and one or more delay multiplexers (MUX) connected with the delay cells. Through selective pins controlling the route selection in the delay multiplexer, the delay device can produce plural delay times to adjust the phase relationship between data and clock, as supposed to using PLL. | 07-02-2009 |
20100079185 | METHOD AND AN APPARATUS FOR PROCESSING A SIGNAL - A method of processing a signal is disclosed. The present invention includes receiving (a) downmix signal being generated from plural-channel signal and (b) spatial information indicating attribute of the plural-channel signal in order to upmix the downmix signal and including phase shift flag indicating whether phase of a frame of at least one channel of the plural-channel signal is shifted; obtaining inter-channel phase difference (IPD) coding flag indicating whether IPD value is used to the spatial information from a header of the spatial information; obtaining IPD mode flag indicating whether the IPD value is used to frame of the spatial information from the frame based on the IPD coding flag; obtaining the IPD value of parameter band in the frame, based on the IPD mode flag; upmixing plural-channel signal by applying the IPD value to the downmix signal; and shifting the phase of the frame of the at least one channel of the plural-channel signal based on the phase shift flag. | 04-01-2010 |
20110012659 | SIGNAL GENERATION APPARATUS AND TEST APPARATUS - Provided is a signal generating apparatus that generates an output signal having a designated phase, comprising a phase difference detecting section that outputs a control signal corresponding to a phase difference between a reference signal having a prescribed period and the output signal; an oscillating section that generates a periodic signal having a frequency corresponding to the control signal; and a phase shifting section that outputs the output signal to have a phase that is shifted from the phase of the periodic signal by a designated phase amount. | 01-20-2011 |
20110012660 | CLOCK CIRCUIT WITH DELAY FUNCTIONS AND RELATED METHOD - A clock circuit with delay functions includes a first clock tree and a delay module. The first clock tree provides a first clock signal and includes a first clock root and a plurality of first sub-trees. The delay module is coupled to the first clock root or a designated sub-tree among the plurality of first sub-trees for delaying the first clock signal. The delay module includes at least two delay segments, wherein each delay segment includes a delay and a connection net. The delay time caused by each delay segment is substantially the same. | 01-20-2011 |
20110163790 | SIGNAL PROCESSING CIRCUIT AND SIGNAL PROCESSING METHOD - A signal processing circuit includes: a phase modulating path arranged to adjust a phase component of an input signal to generate an adjusted phase component such that a phase difference of the input signal falls within a target phase difference range; and an amplitude modulating path arranged to exchange a sign of an amplitude component of the input signal corresponding to the phase component to generate an adjusted amplitude component when the phase modulating path adjusts the phase component. | 07-07-2011 |
20110181332 | RING OSCILLATOR FOR GENERATING OSCILLATING CLOCK SIGNAL - A ring oscillator including a plurality of buffer units, each of which has a cross-coupled structure, for generating clock signals using a bias voltage having a predetermined voltage level applied thereto, wherein the clock signals have a swing width corresponding to the bias voltage. | 07-28-2011 |
20120187994 | SYSTEM FOR I-Q PHASE MISMATCH DETECTION AND CORRECTION - System for I-Q phase mismatch detection and correction. An apparatus to correct a phase mismatch between I and Q signals includes a correction circuit configured to continuously compare a reference signal and a phase error signal associated with the I and Q signals to generate an I bias signal and a Q bias signal, a first CMOS buffer configured to receive the I signal and the I bias signal and output a phase adjusted I signal based on the I bias signal, and a second CMOS buffer configured to receive the Q signal and the Q bias signal and output a phase adjusted Q signal based on the Q bias signal. | 07-26-2012 |
20120187995 | ERROR AMPLIFICATION CIRCUIT, CONTROL METHOD FOR ERROR AMPLIFICATION CIRCUIT, AND SWITCHING REGULATOR EMPLOYING ERROR AMPLIFICATION CIRCUIT - An error amplification circuit includes an integrated circuit and a phase compensation capacitor. The integrated circuit includes an error amplifier to amplify a difference between a predetermined reference voltage and an input feedback voltage for output; a current generator circuit to generate a bias current for supply to the error amplifier; a phase compensation resistor; a bias-current control terminal; and a phase compensation terminal connected to an output terminal of the error amplifier via the phase compensation resistor. The phase compensation capacitor is connected to the phase compensation terminal, the phase compensation capacitor being provided outside the integrated circuit. | 07-26-2012 |
20130135022 | Vector Generator Using Octant Symmetry - In various embodiments, an active vector generator may comprise a vector component switch and a first amplitude adjustment component in parallel with a second amplitude adjustment component. The first and second amplitude adjustment components may operate with different ranges of amplitude. For example, the first amplitude adjustment component may have a full range of amplitude and the second amplitude adjustment component may have a partial range of amplitude. The vector component switch may operate to receive two signals and route the signals to the various amplitude adjustment components based on the relative magnitudes of the two signals. A benefit of having two amplitude adjustment components with selectable signal pathways is that the all the phase states may be obtained but using less robust and expensive amplitude adjustment components. | 05-30-2013 |
20140191789 | Vector Generator Using Octant Symmetry - In various embodiments, an active vector generator may comprise a vector component switch and a first amplitude adjustment component in parallel with a second amplitude adjustment component. The first and second amplitude adjustment components may operate with different ranges of amplitude. For example, the first amplitude adjustment component may have a full range of amplitude and the second amplitude adjustment component may have a partial range of amplitude. The vector component switch may operate to receive two signals and route the signals to the various amplitude adjustment components based on the relative magnitudes of the two signals. A benefit of having two amplitude adjustment components with selectable signal pathways is that the all the phase states may be obtained but using less robust and expensive amplitude adjustment components. | 07-10-2014 |
20160191034 | METHOD, APPARATUS, SYSTEM FOR CENTERING IN A HIGH PERFORMANCE INTERCONNECT - In an example, a system and method for centering in a high-performance interconnect (HPI) are disclosed. When an interconnect is powered up from a dormant state, it may be necessary to “center” the clock signal to ensure that data are read at the correct time. A multi-phase method may be used, in which a first phase comprises a reference voltage sweep to identify an optimal reference voltage. A second phase comprises a phase sweep to identify an optimal phase. A third sweep comprises a two-dimensional “eye” phase, in which a plurality of values within a two-dimensional eye derived from the first two sweeps are tested. In each case, the optimal value is the value that results in the fewest bit error across multiple lanes. In one example, the second and third phases are performed in software, and may include testing a “victim” lane, with adjacent “aggressor” lanes having a complementary bit pattern. | 06-30-2016 |
327234000 | Dependent on variable controlled phase shifts | 3 |
20110043266 | APPARATUS AND METHOD FOR CALIBRATING A VARIABLE PHASE SHIFTER - A reference signal is split and input to first and second variable phase shifters | 02-24-2011 |
20110109365 | DELAY LOCKED LOOP CIRCUIT - The disclosure relates to phase detectors. Charge up and charge down signals that are generated by a phase detector cause i) following detection of a first edge of a reference clock signal, switching on of a switching transistor of sink current; ii) following detection of an edge of a feedback clock signal falling within less than 180 degrees from the first edge, switching on of a switching transistor of source current and switching off of the switching transistor of sink current; and iii) following detection of an edge of another reference signal at a point in time about midway between the first edge and a next similar edge of the reference clock signal has past, switching off of the switching transistor of source current while maintaining the switching transistor of sink current switched off. | 05-12-2011 |
20160036425 | BUFFER CONTROL CIRCUIT AND MULTI-CHIP PACKAGE INCLUDING THE SAME - A buffer control circuit includes: an activation control block suitable for generating a buffer activation control signal by detecting a first input of a repeatedly provided chip select signal; and a buffer suitable for buffering the chip select signal in response to the buffer activation control signal after the generation of the buffer activation control signal. | 02-04-2016 |
327236000 | By phase comparator or detector | 5 |
20110156789 | CONTROL SYSTEM FOR A PHASE GENERATOR AND CORRESPONDING CONTROL METHOD - A control system for a phase generator including a delay block including delay units, and first and second multiplexers configured to receive output signals of each of the delay units and to respectively supply first and second output signals. The control system may include a controller configured to drive the first multiplexer and the second multiplexer respectively with a first select signal and a second select signal, a detection module configured to detect a phase difference between the first output signal and the second output signal and to generate a corresponding digital phase shift signal, the detection module including a phase comparator, and a Time-Digital converter circuit coupled thereto and having logic elements configured to generate the digital phase shift signal, and a logic circuit connected to the detection module and configured to process the digital phase shift signal and to generate a signal indicative of a control executed. | 06-30-2011 |
20130009686 | Methods and Apparatus for Transmission of Data - A system includes a transmitter circuit and a receiver circuit that are coupled together through transmission lines. The transmitter circuit generates an early timing signal, a nominal timing signal, and a late timing signal. A multiplexer circuit selects between the early and the late timing signals based on a data signal to generate an encoded output signal that encodes the data signal. The nominal timing signal and the encoded output signal are transmitted through the transmission lines to the receiver circuit. The receiver circuit samples the encoded output signal in response to the nominal timing signal to generate even and odd sampled data signals. Complementary timing signals can be transmitted through transmission lines on opposite sides of the encoded output signal to provide crosstalk cancellation. | 01-10-2013 |
20150042391 | Calibration Circuit and Method - A circuit comprises a phase combiner and four output ports. The phase combiner adds an in-phase positive input and a quadrature positive input to obtain an in-phase positive output, adds an in-phase negative input and a quadrature negative input to obtain an in-phase negative output, adds the in-phase negative input and the quadrature positive input to obtain a quadrature positive output, and adds the in-phase positive input and the quadrature negative input to obtain a quadrature negative output. The four output ports, are respectively configured to output the in-phase positive output, the in-phase negative output, the quadrature positive output, and the quadrature negative output. | 02-12-2015 |
20160043703 | CIRCUIT FOR DETECTING PHASE SHIFT APPLIED TO AN RF SIGNAL - An RF circuit and method for detecting the amount of phase shift applied to an RF signal. An RF heating apparatus including the RF circuit. The RF circuit includes a phase shifter operable to apply a phase shift to a reference signal to produce a phase shifted reference signal. The RF circuit also includes a phase detector operable to detect a phase difference between the phase shifted RF signal and the phase shifted reference signal. The phase detector has a reduced input range at a frequency of the phase shifted RF signal. The RF circuit further includes a controller operable to control the phase shifter to set the phase of the phase shifted reference signal so that the phase difference between the phase shifted RF signal and the phase shifted reference signal falls within the reduced input range of the phase detector. | 02-11-2016 |
20160072495 | PHASE ADJUSTMENT DEVICE, PHASE DIFFERENCE DETECTING DEVICE AND PHASE-ADJUSTING METHOD - A phase adjustment device includes: a detection signal generator configured to generate a pair of first and second detection signals for detecting a phase difference between two signals whose phases have been adjusted by two phase adjusters, respectively, a maximum sensitivity phase difference of one of the first and second detection signals being not overlap with that of the other, and detection sensitivity of the phase difference becoming maximum at the maximum sensitivity phase difference; a detection signal selector configured to select one of the first and second detection signals whose predetermined range around the maximum sensitivity phase difference covers a preset phase difference; and a phase controller configured to control an amount of phase-adjusting by at least one of the two phase adjusters based on a difference between the phase difference detected within the predetermined range using the selected detection signal and the preset phase difference. | 03-10-2016 |