Class / Patent application number | Description | Number of patent applications / Date published |
327176000 | Having digital device (e.g., logic gate, flip-flop, etc.) | 25 |
20090108895 | Latch Structure and Self-Adjusting Pulse Generator Using the Latch - The disclosure includes a latch structure and self-adjusting pulse generator using the latch. In an embodiment, the system includes a first latch and a pulse generator coupled to provide a timing signal to the first latch. The pulse generator includes a second latch that has characteristics matching the first latch. | 04-30-2009 |
20090140786 | PULSE WIDTH MODULATION CIRCUIT AND SWITCHING AMPLIFIER USING THE SAME - A pulse width modulation circuit includes a first electric-charge accumulator; a second electric-charge accumulator; a first current generator which generates a first current corresponding to the amplitude of an input AC voltage; a second current generator which generates a second current with a constant value; a first current supply controller which supplies the first current to the first electric-charge accumulator; a second current supply controller which supplies the second current to the first electric-charge accumulator; a third current supply controller which supplies the first current to the second electric-charge accumulator; a fourth current supply controller which supplies the second current to the second electric-charge accumulator; and a current limiter which limits the first current to a third current with a predetermined current value, if the amplitude of the AC voltage in the negative side exceeds a predetermined level. | 06-04-2009 |
20090167393 | POWER CONVERSION CONTROL CIRCUIT, POWER CONVERSION CONTROL LSI, DIFFERENTIAL DETECTION CIRCUIT, AND PULSE WIDTH CONTROL SIGNAL GENERATION CIRCUIT - The control accuracy equal with the case controlled according to a reference signal with a high clock frequency when the electric power is converted is obtained according to a reference signal with a low clock frequency. | 07-02-2009 |
20090206902 | METHOD FOR PROVIDING POWER FACTOR CORRECTION INCLUDING SYNCHRONIZED CURRENT SENSING AND PWM GENERATION - A method for providing power factor correction for a boost converter in accordance with an embodiment of the present application includes providing a current sense signal indicative of a current flowing through an inductor of the boost converter, sampling the current sense signal to provide a digital current sense signal, generating a pulse width modulated output signal to control an on time of a PFC switch of the boost converter based on the digital current sense signal, generating a first synchronous signal based on a carrier frequency of a triangular carrier wave used to generate the pulse width modulated output signal, wherein the first synchronous signal triggers generation of the pulse width modulated output signal and generating a second synchronous signal based on the first synchronous signal, wherein the second synchronous signal indicates a sampling rate to be used in sampling the current sense signal to provide the digital current sense signal, such that sampling takes place substantially in a middle of a cycle of the pulse width modulated output signal. | 08-20-2009 |
20090278582 | Circuit for controlling pulse width of auto-refresh signal and circuit for generating internal row address for auto refress - A circuit for controlling a pulse width of a refresh signal is provided. The circuit includes a first pulse width controller for receiving a first refresh signal having a first enable period, and generating a second refresh signal having a second refresh signal, and a second pulse width controller for receiving the second refresh signal, and generating a third refresh signal having a third enable period. | 11-12-2009 |
20100007394 | METHOD AND APPARATUS OF PROVIDING A BIASED CURRENT LIMIT FOR LIMITING MAXIMUM OUTPUT POWER OF POWER CONVERTERS - A biased current-limit circuit for limiting a maximum output power of a power converter includes an oscillator for generating a pulse signal. A waveform generator generates a waveform signal in response to a switching signal and a second-sampling signal. A sample-hold circuit is used to sample the waveform signal to generate a hold signal in response to a first-sampling signal. The sample-hold circuit further samples the hold signal to generate a current-limit threshold in response to the second-sampling signal. A current comparator is utilized to compare a current-sensing signal with the current-limit threshold to limit a maximum on-time of the switching signal. | 01-14-2010 |
20100090739 | Method and Apparatus for Removing Narrow Pulses from a Clock Waveform - A method and a device for controlling and removing narrow pulses in a clock waveform using a delay function are disclosed. A circuit device includes three circuits wherein the first circuit is capable of generating an edge trigger signal in response to a waveform of an input signal and a waveform of an output signal. While the second circuit facilitates removing a narrow pulse from the waveform of the input signal, the third circuit is capable of generating a delayed output waveform having pulses greater than a predefined minimal pulse width. In one embodiment, the first, second, and third circuits are an exclusive OR gate, a delay circuit, and a D flip-flop, respectively. | 04-15-2010 |
20100097113 | PULSE GENERATING CIRCUIT AND PULSE WIDTH MODULATOR - A pulse generating unit receives a clock at a predetermined frequency, and generates a pulse signal which transits synchronously with the positive edge of the clock. A flip-flop acquires the pulse signal every time a positive edge occurs in an inverted clock output from the inverter. A logic gate multiplexes the pulse signal and the output of the flip-flop. A selector selects either the output of the logic gate or the pulse signal. | 04-22-2010 |
20100097114 | PULSE WIDTH MODULATION CIRCUIT AND LIQUID JET PRINTING APPARATUS - A pulse width modulation circuit includes: a reference signal generator which generates a plurality of mutually differing reference signals; a comparator which compares the reference signals and an input signal with respect to magnitude, and outputs results of the comparison as a plurality of comparison signals with mutually differing phases; and a synthesizer which, using a logical operation, outputs the plurality of comparison signals output from the comparator as a pulse width modulated signal configured of one or more binary signals. | 04-22-2010 |
20100156493 | Circuit device to produce an output signal including dither - In a particular embodiment, a circuit device includes a count zero circuit having a first counter to receive a clock signal and to produce a count zero signal based on the clock signal and having a second counter to generate a reset control signal to control a reset of the count zero circuit. The circuit device further includes a turnoff circuit to receive the clock signal and to produce a turn off signal based on the clock signal. Further, the circuit device includes a pulse width modulated (PWM) latch circuit adapted to produce a gate drive signal based on the count zero signal and the turn off signal, where timing of an edge of the gate drive signal varies based on the reset control signal. | 06-24-2010 |
20100237920 | PEAK MAGNETIC FLUX REGULATION METHOD, APPARATUS, AND SYSTEM USING SAME - The present invention discloses a peak magnetic flux regulation method for a power conversion via magnetic flux transformation through an inductive component, comprising the steps of: generating an adaptive reference voltage according to voltage comparison of a current sensing voltage and an expected peak voltage; and generating a PWM signal according to voltage comparison of said current sensing voltage and said adaptive reference voltage. Furthermore, the present invention also provides a peak magnetic flux regulation apparatus for a power conversion, and a system using the peak magnetic flux regulation apparatus for a power conversion. | 09-23-2010 |
20100289548 | Frequency Generator for Generating Signals with Variable Frequencies - A frequency generator for generating signals with variable frequency includes a periodic signal generator for generating a periodic signal according to an output signal of the frequency generator, a first comparator for comparing the periodic signal and a first reference signal to output a first comparison result, a second comparator for comparing the periodic signal and a second reference signal to output a second comparison result, a logic unit for generating the output signal according to the first comparison result and the second comparison result, and a waveform generator for generating the first reference signal and the second reference signal according to a predetermined frequency variation trend to modulate a output frequency of the output signal. | 11-18-2010 |
20100321078 | TIMING CONTROLLER, TIMING CONTROL METHOD, AND TIMING CONTROL SYSTEM - A timing controller includes a controller that controls an operation timing of a controlled unit, and a setting unit that associates a timing obtained by dividing a setting of the operation timing into a plurality of timings, each timing having an identification number, and sets the control unit so that an offset period based on the associated timing is added to the operation timing of the controlled unit. | 12-23-2010 |
20110084747 | VOLTAGE CONVERTING CIRCUIT AND METHOD - A voltage converting circuit for converting an input voltage into an output voltage is disclosed. The voltage converting circuit includes a modulation signal generator, a comparator and a logic unit. The modulation signal generator is configured for generating a pulse width modulation (PWM) signal responsive to a feedback signal corresponding to the output voltage and a load coupled thereto. The comparator is configured for comparing the feedback signal with a reference signal to output a comparing signal. The logic unit is configured for performing a logical conjunction of the PWM signal and the comparing signal to generate a control signal for adjusting an input current corresponding to the input voltage to regulate the output voltage. A method for converting an input voltage into an output voltage is also disclosed herein. | 04-14-2011 |
20110102041 | METHOD AND DEVICE FOR GENERATING PWM SIGNALS - A PWM signal for driving power transistors of a half-bridge of a converter is generated with the aid of a digital circuit, in which an internal reference value is compared to the counter content of a counting ramp. In this context, a logic state of the PWM signal depends upon whether the internal reference value is greater than the counter content of the counting ramp. After each comparison between the internal reference value and the counter content, an n-bit long data word dependent on the result of this comparison is output serially as PWM signal, n being greater than or equal to 2. The resolution of the PWM signal is thereby improved by the factor n in comparison to conventional systems, without markedly increasing the circuit expenditure. | 05-05-2011 |
20110181329 | SEMICONDUCTOR DEVICE AND PULSE WIDTH DETECTION METHOD - An internal pulse waveform shaping circuit provided to an IC chip generates an internal pulse monitor signal that changes in a predetermined direction at a rise timing of an internal pulse signal during a period in which a first enable signal is asserted and a second enable signal is de-asserted and then continues in the changed state for a predetermined period of time or longer, and generates the internal pulse monitor signal that changes in the predetermined direction at a fall timing of the pulse signal during a period in which the first enable signal is de-asserted and the second enable signal is asserted and then continues in the changed state for the predetermined period of time or longer. The generated internal pulse monitor signal is output to a tester for detecting the pulse width of the internal pulse signal. | 07-28-2011 |
20110285442 | PULSE CONVERTER CIRCUIT - A pulse converter circuit includes a logic circuit to which a first signal is input and from which a second signal is output. The logic circuit includes a p-channel transistor which determines whether a voltage of the second signal is set to a first voltage depending on a voltage of the gate; and an n-channel transistor which determines whether the voltage of the second signal is set to a second voltage, which is higher than the first voltage, depending on a voltage of the gate. The p-channel transistor includes a semiconductor layer containing an element of a group 14. The n-channel transistor includes an oxide semiconductor layer. | 11-24-2011 |
20110298514 | PWM SIGNAL GENERATOR FOR DIGITAL CONTROLLED POWER SUPPLY - A forward converter circuit includes a transformer having a primary winding and a secondary winding. A first transistor is coupled in series with the primary winding and a second transistor is coupled in series with the secondary winding. A control circuit generates PWM control signals for controlling operation of the first and second transistors. The control signals are generated responsive to source PWM signals processed through programmable delay timers to generate set/reset control signals which set an output PWM control signal duty cycle. | 12-08-2011 |
20120112812 | CLOCK GENERATOR, PULSE GENERATOR UTILIZING THE CLOCK GENERATOR, AND METHODS THEREOF - Disclosed is a clock generator for generating a target clock signal, which includes: a control circuit, receiving a reference clock signal, and for generating a clock enable signal and a delay selecting signal according to the reference clock signal; a delay module, coupled to the control circuit, for delaying the reference clock signal according to the delay selecting signal to generate a delayed reference clock signal; and a clock gating unit, coupled to the delay module and the control circuit, for receiving the delayed reference clock signal and the clock enable signal, and for passing the delayed reference clock signal according to the clock enable signal, to generate the target clock signal. | 05-10-2012 |
20120235722 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit according to an embodiment includes a clock signal generation section, a clock waveform shaping section and a plurality of function blocks. The clock signal generation section generates a clock signal of a predetermined frequency. The clock waveform shaping section generates a plurality of clock signals having the same phase as a phase of the clock signal generated by the clock signal generation section at rising edges and different phases at falling edges. Each of the plurality of function blocks has a plurality of flip flops that operate with any one of the plurality of clock signals generated by the clock waveform shaping section. | 09-20-2012 |
20130113537 | PULSE GENERATOR - A circuit includes a logic gate and a latch. The logic gate is configured to receive a clock signal at a first input. The latch is disposed in a feedback loop of the logic gate and is configured to output a feedback signal to a second input of the logic gate in response to a signal output by the logic gate and the clock signal. The circuit is configured to output a pulsed signal based on one of a rising edge or a falling edge of the clock signal. | 05-09-2013 |
20130141150 | METHOD FOR GENERATING A MULTIPHASE PWM SIGNAL - A method and a circuit configuration are provided for generating a multiphase PWM signal. For this purpose a number of PWM generators are provided, which respectively have one counter, two comparators and one state memory, each PWM generator outputting a PWM signal, which represents a phase of the multiphase PWM signal, the PWM generators being coupled with one another via multiplexers such that the counters of the PWM generators that are coupled with one another are clocked identically. | 06-06-2013 |
20130249615 | DIGITAL SENSING APPARATUS AND DIGITAL READOUT MODULE THEREOF - A digital sensing apparatus includes a sensing unit capable of providing a sensing response associated with an environmental parameter, and a digital readout module including a reading unit for generating a pulse signal having a pulse width as sociated with the sensing response, and a converting unit. The converting unit includes a clock signal generator for generating a variable-frequency clock signal, and a counter operable to count a width value of the pulse width of the pulse signal using the clock signal, so as to generate a digital sensing code. The frequency of the clock signal from the clock signal generator is adjustable to adjust resolution of the width value of the pulse width of the pulse signal. | 09-26-2013 |
20140015581 | DATA INTERFACE CLOCK GENERATION - In one embodiment, an apparatus may include a clock generator to generate a format clock signal. The apparatus may also include a serializer to generate serial data based on a transmit clock signal and parallel input data. The apparatus may also include a signal generator to generate at least two differential signals based on the format clock signal and the serial data. | 01-16-2014 |
20140084980 | MEMORY ARRAY PULSE WIDTH CONTROL - A clock system includes a local clock buffer adapted to receive a variable global clock signal. The local clock buffer produces a first local clock signal from the variable global clock signal. The clock system includes a pulse width logic control circuit in operable communication with the local clock buffer. The pulse width logic control circuit may be adapted to limit the first local clock signal pulse width to be less than the variable global clock signal pulse width during a slow mode. The pulse width logic control circuit may be adapted to expand the first local clock signal pulse width to be greater than the variable global clock signal pulse width during a fast mode. The limited and expanded first local clock signals may signal a local evaluation circuit to address a memory line. | 03-27-2014 |