Class / Patent application number | Description | Number of patent applications / Date published |
327107000 | Having digital device (e.g., logic gate, flip-flop, etc.) | 46 |
20080297207 | DOUBLE DATA RATE TRANSMITTER AND CLOCK CONVERTER CIRCUIT THEREOF - A double data rate (DDR) transmitter and a clock converter circuit are provided. The clock converter circuit includes a first logic circuit and a second logic circuit. The first logic circuit receives a clock signal as a trigger signal, performs a sequential logic operation based on the clock signal, and outputs a result of the sequential logic operation. The second logic circuit is coupled to the first logic circuit. The second logic circuit performs a combinational logic operation based on the output of the first logic circuit and outputs a result of the combinational logic operation as a converted signal. The converted signal has the same waveform and frequency as those of the clock signal, and the phases of the clock signal and the converted signal are the same or only slightly different. | 12-04-2008 |
20080297208 | PROCESS FOR DITHERING A TIME TO DIGITAL CONVERTER AND CIRCUITS FOR PERFORMING SAID PROCESS - A process inserts a random noise in a Time to Digital Converter (TDC) designed for calculating the phase error between a first high frequency signal F | 12-04-2008 |
20080303557 | CIRCUITS FOR FORMING THE INPUTS OF A LATCH - Circuits for forming the inputs of a latch are provided. In some embodiments, circuits for forming inputs of a latch comprise: a first transistor having a first gate terminal, a first drain terminal, a first source terminal, a first gate length, and a first common mode level at the first gate terminal, wherein the first gate terminal provides a data input to the latch; and a second transistor having a second gate terminal, a second drain terminal, a second source terminal, a second gate length, and a second common mode level at the second gate terminal, wherein the second gate terminal provides a clock input to the latch, the second drain terminal is coupled to the first source terminal, and the first gate length and the second gate length are sized so that the first common model level and the second common mode level are substantially equal. | 12-11-2008 |
20090021285 | HIGH PERFORMANCE MIXED SIGNAL CIRCUIT - The present invention is related to a digital circuit for use in a mixed-signal circuit. The digital circuit comprises:
| 01-22-2009 |
20090033376 | Locked loop circuit - A circuit for receiving an input signal having a first frequency and generating an output signal having a second frequency. The circuit comprises a forward branch for receiving the input signal and generating the output signal and a return branch for generating a feedback signal from the output signal. The forward branch comprises a frequency detector for receiving the input signal and the feedback signal and outputting a value based on a ratio of a frequency of the feedback signal to the first frequency; a word length reduction block for receiving a fractional component of a first division factor and generating a modulated output; an adder for forming a sum of an integer component of the first division factor and the modulated output of the word length reduction block; a subtracting element for subtracting the output value of the frequency detector from the sum; and an oscillator controlled by an output from the subtracting element. | 02-05-2009 |
20090108883 | Digital sine wave generator - In accordance with described exemplary embodiments, correction is inserted into the feedback loop of a second order resonator used at the time of frequency transition. The correction is based upon parameters generated from a desired output signal frequency and a desired sampling frequency. The correction is generated to maintain i) constant amplitude, ii) continuous phase, and iii) the same sampling frequency during the frequency transition. | 04-30-2009 |
20090128198 | DIGITAL FREQUENCY SYNTHESIZER - A digital frequency synthesizer receiving a first signal corresponding to a periodic sequence of first pulses at a first frequency and providing a second signal corresponding to a periodic sequence of second pulses at a second frequency. The synthesizer includes a first circuit clocked by a third signal corresponding to a sequence of third pulses and obtained from the first signal, the first circuit providing a fourth digital signal which, for any set of third successive pulses, increases (decreases) on each pulse and decreases (increases) at the end of said set; and a second circuit receiving the first and fourth signals and providing, for each first pulse from among some at least of the first pulses, a second pulse which is shifted with respect to the first pulse by a duration which depends on the fourth signal. | 05-21-2009 |
20090284286 | Alias-locked loop frequency synthesizer using a regenerative sampling latch - A frequency synthesis phase-locked loop architecture using a regenerative sampling latch is described. The frequency divider typically employed in the feedback path of a frequency synthesis phase-locked loop is replaced by a regenerative sampling latch with a binary output. The regenerative sampling latch subsamples the frequency synthesizer output to produce a low-frequency aliased signal that can be processed further or directly used to lock the phase-locked loop. This architecture is referred to as an alias-locked loop. The relaxed constraints on the regenerative sampling latch make it possible to create high-speed frequency synthesizer phase-locked loops without the suffering the limitations imposed by traditional dividers connected directly to the oscillator output. | 11-19-2009 |
20090295435 | METHOD AND APPARATUS FOR REDUCING SPURS IN A FRACTIONAL-N SYNTHESIZER - A method and apparatus for reducing in-band spurs in a fractional-N synthesizer ( | 12-03-2009 |
20100052736 | SIGNAL GENERATING APPARATUS, TEST APPARATUS AND CIRCUIT DEVICE - There is provided a signal generating apparatus for generating an output signal corresponding to pattern data supplied thereto. The signal generating apparatus includes a timing generating section that generates a periodic signal, a shift register section including a plurality of flip-flops in a cascade arrangement through which each piece of data of the pattern data is propagated sequentially in response to the periodic signal, a waveform generating section that generates the output signal whose value varies in accordance with a cycle of the periodic signal, based on data values output from the plurality of flip-flops, and an analog circuit that enhances a predetermined frequency component in a waveform of the output signal generated by the waveform generating section. | 03-04-2010 |
20100066416 | DIGITALLY-CONTROLLED OSCILLATOR, FREQUENCY SYNTHESIZER AND RADIO COMMUNICATION DEVICE - A frequency synthesizer includes a digitally-controlled oscillator and an oscillation frequency control unit. The digitally-controlled oscillator includes a loop-shaped transmission line path having an odd number of parallel portions in each of which two conductors are arranged in parallel to each other with a space therebetween, and an odd number of intersection portions in each of which two conductors intersect spatially, an active circuit coupled between the two conductors, and a first variable capacitance unit and a second variable capacitance unit. The oscillation frequency control unit includes a ΣΔ modulation circuit for subjecting to ΣΔ modulation a first control signal for switching a high capacitance state and a low capacitance state of a first variable capacitance element included in the first variable capacitance unit. | 03-18-2010 |
20100066417 | HIGH-FREQUENCY COUNTER - The present invention relates to a counter circuit and method of controlling such a counter circuit, wherein a first counting section counts in accordance with a state-cycle, and a second counting section is clocked by the first counting section. At least one invalid counting state is introduced by controlling the second counting section to change its state before the first counting section has completed the state-cycle; and the at least one invalid counting state is then detected and corrected. Thereby, some redundancy is introduced in the counter, which can be used to detect and correct incomplete switching of counter states. | 03-18-2010 |
20100109715 | Method For Use in a Digital Frequency Synthesizer - A method for use in a digital frequency synthesizer, the method comprising phase to amplitude conversion of an output value of a phase accumulator in said synthesizer, said conversion being carried out as an approximation (y) of a phase value (x) which corresponds to said output amplitude value, the method being characterized in that the approximation comprises a combination of a linear interpolation value and a second order sinusoidal value, the second order sinusoidal value being used as an error term to correct for errors in the linear interpolation value. | 05-06-2010 |
20100134151 | METHOD FOR LOCKING A SYNTHESISED OUTPUT SIGNAL OF A SYNTHESISED WAVEFORM SYNTHESISER IN A PHASE RELATIONSHIP - A digital waveform synthesiser ( | 06-03-2010 |
20100134152 | PHASE INTERPOLATOR - A phase interpolator receiving a first signal having an oscillation frequency Fin and providing a second signal having said oscillation frequency and having a phase shift Δφ with respect to the first signal which depends on a third signal. The interpolator includes a variable phase-shifter receiving the first signal and providing the second signal, the phase-shifter circuit includes an oscillator having a variable natural frequency Fo controlled by a fourth signal; a phase comparator capable of receiving the first and second signals and of providing a fifth signal representative of said phase shift; and a unit capable of providing the fourth signal which depends on the third and fifth signals | 06-03-2010 |
20100327916 | FREQUENCY SYNTHESIZER NOISE REDUCTION - A method for reducing noise in a frequency synthesizer includes selecting a design variable k, calibrating a feedback time delay (T | 12-30-2010 |
20110006811 | FREQUENCY SYNTHESIZER FOR A LEVEL MEASURING DEVICE AND A LEVEL MEASURING DEVICE - A frequency synthesizer for a time base generator of a level measuring device which works according to the radar principle, with at least one first output for output of a first frequency signal, with at least one second output for output of a second frequency signal, and with a reference oscillator for producing a reference frequency signal, the first frequency signal and the second frequency signal having a small difference frequency relative to one another, the first frequency signal being producible by interaction of the reference oscillator with a direct digital synthesizer. The first frequency signal and second frequency signal can be generated with especially low noise by the second frequency signal being derived from the reference oscillator without interconnection of a direct digital synthesizer and the direct digital synthesizer being operated such that only a noise spectrum is produced which is at least partially minimized. | 01-13-2011 |
20110074469 | Frequency Generation Circuitry And Method - A method includes generating a plurality of reference phases of a reference signal and selecting a sub-phase from each of the plurality of reference phases to form a set of selected sub-phases. In the method selecting operates in response to synchronized outputs of a multi-phase phase accumulator that operates synchronously in accordance with one of the sub-phases of the set of sub-phases, and where the outputs of the multi-phase phase accumulator may be synchronized using at least one additional sub-phase. | 03-31-2011 |
20110095791 | LOW-POWER OSCILLATOR - Techniques for synthesizing a signal having a desired frequency from an oscillation signal. In an aspect, a reference signal having a known frequency may be periodically used to determine a ratio between the desired frequency and the frequency of the oscillation signal. The oscillation signal may be decimated by the ratio to generate a synthesized signal having approximately the desired frequency. In an aspect, the decimation may be performed by generating a pulse in response to the output of an accumulator that accumulates in steps of the ratio. To save power, the oscillation signal may be derived from a low-power oscillator, while the reference signal may be turned on only during periodic calibration. Further aspects for improving the frequency accuracy of the synthesized signal are disclosed. | 04-28-2011 |
20120105111 | TRANSMITTER INCLUDING POLAR MODULATION CIRCUIT - Provided is a transmitter including a polar modulation circuit which adjusts a timing lag between an amplitude component and a phase component more accurately than a conventional art. The polar modulation circuit includes: an extraction section for extracting an amplitude component and a phase component from an input signal; a first processing section for performing a first signal process on the amplitude component; a second processing section for performing a second signal processing on the phase component; an amplifier for synthesizing an output of the first processing section and an output of the second processing section and amplifying the synthesized outputs; a first calculator for performing an exclusive OR logical operation between the amplitude component before being inputted to the first processing section and the amplitude component after having been inputted to the first processing section; a first accumulation section for accumulating outputs of the first calculator; a second calculator for performing an exclusive OR logical operation between the phase component before being inputted to the second processing section and the phase component after having been inputted to the second processing section; a second accumulation section for accumulating outputs of the second calculator; and a delay fluctuation detection/compensation section for obtaining a delay time of the amplitude component based on an amount of accumulation of the first accumulation section; obtaining a delay time of the phase component based on an amount of accumulation of the second accumulation section; detecting an amount of delay fluctuation by using the delay times; and adjusting timings of the amplitude component and the phase component. | 05-03-2012 |
20120218005 | Semiconductor Device Having On-Chip Voltage Regulator - A semiconductor device having an on-chip voltage regulator to control on-chip voltage regulation and methods for on-chip voltage regulation are disclosed. A semiconductor device includes a circuit positioned between a ground bus and a power bus. A power switch array is positioned between the circuit and one of the ground bus or the power bus to generate a virtual voltage across the circuit. A monitor is positioned between the ground bus and the power bus. The monitor is configured to simulate a critical path of the circuit and to output a voltage adjust signal based on an output of the simulated critical path. A controller is configured to receive the voltage adjust signal and to output a control signal to the power switch array to control the virtual voltage. | 08-30-2012 |
20120229171 | FREQUENCY SYNTHESIZER AND FREQUENCY SYNTHESIZING METHOD FOR CONVERTING FREQUENCY'S SPURIOUS TONES INTO NOISE - One of the advantages of direct frequency synthesis technique (e.g., flying-adder architecture) is its capability of generating arbitrary frequency by utilizing the time-average-frequency concept. In the clock output of the direct frequency synthesizer, instead of one type of cycle, there are two types of cycles. Unlike the conventional one-type-cycle clock wherein clock energy is concentrated at its designed frequency, Time-Average-Frequency based clock spreads some of its energy into spurious tones, which could be harmful to certain applications. The spurious tones are caused by the periodic carry sequence generated from a fractional part accumulator inside the frequency synthesizer. The invention suggests a method and an apparatus to break this periodicity and convert the spurious tones into broadband noise. | 09-13-2012 |
20120293213 | FREQUENCY SYNTHESIZER - In forming a frequency synthesizer by using PLL using processing of digital signals, an A/D converting unit is not required. By the integration of a digital value that depends on a set frequency, a saw-tooth wave serving as a phase signal is generated. A frequency signal output from a voltage-controlled oscillator is input via a frequency divider to an edge detecting unit, which then detects a rising edge or a falling edge of the frequency signal to generate a rectangular-wave signal that depends on a frequency of the frequency signal. Then, a latched circuit latches a value of the saw-tooth wave in response to the rectangular-wave signal, and this value is integrated in a loop filter and the resultant is used as a control voltage of the voltage-controlled oscillator. | 11-22-2012 |
20130063183 | SIGNAL GENERATING APPARATUS AND METHOD OF GENERATING SIGNAL - A signal generating apparatus includes: a direct digital synthesizer configured to generate an output signal of a frequency according to first control data based on a reference clock; and a controller configured to provide the direct digital synthesizer with the first control data at a timing synchronized with the reference clock, wherein the controller includes a table which stores second setting data for controlling the frequency of the output signal based on jitter information and provides the direct digital synthesizer with the second setting data in the table as the first control data at the timing. | 03-14-2013 |
20130082743 | SEMICONDUCTOR DEVICE GENERATES COMPLEMENTARY OUTPUT SIGNALS - A splitter circuit in a semiconductor device includes a first inverter that receives an input signal and outputs an inverted signal, a second inverter that receives the inverted signal and outputs a non-inverted signal (a first output signal), a third inverter that receives the input signal and outputs an inverted signal (a second output signal) and an auxiliary inverter that shares an output signal line with the third inverter. The third inverter and the auxiliary inverter use an inverted signal of the input signal as power supplies. | 04-04-2013 |
20130093469 | FREQUENCY SYNTHESIZER AND ASSOCIATED METHOD - A frequency synthesizer includes an oscillator for providing an RF clock, a phase shifter coupled to said oscillator for providing a shifted RF clock by changing phase of said RF clock, and a time-to-digital converter (TDC) coupled to said phase shifter for quantizing a time difference between a frequency reference clock and said shifted RF clock, wherein a range of said TDC covers significantly less than a full range of said RF clock period. An associated method is also provided. | 04-18-2013 |
20130093470 | FREQUENCY SYNTHESIZER AND ASSOCIATED METHOD - A frequency synthesizer includes an oscillator for providing an RF clock, a phase shifter arranged to provide a shifted reference clock by changing phase of a frequency reference clock, and a time-to-digital converter (TDC) for producing a digital TDC output by quantizing a time difference between said RF clock and said shifted reference clock; wherein a range of said TDC covers significantly less than a full range of said RF clock period. An associated method is also provided. | 04-18-2013 |
20130093471 | TIME-TO-DIGITAL SYSTEM AND ASSOCIATED FREQUENCY SYNTHESIZER - A time-to-digital system, such as a frequency synthesizer, includes a power management circuit and a time-to-digital converter (TDC). Said power management circuit is coupled to a frequency reference clock and a variable clock, and arranged to output a delayed frequency reference clock and a single pulse of said variable clock ahead of a transition of said delayed frequency reference clock. Said TDC is coupled to said power management circuit and arranged to produce a digital TDC output. | 04-18-2013 |
20130147522 | FREQUENCY SYNTHESIZER - A frequency synthesizer for generating a low noise and low jitter timebase of a reference signal generates first and second output signals a difference frequency that is low enough for use in sub-scanning is implemented with a first incrementer, having a preset increment and a preset end value E | 06-13-2013 |
20130200925 | VARIABLE-SIZE MIXER FOR HIGH GAIN RANGE TRANSMITTER - Implementations of a high gain range transmitter with variable-size mixers are described. | 08-08-2013 |
20130257485 | SYSTEMS, CIRCUITS, AND METHODS FOR A DIGITAL FREQUENCY SYNTHESIZER - Systems, methods, and circuits provide a digital frequency synthesizer where the output of the frequency synthesizer is a fractional factor of an input signal frequency. The digital frequency synthesizer may comprise a time to digital converter. A ramp offset signal may be added to the output of the time to digital converter. The ramp offset signal may be added to the output of a TDC until a reference dock signal reaches a value of pi. At such a point, the reference clock signal may be switched and the ramp offset signal may be restarted. As such, a frequency offset may be introduced at the input of the time to digital converter where the frequency offset may be modified by changing the slope of the ramp offset signal. | 10-03-2013 |
20130271186 | Wide Range Frequency Synthesizer with Quadrature Generation and Spur Cancellation - A frequency synthesizer generates a wide range of frequencies from a single oscillator while achieving good noise performance. A cascaded phase-locked loop (PLL) circuit includes a first PLL circuit with an LC voltage controlled oscillator (VCO) and a second PLL circuit with a ring VCO. A feedforward path from the first PLL circuit to the second PLL circuit provides means and signal path for cancellation of phase noise, thereby reducing or eliminating spur and quantization effects. The frequency synthesizer can directly generate in-phase and quadrature phase output signals. A split-tuned ring-based VCO is controlled via a phase error detection loop to reduce or eliminate phase error between the quadrature signals. | 10-17-2013 |
20130300460 | METHOD AND SYSTEM FOR SIGNAL SYNTHESIS - The invention describes methods and systems for digital synthesis of electric signals. According to the invention, one or more bit-patterns are provided, each indicative of a rectangular waveform having a characteristic frequency. Further to determining a selected signal frequency to be synthesized, a selected bit-pattern associated therewith is obtained. Bits of the selected bit-pattern are cyclically serialized to generate a substantially rectangular waveform signal comprising the characteristic frequency. Then, the signal is filtered to suppress spurious frequencies outside a certain unfiltered frequency band which corresponds to the selected bit-pattern to thereby obtain a filtered signal with prominent frequency component corresponding to the selected signal frequency. | 11-14-2013 |
20130314131 | DEVICES INCLUDING PHASE INVERTERS AND PHASE MIXERS - Locked loops, delay lines, delay circuits, and methods for delaying signals are disclosed. An example delay circuit includes a delay line including a plurality of delay stages, each delay stage having an input and further having a single inverting delay device, and also includes a two-phase exit tree coupled to the delay line and configured to provide first and second output clock signals responsive to clock signals from inputs of the delay stages of the plurality of delay stages. Another example delay circuit includes a delay line configured to provide a plurality of delayed clock signals, each of the delayed clock signals having a delay relative to a previous delayed clock signal equal to a delay of a single inverting delay device. The example delay circuit also includes a two-phase exit tree configured to provide first and second output clock signals responsive to the delayed clock signals. | 11-28-2013 |
20140015570 | SWITCHING CONTROL CIRCUIT AND SWITCHING DEVICE - A switching control circuit controls a switching circuit based on decoded signals obtained by decoding several input signals. The switching control circuit is includes a decoder circuit that outputs decoded signals obtained by decoding coded input data signals. The switching control circuit includes a driver circuit that generates control signals for controlling the switching circuit based on the decoded signals. The switching control circuit is provided with a synchronous control circuit that synchronizes the input signals before outputting them for decoding. | 01-16-2014 |
20140028355 | NOISE FILTERING FRACTIONAL-N FREQUENCY SYNTHESIZER AND OPERATING METHOD THEREOF - The present invention discloses a noise filtering fractional-n frequency synthesizer and an operating method thereof. The noise filtering fractional-n frequency synthesizer comprises a filter, a frequency calibration loop, a phase calibration loop and a digitally controlled delay line. The filter receives a first frequency division signal and generates a filtered signal. The frequency calibration loop is coupled to the filter and generates a first control signal. The phase calibration loop is coupled to the filter and the frequency calibration loop, and generates a second control signal. The digitally controlled delay line is coupled to the phase calibration loop and receives the second control signal. Thus, quantization noise of the fractional-n frequency synthesizer can be reduced, and phase noise of the fractional-n frequency synthesizer can be improved. In addition, the system remains locked after the filter outputs the signal. | 01-30-2014 |
20140062537 | FREQUENCY SYNTHESIZER - Disclosed is a frequency synthesizer including first and second shift register circuits | 03-06-2014 |
20140300390 | METHOD FOR SYNTHESIZING FREQUENCY AND ELECTRONIC DEVICE THEREOF - An electronic device for synthesizing a frequency is provided. The electronic device includes a bank changer configured to output a channel code corresponding to a reference frequency signal and a feedback frequency signal, a channel code mapper configured to generate a changed channel code by applying an offset to the channel code output from the bank changer, and a voltage controlled oscillator configured to control a total capacitance of a plurality of capacitors based on the changed channel code and to oscillate a frequency dependent on the total capacitance. | 10-09-2014 |
20140320173 | FRACTIONAL PHASE LOCKED LOOP HAVING AN EXACT OUTPUT FREQUENCY AND PHASE AND METHOD OF USING THE SAME - A fractional-N frequency synthesizer having an exact output frequency and phase includes a phase locked loop including a phase detector responsive to a reference signal and a fractional divider. The phase locked loop has an output signal whose frequency is a fractional multiple of the input reference signal. The synthesizer also includes a modulator having a modulus for providing an output to the fractional divider, in which the modulus multiplied by the ratio of the frequency of the output signal to the frequency of the reference signal is a non-integer number. | 10-30-2014 |
20140361811 | SYNTHESIZER METHOD UTILIZING VARIABLE FREQUENCY COMB LINES AND FREQUENCY TOGGLING - A variable frequency synthesizer and method of outputting the variable frequency is disclosed. The synthesizer comprises a first reference frequency, a direct digital synthesizer (DDS) receiving the first reference frequency and outputting a tuned frequency, a variable frequency comb generator receiving the tuned frequency and outputting a variable frequency comb comprised of a plurality of comb lines, a mixer receiving the variable frequency comb and a signal from an oscillator and outputting an intermediate frequency, a phase lock loop (PLL) receiving a second reference frequency and the intermediate frequency and outputting a phase lock signal, and the oscillator receiving the phase lock signal and outputting a variable synthesized frequency. | 12-11-2014 |
20140361812 | DIRECT DIGITAL SYNTHESIZER, REFERENCE FREQUENCY GENERATING DEVICE, AND SINE WAVE OUTPUTTING METHOD - A DDS achieved in size and cost reductions by removing a ROM for storing a table and the like and suppressing an operation amount is provided. A DDS includes an NCO, a DAC, and a BPF. The NCO outputs a sawtooth wave. The DAC converts either one of the sawtooth wave outputted from the NCO and a triangle wave signal converted by a waveform converting circuit based on the sawtooth wave, from a digital signal into an analog signal. The BPF receives the signal converted into the analog signal by the DAC and extracts a sine wave at a predetermined frequency from the inputted signal, by allowing a signal at a frequency within a fixed range to pass therethrough. | 12-11-2014 |
20150123713 | OPTICALLY CLOCKED DIGITAL/ANALOG CONVERTER AND A DDS UNIT WITH SUCH A CONVERTER - A digital/analog converter ( | 05-07-2015 |
20160028350 | Modified Flying Adder Architecture - According to an embodiment, an improved flying adder circuit, comprises a fine clock, a coarse pulse clock, a rising edge triggered output connected to both the fine clock and the coarse pulse clock, a pulse clock connected to the rising edge triggered output, an adder, a 12-bit register situated to receive a signal from the adder and the pulse clock, and a single bit register situated to receive a signal from the pulse clock. | 01-28-2016 |
20160028411 | FREQUENCY SYNTHESIZER WITH INJECTION PULLING/PUSHING SUPPRESSION/MITIGATION AND RELATED FREQUENCY SYNTHESIZING METHOD THEREOF - A frequency synthesizer includes a phase-locked loop (PLL) and a loop bandwidth controller. The PLL generates an output clock according to a reference clock. The loop bandwidth controller checks at least one indicator indicative of injection pulling/pushing of the PLL to configure a loop bandwidth of the PLL. In one exemplary design, the loop bandwidth controller sets the loop bandwidth of the PLL by controlling a configuration of a loop filter included in the PLL. For example, the PLL is an all-digital phase-locked loop (ADPLL), and the loop filter is a digital loop filter of the ADPLL. | 01-28-2016 |
20160182068 | INJECTION LOCKED DIGITAL FREQUENCY SYNTHESIZER CIRCUIT | 06-23-2016 |
20160197601 | FREQUENCY SYNTHESIZER AND METHOD CONTROLLING FREQUENCY SYNTHESIZER | 07-07-2016 |