Class / Patent application number | Description | Number of patent applications / Date published |
327106000 | Having stored waveform data (e.g., in ROM, etc.) | 19 |
20080224735 | Frequency Synthesis Rational Division - A system and method are provided for synthesizing signal frequencies using rational division. The method accepts a reference frequency value and a synthesized frequency value. In response to dividing the synthesized frequency value by the reference frequency value, an integer value numerator (dp) and an integer value denominator (dq) are determined. The method reduces the ratio of dp/dq to an integer N and a ratio of p/q (dp/dq=N(p/q)), where p/q<1 (decimal). The numerator (p) and the denominator (q) are supplied to a flexible accumulator module, and a divisor is generated as a result. N is summed with a k-bit quotient to create the divisor. In a phase-locked loop (PLL), the divisor and the reference signal are used to generate a synthesized signal having a frequency equal to the synthesized frequency value. | 09-18-2008 |
20090033375 | METHOD AND APPARATUS FOR IDENTIFYING AND REDUCING SPURIOUS FREQUENCY COMPONENTS - A method for identifying and reducing spurious frequency components is provided. A method in accordance with at least one embodiment of the present disclosure may include generating a digital sinusoidal waveform at a direct digital synthesizer (DDS) and receiving the digital sinusoidal waveform at an audio digital-to-analog converter. The method may further include converting the digital sinusoidal waveform to an analog sinusoidal waveform containing spurious frequency components, combining the analog sinusoidal waveform with an analog distortion correction waveform to generate a composite output waveform and receiving the composite output waveform at notch filter circuitry. The method may also include filtering the composite output waveform to generate a filtered composite output waveform and amplifying a difference between the filtered composite output waveform and a signal from a circuit-under-test (CUT) to generate an amplified analog signal. The method may also include converting the amplified analog signal to an amplified digital signal. Of course, additional implementations are also within the scope of the present disclosure. | 02-05-2009 |
20090085611 | Method And System For A Programmable Local Oscillator Generator Based On Quadrature Mixing Using A Phase Shifter - Methods and systems for a local oscillator generator based on quadrature mixing using a phase shifter. Aspects of one method may include generating a local oscillator signal, where a frequency of the local oscillator signal may be determined by controlling a phase of in-phase (I) components and quadrature phase (Q) components of a first signal and a second signal. For example, by appropriately controlling a phase of each component that is to be mixed, the local oscillator signal may have a frequency that is the sum of a frequency of the first signal and a frequency of the second signal, or a difference of the frequency of the first signal and the frequency of the second signal. | 04-02-2009 |
20090128197 | Senthesizer module - To provide a synthesizer module that can be used not only in a destination area but also in the whole world and that can be readily set in output frequency. In the synthesizer module, a calculation formula table of a nonvolatile memory stores a plurality of frequency modes and the calculation formula of carrier frequencies corresponding to those frequency modes, and further stores in its certain area, a frequency mode set during an initial setting of the device. A CPU, when receiving a channel number from a rotary SW during a frequency setting, calculates, based on a calculation formula corresponding to a currently set frequency mode, a carrier frequency corresponding to the channel number. This carrier frequency is set to a CONT of a PLL part. | 05-21-2009 |
20090134918 | JITTER GENERATOR FOR GENERATING JITTERED CLOCK SIGNAL - A jitter generator for generating a jittered clock signal, includes a jitter control signal generator and a jittered clock generator. The jitter control signal generator is utilized for selecting a digital control code from a plurality of candidate digital control codes at individual time points and respectively outputting a plurality of selected digital control codes. The jittered clock generator is coupled to the jitter control signal generator, and utilized for generating the jittered clock signal. The jittered clock generator dynamically adjusts the jittered clock signal according to the plurality of different digital control codes. | 05-28-2009 |
20100164555 | WAVEFORM GENERATION DEVICE, WAVEFORM GENERATION METHOD, AND PROGRAM - Provided is a waveform generating apparatus that generates a signal having an arbitrary waveform, comprising a waveform memory that stores a plurality of pieces of waveform data that each include a sequence of signal values; a filtering section that (i) reads from the waveform memory a piece of waveform data serving as a basis for a waveform to be generated, from among the plurality of pieces of waveform data, (ii) performs a conversion by filtering the read piece of waveform data to obtain a piece of converted waveform data, and (iii) writes to the waveform memory the piece of converted waveform data; and a waveform output section that reads the piece of converted waveform data from the waveform memory and outputs a signal having a waveform corresponding to the sequence of signal values of the read piece of converted waveform data. | 07-01-2010 |
20100182053 | SINE/COSINE VALUE GENERATION APPARATUS - An apparatus for generating sine/cosine values of an input phase is disclosed. The apparatus includes a phase projector, an LUT-arithmetic unit, a temp sine/cosine generator and a sine/cosine value generator. The phase projector maps the input phase angle into an octant phase and determines an octant index indicating which octant the input phase angle actually locates and a flag indicating whether or not the input phase happens to be pi/4, 3*pi/4, 5*pi/4 or 7*pi/4. The LUT-arithmetic unit receives the octant phase for provision of its corresponding sine/cosine values. The temp sine/cosine generator receives the corresponding sine/cosine values of the octant phase for provision of temp sine/cosine values based on the flag. The sine/cosine value generator selectively swaps and inverts the temp sine/cosine values as the sine/cosine values of the input phase based on a swap index derived from the octant index. | 07-22-2010 |
20100194444 | REDUCTION OF SPURIOUS FREQUENCY COMPONENTS IN DIRECT DIGITAL SYNTHESIS - In an embodiment, an apparatus, comprises a phase accumulator configured to provide an output comprising a truncated phase word representative of an instantaneous phase; a multiplexer configured to provide an output representative of a phase rotation, wherein the output representative of the phase rotation is randomly selected from a group of phase rotation representation outputs; an adder configured to receive the output from the phase accumulator and the output from the multiplexer, wherein the adder provides an output representative of the instantaneous phase rotated by the phase rotation; a lookup table configured to receive the output representative of the instantaneous phase and to provide an amplitude output; and a rotator configured to receive the amplitude output and substantially to cancel the phase rotation. Other embodiments do not comprise a rotator. A method is also described. | 08-05-2010 |
20110043258 | DIRECT DIGITAL FREQUENCY SYNTHESIZER USING HYBRID DIGITAL TO ANALOG CONVERTER AND SYNTHESIZING METHOD THEREOF - The present invention relates to d a direct digital frequency synthesizer using a hybrid digital to analog converter, which is capable of synthesizing an analog signal with high quality without base decoding, thereby providing improved size and efficiency, and a synthesizing method thereof. The direct digital frequency synthesizer using a hybrid digital to analog converter, and a synthesizing method thereof are capable of simplifying a configuration of a PAM which matches output data of a phase accumulator to sine wave amplitude with an application of a hybrid DAC including a non-linear DAC and a linear DAC, without increase of complexity of a DAC, by causing the non-linear DAC to output a direct base point current using some bits of output data of a phase accumulator, causing the linear DAC to output a gradient current based on gradient information generated using other bits of the output data of the phase accumulator, and summing these currents for analog output. Accordingly, an effect of greatly reducing a size and power consumption can be achieved. | 02-24-2011 |
20110109349 | Waveform Generation from an Input Data Stream - An output signal is generated from a received input data stream representing a sequence of digital data values. For each group of successive data values in the sequence of data values, a respective waveform pattern is assigned in dependence of the data content of the respective group of successive data values. The output signal is generated by generating the assigned respective waveform patterns corresponding to the input data stream. | 05-12-2011 |
20110121867 | HIGH-SPEED COMPRESSION ARCHITECTURE FOR MEMORY - Memory design techniques are disclosed that provide a high compression ratio at no loss in speed. The techniques can be embodied, for instance, in heterojunction bipolar transistor (HBT) based ROMs. By embedding compression logic (e.g., XOR) functionality directly into the address decoders and sense amplifiers of the memory device, a high compression ratio is achieved at no loss in speed. For example, the logic-based compression functionality can be directly implemented into the buffers that form the address decoder as well as the sense amplifiers. | 05-26-2011 |
20110140743 | Digital Frequency Generator - A digital frequency generator is described. | 06-16-2011 |
20110199128 | ROM-Based Direct Digital Synthesizer with Pipeline Delay Circuit - A DDS system is disclosed that is configured to provide a variable clock delay that allows timing of data coming out of the ROM to be adjusted. In one example case, a DDS system is provided that includes a ROM for storing phase-to-amplitude conversion data and generating digital amplitude values corresponding to respective digital phase values, and delay circuitry for adjusting timing of data output by the ROM to compensate for propagation delay of the DDS system. The delay circuitry may include, for instance, delay elements that can be selected alone or in combination to adjust the timing. The timing can be adjusted, for example, by adjusting delay of a clock signal that clocks one or more ROM pipeline registers. The system may include a phase accumulator and DAC, and adjusting the timing may include adjusting delay of a clock signal that clocks one or more DAC pipeline registers. | 08-18-2011 |
20120139587 | FREQUENCY SYNTHESISER - A low power frequency synthesiser circuit ( | 06-07-2012 |
20130057318 | CLOCKING ARCHITECTURES IN HIGH-SPEED SIGNALING SYSTEMS - Clocking systems and methods are provided below that accurately clock per-pin data transfers of input/output (IO) circuits of integrated circuit devices. These multiplexer-based clock selection systems use a dedicated multiplexer to receive clock signals from multiple mixer circuits and in turn to provide a selected reference clock signal for use by an interface circuit in transferring data to other integrated circuit devices. The timing of the selected reference clock signal is synchronized with the data signals to provide optimal sampling of the data signals. The multiplexer-based clock selection system is for use in memory interfaces of high-speed signaling systems for example. | 03-07-2013 |
20130099829 | Operating a Frequency Synthesizer - An apparatus and method for operating a frequency synthesizer wherein a value of an first control signal associated with a fine frequency feedback loop connected to a signal generator is monitored, and a second control signal associated with a medium or coarse frequency feedback loop connected to the signal generator is adjusted based on the monitoring. The first and second control signals are then output to control the frequency synthesizer. | 04-25-2013 |
20140240004 | PHASE DISCIPLINED, DIRECT DIGITAL SYNTHESIZER BASED, COHERENT SIGNAL GENERATOR - A phase coherent signal generator apparatus is disclosed that has fast frequency shifting and numerous phase memory points, outputting a coherent continuous phase signal that includes fast switched multiple different frequency bursts. The apparatus comprises: a clock generator including an input that receives a reference clock signal, an output that supplies a master clock signal, and an output that supplies a slave clock signal; an accumulating digital synthesizer that includes a first input that receives the slave clock signal, a second input that receives a digital frequency tune word signal, a third input that receives a phase tune word signal, a fourth input that receives a reset signal, and an output that supplies a digital coherent continuous phase signal; a master digital synthesizer that includes a first input that receives the master clock signal, a second input that receives the digital frequency tune word signal, a first output that supplies the digital phase tune word signal, and a second output that supplies a reset signal; and a converter that receives the digital coherent continuous phase signal and supplies the coherent continuous phase signal. | 08-28-2014 |
20150015308 | PHASE-LOCKED LOOP (PLL)-BASED FREQUENCY SYNTHESIZER - This disclosure describes techniques for generating signals that have relatively steep frequency profiles with a phase-locked loop (PLL) circuit architecture. In some examples, the techniques for generating signals that have relatively steep frequency profiles may include modulating an amplitude of a forward path signal in a PLL circuit at a location in a forward circuit path of the PLL circuit based on a control signal. The control signal may have an amplitude profile that is determined based on a target frequency profile to be generated by the PLL circuit. Modulating the forward circuit path of the PLL circuit with a signal that is determined based on a target frequency profile may allow a PLL-based frequency synthesizer to generate signals with relatively steep frequency profiles while still maintaining acceptable levels of phase noise. | 01-15-2015 |
20150311890 | SIGNAL GENERATOR, SIGNAL GENERATION METHOD, AND NUMERICALLY CONTROLLED OSCILLATOR - A waveform conversion unit ( | 10-29-2015 |