Entries |
Document | Title | Date |
20080258774 | Semiconductor device with a logic circuit - The logic gate of the present invention is of a configuration that includes a first transistor, a second transistor, and a connection-switching unit. The first transistor receives a first voltage at its source, a first input signal at its gate, and supplies a first output signal from its drain. The second transistor receives a second voltage that is lower than the first voltage at its source, receives a second input signal at its gate, and supplies a second output signal from its drain. The connection-switching unit is connected between the drains of the first transistor and the second transistor for connecting and cutting off the first transistor and the second transistor. | 10-23-2008 |
20090072862 | Semiconductor Device and Display Device - The invention provides a low cost and high performance functional circuit by reducing time required for the repetition of logic synthesis and routing of layout in a functional circuit design. A standard cell used for the logic synthesis and the routing of layout is configured by a logic circuit on an output side and a logic circuit on an input side and a driving capacity of the logic circuit on the output side is made large while gate input capacitance of the logic circuit on the input side is made small. By forming the standard cell in this manner, a ratio that the gate delay occupies in the delay time of a functional circuit can be relatively increased. Therefore, even when wiring capacitance after the routing of layout is not estimated at high precision in advance, an operating frequency can be obtained at high precision in the logic synthesis as long as a gate delay of each standard cell can be estimated at high precision. That is, a reliability of the logic synthesis result is improved, therefore, the logic synthesis and an automatic routing of layout are not required to be repeated, which can shorten the design period. | 03-19-2009 |
20090174435 | Monolithically-Integrated Graphene-Nano-Ribbon (GNR) Devices, Interconnects and Circuits - The invention discloses new and advantageous uses for carbon/graphene nanoribbons (GNRs), which includes, but is not limited to, electronic components for integrated circuits such as NOT gates, OR gates, AND gates, nano-capacitors, and other transistors. More specifically, the manipulation of the shapes, sizes, patterns, and edges, including doping profiles, of GNRs to optimize their use in various electronic devices is disclosed. | 07-09-2009 |
20090278570 | Circuit Configurations Having Four Terminal JFET Devices - Circuits using four terminal junction field effect transistors (JFETs) are disclosed. Such circuits can include various static and dynamic logic circuits, flip-flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or analog circuit with such four terminal JFETs operating in a linear or nonlinear mode. | 11-12-2009 |
20100013519 | INVERTER CIRCUIT - An inverter circuit for generating an output signal at an output node obtained by inverting an input signal level at an input node includes a common-source MOS transistor having a gate node connected to the input node, a source connected to a predetermined voltage-and a substrate gate, a load resistor connected in series with the MOS transistor, and a resistor connected between the gate node and the substrate gate of the MOS transistor. | 01-21-2010 |
20100033213 | Field effect transistor and electric circuit - The invention relates to a field effect transistor comprising at least one source electrode layer and at least one drain electrode layer arranged in the same plane, a semiconductor layer, an insulator layer and a gate electrode layer, wherein the gate electrode layer, as seen perpendicular to the plane of the at least one source electrode layer and the at least one drain electrode layer, only partly covers a channel arranged between the at least one source electrode layer and the at least one drain electrode layer. | 02-11-2010 |
20100259301 | LOGIC GATE WITH A REDUCED NUMBER OF SWITCHES, ESPECIALLY FOR APPLICATIONS IN INTEGRATED CIRCUITS - Logic Gate ( | 10-14-2010 |
20100315127 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes: a first inverter constituted by a first transistor configured to charge a charge point based on an input signal, and a second transistor configured to discharge a discharge point based on the input signal; a P-type third transistor and an N-type fourth transistor with drain-source paths provided in parallel between the charge point and the discharge point; and a second inverter configured to invert a potential of the charge point or the discharge point and supply the inverted potential to gates of the third and fourth transistors, and obtain a delay signal of the input signal from the charge point or the discharge point. The semiconductor integrated circuit device secures a sufficient delay time with a small area. | 12-16-2010 |
20100315128 | CIRCUIT CONFIGURATIONS HAVING FOUR TERMINAL DEVICES - Circuits using four terminal transistors are disclosed. Such circuits can include various static and dynamic logic circuits, flip-flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or analog circuit with such four terminal transistors operating in a linear or nonlinear mode. | 12-16-2010 |
20100327911 | Semiconductor Device and a Display Device - The invention provides a low cost and high performance functional circuit by reducing time required for the repetition of logic synthesis and routing of layout in a functional circuit design. A standard cell used for the logic synthesis and the routing of layout is configured by a logic circuit on an output side and a logic circuit on an input side and a driving capacity of the logic circuit on the output side is made large while gate input capacitance of the logic circuit on the input side is made small. By forming the standard cell in this manner, a ratio that the gate delay occupies in the delay time of a functional circuit can be relatively increased. Therefore, even when wiring capacitance after the routing of layout is not estimated at high precision in advance, an operating frequency can be obtained at high precision in the logic synthesis as long as a gate delay of each standard cell can be estimated at high precision. That is, a reliability of the logic synthesis result is improved, therefore, the logic synthesis and an automatic routing of layout are not required to be repeated, which can shorten the design period. | 12-30-2010 |
20110121862 | CIRCUIT WITH STACKED STRUCTURE AND USE THEREOF - An NAND circuit has a stacked structure having at least one symmetric NFET at a bottom of the stack. More particularly, the circuit has a stacked structure which includes an asymmetric FET and a symmetric FET. The symmetric FET is placed at the bottom of the stacked structure closer to ground than the asymmetric FET. | 05-26-2011 |
20110187412 | COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICES - Improvements in Complementary Metal Oxide Semiconductor (CMOS) devices; in particular, field effect transistors (FETs) and devices using said transistors which are able to take advantage of the higher carrier mobility of electrons compared to holes by replacing the conventional p-channel transistor with an n-channel transistor having a double gate (or vice versa): Such a Unipolar CMOS (U-CMOS) transistor can be realised by adapting the source and/or the drain such that when the body region undergoes inversion at a first surface current, is able to flow between the drain and the source and when the body region undergoes inversion at a second surface current is not able to flow between the drain and the source. Various logic gates may be constructed using U-CMOS transistors. | 08-04-2011 |
20110193594 | SEMICONDUCTOR INTEGRATED CIRCUIT - Each of a plurality of inverters includes: a first transistor having one end connected to a first terminal; and a second transistor having one end connected to a second terminal and the other end connected to the other end of the first transistor. | 08-11-2011 |
20110241729 | Inverter circuit and display - An inverter circuit includes: first to third transistors; and first and second capacity elements. The first transistor makes/breaks connection between an output terminal and a first voltage line in response to potential difference between an input terminal and the first voltage line or its correspondent. The second transistor makes/breaks connection between a second voltage line and the output terminal in response to potential difference between a gate of the second transistor and the output terminal or its correspondent. The third transistor makes/breaks connection between a gate of the second transistor and a third voltage line in response to potential difference between the input terminal and the third voltage line or its correspondent. The first and second capacity elements are inserted in series between the input terminal and the gate of the second transistor. A junction between the first and second capacity elements is connected to the output terminal. | 10-06-2011 |
20110241730 | Inverter circuit and display - An inverter circuit includes: first to third transistors; and first and second capacity elements. The first transistor makes/breaks connection between an output terminal and a first voltage line in response to potential difference between an input terminal and the first voltage line or its correspondent. The second transistor makes/breaks connection between a second voltage line and the output terminal in response to potential difference between a gate of the second transistor and the output terminal or its correspondent. The third transistor makes/breaks connection between a gate of the second transistor and a third voltage line in response to potential difference between the input terminal and the third voltage line or its correspondent. The first and second capacity elements are inserted in series between the input terminal and the gate of the second transistor. A junction between the first and second capacity elements is connected to the output terminal. | 10-06-2011 |
20120212257 | BI-LAYER PSEUDO-SPIN FIELD-EFFECT TRANSISTOR - A bi-layer pseudo-spin field-effect transistor (BiSFET) is disclosed. The BiSFET includes a first and second conduction layers separated by a tunnel dielectric. The BiSFET transistor also includes a first gate separated from the first conduction layer by an insulating dielectric layer, and a second gate separated from the second conduction layer by an insulating layer. These conduction layers may be composed of graphene. The voltages applied to the first and/or second gates can control the peak current and associated voltage value for current flow between top and bottom conduction channels, and interlayer current voltage characteristic exhibiting negative differential resistance. BiSFETs may be used to make a variety of logic gates. A clocked power supply scheme may be used to facilitate BiSFET-based logic. | 08-23-2012 |
20120218000 | SEMICONDUCTOR INTEGRATED CIRCUIT - Each of a plurality of inverters includes: a first transistor having one end connected to a first terminal; and a second transistor having one end connected to a second terminal and the other end connected to the other end of the first transistor. The first transistors included in the inverters located at either odd-number orders or even-number orders counted from an input terminal side of an inverter chain circuit become conductive when a pre-charge signal has a first state to pre-charge the other end of the first transistors, and become non-conductive when the pre-charge signal has a second state. | 08-30-2012 |
20120242370 | INVERTER, NAND GATE, AND NOR GATE - Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal. | 09-27-2012 |
20140035621 | INVERTER, NAND GATE, AND NOR GATE - Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal. | 02-06-2014 |
20140035622 | INVERTER, NAND GATE, AND NOR GATE - Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal. | 02-06-2014 |
20140062532 | NANO-ELECTRO-MECHANICAL-SWITCH ADIABATIC DYNAMIC LOGIC CIRCUITS - A dynamic logic gate includes a nano-electro-mechanical-switch, preferably a four-terminal-nano-electro-mechanical-switch. The invention further refers to dynamic logic cascade circuits comprising such a dynamic logic gate. In particular, embodiments of the invention concern dynamic logic cascade circuits comprising single or dual rail dynamic logic gates. | 03-06-2014 |
20140145761 | LOW-POWER DUAL-EDGE-TRIGGERED STORAGE CELL WITH SCAN TEST SUPPORT AND CLOCK GATING CIRCUIT THEREFORE - A storage cell having a pulse generator and a storage element is proposed. The storage element input is connected to receive a data input signal. The storage element output is connected to provide a data output signal. The storage element is operable in one of a data retention state and a data transfer state in response to a storage control signal received from the pulse generator. The pulse generator is connected to receive a clock signal with rising and falling clock signal edges and is adapted to provide control pulses in the storage control signal. Each control pulse has a leading edge and a trailing edge. The control pulses have a polarity suited to invoke the data transfer state on their leading edges. The novel feature is that the pulse generator is adapted to initiate a rising-edge control pulse when receiving a rising clock signal edge and to initiate a falling-edge control pulse when receiving a falling clock signal edge. In this way, a dual-edge-triggered flip-flop may be made using only combinatorial logic circuitry and one level- or single-edge-triggered storage element. The storage cell has low power consumption, facilitates scan testing and can be used by existing design tools and test equipment. | 05-29-2014 |
20140232433 | CIRCUIT ELEMENT INCLUDING A LAYER OF A STRESS-CREATING MATERIAL PROVIDING A VARIABLE STRESS AND METHOD FOR THE FORMATION THEREOF - A transistor includes a source region, a drain region, a channel region, a gate electrode and a layer of a stress-creating material. The stress-creating material provides a stress that is variable in response to a signal acting on the stress-creating material. The layer of stress-creating material is arranged to provide a stress in at least the channel region. The stress provided in at least the channel region is variable in response to the signal acting on the stress-creating material. Layers of stress-creating material providing a stress that is variable in response to a signal acting on the stress-creating material may also be used in circuit elements other than transistors, for example, resistors. | 08-21-2014 |
20140266305 | SEMICONDUCTOR DEVICE - A semiconductor device having a power-saving circuit. The semiconductor device includes an input-output terminal and a holding circuit. When the input-output terminal is used, an inverter loop of the holding circuit is made not to operate by controlling a switch, and when the input-output terminal is not used, the inverter loop of the holding circuit operate by controlling the switch. Power consumption of the holding circuit can be reduced. An OS transistor is preferably used for the switch. | 09-18-2014 |
20140300387 | OVER-CURRENT AND/OR OVER-VOLTAGE PROTECTION CIRCUIT - A logic inverter with over-current protection according to one embodiment includes a transistor, an input signal line coupled to a gate terminal or base region of the transistor, an output signal line coupled to a drain terminal or collector region of the transistor, a power supply line coupled to the drain terminal or collector region of the transistor, and a feedback resistor between a source terminal or emitter region of the transistor and ground. | 10-09-2014 |
20160079977 | OVER-CURRENT AND/OR OVER-VOLTAGE PROTECTION CIRCUIT - A logic inverter with over-current protection, according to one embodiment, includes: a transistor, an input signal line coupled to a gate terminal of the transistor or a base region of the transistor, an output signal line coupled to a drain terminal of the transistor or a collector region of the transistor, a power supply line coupled to the drain terminal of the transistor or a collector region of the transistor, a pull up resistor between a power supply and one of: the drain terminal of the transistor and the collector region of the transistor, and a feedback resistor between ground and one of: a source terminal of the transistor and an emitter region of the transistor. Other systems, methods, and computer program products are described in additional embodiments. | 03-17-2016 |