Class / Patent application number | Description | Number of patent applications / Date published |
324766000 | With barrier layer | 50 |
20080224724 | Photoconductive Based Electrical Testing of Transistor Arrays - Apparatus for testing microelectronic components on a substrate, including a scanner operative to scan a light beam over a plurality of thin film transistors disposed on a substrate, one transistor at a time, so as to induce a photoconductive response in the plurality of transistors, one transistor at a time; current sensing circuitry operative, synchronously with said scanner, to measure an output induced by the photoconductive response associated with a transistor and to generate photoconductive response output values, the photoconductive response output values representing a photoconductive response induced by the light beam, for one transistor at a time from among the plurality of transistors; and diagnostic apparatus operative to analyze the electronic response output values and to characterize each of the transistors in accordance therewith. | 09-18-2008 |
20090058456 | MANUFACTURING SYSTEM, MANUFACTURING METHOD, MANAGING APPARATUS, MANAGING METHOD AND COMPUTER READABLE MEDIUM - There is provided a manufacturing system for manufacturing an electronic device through a plurality of manufacturing stages. The manufacturing system includes a plurality of manufacturing apparatuses performing processes corresponding to the plurality of manufacturing stages. The manufacturing system includes a manufacturing line that manufactures the electronic device, a manufacturing control section that causes the manufacturing line to manufacture a wafer having therein a test circuit including a plurality of transistors under measurement, a measuring section that measures an electrical characteristic of each of the plurality of transistors under measurement in the test circuit, an identifying section that identifies, among the plurality of manufacturing stages, a manufacturing stage in which a defect is generated, with reference to a distribution, on the wafer, of one or more transistors under measurement whose electrical characteristics do not meet a predetermined standard, and a setting changing section that changes a setting for a manufacturing apparatus that performs a process corresponding to the manufacturing stage in which the defect is generated. | 03-05-2009 |
20090066358 | METHODS AND APPARATUS FOR DETECTING DEFECTS IN INTERCONNECT STRUCTURES - In some aspects, a method is provided for detecting a void in a test structure that comprises (a) measuring a resistance of the test structure; (b) applying a stress to the test structure at increasing levels until at least one of: (i) the measured resistance of the test structure exceeds a predetermined resistance threshold; and (ii) the stress level reaches a predetermined stress maximum; (c) detecting a void if the measured resistance of the test structure exceeds the predetermined resistance threshold; and (d) determining that the test structure is void free if the stress level reaches the predetermined stress maximum without the measured resistance of the test structure exceeding the predetermined resistance threshold. Numerous other aspects are provided. | 03-12-2009 |
20090085600 | Method and System for Derivation of Breakdown Voltage for MOS Integrated Circuit Devices - A method and system for multi-point (e.g., double-point) GOI test that can efficiently judge failure modes by testing only two points. We can measure leakage currents at only two voltages, which are the cut points of mode A-B and B-C, instead of the whole ramped voltages to save time and cost with the same test effectiveness according to a specific embodiment. By correlating leakage current at extrinsic field to the breakdown voltage, we can also evaluate the intrinsic reliability even if the samples are not subjected to actual breakdown according to a specific embodiment. | 04-02-2009 |
20090102504 | Circuit Assemblage and Method for Functional Checking of a Power Transistor - A circuit assemblage for functional checking of a power transistor includes a power transistor having an insulated gate, a first power electrode configured as a drain or as a collector, and a second power electrode configured as a source or an emitter, the first and second power electrode being connected to a power circuit having a DC voltage source and an electrical DC load. The circuit assemblage further includes a control application device having a signal output that is connected to the gate; a capacitance measuring device for measuring the gate terminal capacitance between the gate terminal contact and the second power electrode terminal contact; and an evaluation device for comparing the gate terminal capacitance with the gate capacitance, and outputting a fault signal as a function of the comparison. | 04-23-2009 |
20090160477 | METHOD AND TEST SYSTEM FOR FAST DETERMINATION OF PARAMETER VARIATION STATISTICS - A method and test system for fast determination of parameter variation statistics provides a mechanism for determining process variation and parameter statistics using low computing power and readily available test equipment. A test array having individually selectable devices is stimulated under computer control to select each of the devices sequentially. A test output from the array provides a current or voltage that dependent on a particular device parameter. The sequential selection of the devices produces a voltage or current waveform, characteristics of which are measured using a digital multi-meter that is interfaced to the computer. The rms value of the current or voltage at the test output is an indication of the standard deviation of the parameter variation and the DC value of the current or voltage is an indication of the mean value of the parameter. | 06-25-2009 |
20100164531 | TUNABLE STRESS TECHNIQUE FOR RELIABILITY DEGRADATION MEASUREMENT - Apparatus and methods are disclosed for examining how reliability in an RF power amplifier circuit changes as a function of variation of the input to output voltage swings. Two output transistors that varying greatly in the size of their respective channel widths are provided for independently evaluating impacts on the output waveform. The gate control for the smaller transistor is separate from the gate control to the larger transistor. The gate and drain stress can thus be adjusted and evaluated independently. | 07-01-2010 |
20100237895 | System and method for characterizing solar cell conversion performance and detecting defects in a solar cell - A system and method for characterizing the solar cell conversion performance and detecting a defect in a solar cell includes applying an optical test signal to the solar cell using the multiple-scanning method, measuring the solar cell photocurrent in response to the solar cell illumination by the multiple-scanning method, and detecting a defect and finding its location based on the characteristic mapping of solar cell photocurrent, which is obtained by the multiple-scanning method through the divisional control of light transmittance by the LVP (light valve panel). The defect may be a solar cell subsection which has abnormally low photocurrent below a critical value and can be caused by a short between the emitter and the base of solar cell. The LVP may be realized in any one of a variety of ways. For example, the LVP may be a flat-panel display such as AMLCD (Active-Matrix Liquid Crystal Display) and AMOLED (Active-Matrix Organic Light Emitting Diode). | 09-23-2010 |
324767000 | Diode | 9 |
20090009208 | SEMICONDUCTOR DEVICE AND INSPECTION METHOD THEREOF - A semiconductor device is disclosed. The device has a photodiode isolated by element isolating regions (Ia, | 01-08-2009 |
20090066359 | SEMICONDUCTOR DEVICE TEST SYSTEM HAVING REDUCED CURRENT LEAKAGE - A test circuit tests a device under test (DUT) uses a first switching device and a second switching device. The device under test (DUT) has a terminal for receiving a test signal. The first switching device has an output terminal for use in coupling the test signal to the terminal of the DUT when the DUT is being tested. The first switching device is high impedance when the DUT is not being tested. The second switching device is high impedance when the DUT is being tested and couples a bias control signal to the output terminal of the first switching device when the DUT is not being tested. The bias control signal substantially tracks the test signal. Leakage from the first switching device when other DUTs are being tested is greatly reduced because the bias control signal results in little or no bias across the first switching device. | 03-12-2009 |
20090096479 | System and method for automated detection of singular faults in diode or'd power bus circuits - A system automatically detects singular faults in diode or'd power bus circuit comprised of a plurality of diodes. The system includes a diode test circuit that selectively applies a voltage pulse to one of the plurality of diodes and detects the presence of singular faults based on the monitored response to the voltage pulse. | 04-16-2009 |
20090115446 | Measurement method of the current-voltage characteristics of photovoltaic device, a solar simulator for the measurement, and a module for setting irradiance and a part for adjusting irradiance used for the solar simulator - [Problem] In a solar simulator for measuring the current-voltage characteristics of photovoltaic devices, it is to provide a measurement method using a solar simulator in which locative unevenness of irradiance on the test plane of the test plane side is drastically improved, not in a light source side, and a means for adjusting irradiance and the like. | 05-07-2009 |
20090302881 | Internal Memory for Transistor Outline Packages - A transistor outline (TO) package includes a housing having a window and a substrate. Circuitry is coupled to the substrate within the housing. The circuitry comprises a laser diode and memory configured to store information related to the TO package. Electrical connectors are coupled to the substrate at the opposite side to the circuitry. At least one of the electrical connectors is electrically connected to the memory. A disclosed method includes assembling a TO package, testing the TO package, storing results of the testing in memory, and making the information stored in the memory, including the results of the testing, available to a device external to the TO package. The TO package includes a laser diode and memory configured to store information related to the TO package. | 12-10-2009 |
20090322372 | AUTOMATIC TEST EQUIPMENT - A coupling line is provided for coupling a signal generator to a device under test and includes a first Zener diode and a second Zener diode. The first Zener diode and the second Zener diode are coupled in an antiserial manner. They are adapted to couple the signal generator to the device under test when the signal generator is active and decouple the signal generator from the device under test when the signal generator is inactive. | 12-31-2009 |
20100164532 | APPARATUS AND METHOD FOR MEASURING CHARACTERISTICS OF SEMICONDUCTOR DEVICE - An apparatus and method for measuring the characteristics of a semiconductor device is disclosed. The measuring apparatus may include first to M-th (wherein M is a positive integer not less than 1) starved devices each being biased in response to a bias voltage varying in accordance with a variable first supply voltage, thereby varying an amount of current flowing through a semiconductor device included in the starved device. Interconnect lines may interconnect the first to M-th starved devices. A measuring unit measures at least one of a delay time caused by the semiconductor devices of the starved devices themselves, and a compound delay time caused by the semiconductor devices of the starved devices themselves plus a delay time caused by the interconnect lines. The measured results can be analyzed under conditions more approximate to diverse situations exhibited in practical chips in accordance with development of manufacturing processes and techniques. It is also possible to provide the basis of a model which more effectively represents coupling geometry of more complex semiconductor devices and interconnect lines. The basis of the model may be applied to development of various tools, etc. | 07-01-2010 |
20100289518 | CIRCUIT AND METHOD FOR DETECTING FAULTY DIODE - A circuit for detecting faulty diode is disclosed, wherein the circuit for detecting faulty diode comprises a diode having an anode connecting to a voltage supply; a first switch having a first end connected to a cathode of the diode; a testing current source connected to the second end of the first switch; a one-shot circuit connected to a control end of the first switch, by which an output signal is generated and transmitted to the control end; and a comparator connected to a reference voltage input terminal for receiving a reference voltage and connected to the second end of the first switch. When the one-shot circuit closes the first switch for a maintaining period to urge the comparator comparing the reference voltage with the voltage applied to the second end of the first switch, whereby a signal used to discriminate whether the diode is fail or not is generated. | 11-18-2010 |
20100289519 | CIRCUIT FOR DETECTING FAULTY DIODE - A circuit for detecting faulty diode comprises a diode having an anode connected to a voltage supply; a resistor having a first end connected to a cathode of the diode; a transistor having a drain connected to a second end of the resistor and a source that is grounded; a differential amplifier having a positive terminal connected to the drain of the transistor, a negative terminal connected to a reference voltage input terminal for receiving a reference voltage, and an output terminal connected to a gate of the transistor; and a buffer having an input terminal connected to the gate of the transistor, and a signal output terminal used to output a faulty signal. | 11-18-2010 |
324768000 | Bipolar transistor | 1 |
20080204068 | METHOD FOR ESTIMATING DEFECTS IN AN NPN TRANSISTOR ARRAY - A method for testing bipolar transistors in an integrated circuit includes first measuring first conductances of leakage paths between collectors and emitters of a first plurality of bipolar transistors with a known number of defects, calculating a per defect conductance value using the measured first conductances and the known number of defects to derive the linear relation. The method then measures second conductances of leakage path between collectors and emitters of a second plurality of bipolar transistors under test and having an unknown number of defects. Using the measured leakage path current from the second conductances and the linear relation, the number of defects related to the second plurality of bipolar transistors under test may be accurately determined. | 08-28-2008 |
324769000 | Field effect transistor | 32 |
20080224725 | TEST CIRCUIT, WAFER, MEASURING APPARATUS, MEASURING METHOD, DEVICE MANUFACTURING METHOD AND DISPLAY APPARATUS - There is provided a wafer on which a plurality of electronic devices and circuits under test are to be formed, where each circuit under test includes a plurality of transistors under measurement provided in electrically parallel, a selecting section which sequentially selects the respective transistors under measurement, and an output section which sequentially outputs the source voltages of the transistors under measurement sequentially selected by the selecting section. | 09-18-2008 |
20080246506 | APPARATUS AND METHOD FOR MEASURING EFFECTIVE CHANNEL - An apparatus and a method for measuring an effective channel. The apparatus includes an automatic measurement system including a testing terminal for a substrate, a switching matrix disposed at one side of the automatic measurement system, a leakage current measuring device and a capacitance measuring device electrically connected to the switching matrix by a predetermined terminal, and a controller which controls the automatic measurement system, the leakage current measuring device, and the capacitance measuring device. | 10-09-2008 |
20080284460 | METHOD AND APPARATUS FOR STATISTICAL CMOS DEVICE CHARACTERIZATION - A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures. | 11-20-2008 |
20080284461 | ACTIVE CANCELLATION MATRIX FOR PROCESS PARAMETER MEASUREMENTS - An active cancellation matrix for process parameter measurements provides feedback paths for each test location wherein each feedback path is used to sense the applied voltage and the sensed voltage is used to adjust the source voltage for any variations along the input path. The devices under test are arranged in a row and column array, and the feedback and voltage input paths are formed along respective rails which extend generally parallel to a row of devices under test. Selectors are used to selectively route the outputs of the test nodes to a measurement unit such as a current sensor. The input voltages can be varied to establish current-voltage (I-V) curves for the devices under various conditions. In the example where the devices under test are transistors, each source input includes three voltage inputs (rails) for a drain voltage, a source voltage, and a gate voltage. | 11-20-2008 |
20080284462 | MECHANICAL STRESS CHARACTERIZATION IN SEMICONDUCTOR DEVICE - Methods of characterizing a mechanical stress level in a stressed layer of a transistor and a mechanical stress characterizing test structure are disclosed. In one embodiment, the test structure includes a first test transistor including a first stress level; and at least one second test transistor having a substantially different second stress level. A testing circuit can then be used to characterize the mechanical stress level by comparing performance of the first test transistor and the at least one second test transistor. The type of test structure depends on the integration scheme used. In one embodiment, at least one second test transistor is provided with a substantially neutral stress level and/or an opposite stress level from the first stress level. The substantially neutral stress level may be provided by either rotating the transistor, removing the stressed layer causing the stress level or de-stressing the stressed layer causing the stress layer. | 11-20-2008 |
20080290892 | EVALUATION DEVICE AND EVALUATION METHOD USING EVALUATION DEVICE - In an evaluation device a plurality of evaluation cells, a signal wiring for applying a voltage to the evaluation cells, and an output terminal pad for a signal taking out wiring for measuring outputs from the evaluation cells through a signal taking out wiring are provided on an insulating substrate. Thus, the in-plane distribution of electric characteristics can be easily measured. Further, the electric characteristics related to the particle diameter of the crystal of a poly-crystal silicon film are evaluated so that the in-plane unevenness of the particle diameter of the crystal of the poly-crystal silicon film can be managed. | 11-27-2008 |
20080309365 | Method for Determining Time Dependent Dielectric Breakdown - The current invention provides a method of determining the lifetime of a semiconductor device due to time dependent dielectric breakdown (TDDB). This method includes providing a plurality of samples of dielectric layer disposed as a gate dielectric layer of a MOS transistor, approximating a source/drain current density distribution as a first function of voltage applied on the samples, approximating a substrate current density distribution as a second function of voltage applied on the samples, approximating a dielectric layer lifetime distribution as a third function of source/drain current density and substrate current density in the samples, deriving, from the first, second, and the third functions, an empirical model wherein a dielectric layer lifetime is a function of voltage applied thereon, and using the model to determine dielectric layer lifetime at a pre-determined operating gate voltage. | 12-18-2008 |
20080315907 | Methods of Operating an Electronic Circuit for Measurement of Transistor Variability and the Like - An electronic circuit includes an output terminal and at least a first measuring FET. The second drain-source terminals of a plurality of FETS to be tested are interconnected with the first drain-source terminal of the first measuring FET and the output terminal. The second drain-source terminal of the first measuring FET is interconnected with a first biasing terminal. The first drain-source terminals of the FETS to be tested are interconnected with a second biasing terminal. A state machine is coupled to the gates of the FETS to be tested and the gate of the first measuring FET. The state machine is configured to energize the gate of the first measuring FET and to sequentially energize the gates of the FETS to be tested, so that an output voltage appears on the output terminal. Circuitry to compare the output voltage to a reference value is also provided. The gate of the first measuring field effect transistor is energized; the gates of the field effect transistors to be tested are sequentially energized, whereby an output voltage appears on the output terminal; and the output voltage is compared to the reference value. | 12-25-2008 |
20090009209 | Multiple Point Gate Oxide Integrity Test Method and System for the Manufacture of Semiconductor Integrated Circuits - A method for testing a semiconductor wafer using an in-line process control, e.g., within one or more manufacturing processes in a wafer fabrication facility and/or test/sort operation. The method includes transferring a semiconductor wafer to a test station. The method includes applying an operating voltage on a gate of a test pattern on a semiconductor wafer using one or more probing devices. The method includes measuring a first leakage current associated with the operating voltage. If the measured first current is higher than a first predetermined amount, the device is an initial failure. If the measured first current is below the first predetermined amount, the device is subjected to a second voltage. The method includes applying the second voltage on the gate of the test pattern on the semiconductor wafer and measuring a second leakage current associated with the second voltage. If the second measured leakage current is higher than a second predetermined amount, the device is an extrinsic failure. If the second measured leakage current is below the second predetermined amount, the device a good device. The method provides a way to monitor gate oxide integrity and/or process stability using extrinsic measurements according to a specific embodiment. The method includes determining a breakdown voltage associated with the second measured leakage value. In a preferred embodiment, the second measured leakage current is characterized as extrinsic information and the breakdown voltage is characterized as intrinsic information. | 01-08-2009 |
20090021280 | Method and test system for determining gate-to-body current in a floating body FET - In one disclosed embodiment, the present method for determining a gate-to-body current for a floating body FET comprises measuring at least three unique gate-to-body currents corresponding to at least three unique body-tied FET structures, determining at least three unique relationships between the at least three unique gate-to-body currents and at least three gate-to-body current density components for the at least three unique body-tied FET structures, and utilizing those at least three unique relationships to determine the at least three gate-to-body current density components; wherein one of the gate-to-body current density components is used to determine the gate-to-body current for the floating body FET. In one embodiment, a test structure implements a method for determining a gate-to-body current in a floating body FET. The determined gate-to-body current may be used to predict hysteresis in the floating body FET. | 01-22-2009 |
20090033355 | Method And Apparatus To Measure Threshold Shifting Of A MOSFET Device And Voltage Difference Between Nodes - An on-chip circuit to quantitatively measure threshold voltage shifts of a MOSFET. The circuit includes a programmable Vt reference sensor; a programmable Vt monitoring sensor; and a comparator for receiving inputs from the reference and monitoring sensors providing an output flag signal. The shifting of the MOSFET device voltage threshold monitors process variations, geometry sensitivity, plasma damage, stress, and hot carriers and other device damages. The same circuit also measures voltage differences between any two nodes in an integrated circuit chip or wafer. | 02-05-2009 |
20090108865 | METHOD AND APPARATUS FOR ARRAY-BASED ELECTRICAL DEVICE CHARACTERIZATION - An electronic circuit to determine current-voltage characteristics of a plurality of electronic devices under test. The electronic circuit is comprised of a plurality of individual test cells, each of the plurality of test cells is configured to electrically couple to a first terminal of one of the plurality of electronic devices under test and to a first current source. A second terminal of each of the plurality of electronic devices under test couples to a second current source. The circuit employs a current-based measurement method. | 04-30-2009 |
20090140763 | METHOD OF MEASURING ON-RESISTANCE IN BACKSIDE DRAIN WAFER - A method of measuring on-resistance in a backside drain wafer includes providing a wafer having a first MOS transistor and a second MOS transistor each having a source and also sharing a drain provided at a backside of the wafer, and then forming a current flow path passing through the first and second MOS transistors, and then measuring a resistance between the sources of the first and second MOS transistors. Accordingly, an on-resistance in a backside drain wafer can be measured without using a chuck. | 06-04-2009 |
20090146678 | SUBSTRATE TESTING CIRCUIT - The present invention relates to a substrate testing circuit comprising a testing bus and a testing signal terminal connected to the testing bus, a signal line to be tested in the substrate being connected to the testing bus via a signal connecting terminal, wherein a plurality of signal access terminals are provided on the testing bus; one testing branch is connected between each the signal access terminal and the testing signal terminal; and resistance values of the testing branches are the same. By means of the present invention, since a plurality of signal access terminals are introduced and the testing branches with the same resistance are added so that input resistances and impedances of testing signals across the display screen are substantially identical without making changes to process flow and device hardware structure, input resistances and impedances of respective signal lines are well averaged, thereby no obvious regional attenuation occurs in the testing signals within the pixel area to be tested irrespective of limitation in size of panel, so as to realize tests for panels with greater sizes. | 06-11-2009 |
20090179661 | SEMICONDUCTOR DEVICE DEFECT TYPE DETERMINATION METHOD AND STRUCTURE - A semiconductor defect type determination method and structure. The method includes providing a semiconductor wafer comprising a first field effect transistor (FET) comprising a first type of structure and a second FET comprising a second different type of structure. A first procedure is performed to determine if a first current flow exists between a first conductive layer formed on the first FET and a second conductive layer formed on the first FET. A second procedure is performed to determine if a second current flow exists between a third conductive layer formed the second FET and a fourth conductive layer formed on the second FET. A determination is made from combining results of the first procedure and results of the second procedure that the first FET and the second FET each comprise a specified type of defect. | 07-16-2009 |
20090219049 | Method and Apparatus for Testing and Protecting Digital Output Circuits - A method and system for testing and protecting the operability of an output module. An output channel includes a transistor having a gate, a source, and a drain. The output channel drives a load with a load voltage and a load current in dependence upon a gate drive signal applied to the gate. The system determines a voltage threshold and a current threshold and monotonically varies the gate drive signal from a starting value for a predetermined time interval while monitoring the load current and the load voltage. The system returns the gate drive signal to the starting value if any of the load voltage reaches the voltage threshold, the load current reaches the current threshold, or a predetermined time interval expires indicating the condition of the output module. | 09-03-2009 |
20090251167 | Array-Based Early Threshold Voltage Recovery Characterization Measurement - A method and test circuit provide measurements to aid in the understanding of time-varying threshold voltage changes such as negative bias temperature instability and positive bias temperature instability. In order to provide accurate measurements during an early stage in the threshold variation, a current generating circuit is integrated on a substrate with the device under test, which may be a device selected from among an array of devices. The current generating circuit may be a current mirror that responds to an externally-supplied current provided by a test system. A voltage source circuit may be included to hold the drain-source voltage of the transistor constant, although not required. A stress is applied prior to the measurement phase, which may include a controllable relaxation period after the stress is removed. | 10-08-2009 |
20090267634 | Switch Module for Semiconductor Characteristic Measurement and Measurement Method of Semiconductor Characteristics - A switch module is disclosed for semiconductor characteristic measurement and a semiconductor characteristic measurement method is disclosed with which the impact of the recovery effect after stress signal elimination is reduced in BTI testing. The switch module for semiconductor characteristic measurement includes a first input terminal for receiving stress signals from a stress signal source, a second input terminal for receiving signals from a first non-stress signal source, a first output terminal for outputting output signals, and a switch part for controlling the connection of the first output terminal and the first input terminal or the second input terminal, wherein the switch part detects a first voltage transition of the signals transmitted to the second input terminal and modifies the connection. | 10-29-2009 |
20090295422 | COMPENSATION SCHEME FOR MULTI-COLOR ELECTROLUMINESCENT DISPLAY - A method of compensating for changes in the characteristics of transistors and electroluminescent devices in an electroluminescent display, includes: providing an electroluminescent display having a two-dimensional array of subpixels arranged forming each pixel having at least three subpixels of different colors, with each having an electroluminescent device and a drive transistor, wherein each electroluminescent device is driven by the corresponding drive transistor; providing in each pixel a readout circuit for one of the subpixels of a specific color having a first readout transistor and a second readout transistor connected in series; using the readout circuit to derive a correction signal based on the characteristics of at least one of the transistors in the specific color subpixel, or the electroluminescent device in the specific color subpixel, or both; and using the correction signal to adjust the drive signals. | 12-03-2009 |
20090295423 | COMPENSATION SCHEME FOR MULTI-COLOR ELECTROLUMINESCENT DISPLAY - A method of determining characteristics of transistors and electroluminescent devices, includes: providing an electroluminescent display; providing for pairs of electroluminescent devices drive circuits and a single readout line, each drive circuit including a readout transistor electrically connected to the readout line; providing a first voltage source; providing a second voltage source; providing a current source; providing a current sink; providing a test voltage source; providing a voltage measurement circuit; sequentially testing the drive transistors to provide a first signal representative of characteristics of the drive transistor of the first drive circuit and a second signal representative of characteristics of the drive transistor of the second drive circuit, whereby the characteristics of each drive transistor are determined; and simultaneously testing the first and second electroluminescent devices to provide a third signal representative of characteristics of the pair of electroluminescent devices, whereby the characteristics of both electroluminescent devices are determined. | 12-03-2009 |
20090309625 | ELECTRONIC CIRCUIT FOR MEASUREMENT OF TRANSISTOR VARIABILITY AND THE LIKE - An electronic circuit includes an output terminal and at least a first measuring FET. The second drain-source terminals of a plurality of FETS to be tested are interconnected with the first drain-source terminal of the first measuring FET and the output terminal. The second drain-source terminal of the first measuring FET is interconnected with a first biasing terminal. The first drain-source terminals of the FETS to be tested are interconnected with a second biasing terminal. A state machine is coupled to the gates of the FETS to be tested and the gate of the first measuring FET. The state machine is configured to energize the gate of the first measuring FET and to sequentially energize the gates of the FETS to be tested, so that an output voltage appears on the output terminal. Circuitry to compare the output voltage to a reference value is also provided. The gate of the first measuring field effect transistor is energized; the gates of the field effect transistors to be tested are sequentially energized, whereby an output voltage appears on the output terminal; and the output voltage is compared to the reference value. | 12-17-2009 |
20090309626 | SYSTEMS AND METHODS FOR ADJUSTING THRESHOLD VOLTAGE - Systems and methods for adjusting threshold voltage. A threshold voltage of a transistor of an integrated circuit is measured. A bias voltage, which when applied to a body well of the transistor corrects a difference between the threshold voltage and a desired threshold voltage for the transistor, is determined. The bias voltage is encoded into non-volatile storage on the integrated circuit. The non-volatile storage can be digital and/or analog. | 12-17-2009 |
20090315585 | TRANSISTOR DIAGNOSTIC CIRCUIT - In one embodiment, a diagnostic circuit is used to test the on-resistance of a transistor. | 12-24-2009 |
20100066403 | TEST APPARATUS AND TEST METHOD - Provided is A test apparatus that tests a device under test, including a power supply section that supplies power to a power supply terminal of the device under test; a power supply control section that controls the power supply section to output the power at a plurality of voltage levels; a current measuring section that measures, at each voltage level, a current value of a quiescent current of the device under test, the quiescent current being supplied to the power supply terminal of the device under test by the power supply section; and an analyzing section that analyzes whether a defect is present in the device under test by using at least three current values from among the current values measured by the current measuring section at the plurality of voltage levels. | 03-18-2010 |
20100097091 | Methodology for Bias Temperature Instability Test - A method for performing a bias temperature instability test on a device includes performing a first stress on the device. After the first stress, a first measurement is performed to determine a first parameter of the device. After the first measurement, a second stress is performed on the device, wherein only the first parameter is measured between the first stress and the second stress. The method further includes performing a second measurement to determine a second parameter of the device after the second stress. The second parameter is different from the first parameter. | 04-22-2010 |
20100097092 | CLOSED LOOP FEEDBACK CONTROL OF INTEGRATED CIRCUITS - Systems and methods for closed loop feedback control of integrated circuits. In one embodiment, a plurality of controllable inputs to an integrated circuit is adjusted to achieve a predetermined value of a dynamic operating indicator of the integrated circuit. An operating condition of an integrated circuit is controlled via closed loop feedback based on dynamic operating indicators of the integrated circuit's behavior. | 04-22-2010 |
20100102845 | Proportional Regulation for Optimized Current Sensor Performance - An integrated circuit device comprises a first transistor having a gate coupled to an output of a first operational amplifier, a second transistor having a threshold voltage proportional to a threshold voltage of the first transistor, the second transistor having a gate coupled to an inverting input of a second operational amplifier, an output of the second operational amplifier coupled to an inverting input of the first operational amplifier, a first resistor coupled between the second transistor gate and the inverting input of the second operational amplifier, and a second resistor coupled between the output of the second operational amplifier and the inverting input of the second operational amplifier, a ratio of the second resistor to the first resistor selected based upon a ratio of a production distribution of a transistor source voltage offset to a production distribution of a transistor threshold voltage mismatch. | 04-29-2010 |
20100156454 | Hot-Electron Injection Testing of Transistors on a Wafer - A hot-carrier injection (HCI) test that permits rapid screening of integrated circuit wafers susceptible to possible HCI-induced failures is disclosed. A method is described that determines transistor stress voltages that results in a transistor HCI-induced post-stress drain current differing from a pre-stress drain current within a desired range. These stress voltages are determined using a wafer with acceptable HCI susceptibility. Additional wafers to be tested are first tested using a described method that uses the determined transistor stress voltages to quickly screen the wafers for HCI susceptibility and, if HCI susceptibility is found, then additional conventional HCI testing may be applied to the susceptible wafers. | 06-24-2010 |
20100164533 | METHOD AND APPARATUS FOR EVALUATING THE EFFECTS OF STRESS ON AN RF OSCILLATOR - Apparatus and methods are disclosed for evaluating degradation of a transistor in a cross coupled pair of an RF oscillator independently. A MOS device can be coupled between a separated center-tap inductor. By appropriately sizing the MOS device and turning the MOS device on during operation of RF oscillator, a good contact can again be made that allows the oscillator to operate at design performance. By turning the MOS device off, the supplies can be separates such that I-V characteristics of both transistors of the cross-coupled pair may be obtained. | 07-01-2010 |
20100164534 | Radiation Sensor and Dosimeter - A semiconductor radiation sensor ( | 07-01-2010 |
20100225348 | METHOD AND APPARATUS FOR STATISTICAL CMOS DEVICE CHARACTERIZATION - A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures. | 09-09-2010 |
20100244884 | TEST APPARATUS AND DRIVER CIRCUIT - Provided is a test apparatus that tests a device under test, comprising a driver circuit that generates an output signal according to a prescribed input pattern and supplies the output signal to the device under test; and a measuring section that judges acceptability of the device under test by measuring a response signal output by the device under test. The driver circuit includes an input terminal that receives the input pattern; a switching section that operates according to a logic value of the input pattern to generate the output signal; and an emphasized component generating section that is provided between the input terminal and the switching section, and that (i) generates an emphasized component according to a prescribed high frequency component of the input pattern and (ii) superimposes the emphasized component onto a voltage supplied to the switching section. | 09-30-2010 |