Entries |
Document | Title | Date |
20080197512 | Process for manufacturing deep through vias in a semiconductor device, and semiconductor device made thereby - A process for manufacturing a through via in a semiconductor device includes the steps of: forming a body having a structural layer, a substrate, and a dielectric layer set between the structural layer and the substrate; insulating a portion of the structural layer to form a front-side interconnection region; insulating a portion of the substrate to form a back-side interconnection region; and connecting the front-side interconnection region and the back-side interconnection region through the dielectric layer. | 08-21-2008 |
20080197513 | BEOL INTERCONNECT STRUCTURES WITH IMPROVED RESISTANCE TO STRESS - A chip is provided which includes a back-end-of-line (“BEOL”) interconnect structure. The BEOL interconnect structure includes a plurality of interlevel dielectric (“ILD”) layers which include a dielectric material curable by ultraviolet (“UV”) radiation. A plurality of metal interconnect wiring layers are embedded in the plurality of ILD layers. Dielectric barrier layers cover the plurality of metal interconnect wiring layers, the dielectric barrier layers being adapted to reduce diffusion of materials between the metal interconnect wiring layers and the ILD layers. One of more of the dielectric barrier layers is adapted to retain compressive stress while withstanding UV radiation sufficient to cure the dielectric material of the ILD layers, making the BEOL structure better capable of avoiding deformation due to thermal and/or mechanical stress. | 08-21-2008 |
20080211114 | SEMICONDUCTOR COMPONENT - A semiconductor component is provided, particularly for LIN bus systems, having an integrated circuit, which on a top side has a plurality of terminal pads for coupling and/or decoupling of electrical signals, and having a plurality of electrically conductive contact reeds, which are electrically connected at least partially by connecting bonding wires to the respectively assigned terminal pads of the integrated circuit. Also, a connecting bonding wire and a shielding bonding wire is provided, which is disposed with both ends on a uniform electric potential, particularly on one of the contact reeds. | 09-04-2008 |
20080224330 | Power delivery package having through wafer vias - An integrated circuit chip package and a method of manufacture thereof are provided. In one embodiment, the integrated circuit chip package comprises a semiconductor die having power and ground routings, a plurality of through wafer vias disposed within the semiconductor die, the through wafer vias connected to the power and ground routings, and a substrate attached to the semiconductor die, the substrate having power and ground leads connected to the through wafer vias for transferring power from the substrate to the semiconductor die. | 09-18-2008 |
20080230928 | Module comprising a semiconductor chip - A module includes a semiconductor chip having at least a first terminal contact surface and a second terminal contact surface. A first bond element made of a material on the basis of Cu is attached to the first terminal contact surface, and a second bond element is attached to the second terminal contact surface. The second bond element is made of a material different from the material of the first bond element or is made of a type of bond element different from the type of the first bond element. | 09-25-2008 |
20080246165 | Novel interconnect for chip level power distribution - A semiconductor device ( | 10-09-2008 |
20080246166 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device that improves adhesion between a resin and a die pad and prevents cracking of the resin includes: a semiconductor chip; a die pad on which the semiconductor chip is mounted; a bonding agent for bonding the semiconductor chip to the die pad; a plurality of inner leads provided at the outer periphery of the die pad; outer leads extending from the inner leads; bonding wires connecting the inner leads to the semiconductor chip mounted on the die pad; and a resin for sealing the inner leads, the die pad, the semiconductor chip, the bonding agent and the bonding wires. The bonding agent is further disposed in all or part of a margin of the die pad at a peripheral portion where the semiconductor chip is mounted, and a plurality of dimples are formed in the surface of the bonding agent in the die pad margin. | 10-09-2008 |
20080258314 | FABRIC TYPE SEMICONDUCTOR DEVICE PACKAGE AND METHODS OF INSTALLING AND MANUFACTURING SAME - A fabric type semiconductor device package is provided. The fabric type semiconductor device package comprises a fabric type printed circuit board comprising a fabric and a lead unit formed by patterning a conductive material on the fabric, a semiconductor device comprising an electrode unit bonded to the lead unit of the fabric type printed circuit board, and a molding unit for sealing the fabric type printed circuit board and the semiconductor device. In the fabric type semiconductor device package according to the present invention, a fabric type printed circuit board formed of fabric is used so that a feeling of an alien substance can be minimized. The fabric type semiconductor device package can be easily installed. The productivity of the fabric type semiconductor device package can be improved. | 10-23-2008 |
20080258315 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD OF THE SAME SEMICONDUCTOR DEVICE - The present invention aims to provide a semiconductor device which can enhance area efficiency, and the semiconductor device includes a plurality of electroconductive member regions formed in a predetermined layer, an insulating film region which is formed in the insulating layer which is an upper layer of the predetermined layer and which covers a region other than at least the plurality of electroconductive member regions, and wiring for making a connection which is formed along the insulating film region and which connects the plurality of electroconductive member regions mutually. | 10-23-2008 |
20080258316 | Power Semiconductor Module - A power semiconductor module having a surface of the power semiconductor chip and an external circuit pattern connected by an aluminum wire, and sealed with an epoxy resin, wherein wire diameter of the aluminum wire is 0.4±0.05 mmφ, and coefficient of linear expansion of the epoxy resin in a rated temperature range of a module is from 15 to 20 ppm/K. | 10-23-2008 |
20080272502 | PACKAGING BOARD AND MANUFACTURING METHOD THEREFOR, SEMICONDUCTOR MODULE AND MANUFACTURING METHOD THEREFOR, AND PORTABLE DEVICE - A method for manufacturing a semiconductor module includes: a first process of forming a conductor on one face of an insulating layer; a second process of exposing the conductor from the other face of the insulating layer; a third process of providing a first wiring layer on an exposed area of the conductor and on the other face of the insulating layer; a fourth process of preparing a substrate on which a circuit element is formed, the second wiring being formed on the substrate; and a fifth process of embedding the conductor in the insulating layer by press-bonding the insulating layer and the substrate in a state where the conductor on which the first wiring layer is provided by the third process is disposed counter to the second wiring layer. Wiring is formed without causing damaging to the circuit element. | 11-06-2008 |
20080296784 | Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device - A semiconductor device is disclosed which includes a tab ( | 12-04-2008 |
20090001611 | ADHESIVE SHEET FOR MANUFACTURING SEMICONDUCTOR DEVICE, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE USING THE SHEET, AND SEMICONDUCTOR DEVICE OBTAINED BY THE METHOD - The adhesive sheet for manufacturing a semiconductor device is an adhesive sheet for manufacturing a semiconductor device used when a semiconductor element is adhered to an adherend and the semiconductor element is wire-bonded, and is a peelable adhesive sheet in which the 180 degree peeling adhesive strength against a silicon wafer is 5 (N/25 mm width) or less. | 01-01-2009 |
20090020892 | SELECTIVELY ALTERING A PREDETERMINED PORTION OR AN EXTERNAL MEMBER IN CONTACT WITH THE PREDETERMINED PORTION - A method for selectively altering a predetermined portion of an object or an external member in contact with the predetermined portion of the object is disclosed. The method includes selectively electrically addressing the predetermined portion, thereby locally resistive heating the predetermined portion, and exposing the object, including the predetermined portion, to the external member. | 01-22-2009 |
20090020893 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH TRIPLE FILM SPACER - An integrated circuit package in package system includes: providing a substrate with a first wire-bonded die mounted thereover, and connected to the substrate with bond wires; mounting a triple film spacer above the first wire-bonded die, the triple film spacer having fillers in a first film and in a third film, and having a second film separating the first film and the third film, and the bond wires connecting the first wire-bonded die to the substrate are embedded in the first film; and encapsulating the first wire-bonded die, the bond wires, and the triple film spacer with an encapsulation. | 01-22-2009 |
20090032975 | Semiconductor Device and Method of Providing Common Voltage Bus and Wire Bondable Redistribution - A semiconductor wafer contains a plurality of semiconductor die. The wafer has contact pads formed over its surface. A passivation layer is formed over the wafer. A stress buffer layer is formed over the passivation layer. The stress buffer layer is patterned to expose the contact pads. A metal layer is deposited over the stress buffer layer. The metal layer is a common voltage bus for the semiconductor device in electrical contact with the contact pads. An adhesion layer, barrier layer, and seed layer is formed over the wafer in electrical contact with the contact pads. The metal layer is mounted to the seed layer. Solder bumps or other interconnect structures are formed over the metal layer. A second passivation layer is formed over the metal layer. In an alternate embodiment, a wirebondable layer can be deposited over the metal layer and wirebonds connected to the metal layer. | 02-05-2009 |
20090045529 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - There is provided a method of manufacturing a semiconductor device. The method includes the successive steps of: (a) providing a semiconductor substrate; (b) forming a plurality of semiconductor chips having electrode pads on the semiconductor substrate; (c) forming internal connection terminals on the electrode pads; (d) forming an insulating layer on the plurality of semiconductor chips to cover the internal connection terminals; (e) forming a metal layer on the insulating layer; (f) pushing a whole area of the metal layer to bring the metal layer into contact with upper end portions of the internal connection terminals; (g) pushing portions of the metal layer which contact the upper end portions of the internal connection terminals, thereby forming first recesses in the internal connection terminals, and thereby forming second recesses in the metal layer; and (h) forming wiring patterns by etching the metal layer. | 02-19-2009 |
20090051050 | CORNER I/O PAD DENSITY - An integrated circuit die has a plurality of I/O cells disposed about its periphery, each I/O cell having an I/O bonding pad. A first group of I/O cells is disposed at the periphery of the die at locations away from corners of the die, each of the first group of I/O cells having an I/O pad disposed thereon and spaced at a first distance from the periphery of the die. A second group of I/O cells is disposed at the periphery of the die at locations away from corners of the die, each of the second group of I/O cells having an I/O pad disposed thereon and spaced at a distance from the periphery of the die more than the first distance, the distance increasing as a function of the proximity of each I/O cell to a corner of the die. | 02-26-2009 |
20090057923 | Methods of Fabricating Semiconductor Devices and Structures Thereof - Methods of fabricating semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming a first insulating material over the semiconductor wafer, and forming a plurality of first features and a plurality of second features in the first insulating material. The plurality of first features is removed, leaving an unfilled pattern in the first insulating material. The unfilled pattern in the first insulating material is filled with a second insulating material. | 03-05-2009 |
20090057924 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR MOUNTING STRUCTURE, AND ELECTRO-OPTICAL DEVICE - A semiconductor device includes a base substrate including an internal circuit, a resin protrusion part that is disposed to protrude on an active face side of the base substrate, and a plurality of terminals that are formed by including an island-shaped conductive film disposed on the resin protrusion part. The plurality of terminals includes a terminal that a conductive state with the internal circuit, and a wiring line that electrically connects at least two terminals among the plurality of terminals is disposed on the active face side. | 03-05-2009 |
20090057925 | Semiconductor apparatus - A semiconductor apparatus capable of detecting a crack generated in a semiconductor chip while the design freedom, the layout freedom of a wiring, the layout efficiency of LSI, and the layout efficiency of a package substrate are improved. The semiconductor apparatus according to the invention includes a semiconductor chip having a multilayered wiring structure; plural electrode pads being formed on a top surface along the outer periphery of the semiconductor chip; and a wiring being coupled to a first electrode pad and a second electrode pad selected from the plural electrode pads and formed along the entire outer periphery of the semiconductor chip in plan view. The wiring includes a first wiring and a second wiring that are formed on different layers, and the first wiring and the second wiring are connected in series by a connection plug. | 03-05-2009 |
20090057926 | Semiconductor apparatus - A semiconductor apparatus capable of simply detecting a crack generated in plural semiconductor chips while the design freedom is improved, includes a first semiconductor chip and a second semiconductor chip that is laminated on the first semiconductor chip, in which a first wiring that is formed along the outer periphery of the first semiconductor chip and a second wiring that is formed along the outer periphery of the second semiconductor chip are connected in series. | 03-05-2009 |
20090065954 | Packaging Method For Wideband Power Using Transmission Lines - Embodiments of the invention relate to a package design incorporating an ultra-low characteristic impedance transmission line (T-line) bundle. The T-line bundle can extend from inside the package to outside the package in order to provide power delivery and power interconnect for a chip. In one embodiment, the T-line bundle can be attached at the die. In another embodiment, the T-line bundle can be attached to the package substrate. The T-line bundle can be a stack of parallel planar transmission line strips in a periodic pattern where the dielectric material of the strips can be a high-k dielectric and can be flexible, semi-rigid, or precision rigid. | 03-12-2009 |
20090065955 | METHOD AND STRUCTURES FOR ACCELERATED SOFT-ERROR TESTING - An integrated circuit, method of forming the integrated circuit and a method of testing the integrated circuit for soft-error fails. The integrated circuit includes: a silicon substrate; a dielectric layer formed over the substrate; electrically conductive wires formed in the dielectric layer, the wires interconnecting semiconductor devices formed in the substrate into circuits; and an alpha particle emitting region in the integrated circuit chip proximate to one or more of the semiconductor devices. The method includes exposing the integrated circuit to an artificial flux of thermal neutrons to cause fission of atoms in the alpha particle emitting region into alpha particles and other atoms. | 03-12-2009 |
20090072415 | INTEGRATED CIRCUIT DEVICE HAVING A GAS-PHASE DEPOSITED INSULATION LAYER - An integrated circuit device includes a semiconductor device having an integrated circuit. A gas-phase deposited insulation layer is disposed on the semiconductor device, and a conducting line is disposed over the gas-phase deposited insulation layer. | 03-19-2009 |
20090072416 | Semiconductor device, and manufacturing method of semiconductor device - In a technique connecting between bonding pads of semiconductor chips, contact between wires is prevented. A semiconductor device of the present embodiment is provided with a semiconductor chip | 03-19-2009 |
20090085229 | AUDIO POWER AMPLIFIER PACKAGE - An audio power amplifier package includes a non-signal lead, a first non-signal pad, a second non-signal pad and a plurality of bonding wires. The first non-signal pad and the second non-signal pad are disposed on a substrate. The bonding wires connect the non-signal lead to the first non-signal pad and the second non-signal pad respectively. | 04-02-2009 |
20090102065 | BONDING PAD FOR ANTI-PEELING PROPERTY AND METHOD FOR FABRICATING THE SAME - A bonding pad includes an insulation layer with a trench, and a conductive pattern one portion of which is buried into the trench and the other portion of which is formed in a plate shape over the insulation layer. | 04-23-2009 |
20090102066 | Chip package structure and method of manufacturing the same - A chip package structure and a method of manufacturing the same are provided. The chip package structure includes a package portion and a plurality of external conductors. The package portion includes a distribution layer, a chip, a plurality internal conductors and a sealant. The distribution layer has a first surface and a second surface, and the chip is disposed on the first surface. Each internal conductor has a first terminal and a second terminal. The first terminal is disposed on the first surface. The sealant is disposed on the first surface for covering the chip and partly encapsulating the internal conductors, so that the first terminal and the second terminal of each internal conductor are exposed from the sealant. The external conductors disposed on the second surface of the distribution layer of the package portion are electrically connected to the internal conductors. | 04-23-2009 |
20090102067 | ELECTRICALLY ENHANCED WIREBOND PACKAGE - Consistent with an example embodiment, there is an integrated circuit (IC) device in a packaging having electrically insulated connections. The IC device comprises a semiconductor device ( | 04-23-2009 |
20090108474 | JUNCTION STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A junction structure and a method of manufacturing the same are provided which can achieve stable wire bonding between a Poly-Si film bonding pad and an Al wire. The junction structure is made up of a SiO | 04-30-2009 |
20090127720 | DROP-MOLD CONFORMABLE MATERIAL AS AN ENCAPSULATION FOR AN INTEGRATED CIRCUIT PACKAGE SYSTEM - An integrated circuit package system includes: providing an integrated circuit; mounting a lead on the periphery of the integrated circuit; connecting the integrated circuit to the lead with an interconnect; and forming a conformable material by pressing the conformable material on the integrated circuit, the lead, and the interconnect. | 05-21-2009 |
20090134530 | WIRING SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - There is provided a wiring substrate. The wiring substrate includes a wiring member and a reinforcing layer. The wiring member is formed by layering insulating layers and wiring layers and has connection pads thereon. The reinforcing layer is provided on the wiring member to surround the connection pads and has a plurality of concave-convex portions thereon. | 05-28-2009 |
20090146321 | WIRE BONDING PERSONALIZATION AND DISCRETE COMPONENT ATTACHMENT ON WIREBOND PADS - Inner wire bond pads are formed within a peripheral region of a semiconductor chip and at least one bonding wire is attached to the inner wire bond pads. The semiconductor chip may be customized for a specific configuration of choice by wiring inner wire bond pads. Alternately, the bonding wires may be employed to reinforce a power network or a ground network. Further, the bonding wire may serve as a passive radio frequency (RF) component. In addition, the bonding wire may be used a heat conduction path to transfer heat from the semiconductor chip to the upper package housing. | 06-11-2009 |
20090160070 | METAL LINE IN A SEMICONDUCTOR DEVICE - A semiconductor having a metal line and a method of manufacturing a metal line in a semiconductor device is disclosed. In one example embodiment, a method of manufacturing a metal line in a semiconductor device includes various acts. A metal film for a metal line is formed on an interlayer dielectric layer of a semiconductor substrate. A silicon oxide hard mask film is formed on the metal film. A bottom anti-reflection (BARC) layer is formed on the hard mask film. The BARC layer, the hard mask film, and the metal film are selectively dry etched to form a metal line. | 06-25-2009 |
20090166892 | CIRCUIT BOARD FOR SEMICONDUCTOR PACKAGE HAVING A REDUCED THICKNESS, METHOD FOR MANUFACTURING THE SAME, AND SEMICONDUCTOR PACKAGE HAVING THE SAME - A circuit board includes an insulation body having a first surface and a second surface facing away from the first surface. The circuit board comprises a hardened insulation material. Circuit patterns having first conductive surfaces, second conductive surfaces facing away from the first conductive surfaces, and side surfaces connecting the first and second conductive surfaces embedded in the insulation body. That is, the second conductive surfaces and the side surfaces are embedded in the insulation body through the first surface of the insulation body, and the first conductive surfaces are exposed out of the insulation body. Recognition patterns are formed on the second surface of the insulation body. | 07-02-2009 |
20090166893 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention includes: an insulating substrate; a metal bonding member being disposed on the insulating substrate and having a porous region and a metal region, the porous region being provided with multiple pores therein and being adjacent to the metal region in a plane direction of the insulating substrate; a solder material impregnated into the pores; a semiconductor element disposed on the surface of the porous region in the metal bonding member; a bonding wire connected to the surface of the metal region in the metal bonding member. This makes it possible to provide a semiconductor device having improved electrical conductivity and thermal conductivity, and enabling the weight reduction. | 07-02-2009 |
20090179336 | Electronic Module and a Method of Assembling Such a Module - The module is of the type comprising an electronic component provided with a conductive face that is electrically connected to a connection member of the component by means of a conductor that is corrugated at least in part so as to define an alternating sequence of oppositely-directed arcs, a first series of arcs being connected to the conductive face of the electronic component. The conductor also includes a second series of arcs opposite to the arcs of the first series and interposed between the arcs of the first series, the second series of arcs being connected to the conductive face of the connection member. | 07-16-2009 |
20090194888 | SEMICONDUCTOR DEVICE INCLUDING WIRING AND MANUFACTURING METHOD THEREOF - A semiconductor construct is provided which has a semiconductor substrate, an external connection electrode, and an electrode enveloping layer for enveloping the external connection electrode. Also, a base plate is provided which includes a wiring having a first opening corresponding to the external connection electrode. Subsequently, the base plate is removed after the semiconductor construct is fixed to the base plate, and a second opening which reaches the external connection electrode is formed on the electrode enveloping layer corresponding to the first opening of the wiring. Then, a connection conductor for electrically connecting the wiring and the external connection electrode is formed. | 08-06-2009 |
20090200686 | ELECTRICAL CONNECTING STRUCTURE AND BONDING STRUCTURE - A electrical connecting structure including a conductive pad, a polymer bump and a patterned conductive layer is provided. The conductive pad is on a substrate and the polymer bump is disposed over the substrate. The patterned conductive layer is disposed on the polymer bump and electrically connects to the conductive pad, wherein the patterned conductive layer covers a portion of the polymer bump and exposes another portion of the polymer bump. | 08-13-2009 |
20090206494 | WIRING OVER SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHODS FOR MANUFACTURING THEREOF - A wiring over a substrate capable of reducing particles between wirings and a method for manufacturing the wiring is disclosed. A wiring over a substrate capable of preventing short-circuiting between wirings due to big difference in projection and depression between wirings and a method for manufacturing the wiring is also disclosed. Further, a wiring over a substrate capable of preventing cracks in the insulating layer due to stress at the edge of a wiring or particles and a method for manufacturing the wiring is also disclosed. According to the present invention, a method for manufacturing a wiring over a substrate is provided that comprises the steps of: forming a first conductive layer over an insulating surface; forming a first mask pattern over the first conductive layer; forming a second mask pattern by etching the first mask pattern under a first condition, simultaneously, forming a second conductive layer having a side having an angle of inclination cross-sectionally by etching the first conductive layer; and forming a third conductive layer and a third mask pattern by etching the second conductive layer and the second mask pattern under a second condition; wherein a selective ratio under the first condition of the first conductive layer to the first mask pattern is in a range of 0.25 to 4, and a selective ratio under the second condition of the second conductive layer to the second mask pattern is larger than that under the first condition. | 08-20-2009 |
20100001413 | Semiconductor Device and Semiconductor Device Manufacturing Method - The present invention aims at providing a semiconductor device capable of reliably preventing a wire bonded to an island from being disconnected due to a thermal shock, a temperature cycle and the like in mounting and capable of preventing remarkable increase in the process time. In the semiconductor device according to the present invention, a semiconductor chip is die-bonded to the surface of an island, one end of a first wire is wire-bonded to an electrode formed on the surface of the semiconductor chip to form a first bonding section and the other end of the first wire is wire-bonded to the island to form a second bonding section, while the semiconductor device is resin-sealed. A double bonding section formed by wire-bonding a second wire is provided on the second bonding section of the first wire wire-bonded onto the island. | 01-07-2010 |
20100001414 | MANUFACTURING A SEMICONDUCTOR DEVICE VIA ETCHING A SEMICONDUCTOR CHIP TO A FIRST LAYER - A method of manufacturing a semiconductor device. The method includes providing a semiconductor chip including contact elements on a first face and a first layer between the first face and a second face opposite the first face. Placing the semiconductor chip on a carrier with the contact elements facing the carrier and etching the semiconductor chip until the first layer is reached. | 01-07-2010 |
20100007034 | LENS SUPPORT AND WIREBOND PROTECTOR - A wirebond protector has an elongated shape that corresponds to the elongated array of wirebonds along the edge of a microelectronic device that connect a semiconductor die to electrical conductors on a substrate. In making the microelectronic device with wirebond protection, wirebonds are first formed in the conventional manner The wirebond protector is then attached to the device in an orientation in which it extends along the array of wirebonds to at least partially cover the wirebonds. | 01-14-2010 |
20100019396 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device may be fabricated according to a method that reduces stain difference of a passivation layer in the semiconductor device. The method may include forming top wiring patterns in a substrate, depositing a primary undoped silicate glass (USG) layer on the top wiring patterns to fill a gap between the top wiring patterns, and coating a SOG layer on the substrate on which the primary USG layer has been deposited. Next, the SOG layer on the surface of the substrate may be removed until the primary USG layer is exposed, and a secondary USG layer may be deposited on the substrate on which the primary USG layer has been exposed. | 01-28-2010 |
20100019397 | ELECTRICAL CONNECTIONS FOR MULTICHIP MODULES - Conductive lines are formed on a wafer containing multiple circuits. The conductive lines are isolated from the circuits formed within the wafer. Chips are mounted on the wafer and have their chip pads connected to the conductive lines of the wafer. The wafer may then be protected with a packaging resin and singulated | 01-28-2010 |
20100025864 | SHIELDED WIREBOND - A wirebond interconnect structure, having ground pads and signal pads, to which wirebonds are electrically coupled, disposed on a component, is provided and includes a first coating to insulate at least the wirebonds and the signal pads with at least the ground pads exposed, and a second coating, surrounding the first coating, in electrical communication with the ground pads. The first coating is sufficiently thick to achieve a consistent characteristic impedance when the second coating is applied. | 02-04-2010 |
20100044885 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A semiconductor device and manufacturing method. One embodiment provides at least two semiconductor chips. A dielectric material is applied to the at least two semiconductor chips to attach the at least two semiconductor chips to each other. A portion of the dielectric material is selectively removed between the at least two semiconductor chips to form at least one recess in the dielectric material. Metal particles including paste is applied to the at least one recess in the dielectric material. | 02-25-2010 |
20100072633 | Semiconductor apparatus with thin semiconductor film - A semiconductor apparatus includes a substrate having at least one terminal, a thin semiconductor film including at least one semiconductor device, the thin semiconductor film being disposed and bonded on the substrate; and an individual interconnecting line formed as a thin conductive film extending from the semiconductor device in the thin semiconductor film to the terminal in the substrate, electrically connecting the semiconductor device to the terminal. Compared with conventional semiconductor apparatus, the invented apparatus is smaller and has a reduced material cost. | 03-25-2010 |
20100084773 | SEMICONDUCTOR DEVICE AND METHOD OF BONDING WIRES BETWEEN SEMICONDUCTOR CHIP AND WIRING SUBSTRATE - A wiring substrate and a semiconductor chip mounted on the wiring substrate are connected together via a bonding wire. The distance from each end of the semiconductor chip to a wire bond pad provided on the wiring substrate is smaller than the height of the semiconductor chip. | 04-08-2010 |
20100207280 | Wire bonding method and semiconductor device - After forming a pressure-bonded ball and a ball neck by bonding an initial ball to a pad, a capillary is moved upward, away from a lead, and then downward, thereby the ball neck is trodden on by a face portion that is on the lead side of the capillary. Subsequently, the capillary is moved upward and then toward the lead until the face portion of the capillary is positioned above the ball neck, thereby a wire is folded back toward the lead. Then, the capillary is moved downward such that a side of the wire is pressed by the capillary against the ball neck that has been trodden on. After the capillary is moved obliquely upward toward the lead and then looped toward the lead, the wire is pressure-bonded to the lead. | 08-19-2010 |
20100230828 | MICROELECTRONIC ASSEMBLY WITH IMPEDANCE CONTROLLED WIREBOND AND CONDUCTIVE REFERENCE ELEMENT - A microelectronic assembly can include a microelectronic device having device contacts exposed at a surface thereof and an interconnection element having element contacts and having a face adjacent to the microelectronic device. Conductive elements, e.g., wirebonds connect the device contacts with the element contacts and have portions extending in runs above the surface of the microelectronic device. A conductive layer has a conductive surface disposed at at least a substantially uniform distance above or below the plurality of the runs of the conductive elements. In some cases, the conductive material can have first and second dimensions in first and second horizontal directions which are smaller than first and second corresponding dimensions of the microelectronic device. The conductive material is connectable to a source of reference potential so as to achieve a desired impedance for the conductive elements. | 09-16-2010 |
20100237511 | Structure and Method for Thin Single or Multichip Semiconductor QFN Packages - A semiconductor device has one or more semiconductor chips with active and passive surfaces, wherein the active surfaces include contact pads. The device further has a plurality of metal segments separated from the chip by gaps; the segments have first and second surfaces, wherein the second surfaces are coplanar with the passive chip surface. Conductive connectors span from the chip contact pads to the respective first segment surface. Polymeric encapsulation compound covers the active chip surface, the connectors, and the first segment surfaces, and are filling the gaps so that the compound forms surfaces coplanar with the passive chip surface and the second segment surfaces. In this structure, the device thickness may be only about 250 μm. Reflow metals may be on the passive chip surface and the second segment surfaces. | 09-23-2010 |
20100244280 | METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE - A board on which a wiring having an electrode pad is formed is prepared. A resist film is formed on the board in order to cover the wiring and then the resist film is left on the electrode pad through patterning. An inorganic insulating film is formed on the board in order to cover the wiring and then the resist film is removed, thereby removing the inorganic insulating film provided on the resist film to leave the inorganic insulating film between the wirings. A solder resist layer is formed on the board in order to cover the wiring and then the electrode pad is exposed. | 09-30-2010 |
20100244281 | FLEXIBLE PRINTED WIRING BOARD AND SEMICONDUCTOR DEVICE EMPLOYING THE SAME - Objects of the present invention is to provide a flexible printed wiring board which has a simple structure, which can be produced at low cost, and which can effectively dissipate heat generated by semiconductor chips, and to provide a semiconductor device employing the flexible printed wiring board. The flexible printed wiring board of the invention has an insulating substrate, and a wiring pattern formed of a conductor layer and provided on one surface of the insulating substrate, wherein the wiring pattern includes inner leads for mounting a semiconductor chip and outer leads for input and output wire connection, and a metal layer is adhered to the wiring pattern via an insulating adhesion layer. | 09-30-2010 |
20100244282 | ASSEMBLY OF ELECTRONIC COMPONENTS - An electronic component assembly that has a supporting structure, an integrated circuit die with a plurality of contacts pads, a printed circuit board with a plurality of conductors, the integrated circuit die and the PCB being mounted to the supporting structure by a die attach film such that they are adjacent and spaced from each other and, wire bonds electrically connecting the contact pads to the conductors. An intermediate portion of each of the wire bonds is adhered to the die attach film to lower the profile of the wire bond arcs. | 09-30-2010 |
20100258954 | ELECTRODE STRUCTURE AND ITS MANUFACTURING METHOD, AND SEMICONDUCTOR MODULE - There is a highly reliable semiconductor module having a satisfactory bonding strength in the electrical bonded portion. In the semiconductor module | 10-14-2010 |
20100258955 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor device includes a substrate over one surface of which an electroless plating electrode film is formed; a semiconductor chip mounted over the one surface of the substrate; and a bonding wire which connects the semiconductor chip and one surface of the electroless plating electrode film, a recessed depth which is a difference between a lowermost height of a bonding portion of the one surface of the electroless plating electrode film to the bonding wire, and an uppermost height of the one surface other than the bonding portion being equal to or less than 1.5 μm. | 10-14-2010 |
20100276817 | SEMICONDUCTOR DEVICE - A protective coating is formed on the surface of a semiconductor device. The surface is located on the side to which an extension portion of a wire connected to a pad of the semiconductor device is pulled. The protective coating is formed such that its height decreases toward the pad. | 11-04-2010 |
20100289160 | LENS SUPPORT AND WIREBOND PROTECTOR - A wirebond protector has an elongated shape that corresponds to the elongated array of wirebonds along the edge of a microelectronic device that connect a semiconductor die to electrical conductors on a substrate. In making the microelectronic device with wirebond protection, wirebonds are first formed in the conventional manner The wirebond protector is then attached to the device in an orientation in which it extends along the array of wirebonds to at least partially cover the wirebonds. | 11-18-2010 |
20100295191 | WIRING BOARD, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING WIRING BOARD AND SEMICONDUCTOR DEVICE - In the wiring board, insulating layers and wiring layers are alternately laminated, and the wiring layers are electrically connected by the vias. The wiring board includes first terminals arranged in a first surface and embedded in an insulating layer, second terminals arranged in a second surface opposite to the first surface and embedded in an insulating layer, and lands arranged in an insulating layer and in contact with the first terminals. The vias electrically connect the lands and the wiring layers laminated alternately with the insulating layers. No connecting interface is formed at an end of each of the vias on the land side but a connecting interface is formed at an end of each of the vias on the wiring layer side. | 11-25-2010 |
20100320623 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A multi-pin semiconductor device with improved reliability. In a multi-pin BGA, a plurality of wires for electrically coupling a semiconductor chip and a wiring substrate include a plurality of short and thin first wires located in an inner position and a plurality of second wires longer and thicker than the first wires. Since resin flows in from between thin first wires during resin molding, the resin pushes out air, thereby suppressing formation of voids. The reliability of the multi-pin BGA is thus improved. | 12-23-2010 |
20110018144 | WIRING BOARD AND SEMICONDUCTOR DEVICE - A wiring board includes a core substrate including an insulation base member; linear conductors configured to pierce from a first surface of the insulation base member to a second surface of the insulation base member; a ground wiring group including a first ground wiring formed on the first surface of the core substrate, and a belt-shaped second ground wiring formed on the second surface of the core substrate and electrically connected to the first ground wiring by way of a part of the linear conductors; and an electric power supply wiring group including a first electric power supply wiring formed on the first surface, and a second electric power supply wiring formed on the second surface and electrically connected to the first electric power supply wiring by way of a part of the plural linear conductors. | 01-27-2011 |
20110024920 | COMPONENT ARRANGEMENT AND METHOD FOR PRODUCING A COMPONENT ARRANGEMENT - A component assembly including a carrier element including a first contact face and a semiconductor component disposed on the carrier element, wherein the semiconductor component includes a second contact face. The component assembly further includes a contact-making bonding wire, wherein one end of the contact-making bonding wire is connected to the first contact face and a second end of the contact-making bonding wire is connected to the second contact face. The component assembly includes a flow stop bonding wire positioned on the second contact face, wherein the flow stop bonding wire defines on the second contact face a first zone and a second zone. An encapsulation material is applied from the first zone to the first contact face so as to define an encapsulation for the flow stop bonding wire, wherein the flow stop bonding wire prevents an uncontrolled flow of the encapsulation material into the second zone. | 02-03-2011 |
20110062600 | SEMICONDUCTOR ELEMENT MODULE AND METHOD FOR MANUFACTURING THE SAME - An object is to provide a semiconductor element module having high reliability, superior electric connection and thermal connection and capable of securing sufficient cooling performance, and also to provide a method for manufacturing the same. The semiconductor element module ( | 03-17-2011 |
20110084410 | Wiring Substrate for a Semiconductor Chip, and Semiconducotor Package Having the Wiring Substrate - A wiring substrate for a semiconductor chip includes a substrate, first and second wiring layers and a plurality of first and second bonding pads. The substrate has a first surface and a second surface opposite to the first surface, a window extending from the first surface to the second surface to expose chip pads of a semiconductor chip adherable to the first surface. The first and second wiring layers of a multi-layered structure are sequentially formed on the second surface of the substrate with at least one insulation layer interposed between the first and second wiring layers. A plurality of the first and second bonding pads are respectively connected to the first and second wiring layers, the first and second bonding pads having a concavo-convex arrangement on the second surface of the substrate along a side of the window. | 04-14-2011 |
20110101544 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device permitting the reduction of cost is disclosed. In a semiconductor package wherein electrode pads of a semiconductor chip and corresponding inner leads are electrically coupled with each other through a plurality of bonding wires, sensing wires (second and fourth bonding wires) are made thinner than other bonding wires (first and third bonding wires) coupled to inner leads same as those with the sensing wires coupled thereto, thereby reducing the cost of gold wires to attain the reduction in cost of the semiconductor package. | 05-05-2011 |
20110108999 | Microelectronic package and method of manufacturing same - A microelectronic package comprises a die ( | 05-12-2011 |
20110140287 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH BOND WIRE PADS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a device over a substrate including a bond wire pad row located between a perimeter of the substrate and the device; configuring the bond wire pad row to include three sided bond wire pads that horizontally overlap; and forming an interconnection between the device and the bond wire pad row. | 06-16-2011 |
20110147953 | MICROELECTRONIC ASSEMBLY WITH JOINED BOND ELEMENTS HAVING LOWERED INDUCTANCE - A microelectronic assembly includes a semiconductor chip having chip contacts exposed at a first face and a substrate juxtaposed with a face of the chip. A conductive bond element can electrically connect a first chip contact with a first substrate contact of the substrate, and a second conductive bond element can electrically connect the first chip contact with a second substrate contact. The first bond element can have a first end metallurgically joined to the first chip contact and a second end metallurgically joined to the first substrate contact. A first end of the second bond element can be metallurgically joined to the first bond element. The second bond element may or may not touch the first chip contact or the substrate contact. A third bond element can be joined to ends of first and second bond elements which are joined to substrate contacts or to chip contacts. In one embodiment, a bond element can have a looped connection, having first and second ends joined at a first contact and a middle portion joined to a second contact. | 06-23-2011 |
20110169174 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for forming a semiconductor device is disclosed. A method for forming a semiconductor device includes forming a first bit line contact over a semiconductor substrate, forming a second bit line contact that is coupled to the first bit line contact and has a larger width than the first bit line contact, and forming a bit line over the second bit line contact. When using the semiconductor device having a buried gate, although the bit line is formed to have a small width and the bit line pattern is misaligned, the method prevents incorrect coupling between a bit line and a bit line contact, so that it basically deteriorates unique characteristics of the semiconductor device. | 07-14-2011 |
20110175241 | Semiconductor device and manufacturing method thereof - A semiconductor device includes a bonding pad, and an area designation marking, wherein the bonding pad includes a first region, a second region, and a third region placed between the first region and the second region, wherein the area designation marking includes a first area designation mark configured to designate a first boundary between the first region and the third region and a second area designation mark configured to designate a second boundary between the second region and the third region, wherein the first region and the second region are configured to be contacted with a test probe, The first area designation mark includes a first notch or a first protrusion. The second area designation mark includes a second notch or a second protrusion. The first area designation mark includes a first pair of notches that is linearly spaced apart from each other to designate the first boundary line. | 07-21-2011 |
20110180940 | INTERCONNECTION STRUCTURE AND ITS DESIGN METHOD - An interconnection structure includes a semiconductor chip, a mounting substrate on which the semiconductor chip is mounted, and a group of bonding wires provided to connect the semiconductor chip and the mounting substrate. The group of bonding wires includes: a first signal bonding wire contained in a first envelope and provided to propagate a signal; a first power supply bonding wire contained in the first envelope and applied with a first power supply voltage; and a second power supply bonding wire contained in a second envelope and applied with a second power supply voltage. One of the first envelope and the second envelope is arranged between the other of the first envelope and the second envelope and the mounting substrate. The second power supply bonding wire is arranged in a position in which electromagnetic coupling between the second power supply bonding wire and the first signal bonding wire is smaller than electromagnetic coupling between the second power supply bonding wire and the first power supply bonding wire. | 07-28-2011 |
20110187007 | EDGE CONNECT WAFER LEVEL STACKING - A stacked microelectronic assembly includes a first stacked subassembly and a second stacked subassembly overlying a portion of the first stacked subassembly. Each stacked subassembly includes at least a respective first microelectronic element having a face and a respective second microelectronic element having a face overlying and parallel to a face of the first microelectronic element. Each of the first and second microelectronic elements has edges extending away from the respective face. A plurality of traces at the respective face extend about at least one respective edge. Each of the first and second stacked subassemblies includes contacts connected to at least some of the plurality of traces. Bond wires conductively connect the contacts of the first stacked subassembly with the contacts of the second stacked subassembly. | 08-04-2011 |
20110198760 | Semiconductor device, semiconductor package, interposer, semiconductor device manufacturing method and interposer manufacturing method - A technique which prevents cracking in a solder resist layer covering an interposer surface between external coupling terminals of an interconnection substrate, thereby reducing the possibility of interconnect wire disconnection resulting from such cracking. A semiconductor package is mounted over an interconnection substrate. An underfill resin layer seals the space between the semiconductor package and the interconnection substrate. External coupling terminals, interconnect wires and a solder resist layer are formed over the surface of an interposer (constituent of the semiconductor package) where the semiconductor chip is not mounted. In an area where an interconnect wire passing between two neighboring ones of the external coupling terminals intersects with a line connecting the centers of the two external coupling terminals, the interconnect wire is not covered by the solder resist layer. | 08-18-2011 |
20110204527 | WIRELESS COMMUNICATION SYSTEM - A wireless communication system includes: a filter; and a semiconductor chip including a signal processing integrated circuit having an amplifier, wherein a main surface of the semiconductor chip is provided with a plurality of electrode terminals along an edge portion thereof; wherein the amplifier has a transistor including a control electrode, a first electrode through which a signal is outputted, and a second electrode to which a voltage is applied; wherein the control electrode, the first electrode and the second electrode of the transistor are connected to the electrode terminals, respectively; and wherein none of wirings are arranged between the electrode terminals and placements of the control electrode, the first electrode and the second electrode, making space between the electrodes and the electrode terminals narrow. | 08-25-2011 |
20110227234 | MULTI-FUNCTION CARD DEVICE - A multifunction card device has an external connection terminal, an interface controller, a memory, and the security controller connected to the interface controller and the external connection terminal. The interface controller has a plurality of interface control modes, and controls an external-interface action and a memory interface action by the control mode according to the instruction from the outside. The external connection terminals have an individual terminal individualized for every interface control mode, and a communalized common terminal. A clock input terminal, a power supply terminal, and an earthing terminal are included in the common terminals. A data terminal, and a dedicated terminal of the security controller are included in the individual terminals. Partial communalization and individualization of an external connection terminal attain a guarantee of the reliability of an interface, and increase control of physical magnitude to some kinds of interface control modes. The security process by a security controller independent interface can also be guaranteed. | 09-22-2011 |
20110241224 | WIRE BONDING STRUCTURE OF SEMICONDUCTOR DEVICE AND WIRE BONDING METHOD - A wire bonding structure is provided which includes a wire having a first bonding portion and a second bonding portion. The first bonding portion is bonded to an electrode pad of a semiconductor element, whereas the second bonding portion is bonded to a pad portion of a lead. The first bonding portion includes a front bond portion, a rear bond portion, and an intermediate portion sandwiched between these two bond portions. The front bond portion and the rear bond portion are bonded to the electrode pad more strongly than the intermediate portion is. In the longitudinal direction of the wire, the second bonding portion is smaller than the first bonding portion in bonding length. | 10-06-2011 |
20110260341 | Power switch component having improved temperature distribution - A power switch component having a semiconductor switch and a contacting applied to a contact zone of the semiconductor switch is introduced. The contact zone has a semiconductor layer and a metal plating applied to the semiconductor layer. The semiconductor layer has at least one conducting region and at least one non-conducting region situated directly under the metal plating. | 10-27-2011 |
20110278742 | Circuitry and Method for Encapsulating the Same - A circuitry comprises a substrate with a terminal region, a semiconductor device with a contact terminal, a bond wire connecting the terminal region to the contact terminal and a solder glass encapsulating material. The solder glass encapsulating material is mounted on the semiconductor device with the bond wire, so that at least the bond wire is hermetically enclosed. The substrate has a substrate material with a first coefficient of thermal expansion, the semiconductor device has a device material with a second coefficient of thermal expansion and the bond wire has a bond wire material with a third coefficient of thermal expansion. The solder glass encapsulating material has a coefficient of thermal expansion adjusted to a predefined value with regard to the second and third coefficients of thermal expansion. | 11-17-2011 |
20110316173 | ELECTRONIC DEVICE COMPRISING A NANOTUBE-BASED INTERFACE CONNECTION LAYER, AND MANUFACTURING METHOD THEREOF - An electronic device including a first region belonging to a semiconductor device having a first surface; a second region having a second surface; and an adhesion layer, set between the first and second regions, including first fibrils each having respective first and second ends. The first fibrils extend between the first and second surfaces and are fixed in a chemico-physical way to the first and second surfaces at the respective first and second ends. | 12-29-2011 |
20120032354 | WIREBONDING METHOD AND DEVICE ENABLING HIGH-SPEED REVERSE WEDGE BONDING OF WIRE BONDS - Methods and systems are described for enabling the efficient fabrication of wedge bonding of integrated circuit systems and electronic systems. In particular a reverse bonding approach can be employed. | 02-09-2012 |
20120038065 | Method for Producing an Electrical Circuit and Electrical Circuit - A method for producing an electrical circuit having at least one semiconductor chip is disclosed. The method includes forming a wiring layer at a contact side of the at least one semiconductor chip, which is encapsulated with a potting compound apart from the contact side. The wiring layer has at least one conductor loop for the purpose of forming an electrical coil. | 02-16-2012 |
20120068365 | METAL CAN IMPEDANCE CONTROL STRUCTURE - A microelectronic assembly includes an interconnection element, element contacts, first and second metal layers, conductive elements, and first and second microelectronic devices. The first metal layer may extend beyond at least one of the edges of the first microelectronic device. The conductive elements may respectively extend beyond at least one of the edges of the first metal layer. The first metal layer may have a surface disposed at a substantially uniform spacing from at least substantial portions of the conductive elements, such that a desired impedance may be achieved for the conductive elements. The conductive elements may be spaced a smaller distance from the metal layer than the distance of the conductive elements from the front surface of the first microelectronic device. The second metal layer may be connectable to a source of reference potential. | 03-22-2012 |
20120112369 | SILICON STRUCTURE HAVING BONDING PAD - A silicon structure includes a silicon substrate having an electric element; a wiring conductor and a bonding pad, connecting the electric element and an external circuit; a protective layer disposed on the silicon substrate; and a pad opening pattern provided in the protective layer to exposed the bonding pad, wherein a probe mark position and a wire bonding position differ, without increasing the size of the bonding pad in plan view. A substrate exposure part, which is not covered with the protective layer, is provided at part of an outer edge of the bonding pad disposed inside the pad opening pattern in the protective film, and the wiring conductor is not exposed through substrate exposure part. | 05-10-2012 |
20120133057 | EDGE CONNECT WAFER LEVEL STACKING - A stacked microelectronic assembly includes a first stacked subassembly and a second stacked subassembly overlying a portion of the first stacked subassembly. Each stacked subassembly includes at least a respective first microelectronic element having a face and a respective second microelectronic element having a face overlying and parallel to a face of the first microelectronic element. Each of the first and second microelectronic elements has edges extending away from the respective face. A plurality of traces at the respective face extend about at least one respective edge. Each of the first and second stacked subassemblies includes contacts connected to at least some of the plurality of traces. Bond wires conductively connect the contacts of the first stacked subassembly with the contacts of the second stacked subassembly. | 05-31-2012 |
20120139130 | Semiconductor Device - The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other. | 06-07-2012 |
20120153509 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREFOR - According to one embodiment, there is provided a semiconductor package including: a semiconductor chip; a resin portion formed to cover the semiconductor chip; a wiring structure formed on the resin portion and electrically connected to the semiconductor chip; and a warpage preventing member provided above the resin portion to have a thermal expansion coefficient closer to that of the semiconductor chip than to that of the wiring structure. | 06-21-2012 |
20120153510 | SEMICONDUCTOR DEVICE, AND METHOD FOR SUPPLYING ELECTRIC POWER TO SAME - Disclosed is a liquid crystal driver having a plurality of output cells ( | 06-21-2012 |
20120181707 | Distributed Metal Routing - A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias. | 07-19-2012 |
20120187581 | SEMICONDUCTOR DEVICE AND WIRING BOARD - A semiconductor device includes: a board; a power wire formed on the board; a signal wire formed on the board; a ground wire formed on the board; an insulating layer covering the signal wire, the power wire and the ground wire; and a metal film formed on the insulating layer, wherein a thickness of the insulating layer covering the power wire is different from a thickness of the insulating layer covering the signal wire, and the metal film is connected to a ground potential. | 07-26-2012 |
20120199990 | Semiconductor Module Having Deflecting Conductive Layer Over a Spacer Structure - A module includes a semiconductor chip and a conductive layer arranged over the semiconductor chip. The module also includes a spacer structure arranged to deflect the conductive layer away from the semiconductor chip. | 08-09-2012 |
20120211902 | BOND PAD STRUCTURE - A bonding pad structure is provided that includes two conductive layers and a connective layer interposing the two conductive layers. The connective layer includes a contiguous, conductive structure. In an embodiment, the contiguous conductive structure is a solid layer of conductive material. In other embodiments, the contiguous conductive structure is a conductive network including, for example, a matrix configuration or a plurality of conductive stripes. At least one dielectric spacer may interpose the conductive network. Conductive plugs may interconnect a bond pad and one of the conductive layers. | 08-23-2012 |
20120211903 | SEMICONDUCTOR DEVICE - A pad for a line which supplies an electric power potential is disposed on a semiconductor integrated circuit and a pad which is not electrically connected to any other electric circuit is disposed on a semiconductor integrated circuit board, and the two pads are connected through a bonding wire. An LC resonant circuit is configured with ease using a floating capacitance C of the pad which is in an electrically open state and which is disposed in a vacant region and an inductance value L of the bonding wire which is disposed in a three-dimensional manner. High-frequency noise is filtered and high-density implementation is realized. | 08-23-2012 |
20120223443 | ACTIVE MATRIX SUBSTRATE - An active matrix substrate includes a substrate and an insulating unit arranged on the substrate. The substrate includes a display region and a periphery circuit region beside the display region. The periphery circuit region has at least a chip connecting unit. Each chip connecting unit includes a number of connecting elements. Each of the connecting elements includes a conducting pad and a wire electrically connected to the conducting pad. The conducting pads of the connecting elements are arranged in at least two rows. The insulating unit has a number of contact holes corresponding to the conducting pads so that each of the conducting pads is entirely exposed by the corresponding contact hole. The active matrix substrate is applied to a display device to increase reliability of the display device and improve the quality of the display device. | 09-06-2012 |
20120241986 | Pin Routing in Standard Cells - Cells designed to accommodate metal routing tracks having a pitch that is an odd multiple of a manufacturing grid. The cells includes cell pins that are located within the cell based on the offsets of the routing tracks relative to the cell boundaries. The cell pins are wider than wires that are routed along the metal routing tracks. The standard cell may be placed in a layout in either a normal orientation or in a flipped orientation. In both orientations, the cell pins are aligned with the wires that are routed along the metal routing tracks. | 09-27-2012 |
20120248631 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES HAVING A GLASS SUBSTRATE - A method for manufacturing semiconductor devices is disclosed. A semiconductor wafer is provided having a first surface and a second surface opposite to the first surface. A first glass substrate is provided which has at least one of cavities and openings at the bonding surface. The first glass substrate is bonded to the first surface of the semiconductor wafer such that the metal pads are arranged within respective cavities or openings of the first glass substrate. The second surface of the semiconductor wafer is machined. At least one metallisation region is formed on the machined second surface of the semiconductor wafer. | 10-04-2012 |
20120306106 | SEMICONDUCTOR DEVICE HAVING DUMMY PATTERN AND DESIGN METHOD THEREOF - Disclosed herein is the semiconductor substrate, wiring patterns and dummy patterns. A margin region is formed around the wiring pattern. The dummy region is further formed around the margin region. The dummy patterns are formed in the dummy region. The dummy patterns are arranged along the extending direction of the dummy region. Margin regions and dummy regions are allocated alternately with respect to the wiring pattern. | 12-06-2012 |
20130001805 | POWER SEMICONDUCTOR MODULE - The respective main electrodes of the semiconductor switching elements such as IGBTs, which are respectively mounted on the plurality of insulating boards, are electrically connected to each other via the conductor member. This configuration makes it possible to suppress the occurrence of the resonant voltage due to the junction capacity and the parasitic inductance of each semiconductor switching element. | 01-03-2013 |
20130020724 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, ADHESIVE SHEET USED THEREIN, AND SEMICONDUCTOR DEVICE OBTAINED THEREBY - The present invention includes a temporary fixing step of temporarily fixing a semiconductor element on an adherend interposing an adhesive sheet therebetween, a wire-bonding step of bonding wires to the semiconductor element, and a step of sealing the semiconductor element with a sealing resin, and in which the loss elastic modulus of the adhesive sheet at 175-C is | 01-24-2013 |
20130020725 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, an insulating substrate mounted on the substrate, a metal pattern formed on the insulating substrate, an electronic part mounted on the metal pattern across a bond, and a wire member, separate from a wiring wire, which contains a material repellent to the bond and is formed on the metal pattern and around the electronic part. | 01-24-2013 |
20130026658 | WAFER LEVEL CHIP SCALE PACKAGE FOR WIRE-BONDING CONNECTION - Primarily disclosed is a wafer-level chip-scale-package (WLCSP) for wire-bonding connection. A first encapsulating layer is formed over a passivation layer of a chip. An RDL (redistribution wiring layer) is formed on the first encapsulating layer. A plurality of wire-bonding pads are stacked on the wiring terminals of the RDL on the first encapsulating layer. Each wire-bonding pad has a top surface and a sidewall. A surface plated layer completely covers the top surfaces of the wire-bonding pads. A second encapsulating layer is formed over the first encapsulating layer to encapsulate the RDL and the sidewalls of the wire-bonding pads. The openings of the second encapsulating layer are smaller than the top surfaces of the corresponding wire-bonding pads to partially encapsulate the surface plated layer. Accordingly, it can resolve the issue of die crack when wire-bonding on thinned chips. | 01-31-2013 |
20130062788 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a semiconductor chip, a lead frame that has a first surface having the semiconductor chip mounted thereover and a second surface opposite to the first surface, a bonding wire that couples the semiconductor chip and the lead frame, and a high-dielectric layer that is disposed over a surface of the lead frame opposite to a surface having the semiconductor chip mounted thereover and that has a relative permittivity of 5 or more. The lead frame includes a source electrode lead coupled to the source of a semiconductor device formed over the semiconductor chip and a source-wire junction at which the source electrode lead and the bonding wire are coupled together. The high-dielectric layer is disposed in a region including at least a position corresponding to the source-wire junction over the second surface of the lead frame. | 03-14-2013 |
20130069251 | WIRING SUBSTRATE, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE - A wiring substrate includes: a substrate layer made of glass or silicon and including: a first surface formed with a first hole; and a second surface formed with a second hole and being opposite to the first surface, wherein the first hole is communicated with the second hole; a connection pad formed in the second hole; a first wiring layer formed in the first hole and electrically connected to the connection pad; a first insulation layer formed on the first surface of the substrate layer to cover the first wiring layer; and a second wiring layer formed on the first insulation layer and electrically connected to the first wiring layer. A diameter of the first hole is gradually decreased from the first surface toward the second surface, and a diameter of the second hole is gradually decreased from the second surface toward the first surface. | 03-21-2013 |
20130113120 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes a metal substrate; a semiconductor element placed on the metal substrate; a flexible circuit substrate that has one end placed on the metal substrate and is electrically connected to the semiconductor element, the flexible circuit substrate extending over an edge of the metal substrate to outside the metal substrate; a resin wall portion placed, in an outer periphery of the metal substrate, at least at the edge of the metal substrate over which the flexible circuit substrate extends, the resin wall portion being provided on the flexible circuit substrate at the edge; and a resin seal portion provided inside the resin wall portion so as to cover the metal substrate. | 05-09-2013 |
20130140716 | MICROELECTRONIC ASSEMBLY WITH IMPEDANCE CONTROLLED WIREBOND AND REFERENCE WIREBOND - A microelectronic device, e.g., semiconductor chip, is connected with an interconnection element having signal contacts and reference contacts, the reference contacts being connectable to a reference potential such as ground or power. Signal conductors, e.g., signal wirebonds can be connected to device contacts of the microelectronic device, and at least one reference conductor, e.g., reference wirebond can be connected with two reference contacts. The reference wirebond can have a run extending at an at least substantially uniform spacing from an at least a substantial portion of a length of a signal conductor, e.g., signal wirebond. In such manner a desired impedance may be achieved for the signal conductor. | 06-06-2013 |
20130140717 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a multi-layer wiring layer formed on the substrate, and including a signal line and ground lines extending above the signal line, one of the ground lines extending toward a direction in a layer and another one of the ground lines extending from the one of the ground lines toward another direction in the layer, a first pad on the multi-layer wiring layer, and a redistribution layer formed on the multi-layer wiring layer, including a second pad, a redistribution line coupling the first pad and the second pad, and an insulation film covering the redistribution line. | 06-06-2013 |
20130154126 | SEMICONDUCTOR DEVICE - A semiconductor device is provided which can change electrode pads of a semiconductor chip which are allocated to balls without any increase in the number of wires and without any change in a substrate. The semiconductor device includes a semiconductor chip having first and second electrode pads, and a package substrate on which the semiconductor chip is mounted. The package substrate includes a first stitch having a width larger than widths of first and second wires, a second stitch having a width larger than the widths of the first and second wires, a ball that can be coupled with an external, the first wire that couples the first stitch and the ball, and the second wire that couples the first stitch and the second stitch. A first bonding wire couples the first stitch and the first electrode pad, or the second stitch and the second electrode pad. | 06-20-2013 |
20130175709 | INTEGRATED CIRCUIT PACKAGE AND METHOD OF ASSEMBLING AN INTEGRATED CIRCUIT PACKAGE - A method of assembling an integrated circuit package is disclosed. The method comprises placing a die on a substrate of the integrated circuit package; coupling a plurality of wire bonds from a plurality of bond pads on the die to corresponding bond pads on the substrate; applying a non-conductive material to the plurality of wire bonds; and encapsulating the die and the plurality of wire bonds. An integrated circuit package is also disclosed. | 07-11-2013 |
20130193589 | PACKAGED INTEGRATED CIRCUIT USING WIRE BONDS - A semiconductor device includes an integrated circuit die on a substrate. A first subset of wire bonds is between the substrate and the die. A second subset of wire bonds is between the substrate and the die. A dielectric material coats the first subset of the wire bonds along a majority of length of the first subset of the wire bonds. A medium is in contact with the second subset of the wire bonds along a majority of length of the second subset of the wire bonds. | 08-01-2013 |
20130193590 | SEMICONDUCTOR DEVICE INCLUDING VOLTAGE CONVERTER CIRCUIT, AND METHOD OF MAKING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a first bonding pad, a second bonding pad, a wire bonded to a selected one of the first and second bonding pads, a power supply line electrically connected to the first bonding pad, and a voltage converter circuit coupled to the second bonding pad, the voltage converter circuit being activated when the wire is bonded to the second pad to produce an internal power voltage, which is different from a voltage received by the voltage converter circuit through the wire and the second bonding pad, and supply the internal power voltage to the power supply line, and the voltage converter circuit being deactivated when the wire is connected to the first bonding pad to allow the power supply line to receive a power voltage through the wire and the first bonding pad. | 08-01-2013 |
20130200533 | PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS - A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer. | 08-08-2013 |
20130241084 | SEMICONDUCTOR DEVICE - A semiconductor device disclosed in this description has a semiconductor substrate including an element region in which a semiconductor element is formed, and an upper surface electrode formed on an upper surface of the element region of the semiconductor substrate. The upper surface electrode has a first thickness region and a second thickness region which is thicker than the first thickness region, and a bonding wire is bonded on the second thickness region. | 09-19-2013 |
20130264723 | METAL BASE SUBSTRATE AND MANUFACTURING METHOD THEREOF - In a metal base substrate with a low-temperature sintering ceramic layer located on a copper substrate, bonding reliability is increased between the copper substrate and the low-temperature sintering ceramic layer. A raw laminated body is prepared by stacking, on a surface of a copper substrate, a low-temperature sintering ceramic green layer including a low-temperature sintering ceramic material containing about 10 mol % to about 40 mol % of barium in terms of BaO and about 40 mol % to about 80 mol % of silicon in terms of SiO | 10-10-2013 |
20130300001 | SEMICONDUCTOR DEVICE - The semiconductor device according to the present invention includes a semiconductor layer, an interlayer dielectric film formed on the semiconductor layer, a wire formed on the interlayer dielectric film with a metallic material to have a width of not more than 0.4 μm, and a broad portion integrally formed on the wire to extend from the wire in the width direction thereof. | 11-14-2013 |
20130320571 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Of three chips ( | 12-05-2013 |
20130328219 | PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS - A structure includes a substrate having a first region and a second region, the substrate also having a first surface and a second surface. Electrically conductive elements are exposed at the first surface within the second region. Wire bonds have bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. At least one of the wire bonds has a shape such that the wire bond defines an axis between the free end and the base thereof and such that the wire bond defines a plane. A bent portion of the at least one wire bond extends away from the axis within the plane. A dielectric encapsulation layer covers portions of the wire bonds such that unencapsulated portions, including the ends, of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer. | 12-12-2013 |
20140021641 | MICROELECTRONIC PACKAGES HAVING CAVITIES FOR RECEIVING MICROELECTRONIC ELEMENTS - Packaged microelectronic elements are provided which include a dielectric element, a cavity, a plurality of chip contacts and a plurality of package contacts, and microelectronic elements having a plurality of bond pads connected to the chip contacts. | 01-23-2014 |
20140035169 | TOP CORNER ROUNDING OF DAMASCENE WIRE FOR INSULATOR CRACK SUPPRESSION - A structure and method for fabricating the structure that provides a metal wire having a first height at an upper surface. An insulating material surrounding said metal wire is etched to a second height below said first height of said upper surface. The metal wire from said upper surface, after etching said insulating material, is planarized to remove sufficient material from a lateral edge portion of said metal wire such that a height of said lateral edge portion is equivalent to said second height of said insulating material surrounding said metal wire. | 02-06-2014 |
20140117567 | MICROELECTRONIC ASSEMBLY WITH IMPEDANCE CONTROLLED WIREBOND AND REFERENCE WIREBOND - A microelectronic assembly can include a microelectronic device, e.g., semiconductor chip, connected together with an interconnection element, e.g., substrate, the latter having signal contacts and reference contacts. The reference contacts can be connectable to a source of reference potential such as ground or a voltage source other than ground such as a voltage source used for power. Signal conductors, e.g., signal wirebonds can be connected to device contacts exposed at a surface of the microelectronic device. Reference conductors, e.g., reference wirebonds can be provided, at least one of which can be connected with two reference contacts of the interconnection element. The reference wirebond can have a run which extends at an at least substantially uniform spacing from a signal conductor, e.g., signal wirebond that is connected to the microelectronic device over at least a substantial portion of the length of the signal conductor. In such manner a desired impedance may be achieved for the signal conductor. | 05-01-2014 |
20140131899 | PACKAGE FOR AN INTEGRATED CIRCUIT - The invention refers to method for packaging an integrated circuit (IC) comprising steps of:
| 05-15-2014 |
20140151905 | Devices and Methods for Providing an Electrical Connection - A device includes a tube extending in a longitudinal direction and a hollow channel arranged in the tube. An end part of the tube is formed such that first electromagnetic radiation paths extending in the tube and outside of the hollow channel in the longitudinal direction are focused in a first focus. | 06-05-2014 |
20140167292 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The present invention provides a multichip package in which a first semiconductor chip having an RF analog circuit area and a digital circuit area, and a second semiconductor chip having a digital circuit area are plane-arranged over an organic multilayer wiring board and coupled to each other by bonding wires. In the multichip package, the first semiconductor chip is made thinner than the second semiconductor chip. | 06-19-2014 |
20140175679 | SEMICONDUCTOR DEVICES, PACKAGE SUBSTRATES, SEMICONDUCTOR PACKAGES, PACKAGE STACK STRUCTURES, AND ELECTRONIC SYSTEMS HAVING FUNCTIONALLY ASYMMETRIC CONDUCTIVE ELEMENTS - A package stack structure may an upper package include an upper package substrate having a first edge and a second edge opposite to the first edge. The upper package substrate has a first region arranged near the first edge and a second region arranged near the second edge. A first upper semiconductor device is mounted on the upper package substrate. The package stack structure may also include a lower package having a lower package substrate and a lower semiconductor device. The lower package is connected to the upper package through a plurality of inter-package connectors. The plurality of the inter-package connectors may include first inter-package connectors configured to transmit data signals; second inter-package connectors configured to transmit address/control signals; third inter-package connectors configured to provide a supply voltage for an address/control circuit; and fourth inter-package connectors configured to provide a supply voltage for a data circuit. | 06-26-2014 |
20140191421 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, an interlayer insulation film, multiple wiring layers, a first hard film, and an electrical pad. The semiconductor substrate has a semiconductor element. The interlayer insulation film is disposed above the semiconductor substrate. The multiple wiring layers are disposed within the interlayer insulation film. The first hard film is disposed above the interlayer insulation film, and the first hard film is harder than the interlayer insulation film. The electrical pad is disposed above the first hard film, and the electrical pad is used for an external connection. The electrical pad includes a lower layer pad, the upper layer pad, and a second hard film. | 07-10-2014 |
20140197550 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate having a first surface, a height adjuster mounted on the first surface of the substrate via a first adhesive layer, a semiconductor chip mounted on the height adjuster via a second adhesive layer, an electronic component mounted on the first surface of the substrate via a third adhesive layer, a bonding wire, and a sealing member. The length of the electronic component in a first direction corresponding to the thickness direction of the substrate is larger than the length of the semiconductor chip in the first direction, and the sum of the lengths of the height adjuster, the second adhesive layer, and the semiconductor chip in the first direction is larger than the length of the electronic component in the first direction. | 07-17-2014 |
20140217619 | MICROELECTRONIC PACKAGE HAVING WIRE BOND VIAS AND STIFFENING LAYER - Microelectronic components and methods forming such microelectronic components are disclosed herein. The microelectronic components may include a plurality of electrically conductive vias in the form of wire bonds extending from a bonding surface of a substrate, such as surfaces of electrically conductive elements at a surface of the substrate. | 08-07-2014 |
20140252658 | SEMICONDUCTOR DEVICE - A semiconductor device has an FET, a mounting member, an output matching circuit board, a relay board, and first and second bonding wire. The FET has plural cell region arranged dispersedly and plural drain terminal electrodes connected to each cell region. The mounting member has an input conductive part and an output conductive part. The output matching circuit board is provided between an output conductive part and the FET, and has a first insulating substrate and a conductive part. The relay board is provided between the output matching circuit board and the FET, has a second insulating substrate having a permittivity lower than a permittivity of the first insulating substrate, and has a relay conductive part. The first bonding wire connects each drain terminal electrode and the relay conductive part. The second bonding wire connects the relay conductive part and the conductive part of the output matching circuit board. | 09-11-2014 |
20140264952 | SUPPLEMENTING WIRE BONDS - Systems and techniques for supplementing wire bonds. In one embodiment, a device includes a body having a first surface, a first wire bond pad disposed on the first surface, a first wire that is wire bonded to the first wire bond pad to form a contact between the first wire and the first wire bond pad, a first supplemental conductor disposed to form a supplemental conduit between the first wire and the first wire bond pad, a second wire bond pad disposed on the first surface, a second wire that is wire bonded to the second wire bond pad to form a contact between the second wire and the second wire bond pad, and a second supplemental conductor disposed to form a supplemental conduit between the second wire and the second wire bond pad. The first supplemental conductor is discrete from the second supplemental conductor. | 09-18-2014 |
20140291871 | IMPEDANCE CONTROLLED PACKAGES WITH METAL SHEET OR 2-LAYER RDL - A microelectronic assembly is disclosed that is capable of achieving a desired impedance for raised conductive elements. The microelectronic assembly may include an interconnection element, a surface conductive element, a microelectronic device, a plurality of raised conductive elements, and a bond element. The microelectronic device may overlie the dielectric element and at least one surface conductive element attached to the front surface. The plurality of raised conductive elements may connect the device contacts with the element contacts. The raised conductive elements may have substantial portions spaced a first height above and extending at least generally parallel to at least one surface conductive element, such that a desired impedance may be achieved for the raised conductive elements. A bond element may electrically connect at least one surface conductive element with at least one reference contact that may be connectable to a source of reference potential. | 10-02-2014 |
20140300009 | PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING SAME - A package structure includes a flexible-rigid PCB and a chip. The flexible PCB includes a flexible PCB, a glue piece and an outer trace layer. The flexible PCB includes two bending portions and a fixing portion connected between the two bending portions, and includes an insulating layer and an inner trace layer formed on the insulating layer. The glue piece is adhered to the fixing portion. The outer trace layer is adhered to the glue piece and includes conductive pads. The fixing portion, the glue piece and the outer trace layer form a rigid portion, the bending portions form flexible portions. The chip is packaged on the rigid portion and includes electrode pads electrically connected to the conductive pads. | 10-09-2014 |
20140319703 | SELF-DEFINING, LOW CAPACITANCE WIRE BOND PAD - A bond pad region is provided that reduces parasitic capacitance generated between bond pad metallization and underlying silicon by reducing the effective area of the bond pad, while maintaining flexibility of wire bond sites and ensuring mechanical integrity of the wire bonds. Embodiments provide, in a region that would be populated by a traditional bus bar bond pad, a small bus bar bond pad that is less than half the area of the region and populating at least a portion of the remaining area with metal tiles that are not electrically connected to the small bus bar bond pad or to each other. The metal tiles provide an attachment area for at least a portion of one or more wire bonds. Only those tiles involved in connection to a wire bond contribute to parasitic capacitance, along with the small bus bar pad. | 10-30-2014 |
20140332985 | CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area. A plurality of conductive pads is disposed at the peripheral bonding pad area and a passivation layer is formed over the semiconductor substrate to expose the conductive pads. An insulating protective layer is formed on the passivation layer at the device area. A packaging layer is disposed over the insulating protective layer to expose the conductive pads and the passivation layer at the peripheral bonding pad area. The method includes forming an insulating protective layer to cover a plurality of conductive pads during a cutting process and removing the insulating protective layer on the conductive pads through an opening of a packaging layer. | 11-13-2014 |
20140339711 | SEMICONDUCTOR DEVICE, METHOD OF POSITIONING SEMICONDUCTOR DEVICE, AND POSITIONING APPARATUS FOR SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor chip that has a first connection terminal for wiring connection; a substrate that has a second connection terminal for wiring connection, the second connection terminal being electrically connected to the first connection terminal; and a reflective surface that reflects light from the first connection terminal and the second connection terminal in a thickness direction of the substrate or the semiconductor chip. | 11-20-2014 |
20140353849 | SYSTEM FOR PREVENTING TAMPERING WITH INTEGRATED CIRCUIT - A system for generating a tamper detection signal indicating tampering with one or more circuits of an integrated circuit (IC) includes a tamper detection module, and wire-pairs connected to the tamper detection module and arranged in a winding configuration to form a wire-mesh. The wire-mesh is placed a predefined distance from the circuits. The tamper detection module generates and provides serial bit-streams to the wire-pairs for detecting a breach in the wire-mesh by an external probe. | 12-04-2014 |
20140353850 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is disclosed, which includes: a circuit board; a carrier disposed on the circuit board; an RF chip disposed on the carrier; a plurality of high level bonding wires electrically connecting electrode pads of the RF chip and the circuit board; and an encapsulant formed on the circuit board for encapsulating the carrier, the high level bonding wires and the RF chip. The present invention positions the RF chip at a high level so as to facilitate element arrangement and high frequency wiring on the circuit board, thereby achieving a highly integrated wireless SiP (System in Package) module. | 12-04-2014 |
20150021792 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING AN ELECTRONIC DEVICE - An embodiment method for fabricating electronic devices having two components connected by a metal layer includes applying a metal layer to each component and connecting the metal layers such that a single metal layer is formed. | 01-22-2015 |
20150021793 | SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURE - Wire-bonded semiconductor structures using organic insulating material and methods of manufacture are disclosed. The method includes forming a metal wiring layer in an organic insulator layer. The method further includes forming a protective layer over the organic insulator layer. The method further includes forming a via in the organic insulator layer over the metal wiring layer. The method further includes depositing a metal layer in the via and on the protective layer. The method further includes patterning the metal layer with an etch chemistry that is damaging to the organic insulator layer. | 01-22-2015 |
20150035174 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first component that generates heat when used, a second component, and a sealing portion. The sealing portion includes a first region and a second region. The first region covers the first component. The second region is thermally divided from the first region and covers the second component. | 02-05-2015 |
20150061159 | Semiconductor Device - Even when a thermal stress is applied to an electrode pad, the electrode pad is prevented from being moved. A substrate of a semiconductor chip has a rectangular planar shape. The semiconductor chip has a plurality of electrode pads. The center of a first electrode pad is positioned closer to the end of a first side in the direction along the first side of the substrate as compared to the center of a first opening. Thus, in a part of the first electrode pad covered with an insulating film, a width of the part closer to the end of the first side in the direction along the first side is larger than another width of the part opposite to the above-mentioned width. | 03-05-2015 |
20150061160 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device in which, when two adjacent semiconductor chips are coupled with bonding wires, a short circuit between the adjacent bonding wires can be suppressed. A first bonding wire, a second bonding wire, a third bonding wire, and a fourth bonding wire are lined up in this order along a first side. When viewed from a direction perpendicular to a chip mounting part, a maximum of the space between the first bonding wire and the second bonding wire is larger than that of the space between the second bonding wire and the third bonding wire. Further, a maximum of the space between the second bonding wire and the third bonding wire is larger than that of the space between the third bonding wire and the fourth bonding wire. | 03-05-2015 |
20150061161 | WIRE STRUCTURE AND SEMICONDUCTOR DEVICE HAVING THE SAME, AND METHOD OF MANUFACTURING THE WIRE STRUCTURE - According to example embodiments, a wire structure includes a first wire that includes a first wire core and a first carbon shell surrounding the first wire core, and a second wire that extends in a longitudinal direction from the first wire. The first wire core has a wire shape. The first carbon shell contains carbon. | 03-05-2015 |
20150069638 | METALLIC PARTICLE PASTE, CURED PRODUCT USING SAME, AND SEMICONDUCTOR DEVICE - According to one embodiment, a metallic particle paste includes a polar solvent and particles dispersed in the polar solvent and containing a first metal. A second metal different from the first metal is dissolved in the polar solvent. | 03-12-2015 |
20150069639 | Substrate-Less Stackable Package With Wire-Bond Interconnect - A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a structure comprising a patternable metallic element. The wire bonds are formed having bases joined to the first surface and end surfaces remote from the first surface. The wire bonds have edge surfaces extending between the bases and the end surfaces. The method also includes forming a dielectric encapsulation layer over a portion of the first surface of the conductive layer and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by end surfaces or portions of the edge surfaces that are uncovered by the encapsulation layer. The metallic element is patterned to form first conductive elements beneath the wire bonds and insulated from one another by portions of the encapsulation layer. | 03-12-2015 |
20150076714 | MICROELECTRONIC ELEMENT WITH BOND ELEMENTS TO ENCAPSULATION SURFACE - A microelectronic structure includes a semiconductor having conductive elements at a first surface. Wire bonds have bases joined to the conductive elements and free ends remote from the bases, the free ends being remote from the substrate and the bases and including end surfaces. The wire bonds define edge surfaces between the bases and end surfaces thereof. A compliant material layer extends along the edge surfaces within first portions of the wire bonds at least adjacent the bases thereof and fills spaces between the first portions of the wire bonds such that the first portions of the wire bonds are separated from one another by the compliant material layer. Second portions of the wire bonds are defined by the end surfaces and portions of the edge surfaces adjacent the end surfaces that are extend from a third surface of the compliant later. | 03-19-2015 |
20150097302 | SEMICONDUCTOR CONSTRUCT AND MANUFACTURING METHOD THEREOF AS WELL AS SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor construct includes a semiconductor substrate and connection pads provided on the semiconductor substrate. Some of the connection pads are connected to a common wiring and at least one of the remaining of the connection pads are connected to a wiring. The construct also includes a first columnar electrode provided to be connected to the common wiring and a second columnar electrode provided to be connected to a connection pad portion of the wiring. | 04-09-2015 |
20150108665 | CIRCUIT MODULE AND MANUFACTURING METHOD THEREOF - A circuit module including: a wiring substrate having a shape elongated in one direction; a semiconductor chip mounted on the wiring substrate; and a molding material that molds the semiconductor chip, wherein end faces of the molding material that extend along a lengthwise direction of the wiring substrate and intersect with a lateral direction of the wiring substrate are formed by dicing performed along end faces of a partial region of the wiring substrate. | 04-23-2015 |
20150115478 | SEMICONDUCTOR MODULE - A power module includes: a base plate having a front surface provided with positioning wire bonding portions; an insulating substrate provided with hole portions accommodating the positioning wire bonding portions on a side of a back surface facing the base plate, and fixed to the base plate with being positioned with respect to the base plate by the hole portions accommodating the positioning wire bonding portions; and a semiconductor chip arranged on a side of a front surface of the insulating substrate opposite to the back surface. | 04-30-2015 |
20150115479 | SEMICONDUCTOR DIE LAMINATING DEVICE WITH INDEPENDENT DRIVES - A laminating device ( | 04-30-2015 |
20150123293 | MICROELECTRONIC PACKAGE AND METHOD OF MANUFACTURE THEREOF - A microelectronic assembly may include a substrate having an opening extending between first and second oppositely facing surfaces of the substrate, the opening elongated in a first direction; and at least one microelectronic element having a front face facing and attached to the first surface of the substrate and a plurality of contacts at the front face overlying the opening, the microelectronic element having first and second opposite peripheral edges extending away from the front face. The first peripheral edge extends beyond, or is aligned in the first direction with, an inner edge of the opening, and the opening extends beyond the second peripheral edge. | 05-07-2015 |
20150137391 | ELECTRONIC COMPONENT HAVING A CORROSION-PROTECTED BONDING CONNECTION AND METHOD FOR PRODUCING THE COMPONENT - The invention relates to an electronic component ( | 05-21-2015 |
20150311173 | STRUCTURES AND METHODS FOR REDUCING CORROSION IN WIRE BONDS - A semiconductor structure includes a bond pad and a wire bond coupled to the bond pad. The wire bond includes a bond in contact with the bond pad. The wire bond includes a coating on a surface of the wire bond, and a first exposed portion of the wire bond in a selected location. The wire bond is devoid of the coating over the selected location of the wire bond, and an area of the first exposed portion is at least one square micron. | 10-29-2015 |
20150311185 | STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH SUPPORT MEMBERS AND ASSOCIATED SYSTEMS AND METHODS - Stacked semiconductor die assemblies with support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a plurality of support members also attached to the package substrate. The plurality of support members can include a first support member and a second support member disposed at opposite sides of the first semiconductor die, and a second semiconductor die can be coupled to the support members such that at least a portion of the second semiconductor die is over the first semiconductor die. | 10-29-2015 |
20150325491 | FLEXIBLE MICROELECTRONIC SYSTEMS AND METHODS OF FABRICATING THE SAME - Microelectronic systems encapsulated in a stretchable/flexible material, which is skin/bio-compatible and able to withstand environmental conditions. In one embodiment of the present description, the microelectronic system includes a microelectronic device that is substantially encapsulated in a non-permeable encapsulant, such as, butyl rubbers, ethylene propylene rubbers, fluoropolymer elastomers, or combinations thereof. In another embodiment, the microelectronic system includes a microelectronic device that is substantially encapsulated in a permeable encapsulant, such as polydimethylsiloxane, wherein a non-permeable encapsulant substantially encapsulates the permeable encapsulant. | 11-12-2015 |
20150371967 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a semiconductor device having improved reliability. In the semiconductor device in an embodiment, a mark is provided correspondingly to the bonding area of a belt-like wiring exposed from an opening provided in a solder resist. As a result, in an alignment step for the wire bonding area, the coordinate position of the wire bonding area can be adjusted using not the end portion of the opening formed in the solder resist, but the mark formed correspondingly to the wire bonding area as a reference. Also, in the semiconductor device in the embodiment, the mark serving as a characteristic pattern is formed. This allows the wire bonding area to be adjusted based on camera recognition. | 12-24-2015 |
20160049380 | WIRE BONDS FOR ELECTRONICS - A circuit element includes a semiconductor chip and a wire for connecting between the semiconductor chip and an additional circuit element. A plurality of wire bond connections electrically connect the wire and the semiconductor chip. The plurality of wire bond connections can be disposed on a surface of the semiconductor chip and on a surface of the wire. | 02-18-2016 |
20160056122 | SEMICONDUCTOR PACKAGE HAVING OVERHANG PORTION - A semiconductor package may include a substrate, and a structural body disposed over the substrate. The semiconductor package may include a semiconductor chip stacked over the structural body, and having an overhang portion projecting over a side surface of the structural body and overhanging out over the side surface of the structural body. The semiconductor package may include one or more bonding pads disposed on the overhang portion, and one or more wires electrically coupling the bonding pads to the substrate. The semiconductor package may include a wire fixing film attached onto the structural body, and overhanging out over the side surface of the structural body to fix the one or more wires. | 02-25-2016 |
20160093594 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns. | 03-31-2016 |
20160099224 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to the present invention includes an insulating substrate having a circuit pattern, semiconductor elements bonded on the circuit pattern with a brazing material, and a wiring terminal bonded with a brazing material on an electrode provided on each of the semiconductor elements on an opposite side of the circuit pattern, in which a part of the wiring terminal is in contact with the insulating substrate, and insulated from the circuit pattern. | 04-07-2016 |
20160126209 | SEMICONDUCTOR DEVICE - A semiconductor device includes: an insulating substrate including an insulating plate and a circuit board on the insulating plate; a semiconductor chip having an electrode on a front surface thereof, a back of the semiconductor chip being fixed to the circuit board; a printed circuit board that faces the circuit board and the front surface of the semiconductor chip; and one or more conductive posts each having one end connected via solder to the circuit board or to the electrode on the semiconductor chip, another end connected to the printed circuit board, and one or more grooves that extend from said one end of the conductive post that contacts the solder to said another end of the conductive post connected to the printed circuit board. | 05-05-2016 |
20160163624 | PACKAGE STRUCTURE - A package structure includes a chip, a substrate, wires and a molding compound. The chip includes an active surface, a back surface opposite to the active surface and bonding pads disposed on the active surface. The substrate includes a first solder mask, a first patterned circuit layer and a core layer having a first surface and a second surface opposite to the first surface. The first patterned circuit layer is disposed on the first surface. The first solder mask disposed on the first surface partially exposes the first patterned circuit layer. The substrate disposed on the active surface with the second surface exposes the bonding pads. The wires are connected between the first patterned circuit layer and the bonding pads. The molding compound covers the chip, the wire and the substrate. A top surface of the molding compound is coplanar with a top surface of the first solder mask. | 06-09-2016 |
20190148315 | AMPLIFIER | 05-16-2019 |