Class / Patent application number | Description | Number of patent applications / Date published |
257776000 | Cross-over arrangement, component or structure | 56 |
20080237886 | Three-dimensional crossbar array systems and methods for writing information to and reading information stored in three-dimensional crossbar array junctions - Various embodiments of the present invention are directed to three-dimensional crossbar arrays. In one aspect of the present invention, a three-dimensional crossbar array includes a plurality of crossbar arrays, a first demultiplexer, a second demultiplexer, and a third demultiplexer. Each crossbar array includes a first layer of nanowires, a second layer of nanowires overlaying the first layer of nanowires, and a third layer of nanowires overlaying the second layer of nanowires. The first demultiplexer is configured to address nanowires in the first layer of nanowires of each crossbar array, the second demultiplexer is configured to address nanowires in the second layer of nanowires of each crossbar array, and the third demultiplexer is configured to supply a signal to the nanowires in the third layer of nanowires of each crossbar array. | 10-02-2008 |
20080258311 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first wiring layer, a second wiring layer and a third wiring layer. The first wiring layer is formed on a semiconductor substrate. The second and the third wiring layer wiring layers are arranged in a direction intersecting with the first wiring layer on respective sides of the wiring layer. An air bridge wiring intersects the second and third wiring layers sandwiching an air layer above the first wiring layer therewith. The overall shape of the air bridge wiring has an upward convex curvature in an arch shape and the transverse sectional shape of the air bridge wiring is in the form of a downward concave curvature. | 10-23-2008 |
20090001596 | CONDUCTIVE LINE STRUCTURE - A conductive line structure is defined with an OPC photomask and is suitably applied to a semiconductor device. The conductive line structure includes a first conductive line and a second conductive line. The first conductive line includes a first line body oriented in the X-direction of a plane coordinate system, a first end portion at one end of the first line body slanting toward the Y-direction of the plane coordinate system, and a second end portion at the other end of the first line body also slanting toward the Y-direction. The second conductive line arranged in an end-to-end manner with the first conductive line includes a second line body oriented in the X-direction, a third end portion at one end of the second line body slanting toward the Y-direction, and a fourth end portion at the other end of the second line body also slanting toward the Y-direction. | 01-01-2009 |
20090032967 | Semiconductor Device with Dynamic Array Section - A semiconductor chip is provided to include one or more distinct but functionally interfaced dynamic array sections. Each dynamic array section follows a dynamic array architecture that requires conductive features to be linearly defined along a virtual grate in each of a plurality of levels of the semiconductor chip. Each virtual grate is perpendicular to another virtual grate that is either a level above or a level below. Each virtual grate is defined by a framework of parallel lines spaced at a constant pitch. Some of the lines in the virtual grate are occupied by multiple conductive features. A substantially uniform gap can be maintained between proximate ends of adjacent conductive features that occupy a common line in the virtual grate. The substantially uniform gap between the proximate ends of adjacent conductive features can be maintained within each line in the virtual grate that is occupied by multiple conductive features. | 02-05-2009 |
20090032968 | VIA CONFIGURABLE ARCHITECTURE FOR CUSTOMIZATION OF ANALOG CIRCUITRY IN A SEMICONDUCTOR DEVICE - A semiconductor device having a plurality of layers and a plurality of circuit elements arranged in tiles. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections of the plurality of circuit elements. The semiconductor device may include an interconnection quilt having a plurality of metal layers disposed to interconnect the plurality of circuit elements. The plurality of circuit elements may be analog circuit element and/or digital circuit elements. The tiles may be analog tiles and digital tiles that form a mixed signal structured array. | 02-05-2009 |
20090072411 | SEMICONDUCTOR DEVICE WITH CONDUCTIVE INTERCONNECT - One or more embodiments are related to a semiconductor structure, comprising: a semiconductor chip; a conductive layer comprising at least a first conductive pathway and a second conductive pathway spacedly disposed from the first conductive pathway, the first conductive pathway electrically coupled to the chip, at least a portion of the first conductive pathway disposed outside the lateral boundary of the chip, at least a portion of the second conductive pathway disposed outside the lateral boundary of the chip; and a conductive interconnect disposed outside the lateral boundary of the chip, the conductive interconnect electrically coupling the first conductive pathway to the second conductive pathway. | 03-19-2009 |
20090085219 | POWER SEMICONDUCTOR ARRANGEMENT - A power semiconductor arrangement is provided that includes a power semiconductor chip being electrically connected to a set of plug-like elements with at least two plug-like elements and further including a sheet metal strip line including a set of openings receiving the first set of plug-like elements, where the set of openings in the sheet metal strip line and the set of plug-like elements establish a press fit connection. | 04-02-2009 |
20090108466 | SEMICONDUCTOR DEVICE AND METHOD FOR PATTERNING VERTICAL CONTACTS AND METAL LINES IN A COMMON ETCH PROCESS - Interlayer connections, i.e., vertical connections, may be formed on the basis of a hard mask material, which may be positioned below, within or above an interlayer dielectric material, wherein one lateral dimension is defined by a trench mask, thereby obtaining a desired interlayer connection in a common patterning process. Furthermore, the thickness of at least certain portions of the metal lines may be adjusted with a high degree of flexibility, thereby providing the possibility of significantly reducing the overall resistivity of metal lines in metal levels, in which device performance may significantly depend on resistivity rather than parasitic capacitance. | 04-30-2009 |
20090140437 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device including an intermediate insulating film formed over a plurality of first conductors over a semiconductor substrate. Contact holes are formed in the intermediate insulating film over the first conductors, and contact plugs are buried in the contact holes, respectively. A plurality of second conductors are formed over the plurality of contact plugs on the intermediate insulating film, respectively, and are electrically connected to the plurality of first conductors via the contact plugs. In certain regions of the semiconductor device, the contact plugs may terminate within the intermediate insulating film, thereby electrically insulating the second conductors from the first conductors. | 06-04-2009 |
20090140438 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Wirings each having a side face with a different angle, which is made accurately, in a desired portion over one mother glass substrate are provided without increasing the steps. With the use of a multi-tone mask, a photoresist layer is formed, which has a tapered shape in which the area of a cross section is reduced gradually in a direction away from one mother glass substrate. At the time of forming one wiring, one photomask is used and a metal film is selectively etched, whereby one wiring having a side face, the shape (specifically, an angle with respect to a principal plane of a substrate) of which is different depending on a place, is obtained. | 06-04-2009 |
20090140439 | METHOD OF MANUFACTURING A CHIP AND A CHIP STACK - Provided are a chip, a chip stack, and a method of manufacturing the Same. A plurality of chips which each include: at least one pad formed on a wafer; and a metal layer which protrudes up to a predetermined thickness from the bottom of the wafer and is formed in a via hole exposing the bottom of the pad are stacked such that the pad and the metal layer of adjacent chips are bonded. This leads to a simplified manufacturing process, high chip performance and a small footprint for a chip stack. | 06-04-2009 |
20090283915 | Oversized Contacts and Vias in Layout Defined by Linearly Constrained Topology - A rectangular-shaped interlevel connection layout structure is defined to electrically connect a first layout structure in a first chip level with a second layout structure in a second chip level. The rectangular-shaped interlevel connection layout structure is defined by an as-drawn cross-section having at least one dimension larger than a corresponding dimension of either the first layout structure, the second layout structure, or both the first and second layout structures. A dimension of the rectangular-shaped interlevel connection layout structure can exceed a normal maximum size in one direction in exchange for a reduced size in another direction. The rectangular-shaped interlevel connection layout structure can be placed in accordance with a gridpoint of a virtual grid defined by two perpendicular sets of virtual lines. Also, the first and/or second layout structures can be spatially oriented and/or placed in accordance with one or both of the two perpendicular sets of virtual lines. | 11-19-2009 |
20090302482 | Structure and Method for Forming Hybrid Substrate - A first and a second substrate are bonded together to thereby form a unitary hybrid substrate. Predefined portions of the first substrate are removed to form openings in the first substrate through which surface regions of the second substrate are exposed. A selective epitaxial growth process that is selective with respect to the crystalline orientations of the first and second substrates is carried out to thereby form epitaxial silicon from the exposed surfaces of the second substrate but not from exposed surfaces of the first substrate. The epitaxial silicon formed from the exposed surfaces of the second substrate has the same crystalline orientation as the second substrate. | 12-10-2009 |
20100109166 | DEVICE WITH CHIPLETS AND ADAPTABLE INTERCONNECTIONS - An active-matrix device includes a device substrate including a plurality of pixels formed thereon, each pixel having a separate control electrode, a plurality of chiplets having at least first and second corresponding chiplets disposed at different locations over the device substrate, a plurality of wires formed over the device substrate, each wire being connected to a connection pad and to a different pixel control electrode, and wherein the shape of at least one of the wires connecting a connection pad for the first chiplet is different from the shape of at least one of the wires connecting a corresponding connection pad for the second chiplet. | 05-06-2010 |
20100127405 | WIRING BOAD, SEMICONDUCTOR DEVICE IN WHICH WIRING BOARD IS USED, AND METHOD FOR MANUFATURING THE SAME - A wiring board comprising a first surface on which a first electrode is disposed and a second surface on which a second electrode is disposed; at least a single insulation layer and at least a single wiring layer; and one or a plurality of mounted semiconductor elements, wherein the second electrode disposed on the second surface is embedded in the insulation layer, the surface on the opposite side of the exposed surface on the second surface side of the second electrode is connected to the wiring layer, and all or part of the side surface of the second electrode does not make contact with the insulation layer. | 05-27-2010 |
20100127406 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device including: plural first output pads formed along one edge of an outer periphery of a substrate; plural second output pads formed along at least one of an edge at an opposite side of the substrate from the one edge, and an edge adjoining the one edge; plural internal circuits, each of which is provided with an output terminal connected with an output pad of one of the first output pads and the second output pads; plural first lines, each of which connects one of the output terminals of the internal circuits with one of the plurality of first output pads; and plural second lines, each of which connects one of the output terminals of the internal circuits with one of the plural second output pads, resistance values per unit of wiring length being lower in the second lines than in the first lines. | 05-27-2010 |
20100187699 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - There is provided a layout structure of a semiconductor integrated circuit capable of preventing the thinning of a metal wiring line close to a cell boundary and wire breakage therein without involving increases in the amount of data for OPC correction and OPC process time. In a region interposed between a power supply line and a ground line each placed to extend in a first direction, first and second cells each having a transistor and an intra-cell line each for implementing a circuit function are placed to be adjacent to each other in the first direction. In a boundary portion between the first and second cells, a metal wiring line extending in a second direction orthogonal to the first direction is placed so as not to short-circuit the power supply line and the ground line. | 07-29-2010 |
20100201000 | BOND PAD SUPPORT STRUCTURE FOR SEMICONDUCTOR DEVICE - According to certain embodiments, integrated circuits are fabricated using brittle low-k dielectric material to reduce undesired capacitances between conductive structures. To avoid permanent damage to such dielectric material, bond pads are fabricated with support structures that shield the dielectric material from destructive forces during wire bonding. In one implementation, the support structure includes a passivation structure between the bond pad and the topmost metallization layer. In another implementation, the support structure includes metal features between the topmost metallization layer and the next-topmost metallization layer. In both cases, the region of the next-topmost metallization layer under the bond pad can have multiple metal lines corresponding to different signal routing paths. As such, restrictions on the use of the next-topmost metallization layer for routing purposes are reduced compared to prior-art bond-pad support structures that require the region of the next-topmost metallization layer under the bond pad to be a single metal structure. | 08-12-2010 |
20100201001 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes: a) preparing a structure including a semiconductor substrate, an electrode provided on a first surface of the semiconductor substrate, and an insulation film provided on the first surface and having an opening positioned on a first part of the electrode; b) forming a first metal layer from an upper surface of the first part of the electrode to an upper surface of the insulation film; c) forming a resin layer on a first part of the first metal layer, which is positioned on the first part of the electrode, and on the insulation film after the step b); d) removing at least a second part of the resin layer, which is positioned on the first part of the first metal layer, in a manner to leave a first part of the resin layer so as to form a resin protrusion; and e) forming a second metal layer, which is electrically connected with the electrode, from an upper surface of the first metal layer to an upper surface of the resin protrusion. | 08-12-2010 |
20100270687 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - One aspect of the present invention is a semiconductor device including: a semiconductor substrate; a first wiring that is formed on the semiconductor substrate; a second wiring that is formed to cross over the first wiring with a space interposed therebetween at a cross portion in which the first wiring and the second wiring cross each other; a protective film that is formed on the semiconductor substrate to cover at least a part of the first wiring, the part being located under the second wiring in the cross portion; and an insulator film that is formed in an island shape on the protective film under the second wiring in the cross portion to be located between edges of the protective film and to cover the first wiring in the cross portion. | 10-28-2010 |
20100276815 | INTEGRATED CIRCUIT COMMUNICATION SYSTEM WITH DIFFERENTIAL SIGNAL AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit communication system including providing a semiconductor wafer; and fabricating a cross-over current mirror driver on the semiconductor wafer for generating a crossing point at a reference voltage. | 11-04-2010 |
20100314779 | SEMICONDUCTOR DEVICE THAT SUPPRESSES MALFUNCTIONS DUE TO NOISE GENERATED IN INTERNAL CIRCUIT - A semiconductor device includes a first pad row and a second pad row, a first ground potential supply electrode which is connected to a first interconnect provided near the first pad row, and a second ground potential supply electrode which is connected to a second interconnect provided near the second pad row. The first pad row includes a first pad connected to the first circuit within the chip and connected to the first interconnect via a first bonding wire, and includes a second pad connected to a second circuit within the chip and connected to the second interconnect via a second bonding wire crossing over the second pad row. | 12-16-2010 |
20100327459 | SEMICONDUCTOR DEVICE HAVING PLURALITY OF WIRING LAYERS AND DESIGNING METHOD THEREOF - A semiconductor device includes first and second wirings formed in a first wiring layer and extending parallel to an X direction, third and fourth wirings formed in a third wiring layer and extending parallel to a Y direction; fifth and sixth wirings formed in a second wiring layer positioned between the first and second wiring layers, a first contact conductor that connects the first wiring to the third wiring; and a second contact conductor that connects the second wiring to the fourth wiring. The first and second contact conductors are arranged in the X direction. According to the present invention, because the first and second contact conductors that connect wiring layers that are two or more layers apart are arranged in one direction, a prohibited area that is formed in the second wiring layer can be made narrower. Therefore, the flexibility of the layout of the second wiring layer is enhanced and the restriction on the wiring density can be relaxed. | 12-30-2010 |
20110001249 | Supplying Power to Integrated Circuits Using a Grid Matrix Formed of Through-Silicon Vias - An integrated circuit structure includes a chip including a substrate and a power distribution network. The power distribution network includes a plurality of power through-silicon vias (TSVs) penetrating the substrate, wherein the plurality of power TSVs forms a grid; and a plurality of metal lines in a bottom metallization layer (M | 01-06-2011 |
20110006440 | SYSTEM AND METHOD TO REDUCE THE BONDWIRE/TRACE INDUCTANCE - A method and system for reducing the inductance on an integrated circuit. The method and system comprises providing a first differential line, including a first input and a first output, the first differential line including at least two bondwire traces which are coupled in parallel. The method and system also comprises providing a second differential line including a second input and a second output, the second differential line including at least two bondwire traces which are coupled in parallel, the first differential line being of opposite polarity to the second differential line. The method and system further comprises cross-coupling of the first input with the second input and the first output with the second output to reduce the inductance caused by bondwire traces. A technique in accordance with the invention uses the coupling factor K to help to further reduce the inductance. By changing the input ordering of differential bondwires/traces, the bondwire/trace magnetic coupling factor K can be used to reduce the line inductance. | 01-13-2011 |
20110018142 | ACTIVE MATRIX SUBSTRATE, DISPLAY DEVICE, METHOD FOR INSPECTING ACTIVE MATRIX SUBSTRATE, AND METHOD FOR INSPECTING DISPLAY DEVICE - An active matrix substrate is provided with first inspection wirings ( | 01-27-2011 |
20110074044 | PATTERNABLE LOW-K DIELECTRIC INTERCONNECT STRUCTURE WITH A GRADED CAP LAYER AND METHOD OF FABRICATION - An interconnect structure is provided that includes at least one patterned and cured low-k material located on a surface of a patterned graded cap layer. The at least one cured and patterned low-k material and the patterned graded cap layer each have conductively filled regions embedded therein. The patterned and cured low-k material is a cured product of a functionalized polymer, copolymer, or a blend including at least two of any combination of polymers and/or copolymers having one or more acid-sensitive imageable groups, and the graded cap layer includes a lower region that functions as a barrier region and an upper region that has antireflective properties of a permanent antireflective coating. | 03-31-2011 |
20110079922 | INTEGRATED CIRCUIT WITH PROTECTIVE STRUCTURE, AND METHOD OF FABRICATING THE INTEGRATED CIRCUIT - A structure includes a semiconductor substrate having semiconductor devices formed on or in the substrate. An interconnecting metallization structure is formed over and connected to the devices. The interconnecting metallization structure including at least one dielectric layer. A passivation layer is deposited over the interconnecting metallization structure and the dielectric layer. At least one metal contact pad and at least one dummy metal structure are provided in the passivation layer. The contact pad is conductively coupled to at least one of the devices. The dummy metal structure is spaced apart from the contact pad and unconnected to the contact pad and the devices. | 04-07-2011 |
20110133344 | CURABLE RESIN COMPOSITIONS USEFUL AS UNDERFILL SEALANTS FOR USE WITH LOW-K DIELECTRIC-CONTAINING SEMICONDUCTOR DEVICES - This invention relates to thermosetting resin compositions useful for flip chip (“FC”) underfill sealant materials, where a semiconductor chip is mounted directly onto a circuit through solder electrical interconnections. Similarly, the compositions are useful for mounting onto a circuit board semiconductor devices, such as chip size or chip scale packages (“CSPs”), ball grid arrays (“BGAs”), land grid arrays (“LGAs”) and the like, each of which having a semiconductor chip, such as large scale integration (“LSI”), on a carrier substrate. | 06-09-2011 |
20110241220 | AIR GAPS IN A MULTILAYER INTEGRATED CIRCUIT AND METHOD OF MAKING SAME - A multilayer integrated circuit (IC) including a cross pattern of air gaps in a wiring layer and methods of making the multilayer IC are provided. The patterning of the air gaps is independent of the wiring layout. Patterns of air gaps including: parallel alternating stripes of air gaps and dielectric that are orthogonal to a uni-directional metal wiring layout; parallel alternating stripes of air gaps and dielectric that are diagonal to either a uni- or bi-directional metal wiring layout; and a checkerboard pattern of air gaps and dielectric that crosses either a uni- or bi-directional metal wiring layout are easily formed by conventional photolithography and provide a comparatively uniform reduction in parasitic capacitance between the wires and the surrounding materials, when about one-half of a total length of the metal wiring layout is disposed within the air gaps. | 10-06-2011 |
20120007258 | SEMICONDUCTOR DEVICE WITH SIDE-JUNCTION AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a plurality of bodies that are each isolated from another by a trench and each include a diffusion barrier region with a sidewall exposed to the trench, forming a doped layer gap-filling the trench, forming a sidewall junction at the exposed sidewall of the diffusion barrier region by annealing the doped layer, and forming a conductive line coupled with the sidewall junction to fill the trench. | 01-12-2012 |
20120267795 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer, an active region defined in the semiconductor layer, first fingers provided on the active region and arranged in parallel with respect to a first direction, second fingers provided on the active region and interleaved with the first fingers, a bus line that is provided on an outside of the active region and interconnects the first fingers, first air bridges that are provided on the outside of the active region and are extended over the bus line, and that are connected to the second fingers, and second air bridges that are provided on the outside of the active region and are arranged in a second direction which crosses to the first direction, and that interconnect the first air bridges. | 10-25-2012 |
20130161832 | SEMICONDUCTOR DEVICE WITH BURIED BIT LINE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a punch stop region formed in a substrate; a plurality of buried bit lines formed over the substrate; a plurality of pillar structures formed over the buried bit lines; a plurality of word lines extending to intersect the buried bit lines and being in contact with the pillar structures; and an isolation layer isolating the word lines from the buried bit lines. | 06-27-2013 |
20130193586 | SEMICONDUCTOR DEVICE HAVING PLURALITY OF WIRING LAYERS AND DESIGNING METHOD THEREOF - A semiconductor device includes first and second wirings formed in a first wiring layer and extending parallel to an X direction, third and fourth wirings formed in a third wiring layer and extending parallel to a Y direction; fifth and sixth wirings formed in a second wiring layer positioned between the first and second wiring layers, a first contact conductor that connects the first wiring to the third wiring; and a second contact conductor that connects the second wiring to the fourth wiring. The first and second contact conductors are arranged in the X direction. Because the first and second contact conductors that connect wiring layers that are two or more layers apart are arranged in one direction, a prohibited area that is formed in the second wiring layer can be made narrower. | 08-01-2013 |
20130249113 | SEMICONDUCTOR MEMORY DEVICE - The semiconductor memory device comprises a plurality of first wiring lines extending in a first direction, a plurality of second wiring lines extending in a second direction crossing the first direction, and a memory cell array comprising memory cells, the memory cells being connected to the first wiring lines and second wiring lines in the crossing portions of the first and second wiring lines. A plurality of first dummy-wiring-line regions are formed in the peripheral area around the memory cell array. A contact is formed in the peripheral area, the contact extending in a third direction perpendicular to the first and second directions. A plurality of second dummy-wiring-line regions are formed in the periphery of the contact. The mean value of the areas of the second dummy-wiring-line regions is less than the mean value of the areas of the first dummy-wiring-line regions. | 09-26-2013 |
20130249114 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes a memory cell array layer which includes a first wiring line, a memory cell stacked on the first wiring line, and a second wiring line formed on the memory cell so as to intersect the first wiring line, wherein a step is formed in the first wiring line so that the height of an upper surface of the first wiring line in the memory cell array region where the memory cell array is formed is higher than the height in a peripheral region around the memory cell array region. | 09-26-2013 |
20130285258 | SEMICONDUCTOR DEVICE HAVING MESH-PATTERN WIRINGS - Disclosed herein is a device that includes: first lines formed on a first wiring layer extending in a first direction; second lines formed on a second wiring layer extending in a second direction; and conductor plugs connecting the first lines to the second lines such that the first and second lines form a mesh-structure wiring. The first lines include first enlarged portions at intersection positions where the first and second lines cross to each other, a width in the second direction of the first enlarged portions is wider than a line width of the first lines at other than the intersection position. The second lines include second enlarged portions at the intersection positions, a width in the first direction of the second enlarged portions is wider than a line width of the second lines at other than the intersection position. | 10-31-2013 |
20140117566 | SEMICONDUCTOR DEVICE HAVING LINE-TYPE TRENCH TO DEFINE ACTIVE REGION AND METHOD OF FORMING THE SAME - A semiconductor device includes a plurality of parallel-trenches that are parallel to each other, a plurality of intersect-trenches that are parallel to each other, a plurality of active regions that are confined by the parallel-trenches and the intersect-trenches, a plurality of lower conductive lines that cross the active regions, a plurality of upper conductive lines that are parallel to each other, that cross the lower conductive lines, and that cross over the active regions, and data storage elements connected to the active regions. Each of the parallel-trenches and the intersect-trenches is a straight line. The parallel-trenches cross the upper conductive lines and form a first acute angle with the upper conductive lines. The intersect-trenches cross the parallel-trenches and form a second acute angle with the parallel-trenches. | 05-01-2014 |
20140151903 | REPAIRING METHOD, REPAIRING STRUCTURE, AND REPAIRING SYSTEM FOR DISCONNECTED DEFECT - The present disclosure provides a repairing method, a repairing structure and a repairing system for a disconnected defect, the repairing method includes: forming a first repairing line connecting two ends of a disconnected portion of a scanning line; forming an insulation layer covering the first repairing line; and forming a second repairing line connecting two ends of a disconnected portion of a data line with the insulation layer located at an intersection of the first repairing line and the second repairing line. By forming the insulation layer between the first repairing line and the second repairing line, the present disclosure avoids the short circuit generated after the scanning line and the data line are repaired, repairs the disconnected defect at the intersection of two metal layers, improves the yield rate of the repairing of the disconnected defect, and reduces manufacturing cost. | 06-05-2014 |
20140210105 | METHOD OF FORMING INTERCONNECTION LINES - The invention concerns a method comprising: forming a plurality of parallel lines ( | 07-31-2014 |
20140232014 | SEMICONDUCTOR DEVICE WITH BURIED BIT LINE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a punch stop region formed in a substrate; a plurality of buried bit lines formed over the substrate; a plurality of pillar structures formed over the buried bit lines; a plurality of word lines extending to intersect the buried bit lines and being in contact with the pillar structures; and an isolation layer isolating the word lines from the buried bit lines. | 08-21-2014 |
20140239512 | CONNECTIONS FOR MEMORY ELECTRODE LINES - Subject matter disclosed herein may relate to word line electrodes and/or digit line electrodes in a cross-point array memory device. One or more word line electrodes may be configured to form a socket area to provide connection points to drivers and/or other circuitry that may be located within a footprint of an array of memory cells. | 08-28-2014 |
20140300008 | Wafer scale technique for interconnecting vertically stacked dies - A method and device for interconnecting stacked die surfaces with electrically conductive traces is provided that includes bonding, using a first layer of a photoresist compound, a second die ( | 10-09-2014 |
20140306353 | 3D MEMORY ARRAY - A 3-D memory is provided. Each word line layer has word lines and gaps alternately arranged along a first direction. Gaps include first group and second group of gaps alternately arranged. A first bit line layer is on word line layers and has first bit lines along a second direction. A first conductive pillar array through word line layers connects the first bit line layer and includes first conductive pillars in first group of gaps. A first memory element is between a first conductive pillar and an adjacent word line. A second bit line layer is below word line layers and has second bit lines along the second direction. A second conductive pillar array through word line layers connects the second bit line layer and includes second conductive pillars in second group of gaps. A second memory element is between a second conductive pillar and an adjacent word line. | 10-16-2014 |
20140312509 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes a memory cell array layer which includes a first wiring line, a memory cell stacked on the first wiring line, and a second wiring line formed on the memory cell so as to intersect the first wiring line, wherein a step is formed in the first wiring line so that the height of an upper surface of the first wiring line in the memory cell array region where the memory cell array is formed is higher than the height in a peripheral region around the memory cell array region. | 10-23-2014 |
20140327153 | STANDARD CELL CONNECTION FOR CIRCUIT ROUTING - Embodiments described herein provide approaches for improving a standard cell connection for circuit routing. Specifically, provided is an IC device having a plurality of cells, a first metal layer (M | 11-06-2014 |
20140327154 | MICROMECHANICAL COMPONENT AND METHOD FOR PRODUCING A MICROMECHANCAL COMPONENT HAVING A THIN-LAYER CAP - A micromechanical component having a substrate, a micromechanical functional layer situated above the substrate, and an encapsulation layer situated above the functional layer, and a method for producing the micromechanical component are provided, the encapsulation layer having at least one trench, and a bridging of the trench by at least one electrically insulating connection link is provided. | 11-06-2014 |
20140346682 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of first conductive layers stacked on top of one another, a plurality of first slits passing through the first conductive layers, and a plurality of second slits passing through the first conductive layers and crossing end portions of the first slits to form cross-shaped edges. | 11-27-2014 |
20150069630 | MEMORY CELL FORMED BY IMPROVED CMP PROCESS - Memory cell array architectures and methods of forming the same are provided. An example method for forming an array of memory cells can include forming a plurality of vertical structures each having a switch element in series with a memory element in series with a top electrode, and forming an interconnection conductive material between the respective top electrodes of the plurality of vertical structures. The interconnection conductive material is etched-back and chemical-mechanical polished (CMPed). A conductive line is formed over the interconnection conductive material after CMPing the interconnection conductive material. | 03-12-2015 |
20150102504 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a first interconnection line and a second interconnection line which extend apart from each other on a first plane at a first level on a substrate; a bypass interconnection line that extends on a second plane at a second level on the substrate; and a plurality of contact plugs for connecting the bypass interconnection line to the first interconnection line and the second interconnection line. A method includes forming a bypass interconnection line spaced apart from a substrate and forming on a same plane a plurality of interconnection lines connected to the bypass interconnection line via a plurality of contact plugs. | 04-16-2015 |
20150364439 | SEMICONDUCTOR DEVICE HAVING POWER DISTRIBUTION USING BOND WIRES - A semiconductor device uses insulated bond wires to connect peripheral power supply and ground bond pads on the periphery of the device to array power supply and ground bond pads located on an interior region of a integrated circuit die of the device. Power supply and ground voltages are conveyed from array bond pads using vertical vias down to one or more corresponding inner power distribution layers. The bond wire connections form rows and columns of hops constituting a mesh power grid that reduces the IR drop of the semiconductor device. | 12-17-2015 |
20160056067 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment, includes a plurality of wires, a first dielectric film, and a second dielectric film. The plurality of wires are arranged above a semiconductor substrate so as to extend in a first direction and aligned via a first cavity. The first dielectric film has a plurality of portions arranged above the plurality of wires so as to extend in a second direction substantially perpendicular to the plurality of wires and aligned along the first direction via a second cavity leading to the first cavity. The second dielectric film is formed above the first dielectric film so as to cover the second cavity. | 02-25-2016 |
20160118341 | PRECUT METAL LINES - Embodiments of the present invention provide a method for cuts of sacrificial metal lines in a back end of line structure. Sacrificial Mx+1 lines are formed above metal Mx lines. A line cut lithography stack is deposited and patterned over the sacrificial Mx+1 lines and a cut cavity is formed. The cut cavity is filled with dielectric material. A selective etch process removes the sacrificial Mx+1 lines, preserving the dielectric that fills in the cut cavity. Precut metal lines are then formed by depositing metal where the sacrificial Mx+1 lines were removed. Thus embodiments of the present invention provide precut metal lines, and do not require metal cutting. By avoiding the need for metal cutting, the risks associated with metal cutting are avoided. | 04-28-2016 |
20160163637 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate including active portions including first and second dopant regions, word lines on the substrate and extending in a first direction to intersect the active portions, first and second bit lines on the substrate and extending in a second direction to intersect the word lines, and contact structures in regions between the word lines and between the first and second bit lines when viewed from a plan view. The first and second bit lines are connected to the first dopant regions. The contact structures are in contact with the second dopant regions, respectively. The contact structures each include a contact plug and a contact pad. The contact pads contact the second dopant regions. A separation distance between the contact plugs and the first bit lines is less than separation distance between the contact pads and the first bit lines. | 06-09-2016 |
20160252787 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, LIQUID CRYSTAL PANEL AND DISPLAY DEVICE | 09-01-2016 |
20160377904 | DISPLAY DEVICE - A display device includes a substrate including a plurality of pixels disposed in a display area of the substrate. A non-display area of the substrate is disposed adjacent to the display area. The display device further includes a plurality of gate lines and a plurality of data lines arranged in a matrix form in the display area on the substrate, at least one driver integrated circuit (IC) disposed in the non-display area on the substrate, and a plurality of data fan-out wirings disposed on the substrate and connecting the data lines and the at least one driver IC. Lengths of the data fan-out wirings vary, and the data lines overlap the gate lines more as the lengths of the corresponding data fan-out wirings decrease. | 12-29-2016 |