Entries |
Document | Title | Date |
20080197504 | SINGLE-SIDED, FLAT, NO LEAD, INTEGRATED CIRCUIT PACKAGE - An integrated circuit package comprising an enclosure including a dielectric housing, a first electrical contact, and a second electrical contact. The dielectric housing, the first electrical contact, and the second electrical contact are configured to form a contact side of the enclosure. In addition, the first and second electrical contacts are sized to be substantially alignment insensitive for electro-mechanical connection to corresponding contacts of an end-use equipment. The enclosure encapsulates an integrated circuit die which is electrically coupled to the first and second electrical contacts. The alignment insensitive first and second electrical contacts may be electro-mechanically connected to corresponding contacts of an end-use equipment (e.g., a printer). Further, the integrated circuit package may be hosted by a peripheral device (e.g., a printer cartridge). | 08-21-2008 |
20080197505 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor substrate that has an integrated circuit, a passivation film formed above the integrated circuit, and an electrode electrically connected to the integrated circuit, the passivation film having an uneven surface, the electrode having at least a portion exposed through the passivation film; a first resin layer that is disposed on the passivation film; a second resin layer that covers the passivation film and the first resin layer; and a wiring that extends from the electrode to a first part of the second resin layer above the first resin layer, the electrode passing on a second part of the second resin layer above the passivation film. | 08-21-2008 |
20080197506 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR WAFER STRUCTURE - A semiconductor device manufacturing method, includes the steps of forming an insulating film over a semiconductor substrate, thinning selectively a thick portion, whose film thickness is thicker than a reference value, of the insulating film, forming contact holes in a thinned portion of the insulating film | 08-21-2008 |
20080197507 | Electronic package structure and method - An electronic package structure and method use a conductive strip to bond die-to-die, die-to-lead, chip carrier-to-lead, or lead-to-lead. A conductive strip may carry greater current than a bonding wire, and thus may replace several bonding wires. The bonding of the conductive strip may be carried out by an SMT process, and thus requires lower cost than wire bonding processes. A conductive strip may be bonded to more than two dice or leads to save more bonding wires. A conductive strip is stronger than a bonding wire, and thus lowers the possibility of being broken. | 08-21-2008 |
20080203576 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device including, forming a first insulating film above a silicon substrate, forming an impurity layer in the first insulating film by ion-implanting impurities into a predetermined depth of the first insulating film, and modifying the impurity layer to a barrier insulating film by annealing the first insulating film after the impurity layer is formed, is provided. | 08-28-2008 |
20080203577 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND FABRICATION METHOD FOR THE SAME - The semiconductor integrated circuit device includes: an active element, an interlayer insulting film, first and second metal patterns made of a first metal layer formed right above the active element, first and second buses made of a second metal layer formed right above the first metal layer, and contact pads provided on the first and second buses. The contact pad has a probe testing region and a bonding region. | 08-28-2008 |
20080203578 | CIRCUIT DEVICE, A METHOD FOR MANUFACTURING A CIRCUIT DEVICE, AND A SEMICONDUCTOR MODULE - A circuit device includes a semiconductor substrate on which a circuit element is formed, an electrode formed on a surface of the semiconductor substrate, an insulating layer formed on the electrode, a second wiring layer formed on the insulating layer, and a conductive bump which penetrates the insulating layer and electrically connects the electrode and the second wiring layer. The conductive bump is such that the size of crystal grains in a direction parallel with the surface of the semiconductor substrate is larger than the size of crystal grains in a conduction direction of the electrode and the wiring layer. | 08-28-2008 |
20080203579 | SACRIFICIAL METAL SPACER DUAL DAMASCENE - A method and structure for a dual damascene interconnect structure comprises forming wiring lines in a metallization layer over a substrate, shaping a laminated insulator stack above the metallization layer, patterning a hardmask over the laminated insulator stack, forming troughs in the hardmask, creating sacrificial tungsten sidewall spacers in the troughs, patterning the laminated insulator stack, removing the sacrificial sidewall spacers, forming vias in the patterned laminated insulator stack, and depositing a metal liner and conductive material into the vias and troughs, wherein the laminated insulator stack comprises a dielectric layer further comprising oxide and polyarylene. The step of depositing prevents the laminated insulator stack from sputtering into the vias. Moreover, the step of depositing comprises cleaning the vias and troughs, optionally performing a reactive ion etching or argon sputter cleaning, depositing a plurality of metal layers over the vias and troughs, and depositing copper in the vias and troughs. | 08-28-2008 |
20080217786 | Semiconductor device and method of manufacturing semiconductor device - According to one embodiment of the present invention, a method of manufacturing a semiconductor device includes below steps. | 09-11-2008 |
20080217787 | MICRO-ELECTROMECHANICAL DEVICE AND MANUFACTURING METHOD THEREOF - A micro-electromechanical device includes a substrate, a first patterned conductive layer, a second patterned conductive layer and a first patterned blocking layer. The first patterned conductive layer is disposed on the substrate. The second patterned conductive layer is disposed on the first patterned conductive layer. The first patterned blocking layer is connected with the first patterned conductive layer and the second patterned conductive layer. In addition, a method of manufacturing the micro-electromechanical device is also disclosed. | 09-11-2008 |
20080224320 | SILICON CHIP HAVING INCLINED CONTACT PADS AND ELECTRONIC MODULE COMPRISING SUCH A CHIP - A semiconductor chip has an active face in which an integrated circuit region is implanted. The chip includes an inclined lateral contact pad extending beneath the plane of the active face and electrically linked to the integrated circuit region. An electronic module includes a substrate having a cavity in which the chip is arranged. The module can be applied to the production of thin contactless micro-modules for smart cards and contactless electronic badges and tags. | 09-18-2008 |
20080224321 | CELL DATA FOR SPARE CELL, METHOD OF DESIGNING A SEMICONDUCTOR INTEGRATED CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT - In a cell base design, when a circuit using a spare cell is corrected, a wiring length is shortened as much as possible, and the number of wiring layers which are affected by correction is reduced. Mask pattern data that expresses the configurations of a signal input terminal and a signal output terminal of a spare cell is set to mask pattern data of a wiring layer that is equal to or higher than a second wiring layer. As a result, the length of a wiring that is connected to the spare cell can be shortened as much as possible. | 09-18-2008 |
20080230916 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND FABRICATION PROCESS THEREOF - A semiconductor IC device includes a buried interconnection in interconnection layers over a semiconductor substrate, in which electrical connection of interconnections are provided over and under an interconnection layer of an embedded interconnection from among the interconnection layers such that a first connecting conductor portion within a connecting hole extending from an upper interconnection toward the interconnection layer of a predetermined buried interconnection and a second connecting conductor portion within the connecting hole extending from a lower interconnection toward the interconnection layer of the predetermined buried interconnection are electrically connected via a connecting conductor portion for relay in the connecting groove of the interconnection layer of a predetermined buried interconnection. The connecting conductor portion for relay is sized so that the length of the connecting conductor portion for relay in an extending direction of the predetermined buried interconnection is longer than that of the connecting hole. | 09-25-2008 |
20080237872 | Semiconductor Device and Method For Manufacturing Same - Disclosed is a semiconductor apparatus having a sealing structure that allows high-precision detection of defects occurring in a protective film, and a method of manufacturing the same. A semiconductor apparatus | 10-02-2008 |
20080237873 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH BONDING IN VIA - An integrated circuit package system includes a substrate having an opening provided therein, forming a conductor in the opening in the substrate open at the top and having a closed end at the bottom, attaching an integrated circuit die over the substrate, and connecting a die interconnect to the integrated circuit die and the closed end of the conductor. | 10-02-2008 |
20080237874 | Method of Producing a Silicon Oxide-Based Material with a Low Dielectric Constant - A method for manufacturing a material with a low dielectric constant, comprising a step of forming cavities in silicon dioxide by implantation of a rare gas different from helium and from neon at an implantation dose greater than 10 | 10-02-2008 |
20080237875 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A technique of manufacturing a semiconductor device in which etching in formation of a contact hole can be easily controlled is proposed. A semiconductor device includes at least a semiconductor layer formed over an insulating surface; a first insulating layer formed over the semiconductor layer; a gate electrode formed over the first insulating layer; a second insulating layer formed over the gate electrode; and a conductive layer formed over the second insulating layer connected to the semiconductor layer via an opening which is formed at least in the semiconductor layer and the second insulating layer and partially exposes the insulating surface. The conductive layer is electrically connected to the semiconductor layer at the side surface of the opening which is formed in the semiconductor layer. | 10-02-2008 |
20080237876 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for easily manufacturing a semiconductor device in which variation in thickness or disconnection of a source electrode or a drain electrode is prevented is proposed A semiconductor device includes a semiconductor layer formed over an insulating substrate; a first insulating layer formed over the semiconductor layer; a gate electrode formed over the first insulating layer; a second insulating layer formed over the gate electrode; an opening which reaches the semiconductor layer and is formed at least in the first insulating layer and the second insulating layer; and a step portion formed at a side surface of the second insulating layer in the opening. | 10-02-2008 |
20080237877 | SEMICONDUCTOR DEVICE - This invention is directed to offer a semiconductor device having a structure capable of relaxing a mechanical stress applied to a bonding pad. A third interlayer insulation film having via holes is formed on a second interlayer insulation film to cover a third wiring layer. A third conductive layer is formed in the via hole. The third interlayer insulation film is composed of an array of a plurality of hexagonal column-shaped interlayer insulation films. And the via hole and the third conductive layer are formed to surround each hexagonal column-shaped interlayer insulation film. A fourth wiring layer connected with the third wiring layer through the third conductive layer is formed. The fourth wiring layer makes an uppermost wiring layer in an embodiment of this invention and serves as the bonding pad. | 10-02-2008 |
20080237878 | Semiconductor device and method of producing the same - A semiconductor device includes a semiconductor substrate having a main surface; an element separation film formed on the main surface in an element separation area and extending in a first direction; and a semiconductor element formed on the main surface in an active area and arranged in a second direction perpendicular to the first direction. The semiconductor element includes a metal silicide film. The metal silicide film includes a first portion adjacent to the element separation film. The semiconductor device further includes an interlayer insulation film formed on the main surface of the semiconductor substrate; a wiring portion formed on the interlayer insulation film; and a conductive plug formed in the interlayer insulation film for electrically connecting the semiconductor elements and the wiring portion. The conductive plug is situated on the element separation film and the metal silicide film. | 10-02-2008 |
20080246157 | Surface mount devices with minimum lead inductance and methods of manufacturing the same - A device according to various aspects of the present invention generally includes a surface mount device having a top side, a bottom side, a plurality of sidewalls, and a circuit comprising one or more layers. The device includes a first conductive surface covering a portion of one of the sidewalls for providing an input to the circuit, a second conductive surface covering a portion of one of the sidewalls for providing an output from the circuit, and a third conductive surface covering a portion of one of the sidewalls for providing an electrical ground to the circuit. When the surface mount device is mounted to a provided mounting surface, at least one layer of the circuit is orthogonal to the provided mounting surface. | 10-09-2008 |
20080246158 | Method for Realizing a Nanometric Circuit Architecture Between Standard Electronic Components and Semiconductor Device Obtained with Said Method - A method for realizing a nanometric circuit architecture includes: realizing plural active areas on a semiconductor substrate; realizing on the substrate a seed layer of a first material; realizing a mask-spacer of a second material on the seed layer in a region comprised between the active areas; realizing a mask overlapping the mask-spacer and extending in a substantially perpendicular direction thereto; selectively removing the seed layer exposed on the substrate; selectively removing the mask and the mask-spacer obtaining a seed-spacer comprising a linear portion extending in that region and a portion substantially orthogonal thereto; realizing by MSPT from the seed-spacer an insulating spacer reproducing at least part of the profile of the seed-spacer realizing by MSPT a nano-wire of conductive material from the seed-spacer or insulating spacer, the nano-wire comprising a first portion at least partially extending in the region and a second portion contacting a respective active area. | 10-09-2008 |
20080246159 | PLANARIZED PASSIVATION LAYER FOR SEMICONDUCTOR DEVICES - A semiconductor device includes a substrate having a dielectric layer and a device layer on the substrate. The device layer has an opening. First and second sublayers are disposed on the device layer and line the opening. The second sublayer serves as a stop layer for planarization to provide a substantially planarized top surface for the semiconductor device. | 10-09-2008 |
20080246160 | STANDARD CELL AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire. | 10-09-2008 |
20080251929 | Semiconductor Device and Semiconductor Device Manufacturing Method - An inventive semiconductor device includes at least three interconnection layers sequentially stacked without intervention of a via layer. At least one of the interconnection layers includes an interconnection and a via which connects interconnections provided in interconnection layers underlying and overlying the one interconnection layer. | 10-16-2008 |
20080251930 | SEMICONDUCTOR DEVICE AND DUMMY PATTERN ARRANGEMENT METHOD - A semiconductor device includes a plurality of wiring patterns arranged in a first wiring layer of the semiconductor device and extending in a first direction, and a plurality of dummy patterns arranged in the first wiring layer and extending in a second direction different from the first direction, wherein each of the plurality of dummy patterns is arranged spaced apart from each of the plurality of wiring patterns and includes one or more dummy lands formed by separating a part of the dummy pattern opposed to the wiring pattern, from the rest part of the dummy pattern. | 10-16-2008 |
20080265425 | Semiconductor Device and Method for Manufacturing the Same - A semiconductor device according to an embodiment can include a first group of dummy patterns and a second group of dummy patterns spaced apart from the first group of dummy patterns by a second spacing. The first group of dummy patterns can include a plurality of first dummy patterns formed separated from each other by a first spacing. The second group of dummy patterns can include a plurality of second dummy patterns formed separated from each other by the first spacing. The first dummy patterns and the second dummy patterns can have the same shape and size. | 10-30-2008 |
20080265426 | SEMICONDUCTOR STRUCTURE COMPRISING AN ELECTRICAL CONNECTION AND METHOD OF FORMING THE SAME - A method of forming a semiconductor structure comprises providing a substrate comprising a layer of a first material. A protection layer is formed over the layer of first material. At least one opening is formed in the layer of first material and the protection layer. A layer of a second material is formed over the layer of first material and the protection layer to fill the opening with the second material. A planarization process is performed to remove portions of the layer of second material outside the opening. At least a portion of the protection layer is not removed during the planarization process. An etching process is performed to remove the portions of the protection layer which were not removed during the planarization process. | 10-30-2008 |
20080265427 | Anchoring Structure and Intermeshing Structure - An anchoring structure for a metal structure of a semiconductor device includes an anchoring recess structure having at least one overhanging side wall, the metal structure being at least partly arranged within the anchoring recess structure. | 10-30-2008 |
20080272495 | SEMICONDUCTOR DEVICE HAVING HIGH-FREQUENCY INTERCONNECT - Provided is a semiconductor device including high-frequency interconnect and dummy conductor patterns (second dummy conductor patterns). The dummy conductor patterns are disposed in a interconnect layer different from a interconnect layer in which the high-frequency interconnect is disposed. The dummy conductor patterns are disposed so as to keep away from a region overlapping the high-frequency interconnect in plan view. The semiconductor device further includes dummy conductor patterns (first dummy conductor patterns) in the interconnect layer in which the high-frequency interconnect is disposed. | 11-06-2008 |
20080277798 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same. The semiconductor device includes a first main pattern formed on a substrate and a first dummy pattern formed in a parallel direction to a first main pattern on a layer on which the first main pattern is formed. Additional dummy patterns can be inserted and pattern density can be increased by the insertion of the dummy pattern in consideration of the shape and direction of the main pattern per the metal layer. | 11-13-2008 |
20080284035 | SEMICONDUCTOR DEVICE - A semiconductor device and method is disclosed. In one embodiment, the method includes placing a first semiconductor over an electrically conductive carrier. The first semiconductor is covered with a molding compound. A through hole is formed in the molding compound. A first material is deposited in the through hole. | 11-20-2008 |
20080284036 | STRUCTURE FOR OPTIMIZING FILL IN SEMICONDUCTOR FEATURES DEPOSITED BY ELECTROPLATING - A structure and process are provided that are capable of reducing the occurrence of discontinuities within the metallization, such as voiding or seams, formed during electroplating at the edges of semiconductor metallization arrays. The structure includes a metallization bar located around the periphery of the array. The process employs the structure during electroplating. | 11-20-2008 |
20080296774 | ARRANGEMENT INCLUDING A SEMICONDUCTOR DEVICE AND A CONNECTING ELEMENT - An integrated circuit and an arrangement including a semiconductor device and a connecting element and method for producing such an arrangement is disclosed. One embodiment provides a semiconductor element having a first contact face and a second contact face. The first contact face and the second contact face extend in a first lateral direction. An electrically conductive connecting element which has a third contact face electrically contacts the semiconductor element. The connecting element includes a trench system. A first trench of this trench system extends from the third contact face into the connecting element. | 12-04-2008 |
20080296775 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In one aspect of the present invention, a semiconductor device may include a semiconductor substrate having a semiconductor element on an upper surface, a first dielectric film provided on the semiconductor substrate, a second dielectric film provided on the first dielectric film, a metal ring provided in the first dielectric film and the second dielectric film and configured to form a closed loop in a plan view, a first region surrounded by the metal ring in a plan view, a second region provided outside of the metal ring in a plan view, a plurality of via contacts provided in the first dielectric film in the first and second region, a plurality of wirings provided in the second dielectric film in the first and second region, and an air gap provided in the second dielectric film in the first region. | 12-04-2008 |
20080296776 | Method of Manufacturing Electrical Conductors for a Semiconductor Device - A method of manufacturing an electrical conductor for a semiconductor device having one or more layers includes etching from a first surface to a second surface of at least one layer of the device to form a channel having a wall extending from the first surface to the second surface. The channel defines a gap extending from the first surface to the second surface. An insulating layer is provided on the channel wall. Conductive material is patterned on the channel wall to form multiple separate electrical conductors, which are insulated from material of the at least one layer by the insulating layer, thereon, such that the gap that extends from the first surface to the second surface is maintained. A corresponding semiconductor device is also provided. | 12-04-2008 |
20080296777 | SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device capable of preventing occurrence of cracking and the like, taking a large area, where wiring and the like that function as elemental devices can be arranged, within a plurality of interlayer insulation films, and reducing production cost. The semiconductor device according to the present invention has a low dielectric constant film having a dielectric constant of not less than 2.7. In the low dielectric constant film and the like, materials (e.g., a first dummy pattern, a second dummy pattern) with a larger hardness than that of the low dielectric constant film are formed at a part under a pad part. | 12-04-2008 |
20080303164 | STRUCTURE AND METHOD OF REDUCING ELECTROMIGRATION CRACKING AND EXTRUSION EFFECTS IN SEMICONDUCTOR DEVICES - A structure for reducing electromigration cracking and extrusion effects in semiconductor devices includes a first metal line formed in a first dielectric layer; a cap layer formed over the first metal line and first dielectric layer; a second dielectric layer formed over the cap layer; and a void formed in the second dielectric layer, stopping on the cap layer, wherein the void is located in a manner so as to isolate structural damage due to electromigration effects of the first metal line, the effects including one or more of extrusions of metal material from the first metal line and cracks from delamination of the cap layer with respect to the first dielectric layer. | 12-11-2008 |
20080303165 | CIRCUIT ARRANGEMENT AND INTEGRATED CIRCUIT - A circuit arrangement includes a plurality of type-identical and identically operated active components, or separate sections of an active component, and includes a branched wiring structure for the interconnection of component connections. In each case the wiring end portions lie between a branching point and an input of different components or sections, wherein the wiring end portions are formed with predetermined geometrical asymmetry with respect to one another in such a way that there is an electrical symmetry of the interconnection configuration between all the connected type-identical components or sections. More particularly, the impedance values between the branching point and the different inputs and outputs are substantially identical. | 12-11-2008 |
20080303166 | TWO-SIDED SUBSTRATE LEAD CONNECTION FOR MINIMIZING KERF WIDTH ON A SEMICONDUCTOR SUBSTRATE PANEL - A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages. | 12-11-2008 |
20080303167 | DEVICE HAVING HIGH ASPECT-RATIO VIA STRUCTURE IN LOW-DIELECTRIC MATERIAL AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a device having a via structure includes the following steps. A seed metallic layer is formed on a substrate. A patterned metallic-trace layer is formed on the seed metallic layer. A positive-type photoresist layer is formed on the patterned metallic-trace layer and seed metallic layer. The photoresist layer is patterned for defining a through hole which exposes a part of the patterned metallic-trace layer, wherein the through hole has a high aspect ratio. A metallic material is electroplated in the through hole so as to form a metallic pillar. The photoresist layer is removed. A part of the seed metallic layer is etched, whereby traces of the patterned metallic-trace layer are electrically isolated from each other. A dielectric material layer is formed on the substrate for sealing the patterned metallic-trace layer and a part of the metallic pillar and exposing a top surface of the metallic pillar. | 12-11-2008 |
20080303168 | STRUCTURE FOR PREVENTING PAD PEELING - A structure for preventing pad peeling includes a semiconductor substrate, a dielectric layer, a pad, and a protective layer. The semiconductor substrate has an active circuit structure. The dielectric layer is disposed on the semiconductor substrate and has an opening located in the dielectric layer above an edge position of the corresponding active circuit structure. Besides, the opening exposes a part of the surface of the active circuit structure. The pad disposed above the semiconductor substrate covers the dielectric layer above the position of the corresponding active circuit structure and fills up the opening. The protective layer is disposed on the dielectric layer and covers the edge of the pad. | 12-11-2008 |
20080308943 | WIRING STRUCTURE AND SEMICONDUCTOR DEVICE, AND THEIR FABRICATION METHODS - A fabrication method for a wiring structure of the present invention includes: a process of forming a conductive wiring layer; a process of forming a wiring pattern on the wiring layer; a process of forming an insulative wiring interlayer film between wires of the wiring pattern; and a process of forming a plurality of longitudinal hole-shaped fine pores in the wiring interlayer film in a thickness direction of the wiring interlayer film by etching with a mask including one of nano-particles and material including nano-particles. | 12-18-2008 |
20080315428 | Thin Film Transistor and Display Device, and Method for Manufacturing Thereof - The present invention discloses a display device and a manufacturing method thereof by which a manufacturing process can be simplified. Further, the present invention discloses technique for manufacturing a pattern such as a wiring into a desired shape with good controllability. A method for forming a pattern for constituting the display device according to the present invention comprises the steps of forming a first region and a second region; discharging a composition containing a pattern formation material to a region across the second region and the first region; and flowing a part of the composition discharged to the first region into the second region; wherein wettability with respect to the composition of the first region is lower than that of the second composition. | 12-25-2008 |
20080315429 | METHOD FOR IMPROVING THE SELECTIVITY OF A CVD PROCESS - A method of forming a noble metal cap on a conductive material embedded in a dielectric material in an interconnect structure. The method includes the step of contacting (i) a conductive material having a bare upper surface partially embedded in a dielectric material and (ii) vapor of a noble metal containing compound, in the presence of carbon monoxide and a carrier gas. The contacting step is carried out at a temperature, pressure and for a length of time sufficient to produce a noble metal cap disposed directly on the upper surface of the conductive material without substantially extending into upper surface of the dielectric material or leaving a noble metal residue onto the dielectric material. | 12-25-2008 |
20090001593 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OVERHANGING CONNECTION STACK - An integrated circuit package system comprising: providing a first conductive line adjacent to a second conductive line; forming a first connection stack over the first conductive line with the first connection stack overhanging the second conductive line; connecting an integrated circuit device and the first connection stack; and encapsulating the integrated circuit device and the first connection stack. | 01-01-2009 |
20090001594 | AIRGAP INTERCONNECT SYSTEM - A method may comprise assembling a first dielectric ensemble that comprises a first dielectric layer exhibiting a first porosity, a second dielectric layer exhibiting a second porosity and a third dielectric layer exhibiting a third porosity, and fabricating a first metal line in the dielectric ensemble. A chemical may be applied on the third layer to pass through and dissolve a portion of the second layer. The third layer acts to prevent a via that is partially landed on the dielectric from exposing the air gap underneath. | 01-01-2009 |
20090001595 | Integrated Circuit, Intermediate Structure and a Method of Fabricating a Semiconductor Structure - In a method of fabricating a semiconductor structure, a carbon containing mask is fabricated over a dielectric layer. The mask exposes the surface of the dielectric layer at least partly in a region between two adjacent conducting lines. A contact hole is etched into the dielectric layer in the region between the two adjacent conducting lines. | 01-01-2009 |
20090008787 | HIGH EFFICIENCY SOLAR CELL FABRICATION - A method of forming a contact structure and a contact structure so formed is described. The structure contacts an underlying layer of a semiconductor junction, wherein the junction comprises the underlying layer of a semiconductor material and is separated from an overlying layer of semiconductor material by creating an undercut region to shade subsequent metal formation. Various steps are performed using inkjet printing techniques. | 01-08-2009 |
20090008788 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - A method of forming a semiconductor device. A first wiring level is formed on a top surface of a substrate. The first wiring level includes alternating layers of a first dielectric material and a second dielectric material. The layers of the first dielectric material includes at least two layers of the first dielectric material. The layers of the second dielectric material includes at least two layers of the second dielectric material. The first dielectric material includes an organic dielectric material. The second dielectric material includes an inorganic dielectric material. The substrate includes one or more dielectric materials. A first layer of the layers of the first dielectric material includes the organic dielectric material being in direct mechanical contact with the substrate. The layers of the first dielectric material and the layers of the second dielectric material are a same number of layers. | 01-08-2009 |
20090020877 | TRANSMISSION LINE STRUCTURE AND SIGNAL TRANSMISSION STRUCTURE - A transmission line structure includes a routing trace, a doped region and a first guard trace. The routing trace is disposed over a substrate. The doped region is disposed in the substrate and the projection of at least the partial routing trace falls within the doped region. The first guard trace is located over the substrate and disposed with a space from the routing trace, wherein the first guard trace is grounded and electrically coupled with the doped region. In addition, the conductivity of the first guard trace is higher than the conductivity of the doped region. | 01-22-2009 |
20090020878 | SEMICONDUCTOR PACKAGES AND METHODS OF FABRICATING THE SAME - A semiconductor package is provided. The semiconductor package includes a semiconductor device having a bonding pad and an interlayer insulating layer disposed on the semiconductor device. The interlayer insulating layer has an opening which exposes the bonding pad and has at least one cavity therein. A redistributed interconnection is disposed on the interlayer insulating layer and electrically connected to the exposed bonding pad. The redistributed interconnection is disposed over the cavity. A method of fabricating the semiconductor package is also provided. | 01-22-2009 |
20090020879 | WIRING STRUCTURE IN SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING WIRING STRUCTURE IN SEMICONDUCTOR DEVICE - A wiring structure in a semiconductor device includes a first insulation layer formed on a substrate having first and second contact regions, and first and second pads extending through the first insulation layer and contacting the first and the second contact regions. The first and the second pads are higher than the first insulation layer. A blocking layer pattern is formed on the first insulation layer between the first and the second pads, the blocking layer pattern being higher than the first and the second pads. A second insulation layer is formed on the blocking layer pattern and the first and the second pads. A bit line structure is formed on the second insulation layer, the bit line structure electrically contacting the second pad. A third insulation layer is formed on the second insulation layer and the bit line structure. A plug extends through the second and the third insulation layers and contacts the first pad. | 01-22-2009 |
20090020880 | WIRING STRUCTURE IN A SEMICONDUCTOR DEVICE AND METHOD OF FORMING A WIRING STRUCTURE IN A SEMICONDUCTOR DEVICE - A wiring structure includes a first insulation layer located on a substrate, and first and second plugs located on the substrate and extending through the first insulation layer. The first plug includes an upper peripheral portion that defines a recess and the second plug is adjacent to the first plug. A second insulation layer is located on the first insulation layer, the first plug and the second plug. A bit line structure is located on the second insulation layer and is electrically connected to the first plug. A protection spacer is located on the recess of the first plug and a sidewall of an opening in the second insulation layer. The opening exposes the recess of the first plug, the second plug and the sidewall of the bit line structure. A pad is located in the opening and contacts the second plug. | 01-22-2009 |
20090020881 | SEMICONDUCTOR DEVICE PACKAGE AND FABRICATING METHOD THEREOF - A semiconductor device package and fabricating method thereof are disclosed, by which heat-dissipation efficiency is enhanced in a system by interconnection (SBI) structure. An exemplary semiconductor device package may include a substrate, at least two chips mounted on the substrate to have a space between one or more of the chips and an edge of the substrate, an insulating layer covering the chips, the insulating layer having via holes exposing portions of the at least two chips and a trench between the via holes, the insulating layer having at least two hole patterns within the space, and a metal layer filling the via holes and the trench. | 01-22-2009 |
20090020882 | Semiconductor device and method of producing the same - A semiconductor device includes a package substrate having a front surface and a backside surface; an electrode pad formed on the front surface; an outer connection pad formed on the backside surface and electrically connected to the electrode pad; a semiconductor chip mounted on the front surface and having an electrode electrically connected to the electrode pad; a sealing resin layer having a through hole formed with a die-molding and reaching the electrode pad for sealing the semiconductor chip; and a through electrode filled in the through hole with a conductive material and having one end portion electrically connected to the electrode pad and the other end portion exposed from the sealing resin layer. | 01-22-2009 |
20090032959 | ELECTRICAL FUSES AND RESISTORS HAVING SUBLITHOGRAPHIC DIMENSIONS - Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator layer. Self-assembling block copolymers are applied into the recessed area and annealed to form a first set of polymer blocks and a second set of polymer blocks. The first set of polymer blocks are etched selective to the second set and the at least one insulator layer. Features having sublithographic dimensions are formed in the at least one insulator layer and/or the conductive structure. Various semiconductor structures having sublithographic dimensions are formed including electrical fuses and resistors. | 02-05-2009 |
20090032960 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - Semiconductor devices and methods of manufacturing semiconductor devices. One example of a method of fabricating a semiconductor device comprises forming a conductive feature extending through a semiconductor substrate such that the conductive feature has a first end and a second end opposite the first end, and wherein the second end projects outwardly from a surface of the substrate. The method can further include forming a dielectric layer over the surface of the substrate and the second end of the conductive feature such that the dielectric layer has an original thickness. The method can also include removing a portion of the dielectric layer to an intermediate depth less than the original thickness such that at least a portion of the second end of the conductive feature is exposed. | 02-05-2009 |
20090032961 | SEMICONDUCTOR DEVICE HAVING A LOCALLY ENHANCED ELECTROMIGRATION RESISTANCE IN AN INTERCONNECT STRUCTURE - By forming an alloy in a highly localized manner at a transition or contact area between a via and a metal line, the probability of forming an electromigration-induced shallow void may be significantly reduced, while not unduly affecting the overall electrical resistivity of the metal line. In one illustrative embodiment, an electroless deposition process may provide the alloy-forming species on the exposed metal region on the basis of an electroless plating process. | 02-05-2009 |
20090032962 | CENTRIFUGAL METHOD FOR FILING HIGH ASPECT RATIO BLIND MICRO VIAS WITH POWDERED MATERIALS FOR CIRCUIT FORMATION - The present disclosure relates generally to semiconductor, integrated circuits, and particularly, but not by way of limitation, to centrifugal methods of filling high-aspect ratio vias and trenches with powders, pastes, suspensions of materials to act as any of a conducting, structural support, or protective member of an electronic component. | 02-05-2009 |
20090039518 | Method for forming a damascene structure - A method of forming a damascene structure comprises preparing a film stack on the substrate, wherein the film stack comprises a SiCOH-containing layer formed on the substrate, a silicon oxide (SiO | 02-12-2009 |
20090039519 | SEMICONDUCTOR DEVICE, PHOTOMASK, SEMICONDUCTOR DEVICE PRODUCTION METHOD, AND PATTERN LAYOUT METHOD - A semiconductor device according to an aspect of the invention includes plural line pattern and plural pad patterns. The line patterns are repeatedly disposed with a space pattern interposed therebetween. The pad pattern straddles plural columns of the line patterns. The pad pattern is connected to the line pattern located on one side of the pad pattern in one of the plural columns, the pad pattern is connected to the line pattern located on the other side of the pad pattern in another column of the plural columns, and the line pattern located on one side of the pad pattern includes an open-circuit portion in another column. Therefore, a semiconductor device in which an interconnection pattern including the fine line-and-space-shape line pattern and the pad pattern is accurately formed at low cost, a semiconductor device production method, and a photomask used to produce the semiconductor device can be provided. | 02-12-2009 |
20090039520 | SEMICONDUCTOR CIRCUIT DEVICE, WIRING METHOD FOR SEMICONDUCTOR CIRCUIT DEVICE AND DATA PROCESSING SYSTEM - Via multiplexing technology is provided which can contribute to high density wiring. For coupling wirings of different wiring layers, a multiple via cell section is used which has vias for electrically coupling wirings bent in an L-shape of different wiring layers on both sides with the L-shaped bent portion therebetween. The vias of the multiple via cell section are on a grid line in an X-direction and a grid line in a Y-direction defined with a minimum wiring pitch, and all or part of the vias of the multiple via cell section are deviated from an intersection of the grid line in the X-direction and the grid line in the Y-direction. The vias of the multiple via cell section are placed on each of the grid line in the X-direction and the grid line in the Y-direction, corresponding to the L-shape, so that there is not much difference between the spatial conditions in the X-direction and the spatial conditions in the Y-direction viewed from the multiple via cell section. Thus, the wirability in the X-direction becomes equivalent to that in the Y-direction. | 02-12-2009 |
20090039521 | Semiconductor structure and semiconductor manufacturing method - A semiconductor structure comprising a first signal layer, a second signal layer, a wiring layer and at least one via is provided. The wiring layer is formed between the first signal layer and the second signal layer. A conducting wire is disposed between a first terminal and a second terminal on the wiring layer. At least one via is used to conduct the first signal layer and the second signal layer. The at least one via is disposed adjacent to the first terminal and the second terminal. | 02-12-2009 |
20090045519 | Semiconductor Device and Method of Producing the Same - In one embodiment of the present invention, a process is disclosed for producing a semiconductor device that can suppress the diffusion of an electrically conductive metal into an insulating film. The process for producing a semiconductor device is characterized by including the steps of (1) forming a groove in an insulating film provided on a semiconductor substrate, (2) forming a barrier film on the inner face of the groove and on the insulating film, (3) forming an electrically conductive metal layer on the barrier film so as to fill the groove, (4) removing the electrically conductive metal layer and barrier film on the insulating film and a part of the electrically conductive metal layer within the groove so that the surface of the electrically conductive metal layer is lower than the surface of the insulating film, (5) forming a metal diffusion preventive film on the insulating film and the electrically conductive metal layer, and (6) removing the metal diffusion preventive film on the insulating film and a part of the insulating film so that at least a part of the metal diffusion preventive film on the electrically conductive metal layer remains unremoved. | 02-19-2009 |
20090045520 | IC Device having Compact Design - An IC device has a compact design. Capacitors, resistances and inductances are directly integrated in the IC device without packaging in advance. Thus, the IC device obtained has a slim size and an electric apparatus using the IC device has a big space for use. | 02-19-2009 |
20090051038 | SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR CONSTITUENT AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor constituent having a semiconductor substrate and a plurality of electrodes for external connection provided under the semiconductor substrate. An under-layer insulating film is provided under and around the semiconductor constituent. A plurality of under-layer wires are provided under the under-layer insulating film and electrically connected to the electrodes for external connection of the semiconductor constituent. An insulating layer is provided around the semiconductor constituent and on the under-layer insulating film. A frame-like insulating substrate is embedded in an upper surface of the insulating layer and positioned around the semiconductor constituent. A plurality of upper-layer wires are provided on the insulating substrate. A base plate on which the semiconductor constituent and the insulating layer are mounted is removed. | 02-26-2009 |
20090057910 | METHOD OF EMBEDDING PASSIVE COMPONENT WITHIN VIA - A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein. | 03-05-2009 |
20090057911 | METHOD FOR MANUFACTURING A SEMICONDUCTOR ARRANGEMENT, USE OF A TRENCH STRUCTURE, AND SEMICONDUCTOR ARRANGEMENT - A method for manufacturing a semiconductor arrangement, use of a trench structure, and a semiconductor arrangement is provided that includes a single-crystal semiconductor layer, a conductive substrate region and a buried insulator layer, which isolates the single-crystal semiconductor layer from the conductive substrate region, whereby the conductive substrate region is contacted. A trench structure is formed to separate the single-crystal semiconductor layer into a first semiconductor region outside the trench structure and a second semiconductor region within the trench structure, an opening is formed in the single-crystal semiconductor layer within the second semiconductor region, the buried insulator layer is removed within the opening, and a conductor, which contacts the conductive substrate region and adjoins the second semiconductor region, is introduced into the opening. | 03-05-2009 |
20090065944 | REWORKED INTEGRATED CIRCUIT DEVICE AND REWORKING METHOD THEREOF - Reworking method for removing defects on integrated circuit device is disclosed. An integrated circuit is provided, which has a substrate, a conductive material layer formed in the substrate, a dielectric layer formed on the substrate, at least a contact plug embedded in the dielectric layer, and a conductive layer contacting to the contact plug formed on the dielectric layer. A defect is found in the conductive layer and the reworking method is performed, including an etch back process, a chemical mechanical polishing process, and a deposition process. The reworking method removes the prior formed conductive layer and reform a conductive layer to prevent the integrated circuit from being scraped. | 03-12-2009 |
20090065945 | SEMICONDUCTOR DEVICE FOR PREVENTING INFLOW OF HIGH CURRENT FROM AN INPUT/OUTPUT PAD AND A CIRCUIT FOR PREVENTING INFLOW OF HIGH CURRENT THEREOF - A semiconductor device includes an input/output pad, an input line of an internal circuit, and a plurality of metal lines formed on a lower portion of the input/output pad to have a buffer area overlapping with a plane area of the input/output pad, wherein one of an entirety and a portion of the plurality of metal lines included in the buffer area forms protective resistance interconnecting the input/output pad to the input line. | 03-12-2009 |
20090065946 | Method for fabricating semiconductor device and semiconductor device - A method of fabricating a semiconductor device having an air-gapped multilayer interconnect wiring structure is disclosed. After having formed a first thin film on or above a substrate, define a first opening in the first thin film. Then, deposit a conductive material in the first opening. Then form a second thin film made of a porous material above the first thin film with the conductive material being deposited in the first opening. Next, define in the second thin film a second opening extending therethrough, followed by deposition of a conductive material in the second opening. The first thin film is removed through voids in the second thin film after having deposited the conductive material in the second opening. An integrated semiconductor device as manufactured thereby is also disclosed. | 03-12-2009 |
20090072408 | Connecting and Bonding Adjacent Layers with Nanostructures - An apparatus, comprising two conductive surfaces or layers and a nanostructure assembly bonded to the two conductive surfaces or layers to create electrical or thermal connections between the two conductive surfaces or layers, and a method of making same. | 03-19-2009 |
20090079082 | BONDING PAD STRUCTURE ALLOWING WIRE BONDING OVER AN ACTIVE AREA IN A SEMICONDUCTOR DIE AND METHOD OF MANUFACTURING SAME - A wire bonding pad over an active area of a semiconductor die has grooves in two orthogonal sections thereof in the top surface of said wire bonding pad. | 03-26-2009 |
20090079083 | INTERCONNECT STRUCTURE AND FABRICATING METHOD OF THE SAME - A fabricating method of an interconnect structure is provided. A first dielectric layer is formed on a substrate for covering an air gap region and a non-air gap region. Next, interconnects are formed in the first dielectric layer on the air gap region and in the first dielectric layer on the non-air gap region. Then, a cap layer is formed on the first dielectric layer. Thereafter, on the air gap region, a portion of the cap layer and a portion of the first dielectric layer are removed for forming first openings, and thereby a portion of the first dielectric layer are left between the interconnects for forming support pillars. After that, a second dielectric layer is formed over the substrate for covering the cap layer and the first openings, so as to form an air gap in each of the first openings. | 03-26-2009 |
20090079084 | Preventing breakage of long metal signal conductors on semiconductor substrates - An apparatus includes a volume of insulator disposed over a top surface of a semiconductor substrate, a tube of soft dielectric, and a metal conductor. The insulator has a hardness of more than approximately three gigapascals (gPa) and the soft dielectric has a hardness of less than three gPa. The tube of soft dielectric and the metal conductor are both embedded within the volume of insulator. The tube defines a central volume and the metal conductor extends in a direction through the central volume for a distance of at least one inch. The metal conductor is encircled by the soft dielectric when the apparatus is viewed in a cross-sectional plane perpendicular to the direction. The metal conductor may include a plurality of bend portions. The metal conductor does not break when the apparatus is temperature cycled over a range from zero to eighty five degrees Celsius. | 03-26-2009 |
20090079085 | SEMICONDUCTOR DEVICE - A semiconductor device including a semiconductor section including a semiconductor element and a recess formed in one of main surfaces and a metallic member at least a part of which is embedded in the recess. A void is formed in a region of the metallic member corresponding to the recess. | 03-26-2009 |
20090079086 | Semiconductor Device - A semiconductor device according to the present invention includes: a first interlayer dielectric film; a lower wire formed on the first interlayer dielectric film; a second interlayer dielectric film formed on the first interlayer dielectric film and the lower wire; and an upper wire formed on the second interlayer dielectric film to intersect with a prescribed portion of the lower wire in plan view. The first interlayer dielectric film is provided with a groove dug from the upper surface thereof in a region including the prescribed portion in plan view. The prescribed portion enters the groove. At least a portion of the second interlayer dielectric film formed on the lower wire has a planar upper surface. | 03-26-2009 |
20090079087 | Semiconductor device and method for fabricating the same - A semiconductor device includes a conductive pattern formed on a substrate, a conductive land formed to come into contact with at least part of the top surface of the conductive pattern, and a conductive section formed on the conductive land. The conductive section is electrically connected through the conductive land to the conductive pattern. | 03-26-2009 |
20090091037 | Methods for Fabricating Contacts to Pillar Structures in Integrated Circuits - A pillar structure that is contacted by a vertical contact is formed in an integrated circuit. A hard mask is formed and utilized to pattern a least a portion of the pillar structure. The hard mask comprises carbon. Subsequently, the hard mask is removed. A conductive material is then deposited in a region previously occupied by the hard mask to form the vertical contact. The hard mask may, for example, comprise diamond-like carbon. The pillar structure may have a width or diameter less than about 100 nanometers. | 04-09-2009 |
20090091038 | AIR GAP FOR INTERCONNECT APPLICATION - The present disclosure provides a method for fabricating an integrated circuit. The method includes forming an energy removable film (ERF) on a substrate; forming a first dielectric layer on the ERF; patterning the ERF and first dielectric layer to form a trench in the ERF and the first dielectric layer; filling a conductive material in the trench; forming a ceiling layer on the first dielectric layer and conductive material filled in the trench; and applying energy to the ERF to form air gaps in the ERF after the forming of the ceiling layer. | 04-09-2009 |
20090091039 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR SUBSTRATE - According to the present invention, for collective molding of semiconductor devices, a semiconductor substrate includes first electrodes formed on the front side, second electrodes formed on the back side and connected to external electrode terminals, and a plurality of semiconductor element mounting regions | 04-09-2009 |
20090091040 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes a memory cell transistor and a selective transistor formed on a semiconductor substrate, a first interlayer insulating film which is formed on the semiconductor substrate, an insulating layer formed by use of a material higher in dielectric constant than the first interlayer insulating film, a contact plug which penetrates the insulating layer and the first interlayer insulating film and which is electrically connected to a drain of the selective transistor, and a bit line which is in contact with the contact plug. A partial region in the bottom surface of the bit line is located lower than the upper surface of the contact plug, and is in contact with the surface of the insulating layer, and the partial region is also in contact with the side surface of the contact plug. | 04-09-2009 |
20090102054 | SEMICONDUCTOR PACKAGE - A semiconductor package is disclosed. One embodiment provides a semiconductor package singulated from a wafer includes a chip defining an active surface, a back side opposite the active surface, and peripheral sides extending between the active surface and the back side; a contact pad disposed on the active surface; and a metallization layer extending from the contact pad onto a portion of the peripheral sides of the chip. | 04-23-2009 |
20090102055 | Semiconductor device - It is an object of the invention to provide semiconductor devices which can protect privacy of consumers or holders of commercial products and control the communication range according to use, even when the semiconductor device which can exchange data without contact is mounted on the commercial products. A semiconductor device of the invention includes an element group including a plurality of transistors over a substrate; a first conductive film functioning as an antenna over the element group; a second conductive film surrounding the first conductive film; an insulating film covering the first and second end portions; and a third conductive film over the insulating film. The first conductive film is provided in the shape of a coil, and each end portion of the first conductive film is connected to the element group. First and second end portions of the second conductive film are not connected to each other. | 04-23-2009 |
20090102056 | Patterned Leads For WLCSP And Method For Fabricating The Same - The present invention provides patterned leads for a wafer level chip size package and methods for fabricating the same. The patterned leads include connection leads and solder pads. In designing, a compensation pattern is disposed on the connection lead or on the solder pad, so as to increase the distance between the connection lead and the solder pad. The present invention meets a tendency of increasing quantity per area of peripheral arrayed compatible pads and solder bumps on a semiconductor chip, and also saves more space for layout of leads on the chip bottom surface so as to avoid potential short circuit in between which happens in increasing probability with increasing quantity per area on the condition of the lead and the solder bump. | 04-23-2009 |
20090102057 | SEMICONDUCTOR DEVICE - The semiconductor device according to the present invention includes a semiconductor layer, an interlayer dielectric film formed on the semiconductor layer, a wire formed on the interlayer dielectric film with a metallic material to have a width of not more than 0.4 μm, and a broad portion integrally formed on the wire to extend from the wire in the width direction thereof. | 04-23-2009 |
20090108458 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE - In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, an electrical bus embedded in a dielectric material below a surface of a semiconductor substrate is disclosed. Other embodiments are described and claimed. | 04-30-2009 |
20090108459 | SEMICONDUCTOR DEVICE - A semiconductor device includes first underlying lines in an underlying wiring layer electrically connected to and shaped like a first semiconductor region, second underlying lines in the underlying wiring layer electrically connected to and shaped like a second semiconductor region, a first intermediate line in an intermediate wiring layer electrically connected to the first underlying lines, the first intermediate line including finger regions shaped like the first underlying lines, a coupling section to electrically interconnect the finger regions, a second intermediate line in the intermediate wiring layer electrically connected to the second underlying lines, the second intermediate line including finger regions shaped like the second underlying lines, and a coupling section to electrically connect the finger regions, a first overlying line in an overlying wiring layer electrically connected to the first intermediate line, and a second overlying line in the overlying wiring layer electrically connected to the second intermediate line. | 04-30-2009 |
20090115064 | SPACER PROCESS FOR ON PITCH CONTACTS AND RELATED STRUCTURES - Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. Also disclosed are structures associated with the methods. In one or more embodiments, contacts are formed on pitch with other structures, such as conductive interconnects. The interconnects may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. The features in the selectively definable material are trimmed to desired dimensions. Spacer material is blanket deposited over the features in the selectively definable material and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed to leave a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts. In some embodiments, the on pitch contacts may be used to electrically contact conductive interconnects in the substrate. | 05-07-2009 |
20090115065 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Embodiments relate to a semiconductor device that may include a semiconductor substrate including a cell area and a pad area, a first insulating layer on and/or over the semiconductor substrate, and a first interconnection trench formed in the first insulating layer on and/or over a cell area having a first width. It may also include a first pad trench formed in the first insulating layer on and/or over the pad area and having a second width wider than the first width, and a first metal interconnection formed in the first interconnection trench and a first pad formed in the first pad trench. It may further include a second insulating layer on and/or over the first insulating layer, a second interconnection trench, exposing the first metal interconnection, and a second pad exposing the first pad and having a position and width substantially identical to that of the first pad trench. | 05-07-2009 |
20090115066 | Metal wiring layer and method of fabricating the same - A metal wiring layer and a method of fabricating the metal wiring layer are provided. The method includes forming a dielectric layer on a substrate, forming a plurality of dielectric layer patterns and holes therein on the substrate by etching part of the dielectric layer, with a cross sectional area of the holes in the dielectric layer patterns decreasing with increasing distance away from the substrate and the holes exposing the substrate, forming a trench by etching a portion of the substrate exposed through the holes in the dielectric layer patterns, and forming a metal layer which fills the trench and the holes in the dielectric layer patterns. Thus, it is possible to prevent the occurrence of an edge build-up phenomenon by forming a metal layer in a plurality of holes in the dielectric layer patterns having a cross sectional area decreasing with increasing distance away from the substrate. Therefore, it is possible to prevent the transmittance of a liquid crystal layer from decreasing due to a failure to properly fill liquid crystal molecules in the liquid crystal layer, and thus to increase the quality of display. | 05-07-2009 |
20090121360 | Semiconductor device having dual damascene structure - The semiconductor device includes multilayer wirings of a dual damascene structure. The multilayer wirings include a first wiring layer formed on a semiconductor substrate and a second wiring layer formed on the first wiring layer. The first wiring layer includes a first insulation film, plural first vias provided in the first insulation film, a second insulation film provided on the first insulation film, and a first wiring provided on the first vias and connected to those first vias in the second insulation film. The second wiring layer includes a third insulation film, plural second vias provided in the third insulation film, an adhesive layer provided on the third insulation film, a fourth insulation film provided on the adhesive layer, and a second wiring provided on the second vias and connected to those second vias in the fourth insulation film. In the first wiring layer, the aspect ratio L of a wiring having the minimum wiring width and the via aspect ratio V are in a relationship of L≧V and in the second wiring layer, the aspect ratio L of a wiring having the minimum wiring width and the via aspect ratio V is in a relationship of L05-14-2009 | |
20090127712 | NANOTUBE-BASED DIRECTIONALLY-CONDUCTIVE ADHESIVE - A tape adhesive type material is directionally conductive. According to an example embodiment of the present invention, carbon nanotubes ( | 05-21-2009 |
20090127713 | SEMICONDUCTOR DEVICE - It is an object of the present invention to surely protect a predetermined semiconductor element or a predetermined semiconductor element group in an analog block from a noise generated from a digital block. A semiconductor device according to the present invention includes a semiconductor substrate, a digital block to be a region in which a digital circuit is formed and an analog block to be a region in which an analog circuit is formed, arranged by separating an upper surface of the semiconductor substrate and a substrate potential fixing region provided on the semiconductor substrate so as to surround in a planar view the predetermined semiconductor element group in the analog block, and a pad connected to the substrate potential fixing region and receiving a predetermined potential from an external part. | 05-21-2009 |
20090134523 | Semiconductor device and method of manufacturing the same - A semiconductor chip includes a semiconductor chip region provided with a plurality of internal circuits, and a plurality of electrode pads provided proximate to an outer edge of the semiconductor chip region and each electrically connected to any one of the plurality of internal circuits. The plurality of electrode pads include: a long pad including a probe region with which a probe is brought into contact, and a bonding region provided in a position different from a position of the probe region, for bonding a wire; and a short pad for high frequency, which is formed to have a smaller pad area compared with the long pad and inputs/outputs a high frequency signal by employing a structure including the bonding region but the probe region. | 05-28-2009 |
20090134524 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor device comprising a signal transmission line of a microstrip structure, capable of increasing the characteristic impedance of the signal transmission line and reducing coupling between a plurality of signal lines. In a signal transmission line of a microstrip structure composed of a signal line and a ground plate, the capacitance between wires is reduced and the characteristic impedance can be increased by forming holes in the signal line or in the ground plate. The coupling between a plurality of signal lines can also be reduced. | 05-28-2009 |
20090140432 | PAD STRUCTURE TO PROVIDE IMPROVED STRESS RELIEF - A semiconductor interconnection comprises a semiconductor device, a substrate adjacent the semiconductor device, and a plurality of spring contacts on the semiconductor device or the substrate. A plurality of solder connections are on the opposite semiconductor device or substrate. Each spring contact comprises a contact surface and a conductive material on the contact surface. Upon assembly of the semiconductor device and the substrate, the conductive material on the plurality of spring contacts makes contact with each of the plurality of solder connections. The conductive material is in a liquid state at manufacturing or operating temperatures of the semiconductor device. Thus, the conductive material could be a solid at room temperature and transition to a liquid state at the semiconductor's manufacturing or operating temperatures. | 06-04-2009 |
20090140433 | MEMS chip-to-chip interconnects - A chip-to-chip interconnect system suited for MEMS that do not require low-resistance connections is described. The interconnects may be fabricated simultaneously with MEMS ribbon structures such as are found in MEMS optical modulators. | 06-04-2009 |
20090140434 | FLEXIBLE COLUMN DIE INTERCONNECTS AND STRUCTURES INCLUDING SAME - A flexible column interconnect for a microelectronic substrate includes a plurality of conductive columns extending from a bond pad or other conductive terminal in substantially mutually parallel arrangement, providing redundant current paths between the bond pad and a common cap in the form of a contact pad to which they are all joined. The flexibility of the interconnect may be varied by controlling the column dimensions, height, aspect ratio, number of columns, column material and by applying a supporting layer of dielectric material to a controlled depth about the base of the columns. A large number of interconnects may be formed on a wafer, partial wafer, single die, interposer, circuit board, or other substrate. | 06-04-2009 |
20090146310 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device subjected to an optical annealing process by radiation light whose principal wavelength is 1.5 μm or less includes a circuit pattern region formed on a semiconductor substrate, and a dummy pattern region formed separately from the circuit pattern region on the semiconductor substrate. The circuit pattern region has an integrated circuit pattern containing a gate pattern related to a circuit operation. The dummy pattern region has dummy gate patterns that have the same structure as that of a gate pattern used in the integrated circuit pattern and the dummy gate patterns are repeatedly arranged with a pitch 0.4 times or less the principal wavelength. | 06-11-2009 |
20090146311 | INTERCONNECT STRUCTURE - An interconnect structure is disposed on a substrate with a conductive part thereon and includes a first porous low-k layer on the substrate, a damascene structure in the first porous low-k layer, a second porous low-k layer over the first porous low-k layer and the damascene structure, and a first UV cutting layer at least between the first porous low-k layer and the second porous low-k layer. The damascene structure is electrically connected with the conductive part. The UV cutting layer is a UV reflection layer or a UV reflection-absorption layer. | 06-11-2009 |
20090152730 | Interconnected structure for TFT-array substrate - An exemplary interconnected structure for transferring a voltage signal to a thin film transistor (TFT) array substrate includes a first metal layer ( | 06-18-2009 |
20090152731 | SEMICONDUCTOR PACKAGE - In a semiconductor package, at least two of connection pads are formed into different-shape pads which are different in planar shape from other connection pads, and one different-shape pad and another different-shape pad are disposed in a manner that, when the position of the one different-shape pad is rotated about the center point of the semiconductor package, the position does not coincide with the disposition position of the other different-shape pad. | 06-18-2009 |
20090152732 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - By covering inner surfaces of a wiring groove | 06-18-2009 |
20090152733 | DEEP CONTACTS OF INTEGRATED ELECTRONIC DEVICES BASED ON REGIONS IMPLANTED THROUGH TRENCHES - An embodiment of an integrated circuit includes first and second semiconductor layers and a contact region disposed in the second layer. The first semiconductor layer is of a first conductivity, and the second semiconductor layer is disposed over the first layer and has a surface. The contact region is contiguous with the surface, contacts the first layer, includes a first inner conductive portion, and includes an outer conductive portion of the first conductivity. The contact region may extend deeper than conventional contact regions, because where the inner conductive portion is formed from a trench, doping the outer conductive portion via the trench may allow one to implant the dopants more deeply than conventional techniques allow. | 06-18-2009 |
20090160062 | Semiconductor Devices and Methods of Manufacturing Thereof - Semiconductor devices, methods of manufacturing thereof, lithography masks, and methods of designing lithography masks are disclosed. In one embodiment, a semiconductor device includes a plurality of first features disposed in a first material layer. At least one second feature is disposed in a second material layer, the at least one second feature being disposed over and coupled to the plurality of first features. The at least one second feature includes at least one void disposed between at least two of the plurality of first features. | 06-25-2009 |
20090160063 | Semiconductor Device - A semiconductor device includes a semiconductor substrate; a sealing resin layer formed on a top face of the semiconductor substrate; a metal post formed on the top face of the semiconductor substrate such that a top face of the metal post is exposed through the sealing resin layer; a projecting electrode formed on the top face of the metal post; and a low-elasticity resin layer made of a resin material with an elasticity modulus lower than that of the sealing resin layer and formed on the top face of the sealing resin layer such that part of the low-elasticity resin layer lies between the projecting electrode and the sealing resin layer. | 06-25-2009 |
20090166877 | ELECTRO-OPTIC DEVICE AND A METHOD FOR PRODUCING THE SAME - The present invention relates to a planar electro-optic device and a method for producing the same. The device comprises an embedded woven structure of conductive wires ( | 07-02-2009 |
20090166878 | Semiconductor Device and Method of Fabricating the Same - Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes an interlayer dielectric film on a substrate, a plug in the interlayer dielectric film, a metal layer on the plug, and an impure anti-reflective coating (ARC) layer on the metal layer. | 07-02-2009 |
20090166879 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a semiconductor chip, a package substrate, a first attaching member, a second attaching member, a connecting member and a molding member. The package substrate has a central region and an edge region. The first attaching member attaches the semiconductor chip to the central region of the package substrate. The second attaching member is arranged in the edge region of the package substrate. The second attaching member includes first attaching patterns extending in a first direction, and second attaching patterns extending in a second direction. The connecting member electrically connects the semiconductor chip to the package substrate. The molding member is attached to the package substrate using the second attaching member to molding the semiconductor chip. | 07-02-2009 |
20090166880 | ELECTRICAL BONDING PAD - An electrical bonding pad for an integrated circuit, comprising an encapsulation layer for receiving electrical signals and for covering a portion of a stack of conductive layers. The pad further comprises a conductive area in the stack, with the conductive area being at least partially covered by the encapsulation layer. The conductive area is intended for the passage of electrical signals received by the encapsulation layer and traveling towards a circuit core, and is electrically insulated from the encapsulation layer in a manner that at least partially decouples the electrical signals received from the encapsulation layer. | 07-02-2009 |
20090174079 | PLATED PILLAR PACKAGE FORMATION - A device includes a first plurality of interconnects, a first fill material surrounding the first plurality of interconnects, a first plurality of traces, and a first chip. The first plurality of interconnects extend from a first side of the fill material to an opposite side of the fill material. Each of the traces is connected to at least two of the first plurality of interconnects. The first chip is coupled to at least one of the first plurality of traces. | 07-09-2009 |
20090184426 | CONTACT PLUGS OF SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - The contact plugs of a semiconductor device includes first contact plugs having an elliptical sectional shape, and second contact plugs formed on the first contact plugs and having a circular sectional shape. The second contact plugs being configured to come in contact with the first contact plugs, thereby preventing voids from being formed. | 07-23-2009 |
20090184427 | FLASH MEMORY DEVICE WITH WORD LINES OF UNIFORM WIDTH AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing a semiconductor device, the method including: forming a bit line in a semiconductor substrate; forming a plurality of word lines which intersect with the bit line at predetermined intervals on the semiconductor substrate; eliminating a portion of the plurality of word lines; forming an interlayer insulating film on the semiconductor substrate; and forming a metal plug which penetrates through the interlayer insulating film and is coupled to the bit line in a region where the portion of the plurality of word lines was eliminated. | 07-23-2009 |
20090184428 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor substrate, an interwiring insulating film formed on the semiconductor substrate, a first protective film formed on the interwiring insulating film having an opening and a pad metal formed on the opening are provided. A groove is formed in a portion corresponding to a peripheral portion of the pad metal, and the groove is covered with the pad metal. Thus, without decreasing bonding properties, insulation between pads can be maintained as well as cracks in a protective film around pads can be prevented. | 07-23-2009 |
20090184429 | Integrated Circuit Comprising Conductive Lines and Contact Structures and Method of Manufacturing an Integrated Circuit - An integrated circuit comprises a first conductive lines and second lines as well as contact structures being in contact with the first and second conductive lines. The first conductive lines are arranged in a first metallization level, and second conductive lines are arranged in a second metallization level arranged above the first metallization level. The second conductive lines are arranged above the contact structures, and a pitch of neighboring contact structures is equal to a pitch of neighboring second conductive lines. The distance between neighboring contact structures is smaller than 100 nm. | 07-23-2009 |
20090189288 | ANGLED FLYING LEAD WIRE BONDING PROCESS - A method is described having the steps of providing a surface having a plurality of wire bondable locations; wire bonding a wire to each of the wire bondable locations using a wire capillary tool; controlling the position of the capillary tool with respect to the substrate; after forming a wire bond of the wire to the wire bondable location moving the capillary tool relative to the surface as the capillary tool is moved away from the surface to form a wire having a predetermined shape. | 07-30-2009 |
20090194881 | Method for Manufacturing a Wafer Level Package - A method for manufacturing a wafer level package of an integrated circuit element for direct attachment to a wiring board is disclosed. An integrated circuit element includes input/output pads located on an active side. A non-conductive support structure is formed on the active side of the integrated circuit element in an area that is free from input/output pads. A conductive path is formed upon the support structure and a non-conductive coating is formed on over the active side of the integrated circuit element such that a surface is formed which leaves interface pads accessible. | 08-06-2009 |
20090194882 | ELECTRONIC DEVICE - One embodiment provides a method of manufacturing semiconductor devices. For example, a sawn and expanded wafer is utilized having dielectrical material deposited between the diced and deposited chips. The method includes placing at least two chips on a metallic layer, depositing mold material on the metallic layer and between the chips, and selectively removing a portion of the mold material from the metallic layer to selectively expose a portion of the metallic layer. The method additionally includes covering the selectively exposed portion of the metallic layer with a conductive material, and singulating the at least two chips. | 08-06-2009 |
20090194883 | DATA LINE STRUCTURE IN LEAD REGION AND MANUFACTURING METHOD THEREOF - An embodiment of the invention provides a data line structure in a lead region of a thin film transistor liquid crystal display (TFT-LCD). The data line structure in the lead region comprises a substrate and a gate layer data line segment, a dielectric layer, a data line lead, and a passivation layer, which are formed sequentially in the lead region on the substrate. The gate layer data line segment extends corresponding to the data line lead; the data line lead is formed with a via hole therein; a portion of the gate insulating layer and a portion of the passivation layer in a position corresponding to the via hole are removed so as to form a connection hole together with the via hole; a connection line segment is formed in the connection hole, and the gate layer data line segment and the data line lead are connected by the connection line segment in the connection hole. | 08-06-2009 |
20090194884 | POWER SEMICONDUCTOR MODULE INCLUDING A CONTACT ELEMENT - A power semiconductor module including a contact element. One embodiment provides an electrically conductive contact element extending in a longitudinal direction and having a first end and a second end lying opposite the first end. The contact element has a first flange at its first end. The first flange is embodied such that when the contact element is placed with the first flange ahead onto a plane perpendicular to the longitudinal direction, the first flange has with the plane a number of first contact areas spaced apart from one another. | 08-06-2009 |
20090194885 | SEMICONDUCTOR DEVICE HAVING WIRING LINE AND MANUFACTURING METHOD THEREOF - On the lower surface of a semiconductor construct having an external connection electrode, there are formed an insulating film having a planar size greater than that of the semiconductor construct, and a metal layer and a mask metal layer having a connection pad portion in which a first opening corresponding to the external connection electrode is formed. A laser beam is applied using the mask metal layer as a mask, and a second opening is thereby formed in a part of the insulating film corresponding to the external connection electrode. Then, a connection conductor is formed to connect a wiring line to the external connection electrode via the second opening of the insulating film. | 08-06-2009 |
20090200679 | SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING THE SAME - A semiconductor apparatus including a semiconductor substrate, an insulating layer, a via hole, and a through-hole interconnection is provided. The insulating layer is formed on the semiconductor substrate. The via hole is formed through the semiconductor substrate and the insulating layer. The through-hole interconnection has a conductive layer formed on an insulating layer in the via hole. The surface of the insulating layer formed on the inner surface of the via hole is substantially planarized by filling a recessed portion on a boundary between the semiconductor substrate and the insulating layer formed on the semiconductor substrate. | 08-13-2009 |
20090200680 | SEMICONDUCTOR DEVICE - A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card. | 08-13-2009 |
20090200681 | Forming Compliant Contact Pads For Semiconductor Packages - In one embodiment, the present invention includes a semiconductor package having a substrate with a first surface to support a semiconductor die. A second surface of the substrate includes compliant conductive pads to provide electrical connections to the semiconductor die. In this way, improved connection between the semiconductor package and a socket is provided. Other embodiments are described and claimed. | 08-13-2009 |
20090212438 | INTEGRATED CIRCUIT DEVICE COMPRISING CONDUCTIVE VIAS AND METHOD OF MAKING THE SAME - A semiconductor substrate for an integrated circuit device comprises at least one insulating substrate region being formed of a cohesive insulating material. The insulating substrate region includes at least two conductive vias extending at least between a first surface and a second surface of the insulating substrate region. | 08-27-2009 |
20090212439 | FLUORINE DEPLETED ADHESION LAYER FOR METAL INTERCONNECT STRUCTURE - A line trough and a via cavity are formed within a dielectric layer comprising a fluorosilicate glass (FSG) layer. A fluorine depleted adhesion layer is formed within the line trough and the via cavity either by a plasma treatment that removes fluorine from exposed surfaces of the FSG layer, or by deposition of a substantially fluorine-free dielectric layer. Metal is deposited within the line trough and the via cavity to form a metal line and a metal via. The fluorine depleted adhesion layer provides enhanced adhesion to the metal line compared with prior art structures in which a metal line directly contacts a FSG layer. The enhanced adhesion of metal with an underlying dielectric layer provides higher resistance to delamination for a semiconductor package employing lead-free C4 balls on a metal interconnect structure. | 08-27-2009 |
20090212440 | Semiconductor device - An object of the present invention is to solve the problem that the number of pads increases due to high packaging density and the size of semiconductor devices increases due to increase of the pad density. A semiconductor device according to the present invention uses a conductor trace on an interconnection substrate to interconnect two nonadjacent pads. | 08-27-2009 |
20090218698 | Wafer-Level Integrated Circuit Package with Top and Bottom Side Electrical Connections - A wafer-level, batch processed, die-sized integrated circuit (IC) package with both top and bottom side electrical connections is disclosed. In one aspect, a number of bonding wires can be attached to bond pads on the top side (active circuit side) of an IC wafer. Trenches can be formed in the wafer at scribe regions and the bonding wires can extend through the trench. The trench can be filled with coating material. The bonding wires can be partially exposed on the top and/or bottom sides of the wafer to distribute electrical connections from the bond pads to the top and/or bottom sides of the wafer. | 09-03-2009 |
20090230557 | Semiconductor Device and Method for Making Same - One or more embodiments are related to a semiconductor device, comprising: a metallic layer having a top surface and a sidewall surface; an intermediate layer disposed on a sidewall surface of the metallic layer; a dielectric layer disposed over the metallic layer, the dielectric layer having an opening formed therethrough; and a conductive material disposed within the opening, the conductive material at least partially overlying the top surface of the metallic layer, the conductive material being electrically coupled to the metallic layer. | 09-17-2009 |
20090230558 | Semiconductor device and method for manufacturing the same - The present invention is a method for manufacturing a semiconductor device having a conductor and an insulating film on a substrate, the method including the steps of forming the conductor on the substrate, forming the insulating film on the conductor, removing the insulating film on the conductor, and blowing an organosilane gas and a hydrogen gas to reduce an oxidized region on the conductor, wherein the oxidized region on the conductor is formed when the insulating film is removed. | 09-17-2009 |
20090230559 | Semiconductor device - A semiconductor device having macro circuit including a plurality of fine interconnections, an extension interconnection wider than the fine interconnections, having a first end connected to one or more of the fine interconnections and a second end located in an area of the semiconductor device external to the macro circuit, and one or more of the fine interconnections widened towards the connection to the extension wiring interconnection. The extension interconnection is formed in the same layer as one or more of the interconnections connected to the extension interconnection. | 09-17-2009 |
20090230560 | Semiconductor device and manufacturing method thereof - A semiconductor device and manufacturing method thereof improving moisture resistance of a FeRAM. After a probe test using a pad, a metal film is formed to cover the pad in an opening of a protective film and a region from the pad to an opening outer periphery of the protective film. On the metal film, a metal bump is formed. The metal film is formed to have a two-layer structure of the first and second metal films. Materials of the lower and upper layers are selected mainly in consideration of adhesion to the protective film and adhesion to the metal bump, respectively. Film formation conditions thereof are set to provide metal films with a desired quality and thickness. Thus, penetration of moisture from the pad or the periphery into a ferroelectric capacitor can be prevented and therefore, occurrence of potential inversion abnormalities due to penetrated moisture can be effectively suppressed. | 09-17-2009 |
20090236748 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device may include the following. A diffusion barrier formed over a semiconductor substrate having a conductive layer. An etching stop layer formed over a diffusion barrier. Inter-metal dielectric (IMD) layers (e.g. having via holes formed over an etching stop layer and trenches wider than the via holes). Metal interconnections that fill via holes and trenches. Via holes in IMD layers may pass through a diffusion barrier and an etching stop layer to connect to a conductive layer in a semiconductor substrate. | 09-24-2009 |
20090243114 | Densely packed metal segments patterned in a semiconductor die - A method of patterning a metal layer in a semiconductor die comprises forming a mask on the metal layer to define an open region and a dense region. The method further comprises etching the metal layer at a first etch rate to form a number of metal segments in the open region and etching the metal layer at a second etch rate to form a number of metal segments in the dense region, where the first etch rate is approximately equal to the second etch rate. The method further comprises performing a number of strip/passivate cycles to remove a polymer formed on sidewalls of the metal segments in the dense region. The sidewalls of the metal segments in the dense region undergo substantially no undercutting and residue is removed from the sidewalls of the metal segments in the dense region. | 10-01-2009 |
20090243115 | Semiconductor device and method of manufacturing the same - Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes: a memory array on a first substrate; and a peripheral circuit on a second substrate, wherein the first substrate and the second substrate may be attached to each other so that the memory array and the peripheral circuit are electrically connected to each other. | 10-01-2009 |
20090243116 | REDUCING PATTERNING VARIABILITY OF TRENCHES IN METALLIZATION LAYER STACKS WITH A LOW-K MATERIAL BY REDUCING CONTAMINATION OF TRENCH DIELECTRICS - By forming a protection layer prior to the application of the planarization layer during a dual damascene strategy for first patterning vias and then trenches, enhanced etch fidelity may be accomplished. In other aspects disclosed herein, via openings and trenches may be patterned in separate steps, which may be accomplished by different etch behaviors of respective dielectric materials and/or the provision of an appropriate etch stop layer, while filling the via opening and the trench with a barrier material and a highly conductive metal may be achieved in a common fill sequence. Hence, the via opening may be formed on the basis of a reduced aspect ratio, while nevertheless providing a highly efficient overall process sequence. | 10-01-2009 |
20090243117 | CONTACT STRUCTURE, A SEMICONDUCTOR DEVICE EMPLOYING THE SAME, AND METHODS OF MANUFACTURING THE SAME - A contact structure that includes a first pattern formed on a substrate, wherein the first pattern has a recessed region in an upper surface thereof, a planarized buffer pattern formed on the first pattern, and a conductive pattern formed on the planarized buffer pattern. | 10-01-2009 |
20090243118 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device. | 10-01-2009 |
20090256265 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes a plurality of contact layers located between two lines running in parallel in a first direction. Each of the contact layers has a structure in which an upper contact and a lower contact are coupled together. The plurality of contact layers are arranged zigzag along the first direction, and coupling portions of the upper contact and the lower contact are displaced from the center of the upper contact in a second direction perpendicular to the first direction. | 10-15-2009 |
20090261477 | Semiconductor device and method of manufacturing the same - A method of manufacturing a semiconductor device including a trench and a contact hole filled with a copper line, a diffusion barrier layer formed in inner walls of the trench and the contact hole, and a seed-copper layer formed on and/or over the diffusion barrier layer. The surface roughness of the seed-copper layer can be reduced by performing a plasma process thereon. | 10-22-2009 |
20090267234 | Semiconductor Device and Method of Manufacturing a Semiconductor Device - The invention relates to a semiconductor device comprising a substrate ( | 10-29-2009 |
20090267235 | Reduced Inductance Interconnect for Enhanced Microwave and Millimeter-Wave Systems - According to one embodiment of the present invention, a microwave or millimeter wave module includes a dielectric layer having a pocket formed substantially through the dielectric layer. The dielectric is attached to a metal substrate. The pocket has substantially vertical sidewalls. An integrated circuit is disposed in the pocket. Opposing sides of the integrated circuit are substantially parallel to the sidewalls of the pocket. An interconnect electrically couples the integrated circuit to a bond pad disposed on the outer surface of the dielectric layer. The interconnect has a length that is minimized to result in reduced inductance of the semiconductor device. | 10-29-2009 |
20090273088 | Semiconductor Device and Method for Fabricating the Same - A method for fabricating a semiconductor device includes forming a metal word line additionally over a vertical transistor to obtain a multi-layered structure, thereby preventing degradation of the operating speed of the semiconductor device by preventing an increase of resistance of a damascene word line that connects a surrounding gate of a vertical transistor. As a result, the yield and reliability of the semiconductor device can be improved. | 11-05-2009 |
20090273089 | Method for manufacturing semiconductor device and semiconductor device - A semiconductor device in which a conductor of a bit line may be made as large in thickness as possible to reduce resistance of the bit line and to reduce capacitance across the neighboring bit lines. The device includes a first interlayer film having a first contact metal part accommodated in it, and a second interlayer film. The second interlayer film includes a trench, and is deposited on the first interlayer film. The semiconductor device also includes a metal conductor filled in and protruding above the trench, and a hard mask film deposited on the metal conductor. The semiconductor device also includes sidewalls formed on lateral surfaces of the hard mask film and the metal conductor for overlying the second interlayer film, and a third interlayer film formed above the second interlayer film inclusive of the hard mask film and the sidewalls. The device also includes a contact hole opened through the third interlayer film and the second interlayer film and in the first interlayer film to expose the first contact metal part between the sidewalls. The device further includes a second contact metal part | 11-05-2009 |
20090273090 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Embodiments relate to a semiconductor device and a method for manufacturing the same. Embodiments may include forming a lower porous oxide layer on a semiconductor substrate having a conductive layer, forming a pyrolytic polymer layer on the lower porous oxide layer, forming an upper porous oxide layer on the pyrolytic polymer layer, forming a via hole by sequentially etching the upper porous oxide layer, the pyrolytic polymer layer, and the lower porous oxide layer, forming a trench having a width larger than a width of the via hole by sequentially etching the upper porous oxide layer and the pyrolytic polymer layer in such a manner that the trench is connected with the via hole, forming metal interconnections by filling the via hole and the trench with a metal thin film, and forming a vacuum between the upper and lower porous oxide layers by removing the pyrolytic polymer layer. | 11-05-2009 |
20090273091 | SEMICONDUCTOR DEVICE AND METAL LINE FABRICATION METHOD OF THE SAME - Embodiments relate to a method for forming a wiring in a semiconductor device, that may include laminating a conductive layer for wiring formation on a semiconductor substrate, forming a photoresist layer pattern on the conductive layer, performing primary dry etching for the conductive layer after employing the photoresist layer pattern as a mask, thereby forming a wiring pattern, partially removing the photoresist layer pattern through secondary dry etching, thereby forming a passivation layer on a surface of the wiring pattern, performing tertiary dry etching for the wiring pattern and a diffusion barrier after employing the photoresist layer pattern as a mask, thereby forming a metal wiring, and removing the photoresist layer pattern. | 11-05-2009 |
20090273092 | SEMICONDUCTOR MODULE HAVING AN INTERCONNECTION STRUCTURE - In a method for manufacturing a semiconductor module, a metal layer is formed on a support substrate. Then, first conductive posts and a first insulating layer are formed on the metal layer. The first insulating layer surrounds the sides of the first conductive posts. Then, second conductive posts are formed above the first conductive posts. The second conductive posts are electrically connected to the first conductive posts. Then, a second insulating layer is formed so as to cover the second conductive posts. The second insulating layer is made of adhesive resin. Finally, a semiconductor device is adhered to the second conductive posts by the second insulating layer while a gap between the first semiconductor device and the first insulating layer is sealed by the second insulating layer. | 11-05-2009 |
20090283914 | SILICON INTERPOSER AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a silicon interposer, includes a step of forming a protection film on a surface, on which an element portion is formed, of a silicon wafer, a step of forming open holes according to planar arrangements of through holes which pass through the silicon wafer in a thickness direction, a step of forming the through holes by etching the silicon wafer using the protection film as a mask, a step of forming an oxide film on inner wall surfaces of the through holes by a thermal oxidation, a step of forming a contact hole, which is in communication with the element portion, in the protection film, and a step of forming wirings on both surfaces of the silicon wafer. In the step of forming the wirings, one of the wirings is formed to be connected electrically to the element portion via a contact portion formed in the contact hole. | 11-19-2009 |
20090289371 | SWITCHING ELEMENT AND METHOD OF MANUFACTURING THE SAME - A switching element includes a first electrode, a second electrode, an ionic conductive portion and a buffer portion. The first electrode is configured to be available to feed metal ions. The ionic conductive portion is configured to contact the first electrode and the second electrode, and include an ionic conductor in which the metal ions are movable. The buffer portion is configured to have a smaller hardness than the ionic conductor, and be located between the first electrode and the second electrode along the ionic conductive portion. Electrical characteristics are switched by depositing or melting metal between said first electrode and said second electrode based on a potential difference between said first electrode and said second electrode. | 11-26-2009 |
20090289372 | Power Supply Network - A power supply network ( | 11-26-2009 |
20090289373 | Semiconductor device - The present invention provides a semiconductor device capable of preventing occurrence of cracking and the like, taking a large area, where wiring and the like that function as elemental devices can be arranged, within a plurality of interlayer insulation films, and reducing production cost. The semiconductor device according to the present invention has a low dielectric constant film having a dielectric constant of not less than 2.7. In the low dielectric constant film and the like, materials (e.g., a first dummy pattern, a second dummy pattern) with a larger hardness than that of the low dielectric constant film are formed at a part under a pad part. | 11-26-2009 |
20090289374 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MODULE, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE MODULE - A semiconductor device can include a plurality of semiconductor elements. The characteristics of each of the semiconductor elements can be easily tested during the production of the semiconductor device or when a failure occurs after the semiconductor device is mounted on a substrate, so that the quality can be well managed and a failure can be reliably analyzed. When not mounted on the substrate, the semiconductor device can have a connection structure in which the plurality of semiconductor elements are electrically independent of each other, so that their characteristics can be tested and analyzed by independently energizing the semiconductor elements. In a semiconductor device module having the semiconductor device mounted thereon, the connection structure can include a parallel circuit of the plurality of semiconductor elements. Therefore, all the semiconductor elements can be driven by applying a voltage between a pair of solder-bonding electrode pads disposed on the semiconductor device-mounting substrate. | 11-26-2009 |
20090294975 | Package for a Die - A package for a die comprising
| 12-03-2009 |
20090294976 | Method of Manufacuturing Semiconductor Memory Apparatus and Semiconductor Memory Apparatus Manufactured Thereby - A method of manufacturing a semiconductor memory apparatus includes fabricating a cell array to reduce parasite capacitance generated between a bit line and a gate pattern. The method may include determining a plug region by a storage-node plug contact mask and a bit line plug mask. The method may further include: forming a gate pattern of a cell transistor and depositing an insulation layer over a structure including the gate pattern; and forming a hard mask layer over the insulation layer. | 12-03-2009 |
20090294977 | SEMICONDUCTOR DIE AND BOND PAD ARRANGEMENT METHOD THEREOF - A bond pad arrangement method of a semiconductor die is provided. The bond pad arrangement method includes: determining a bond pad architecture including a plurality of bond pads at a peripheral region of the semiconductor die, where each of the bond pads is defined to have a predetermined connection region; controlling an orientation of each bond pad at the peripheral region of the semiconductor die, thereby selectively configuring the predetermined connection region thereof to be electrically connected to one of a plurality of conductive structures included in at least one metal interconnect layer of the semiconductor die; and storing a bond pad design of the bond pads at the peripheral region of the semiconductor die. | 12-03-2009 |
20090294978 | SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREFOR - To provide a semiconductor device with improved reliability. The semiconductor device includes a wiring board, a microcomputer chip flip-chip bonded over the wiring board via gold bumps, a first memory chip laminated over the microcomputer chip, wires for coupling the first memory chip to the wiring board, an underfill material with which a flip-chip coupling portion of the microcomputer chip is filled, and a sealing member for sealing the microcomputer chip and the first memory chip with resin. Further, the corner of a second opening portion of a solder resist film of the wiring board corresponding to the corner of the chip on the air vent side in charging the underfill material is made close to the microcomputer chip, which can improve the wettability and spread of the underfill material at the second opening portion, thus reducing the exposure of leads to the second opening portion, thereby improving the reliability of the semiconductor device. | 12-03-2009 |
20090294979 | SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - There is provided a method of manufacturing a semiconductor substrate. The method includes: (a) forming a wiring pattern on a substrate; (b) covering the wiring pattern with an insulating resin, thereby forming a first insulating layer; (c) forming a second insulating layer on the first insulating layer; (d) forming a plurality of grooves through the second insulating layer; (e) forming at least one via hole through the first and second insulating layers by irradiating at least one of the grooves with a laser beam; (f) forming a seed metal layer on an inner surface of the at least one via hole, inner surfaces of the grooves, and a surface of the second insulating layer; and (g) forming a plating layer in the at least one via hole and the grooves, by an electrolytic plating using the seed metal layer as a power feeding layer. | 12-03-2009 |
20090294980 | SEMICONDUCTOR DEVICE HAVING WIRING LAYER - Provided is a semiconductor device having a wiring layer formed of damascene wiring. The semiconductor device includes: a first wiring having a width equal to or larger than 0.5 μm; a second wiring adjacent to the first wiring and arranged with a space less than 0.5 μm from the first wiring; and a third wiring adjacent to the second wiring and arranged with a space equal to or smaller than 0.5 μm from the first wiring. In the semiconductor device, the second wiring and the third wiring are structured to have the same electric potential. | 12-03-2009 |
20090294981 | Methods for Defining and Using Co-Optimized Nanopatterns for Integrated Circuit Design and Apparatus Implementing Same - A set of layout nanopatterns is defined. Each layout nanopattern is defined by relative placements of a particular type of layout feature within a lithographic window of influence. A design space is defined as a set of layout parameters and corresponding value ranges that affect manufacturability of a layout. Layouts are created for the set of layout nanopatterns such that the created layouts cover the design space. The layouts for the set of layout nanopatterns are then optimized for manufacturability. A point in the design space is selected where the set of layout nanopatterns are co-optimized for manufacturability. A circuit layout is created based on the selected point in design space using the corresponding set of co-optimized layout nanopatterns. The optimized layouts for the set of layout nanopatterns and the associated circuit layout can be recorded in a digital format on a computer readable storage medium. | 12-03-2009 |
20090294982 | INTERCONNECT STRUCTURES WITH TERNARY PATTERNED FEATURES GENERATED FROM TWO LITHOGRAPHIC PROCESSES - A method for fabricating an interconnect structure for interconnecting a semiconductor substrate to have three distinct patterned structures such that the interconnect structure provides both a low k and high structural integrity. The method includes depositing an interlayer dielectric onto the semiconductor substrate, forming a first pattern within the interlayer dielectric material by a first lithographic process that results in both via features and ternary features being formed in the interconnect structure. The method further includes forming a second pattern within the interlayer dielectric material by a second lithographic process to form line features within the interconnect structure. Hence the method forms the three separate distinct patterned structures using only two lithographic processes for each interconnect level. | 12-03-2009 |
20090302477 | Integrated circuit with embedded contacts - In some embodiments, disclosed is an interconnect structure with embedded plugs. | 12-10-2009 |
20090309229 | Silicon single electron device - A silicon integrated circuit device comprising a near intrinsic silicon substrate in which there are one or more ohmic contact regions. An insulating layer lies above the substrate, and on top of the insulating layer is a lower layer of one or more aluminium gates. The surface of each of the lower gates is oxidised to insulate them from an upper aluminium gate that extends over the lower gates. | 12-17-2009 |
20090309230 | AIR GAP FORMATION AND INTEGRATION USING A PATTERNING CAP - Methods for patterning films and their resulting structures. In an embodiment, an amorphous carbon mask is formed over a substrate, such as a damascene layer. A spacer layer is deposited over the amorphous carbon mask and the spacer layer is etched to form a spacer and to expose the amorphous carbon mask. The amorphous carbon mask is removed selectively to the spacer to expose the substrate layer. A gap fill layer is deposited around the spacer to cover the substrate layer but expose the spacer. The spacer is removed selectively to form a gap fill mask over the substrate. The pattern of the gap fill mask is transferred, in one implementation, into a damascene layer to remove at least a portion of an IMD and form an air gap. | 12-17-2009 |
20090309231 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a first insulating layer having an opening therethrough; a first wiring pattern disposed on the first insulating layer; an external connection terminal provided on a portion of the first wiring pattern exposed from the opening; a second insulating layer which covers the first wiring pattern and having via holes therethrough; a second wiring pattern disposed within the second insulating layer and electrically connected to the first wiring pattern via a conductive material filled in at least one of the via holes; a semiconductor element having an electrode thereon and mounted on the second insulating layer to be electrically connected to the first wiring pattern through the electrode disposed in at least one of the via holes; an underfill resin filled between the semiconductor element and the second insulating layer; and a sealing resin portion which seals the semiconductor element. | 12-17-2009 |
20090315186 | Method for manufacturing semiconductor device and the semiconductor device - An etching stopper film is formed on top of a first insulating film. The etching stopper film is a film formed by depositing at least two films, made of constituent materials identical in quality to each other, one another. Subsequently, a first opening pattern is formed in the etching stopper film. Subsequently, a second insulating film is formed on top of the etching stopper film. Subsequently, a mask pattern is formed on top of the second insulating film. Subsequently, the second insulating film is etched with the use of the mask pattern as a mask to be followed by etching of the first insulating film with the use of the etching stopper film as a mask. | 12-24-2009 |
20090315187 | Semiconductor device - A semiconductor device includes a lower semiconductor layer with first conductive regions and including at least one dummy first conductive region, an upper semiconductor layer with second conductive regions on the lower semiconductor layer and including at least one dummy second conductive region, a penetration hole in the upper semiconductor layer and penetrating the dummy second conductive region and the upper semiconductor layer under the dummy second conductive region, a lower conductive line on the lower semiconductor layer and electrically connected to the first conductive regions, an upper conductive line on the upper semiconductor layer and electrically connected to the second conductive regions, and a first conductive plug in the penetration hole between the lower conductive line and the upper conductive line, the first conductive plug electrically connecting the lower and upper conductive lines and being spaced apart from sidewalls of the penetration hole. | 12-24-2009 |
20090321944 | SEMICONDUCTOR DEVICE WITH IMPROVED INTERCONNECTION OF CONDUCTOR PLUG - The semiconductor device comprises a conductor plug | 12-31-2009 |
20100001402 | Multiple Patterning Method - A self-aligned pitch fragmentation method for manufacturing an integrated circuit includes forming openings in a first layer, wherein the openings uncover first sections of a second layer arranged below the first layer. The first sections of the second layer are removed. The first layer is shrunk and the openings are expanded to form a first mask from the first layer, wherein the first mask exposes second sections and covers third sections of the second layer. The etch properties of the second sections are altered selectively to the third sections to facilitate the self-aligned pitch fragmentation method. | 01-07-2010 |
20100001403 | Method for designing semiconductor integrated circuit which includes metallic wiring connected to gate electrode and satisfies antenna criterion - A method of designing a semiconductor integrated circuit, includes verifying an antenna ratio of a metallic wiring connected to a first gate electrode and the first gate electrode, based on a layout information, and computing a gate area that should be added to avoid a plasma damage to the first gate electrode, based on the verifying. The method further includes modifying a layout of the semiconductor integrated circuit, based on the computing, by arranging a logic cell having a second gate electrode having the gate area or more and is in a state where the logic cell makes no contribution to a logic operation of the semiconductor integrated circuit, in a free region of the layout, and connecting the second gate electrode to the metallic wiring. | 01-07-2010 |
20100001404 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A layout structure of a semiconductor integrated circuit is provided with which narrowing and breaking of metal interconnects near a cell boundary can be prevented without increasing the data amount and processing time for OPC. A cell A and a cell B are adjacent to each other along a cell boundary. The interconnect regions of metal interconnects from which to the cell boundary no other interconnect region exists are placed to be substantially axisymmetric with respect to the cell boundary, while sides of diffusion regions facing the cell boundary are asymmetric with respect to the cell boundary. | 01-07-2010 |
20100007026 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor chip has a main surface. A conductive portion is provided on the main surface and made from a material having conductivity and malleability. A sealing resin portion has a surface facing the main surface. An electrode is provided on the conductive portion and passes through the sealing resin portion between the conductive portion and the surface. As a result, there is provided a semiconductor device that can be downsized. | 01-14-2010 |
20100007027 | INTEGRATED CONNECTION ARRANGEMENTS - A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive structure adjoins the outer conductive structure in a contact zone. A contact area is arranged at the outer conductive structure on the other side of the cutout. The contact zone and the contact area do not overlap. The bottom of the cutout is arranged to overlaps at least half of the contact area, to provide a step in the insulation layer at the edge of the cutout outside a main current path between the contact area and the inner conductive structure. | 01-14-2010 |
20100013101 | Method for Manufacturing a Multichip Module Assembly - A multichip module assembly includes a chipset of at least two chips. The chips have active sides, rear sides and chip contacts on their active sides adjacent each other and are embedded in a polymer matrix in a symmetrical manner relating to the top and the bottom surface of the chipset. Chip contacts are electrically connected by through polymer connectors that each extend from a chip contact to a surface of the polymer matrix. A film wiring line is arranged on a side of the polymer matrix for electrical connection of two through polymer connectors of two chips or a through polymer connector with an interconnect element arranged on a side of the polymer matrix. | 01-21-2010 |
20100019387 | Semiconductor device and fabrication method of the same - A semiconductor device which comprises an SOI substrate having an insulating layer between a semiconductor substrate layer and a semiconductor layer in a surface of which a semiconductor element is formed, and at least one external terminal provided, via an insulating film, on a surface of the semiconductor substrate layer and electrically connected to the semiconductor element. The semiconductor device further comprises a contact portion constituted by a conductive film reaching through the insulating film to electrically connect to the semiconductor substrate layer; and a potential fixing electrode provided, via the insulating film, on the surface of the semiconductor substrate layer and connected to the contact portion. | 01-28-2010 |
20100019388 | METHOD FOR AN INTEGRATED CIRCUIT CONTACT - A process for forming vertical contacts in the manufacture of integrated circuits and devices eliminating the need for precise mask alignment and allowing the etching of the contact hole controlled independent of the etching of the interconnect trough that may be repeated during the formation of multilevel integrated circuits. The process includes forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. | 01-28-2010 |
20100019389 | ELECTRIC LINKAGE IN A SEMICONDUCTOR ELECTRONIC DEVICE BETWEEN A NANOMETRIC CIRCUIT ARCHITECTURE AND STANDARD ELECTRONIC COMPONENTS - A semiconductor electronic device that includes a semiconductor substrate having a top surface; a seed layer positioned on the substrate and having a notched wall extending transversely with respect to the substrate top surface, the wall defining a first recess extending into the seed layer with a height equal to a thickness of the seed layer; a first conductive nanowire in contact with the notched wall, the first conductive nanowire having a contact portion extending into the first recess and covering opposite sidewalls and a bottom of the first recess; a first insulating nanowire in contact with a sidewall of the first conductive nanowire; an insulating layer on the contact portion of the first conductive nanowire and having a first window substantially in correspondence with the contact portion of the first conductive nanowire; and a first conductive die on the insulating layer that includes a conductive contact extending into the first window and contacting the contact portion of the first conductive nanowire. | 01-28-2010 |
20100025855 | ENHANCING STRUCTURAL INTEGRITY AND DEFINING CRITICAL DIMENSIONS OF METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES BY USING ALD TECHNIQUES - During the patterning of sophisticated metallization systems, a damaged surface portion of a sensitive low-k dielectric material may be efficiently replaced by a well-controlled dielectric material, thereby enabling an adaptation of the material characteristics and/or the layer thickness of the replacement material. Thus, established lithography and etch techniques may be used in combination with reduced critical dimensions and dielectric materials of even further reduced permittivity. | 02-04-2010 |
20100025856 | FABRICATION METHOD OF A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes the steps of (a) forming a plasma of a gas having carbon and fluorine, and forming an internal insulation film provided with a fluorine-doped carbon film formed on a substrate using the plasma; (b) forming a metal film on the internal insulation film; (c) etching the metal film according to a pattern to form a hard mask; (d) forming a concave part in the fluorine-doped carbon film by etching the fluorine-doped carbon film using the hard mask; (e) forming a film formation of a wiring material on the substrate for filling the concave part with the wiring material; (f) removing an excess part of the wiring material and the hard mask on the fluorine-doped carbon film for exposing a surface of the fluorine-doped carbon film; and (g) removing an oxide formed on the surface of the fluorine-doped film. | 02-04-2010 |
20100032843 | Through Silicon Via Layout - A system and method for forming under bump metallization layers that reduces the overall footprint of UBMs, through silicon vias, and trace lines is disclosed. A preferred embodiment comprises forming an under bump metallization layer over a plurality of through silicon vias, whereas the UBM is connected to only a portion of the total number of through silicon vias over which it is located. The trace lines connected to the through silicon vias may additionally be formed beneath the UBM to save even more space on the surface of the die. | 02-11-2010 |
20100032844 | INTERLAYER INSULATING FILM, WIRING STRUCTURE AND ELECTRONIC DEVICE AND METHODS OF MANUFACTURING THE SAME - A wiring structure of a semiconductor device or the like includes an interlayer insulating film having a fluorocarbon film formed on an underlayer, and a conductor buried in the interlayer insulating film. The fluorocarbon film contains nitrogen and is low in dielectric constant, excellent in reproducibility and stable. | 02-11-2010 |
20100032845 | SEMICONDUCTOR DEVICE HAVING AN INTERCONNECT STRUCTURE AND A REINFORCING INSULATING FILM AND METHOD OF MANUFACTURING SUCH DEVICE - A semiconductor device includes in an interconnect structure which includes a first interconnect made of a copper-containing metal, a first Cu silicide layer covering the upper portion of the first interconnect, a conductive first plug provided on the upper portion of the Cu silicide layer and connected to the first interconnect, a Cu silicide layer covering the upper portion of the first plug, a first porous MSQ film provided over the side wall from the first interconnect through the first plug and formed to cover the side wall of the first interconnect, the upper portion of the first interconnect, and the side wall of the first plug, and a first SiCN film disposed under the first porous MSQ film to contact with the lower portion of the side wall of the first interconnect and having the greater film density than the first porous MSQ film. | 02-11-2010 |
20100038794 | THREE DIMENSIONAL NANOSCALE CIRCUIT INTERCONNECT AND METHOD OF ASSEMBLY BY DIELECTROPHORESIS - An assembly of nanoelements forms a three-dimensional nanoscale circuit interconnect for use in microelectronic devices. A process for producing the circuit interconnect includes using dielectrophoresis by applying an electrical field across a gap between vertically displaced non-coplanar microelectrodes in the presence of a liquid suspension of nanoelements such as nanoparticles or single-walled carbon nanotubes to form a nanoelement bridge connecting the microelectrodes. The assembly process can be carried out at room temperature, is compatible with conventional semiconductor fabrication, and has a high yield. The current-voltage curves obtained from the nanoelement bridge demonstrate that the assembly is functional with a resistance of −40 ohms for gold nanoparticles. The method is suitable for making high density three-dimensional circuit interconnects, vertically integrated nanosensors, and for in-line testing of manufactured conductive nanoelements. | 02-18-2010 |
20100038795 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device according to an embodiment includes forming a first pattern having linear parts of a constant line width and a second pattern on a foundation layer, the second pattern including parts close to the linear parts of the first pattern and parts away from the linear parts of the first pattern and constituting closed loop shapes independently of the first pattern or in a state of being connected to the first pattern and carrying out a closed loop cut at the parts of the second pattern away from the linear parts of the first pattern. | 02-18-2010 |
20100038796 | HIGH ASPECT RATIO CONTACTS - A contact formed in accordance with a process for etching a insulating layer to produce an opening having an aspect ratio of at least 15:1 by first exposing the insulating layer to a second plasma of a second gaseous etchant comprising Ar, Xe, and combinations thereof to form an opening having an aspect ratio of less than 15:1. Secondly, the insulating layer is exposed to a first plasma of a first gaseous etchant having at least fifty percent helium (He) to etch the opening having an aspect ratio of at least 15:1, thereby increasing the aspect ratio to greater than 15:1, where the first gaseous etchant has a lower molecular weight than the second gaseous etchant. | 02-18-2010 |
20100038797 | CONTROLLING LATERAL DISTRIBUTION OF AIR GAPS IN INTERCONNECTS - Properties of a hard mask liner are used against the diffusion of a removal agent to prevent air cavity formation in specific areas of an interconnect stack. According to one embodiment, there is provided a method in which there is defined a portion on a surface of an IC interconnect stack as being specific to air cavity introduction, with the defined portion being smaller than the surface of the substrate. At least one metal track is produced within the interconnect stack, and there is deposited at least one interconnect layer having a sacrificial material and a permeable material within the interconnect stack. There is defined at least one trench area surrounding the defined portion and forming at least one trench, and a hard mask layer is deposited to coat the trench. At least one air cavity is formed below the defined portion of the surface by using a removal agent for removing the sacrificial material to which the permanent material is resistant. | 02-18-2010 |
20100038798 | METHOD FOR CORRECTING MASK PATTERN, PHOTOMASK, METHOD FOR FABRICATING PHOTOMASK, ELECTRON BEAM WRITING METHOD FOR FABRICATING PHOTOMASK, EXPOSURE METHOD, SEMICONDUCTOR DEVICE, AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for correcting a mask pattern to be formed on a photomask used in a lithographic step of a semiconductor device fabrication process. The method includes the steps of extracting an isolated pattern having an optically isolated portion from the mask pattern and providing, in an adjacent pattern extending parallel to the isolated portion of the isolated pattern and having a terminal end, an extended portion extending from the terminal end next to the isolated portion of the isolated pattern along a direction in which the isolated portion of the isolated pattern extends. | 02-18-2010 |
20100038799 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, MOUNTING STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device can be mounted on a circuit board through capacitive coupling even when being miniaturized. A passivation film disposed on a principal surface of a semiconductor substrate provided with a plurality of wirings laminated sequentially with insulating films therebetween has an opening at which at least a portion of the uppermost layer wiring is exposed. An electrode is arranged to cover the uppermost layer wiring exposed at the opening of the passivation film and the periphery of the opening of the passivation film. A dielectric layer is arranged to cover the electrode. An extension portion of the electrode on the surface of the passivation film and an electrode of a circuit board are capacitively coupled with a dielectric layer therebetween. | 02-18-2010 |
20100044869 | RELIABLE INTERCONNECTS - A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with a dielectric layer formed thereon. The dielectric layer having a conductive line disposed in an upper portion of the dielectric layer. The substrate is processed to produce a top surface of the dielectric layer that is not coplanar with a top surface of the conductive line to form a stepped topography. | 02-25-2010 |
20100044870 | Electrode connection structure of semiconductor chip, conductive member, and semiconductor device and method for manufacturing the same - An electrode connection structure of a semiconductor chip is provided to realize a highly reliable electrical connection with low stress without using a bump. A conductive member may be used for such an electrode connection structure. A semiconductor device is provided wherein semiconductor chips are arranged in layers without providing the semiconductor chips with a through via, and a method is provided for manufacturing such a semiconductor device. A part or all of the surface of a horizontal recess, which is formed in an adhesive layer arranged between a first electrode of a lower layer and a second electrode of an upper layer, is provided with a conductive member for connecting the first electrode and the second electrode. | 02-25-2010 |
20100044871 | SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND ELECTRONIC DEVICE - In order to attain, in a semiconductor device in which a semiconductor element is mounted, formation of a mark of a relatively large size which is easily recognizable by the naked eye or a machine, and which can apply a code system containing enough amount of information for tracing a manufacturing history, a semiconductor device according to the present invention includes an interposer electrically connected to a semiconductor element, which semiconductor device has a mark for displaying at least predetermined information relevant to the semiconductor element. | 02-25-2010 |
20100044872 | SEMICONDUCTOR MEMORY DEVICE HAVING PADS - A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power. | 02-25-2010 |
20100044873 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - When a thin semiconductor device is formed by grinding a wafer, it has been necessary to dice the wafer into dies and process the back surfaces of the dies separately. In the invention, a wafer | 02-25-2010 |
20100044874 | INTEGRATED CIRCUIT OF DECREASED SIZE - An integrated circuit including an insulating layer having first and second opposite surfaces. The circuit includes, in a first area, first conductive portions of a first conductive material, located in the insulating layer, flush with the first surface and continued by first vias of the first conductive material, of smaller cross-section and connecting the first conductive portions to the second surface. The circuit further includes, in a second area, second conductive portions of a second material different from the first conductive material and arranged on the first surface and second vias of the first conductive material, in contact with the second conductive portions and extending from the first surface to the second surface. | 02-25-2010 |
20100044875 | METHODS AND APPARATUS FOR DEFINING MANHATTAN POWER GRID STRUCTURES HAVING A REDUCED NUMBER OF VIAS - A method for defining and producing a power grid structure (having stripe, rail, and via components) of an IC. The method reduces the number of vias in the power grid structure and the diagonal wiring blockage caused by the vias while still meeting design specifications. Other embodiments provide a method for locating vias in the power grid structure in such a way as to be especially beneficial to 45° or 135° diagonal wiring paths. The method includes processes of a power grid planner, power grid router, power grid verifier, and global signal router that are used iteratively to define and produce a power grid structure. Other embodiments of the invention provide for arrangements of vias in via arrays where diagonal wiring paths are facilitated near the edges of the via arrays. A bounding box enclosing these via arrays have an aspect ratio that is approximately equal to 1. | 02-25-2010 |
20100052177 | METHOD FOR MANUFACTURING A CROSSBAR CIRCUIT DEVICE - Method for manufacturing a crossbar circuit on a substrate ( | 03-04-2010 |
20100052178 | Semiconductor Device and Method for Making Same - One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally extending beyond the sidewall of the conductive layer by a lateral overhang; and a conductive via in electrical contact with the conductive capping layer. | 03-04-2010 |
20100052179 | MEMS STRUCTURE AND METHOD FOR FABRICATING THE SAME - A microelectromechanical system (MEMS) structure and a fabricating method thereof are described. The MEMS structure includes a fixed part and a movable part. The fixed part is disposed on and connects with a substrate. The movable part including at least two first metal layers, a first protection ring and a first dielectric layer is suspended on the substrate. The first protection ring connects two adjacent first metal layers, so as to define a first enclosed space between the two adjacent first metal layers. The first dielectric layer is disposed in the enclosed space and connects the two adjacent first metal layers. | 03-04-2010 |
20100052180 | Semiconductor Device for Low-Power Applications and a Method of Manufacturing Thereof - The invention relates to a semiconductor device manufactured in a process technology, the semiconductor device having at least one wire ( | 03-04-2010 |
20100052181 | USING A CAP LAYER IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES AS A CMP AND ETCH STOP LAYER - During the manufacture of advanced metallization systems, a dielectric cap layer formed on a sensitive dielectric material may be partially maintained during a CMP process for removing excess metal, thereby avoiding the necessity for depositing a dedicated etch stop material, as may be required in conventional approaches when substantially completely consuming the dielectric cap material during the CMP process. Hence, reduced process complexity and/or enhanced flexibility may be accomplished in combination with increased integrity of the low-k dielectric material. | 03-04-2010 |
20100052182 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - A lack of exposure margin is avoided in a region, where an interconnection is required in a direction different from that of an interconnection of a region where an exposure condition is optimized. A semiconductor device According to an aspect of the invention includes a semiconductor substrate | 03-04-2010 |
20100052183 | MICROFEATURE WORKPIECE SUBSTRATES HAVING THROUGH-SUBSTRATE VIAS, AND ASSOCIATED METHODS OF FORMATION - Microfeature workpiece substrates having through-substrate vias, and associated methods of formation are disclosed. A method in accordance with one embodiment for forming a support substrate for carrying microfeature dies includes exposing a support substrate to an electrolyte, with the support substrate having a first side with a first conductive layer, a second side opposite the first side with a second conductive layer, and a conductive path extending through the support substrate from the first conductive layer to the second conductive layer. The method can further include forming a bond pad at a bond site of the first conductive layer by disposing at least one conductive bond pad material at the bond site, wherein disposing the at least one conductive bond pad material can include passing an electrical current between the first and second conductive layers via the conductive path, while the substrate is exposed to the electrolyte. | 03-04-2010 |
20100072625 | Semiconductor device including power supply pad and trunk wiring which are arranged at the same layer level - A semiconductor device includes a semiconductor substrate which includes a functional circuit, a trunk wiring which passes through a portion near a position immediately above a center portion of the functional circuit, a power supply pad which is connected to an end of the trunk wiring and placed at a layer level which is same as a layer level where the trunk wiring is placed, and a connection wiring which connects a substantially center portion of the functional circuit and the trunk wiring. | 03-25-2010 |
20100078822 | Electronic Device and Method of Manufacturing Same - This application relates to a method of manufacturing a semiconductor device comprising: providing multiple chips each comprising contact elements on a first main face of each of the multiple chips, and a first layer applied to each of the first main faces of the multiple chips; placing the multiple chips over a carrier with the first layers facing the carrier; applying encapsulation material to the multiple chips and the carrier to form an encapsulation workpiece embedding the multiple chips; and removing the carrier from the encapsulation workpiece. | 04-01-2010 |
20100078823 | CONTACTS AND VIAS OF A SEMICONDUCTOR DEVICE FORMED BY A HARD MASK AND DOUBLE EXPOSURE - A contact element may be formed on the basis of a hard mask, which may be patterned on the basis of a first resist mask and on the basis of a second resist mask, to define an appropriate intersection area which may represent the final design dimensions of the contact element. Consequently, each of the resist masks may be formed on the basis of a photolithography process with less restrictive constraints, since at least one of the lateral dimensions may be selected as a non-critical dimension in each of the two resist masks. | 04-01-2010 |
20100078824 | Method for forming three-dimensional structure, method for manufacturing semiconductor device, and semiconductor device - A method for forming a three-dimensional structure comprises: a first step of dropping a liquid material containing a structure-forming material and a solvent onto a structure forming surface; and a second step of drying at least a part of the solvent in the dropped liquid material to form a deposit layer on the structure forming surface, wherein the first step and the second step are repeated while a dropping position of the liquid material is shifted such that a next droplet of the liquid material is dropped onto the deposit layer formed of the previously-dropped liquid material to repeatedly accumulate the deposit layers on the structure forming surface, thereby forming a three-dimensional structure having at least one inclination portion inclined with respect to the structure forming surface. | 04-01-2010 |
20100084768 | ELECTRONIC COMPONENT, A SEMICONDUCTOR WAFER AND A METHOD FOR PRODUCING AN ELECTRONIC COMPONENT - An electronic component includes a semiconductor substrate defined by a generally planar first face, a generally planar second face and side faces extending between the generally planar second face and the generally planar first face. The semiconductor substrate has a curved contour between the generally planar second face and the side faces. | 04-08-2010 |
20100084769 | SEMICONDUCTOR DEVICE AND DUMMY PATTERN ARRANGEMENT METHOD - A semiconductor device includes a plurality of wiring patterns arranged in a first wiring layer of the semiconductor device and extending in a first direction, and a plurality of dummy patterns arranged in the first wiring layer and extending in a second direction different from the first direction, wherein each of the plurality of dummy patterns is arranged spaced apart from each of the plurality of wiring patterns and includes one or more dummy lands formed by separating a part of the dummy pattern opposed to the wiring pattern, from the rest part of the dummy pattern. | 04-08-2010 |
20100090346 | INTEGRATION OF SELF-ALIGNED TRENCHES IN-BETWEEN METAL LINES - The present invention provides an improved method of forming air cavities to overcome IC via-misalignment issues. The method of forming air cavity trenches in-between metal lines of an integrated circuit includes the steps of partially removing ( | 04-15-2010 |
20100090347 | APPARATUS AND METHOD FOR CONTACT FORMATION IN SEMICONDUCTOR DEVICES - The present disclosure is directed to the preparation of a semiconductor substrate, and metallization of a contact area on the substrate to produce a contact in a semiconductor device. The method includes pre-treating the substrate by ultra fast laser treatment of a contact area, and depositing an interconnect metal layer on the contact area to create a contact. The process may include depositing a layer of dielectric-forming material on the substrate and removing a portion of the dielectric material from the substrate to reveal a contact area, prior to laser treating and metallization. | 04-15-2010 |
20100090348 | Single-Sided Trench Contact Window - An integrated circuit is manufactured from a semiconductor substrate having trenches with first and second sidewalls facing each other and a conductive line arranged in a bottom region of the trenches. At least the bottom region of the trenches is lined with an insulative material between the conductive line and the substrate. A first sacrificial layer is formed above the conductive line adjacent the first and second sidewalls. The trenches are filled with one or more additional sacrificial layers having a different etch selectivity than the first sacrificial layer. A portion of the one or more additional sacrificial layers and a portion of the insulative material are selectively removed to the first sacrificial layer so that the substrate is exposed below the first sacrificial layer along the first trench sidewalls and covered by the insulative material along the second trench sidewalls. | 04-15-2010 |
20100090349 | METHODS OF FORMING FINE PATTERNS IN THE FABRICATION OF SEMICONDUCTOR DEVICES - In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region. The feature layer is etched using the mask layer patterns as an etch mask in the second region and using the spacers as an etch mask in the first region to provide a feature layer pattern having fine features in the first region and broad features in the second region. | 04-15-2010 |
20100096757 | Method and System for Distributing Clock Signals on Non Manhattan Semiconductor Integrated Circuits - The present invention introduces methods, systems, and architectures for routing clock signals in an integrated circuit layout. The introduced clock signal clock signal structures are rendered with non Manhattan routing. In a first embodiment, the traditional recursive H clock signal structure is rendered after transforming the coordinates system such that a rotated recursive H clock signal structure is rendered. In another embodiment, a recursive Y structure is used to create a clock signal structure. The recursive Y structure may also be implemented in a rotated alignment. For clock signal redundancy, non Manhattan wiring may be used to create a clock signal mesh network. | 04-22-2010 |
20100096758 | ELECTRIC POWER SEMICONDUCTOR DEVICE - An electric power semiconductor device including first and second circuit patterns formed on main surfaces of first and second insulating substrates, respectively, first and second semiconductor chips mounted on the first and second circuit patterns, respectively, a multilayer electrode plate assembly disposed between the first and second insulating substrates, having first, second and third electrode terminals provided with a distance from each other, a first connecting conductor made by wire bonding for connecting the first and second semiconductor chips to the first and second electrode terminals, and a second connecting conductor having an extending portion extended from a part of the third electrode terminal to be connected to the second circuit pattern, and the connection between the extending portion of the third electrode terminal and the second circuit pattern is implemented by a solder. | 04-22-2010 |
20100102451 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A trench is formed by a process which removes a damage layer formed on a sidewall of a low dielectric constant layer, a process which forms a second protection insulating layer by a chemical vapor deposition (CVD) technique and forms a second concave portion by covering a sidewall of the low dielectric constant layer with the second protection insulating layer, and a process which shapes the second protection insulating layer by etch back so that a trench has a sidewall that the second protection insulating layer is selectively formed on a surface of the low dielectric constant layer. | 04-29-2010 |
20100102452 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device, includes forming a dielectric film above a substrate; forming a cap film, in which pores are formed, on the dielectric film; forming an opening in the cap film and the dielectric film; depositing a conductive material inside the opening; and forming a diffusion barrier film for preventing diffusion of the conductive material on the cap film, after the conductive material is deposited inside the opening, in such a way that a portion of the diffusion barrier film intrudes into the cap film and that a portion of the pores remains. | 04-29-2010 |
20100109162 | High Integrated Semiconductor Memory Device - Disclosed herein is a semiconductor memory device for reducing a junction resistance and increasing amount of current throughout the unit cell. A semiconductor memory device comprises plural unit cells, each coupled to contacts formed in different shape at both sides of a word line in a cell array. | 05-06-2010 |
20100109163 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To provide a semiconductor device comprising a first layer that is provided on a semiconductor substrate and includes a first wiring pattern planarized by CMP and a plurality of first dummy patterns made of a same material as the first wiring pattern and a second layer that is provided above the semiconductor substrate and includes a second wiring pattern planarized by CMP and a plurality of second dummy patterns made of a same material as the second wiring pattern. A central axis of each of the second dummy patterns coincides with that of a corresponding one of the first dummy patterns in a direction perpendicular to the semiconductor substrate. | 05-06-2010 |
20100117241 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME - A semiconductor device includes: a plurality of semiconductor substrates each having a pad-formed surface and being mutually laminated; a connection electrode pad formed on the pad-formed surface; a wire connecting the connection electrode pads of the plurality of semiconductor substrates so as to electrically connect the semiconductor substrates; a relay electrode pad that is provided on the pad-formed surface of a lower one of the laminated semiconductor substrates so as to be exposed by an upper one of the laminated semiconductor substrates, and that is connected to the connection electrode pad by a relay wire included in the wire; and a mounting electrode pad that is formed on a mounting surface on which the laminated semiconductor substrates are mounted, and that is connected to the relay electrode pad of the lower semiconductor substrate by the wire. In the device, the wire electrically connects the connection electrode pad of the upper semiconductor substrate to the relay electrode pad of the lower semiconductor substrate. | 05-13-2010 |
20100123250 | Feature Patterning Methods and Structures Thereof - Methods of patterning features, methods of manufacturing semiconductor devices, and semiconductor devices are disclosed. In one embodiment, a method of patterning a feature includes forming a first portion of the feature in a first material layer. A second portion of the feature is formed in the first material layer, and a third portion of the feature is formed in a second material layer. | 05-20-2010 |
20100123251 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTI LEVEL CONTACT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a first level contact on a first external connection level; forming a second level contact on a second external connection level next to the first external connection level; attaching a device adjacent the first level contact and the second level contact; attaching a first level device connector to the first level contact and the device; attaching a second level device connector to the second level contact and the device; and forming an encapsulant over the first level contact, the second level contact, the first level device connector, and the second level device connector. | 05-20-2010 |
20100123252 | LAYOUT DESIGN METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT - A circuit and a method of layout-designing a circuit based on circuit information. The method includes generating layout information including a core region based on the circuit information, laying out an I/O circuit in a region other than the core region on the layout information based on the circuit information, determining a layout-permitted region of pads, which is included in regions other than the core region and a layout region of said I/O circuit, based on circuit information, and laying out the pads in the layout-permitted region. | 05-20-2010 |
20100123253 | SEMICONDUCTOR DEVICE - An exemplary embodiment of the present invention is a semiconductor device having a regular layout region and an irregular layout region formed on one chip, including: a lower conductive layer; an interlayer insulating film formed on the lower conductive layer; an upper interconnect layer formed on the interlayer insulating film; and connection plugs disposed to electrically connect the lower conductive layer and the upper interconnect layer at a substantially shortest distance. In at least part of the regular layout region, the lower conductive layer and the upper interconnect layer are electrically connected to each other through at least two connection plugs and an intermediate connection layer for electrically connecting the at least two connection plugs, the at least two connection plugs being disposed at an immediately above position extending from immediately above the lower conductive layer and a shift position spaced apart from the immediately above position, respectively. | 05-20-2010 |
20100123254 | Semiconductor Device and a Method for Making the Semiconductor Device - An opening ( | 05-20-2010 |
20100123255 | ELECTRONIC PACKAGE STRUCTURE AND METHOD - An electronic package structure and method use a conductive strip to bond die-to-die, die-to-lead, chip carrier-to-lead, or lead-to-lead. A conductive strip may carry greater current than a bonding wire, and thus may replace several bonding wires. The bonding of the conductive strip may be carried out by an SMT process, and thus requires lower cost than wire bonding processes. A conductive strip may be bonded to more than two dice or leads to save more bonding wires. A conductive strip is stronger than a bonding wire, and thus lowers the possibility of being broken. | 05-20-2010 |
20100127396 | INTEGRATED CIRCUIT MODULE AND METHOD OF PACKAGING SAME - An integrated circuit (IC) module ( | 05-27-2010 |
20100127397 | Optoelectronic semiconductor device - An optoelectronic semiconductor device includes a substrate, a semiconductor system having an active layer formed on the substrate and an electrode structure formed on the semiconductor system, wherein the layout of the electrode structure having at least a first conductivity type contact zone or a first conductivity type bonding pad, a second conductivity type bonding pad, a first conductivity type extension electrode, and a second conductivity type extension electrode wherein the first conductivity type extension electrode and the second conductivity type extension electrode have three-dimensional crossover, and partial of the first conductivity type extension electrode and the first conductivity type contact zone or the first conductivity type bonding pad are on the opposite sides of the active layer. | 05-27-2010 |
20100127398 | Wiring structure of a semiconductor device - In a wiring structure of a semiconductor device and a method of manufacturing the same, a wiring structure includes a contact pad, a contact plug, a spacer and an insulation interlayer pattern. The contact pad is electrically connected to a contact region of a substrate. The contact plug is provided on the contact pad and is electrically connected to the contact pad. The spacer faces an upper side surface of the contact pad and sidewalls of the contact plug. The insulation interlayer pattern has an opening, the contact plug and the spacer being provided in the opening. The spacer of the wiring structure may prevent the contact pad from being damaged by a cleaning solution while forming a contact plug to be connected to a capacitor. | 05-27-2010 |
20100127399 | WIRING STRUCTURE BETWEEN STEPS AND WIRING METHOD THEREOF - In a wiring structure between steps in which a step portion is covered by an insulating slope formed by providing and drying droplets of an insulating ink in which an insulating material is dispersed in a dispersion medium and a wiring line formed by drying and firing provided droplets of a conductive ink in which a conductive material is dispersed in a dispersion medium is laid out between the steps and passes on a top surface of the insulating slope, the structure includes a liquid repellent layer formed of a liquid repellent material repelling the dispersion medium in the insulating ink, and a plurality of dot lines including a plurality of dots that is formed by hardening arranged droplets of a resin ink including a resin material. In the structure, the liquid repellent layer covers a surface including the step portion where the wiring line to be laid out. The droplets for forming the dot lines are arranged on a surface of the liquid repellent layer so as not to contact with each other in a region partitioned by a side serving as a start point and a side serving as an end point in a direction in which the wiring line is laid out. The insulating slope is formed by drying the droplets of the insulating ink provided to the step portion so as to connect the plurality of dot lines. | 05-27-2010 |
20100127400 | SEMICONDUCTOR MODULE AND PROCESS FOR ITS FABRICATION - A semiconductor module is disclosed, including a substrate and at least one semiconductor component in bottom contact with the substrate. The semiconductor component including a main current branch sandwiched between the bottom and top of the semiconductor component. The side edges of a barrier layer zone coincide with the side edge portions of the semiconductor component between the top and the bottom. The space above the substrate and to the side of the semiconductor component is packed with an insulating compound at least up to the level of the top of the semiconductor component. Topping the semiconductor component and parallel thereto is a patterned or unpatterned metallization connected to a contact pad on the top of the semiconductor component. | 05-27-2010 |
20100127401 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device. The semiconductor device includes a circuit part, a pad metal aligned over the circuit part to electrically connect the circuit part, and a metal layer interposed between the pad metal and the circuit part to electrically connect the pad metal to the circuit part. A buffer layer including an insulating layer with metal patterns having a slit shape formed therein is formed within the metal layer. | 05-27-2010 |
20100127402 | Interconnect System without Through-Holes - Structures employed by a plurality of packages, printed circuit boards, connectors and interposers to create signal paths which reduce the deleterious signal quality issues associated with the use of through-holes. Disclosed structures can coexist with through-hole implementations. | 05-27-2010 |
20100133695 | ELECTRONIC CIRCUIT WITH EMBEDDED MEMORY - Circuitry includes first and second circuits spaced apart by an interconnect region. The interconnect region includes a first interconnect, and the second circuit includes a stack of semiconductor layers. The first interconnect extends between the first and second circuits to provide communication therebetween. The second circuit operates as a memory circuit. | 06-03-2010 |
20100140805 | Bump Structure for Stacked Dies - A bump structure that may be used for stacked die configurations is provided. Through-silicon vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-silicon vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-silicon vias. The isolation film is thinned to re-expose the through-silicon vias. Bump pads and redistribution lines are formed on the backside of the semiconductor substrate providing an electrical connection to the through-silicon vias. Another isolation film is deposited and patterned, and a barrier layer is formed to provide contact pads for connecting to an external device, e.g., another die/wafer or circuit board. | 06-10-2010 |
20100140806 | Method for Forming Super Contact in Semiconductor Device - A method for forming a super contact in a semiconductor device is disclosed. The method enables forming a barrier film selectively on the silicon substrate, leaving the metal contact exposed for perfect isolation of the metal pad from the silicon substrate after formation of the super contact. | 06-10-2010 |
20100148369 | Wire bonding method and semiconductor device - Wire bonding method for reducing height of a wire loop in a semiconductor device, including a first bonding step of bonding an initial ball formed at a tip end of a wire onto a first bonding point using a capillary, thereby forming a pressure-bonded ball; a wire pushing step of pushing the wire obliquely downward toward the second bonding point at a plurality of positions by repeating a sequential movement for a plurality of times, the sequential movement including moving of the capillary substantially vertically upward and then obliquely downward toward the second bonding point by a distance shorter than a rising distance that the capillary has moved upward; and a second bonding step of moving the capillary upward and then toward the second bonding point, and bonding the wire onto the second bonding point by pressure-bonding. | 06-17-2010 |
20100155956 | FILL PATTERNING FOR SYMMETRICAL CIRCUITS - A fill-placement method, according to which symmetrical fill patterns are used to insert fill tiles into one or more interconnect levels corresponding to symmetrical circuitry. The fill-placement method can be used, for example, in the fabrication of an integrated circuit having at least two complementary portions for which relatively tight circuit-matching requirements need to be met. | 06-24-2010 |
20100155957 | PAD LAYOUT STRUCTURE OF SEMICONDUCTOR CHIP - Provided is a pad layout structure of a semiconductor chip capable of preventing lead-broken problems when packaging the semiconductor chip with a high aspect ratio in a tape carrier package (TCP). In the pad layout structure of the semiconductor chip, a plurality pads are arranged along upper, lower, left and right sides of the semiconductor chip with a high aspect ratio, and a longitudinal width of pads arranged at the left and right sides and a transverse width of pads arranged at both edges of the upper and lower sides are greater than a transverse width of pads arranged at centers of the upper and lower sides. | 06-24-2010 |
20100155958 | BONDING PAD STRUCTURE AND MANUFACTURING METHOD THEREOF - A bonding pad structure of a semiconductor device and a method of manufacturing the same reduce the likelihood of peel-off defects from occurring. The bonding pad structure includes a substrate, an interlayer insulation layer on the substrate, an upper wiring layer on the interlayer insulation layer, and a plurality of lower wiring layers disposed in the interlayer insulation layer between the upper wiring layer and the substrate and configured to prevent the interlayer insulation layer from cracking especially during a wire bonding process in which a wire is bonded to the upper wiring layer. For example, the respective areas occupied by the lower wiring layers sequentially increase in the interlayer insulation layer in a downward direction from the upper wiring layer towards the substrate. Also, each of the lower wiring layers may project further inwardly toward a central part of the bonding pad than the lower layer of wiring disposed above it in the interlayer insulation layer. | 06-24-2010 |
20100155959 | Semiconductor Devices Having Narrow Conductive Line Patterns and Related Methods of Forming Such Semiconductor Devices - Semiconductor devices and methods of forming semiconductor devices are provided in which a plurality of patterns are simultaneously formed to have different widths and the pattern densities of some regions are increased using double patterning. The semiconductor device includes a plurality of conductive lines each including a first line portion and a second line portion, where the first line portion extends on a substrate in a first direction, the second line portion extends from one end of the first line portion in a second direction, and the first direction is different from the second direction; a plurality of contact pads each of which is connected with a respective conductive line of the plurality of conductive lines via the second line portion of the corresponding conductive line; and a plurality of dummy conductive lines each including a first dummy portion extending from a respective contact pad of the plurality of contact pads, in parallel with the corresponding second line portion in the second direction. | 06-24-2010 |
20100155960 | SEMICONDUCTOR DEVICE - The present invention aims at offering the semiconductor device which can improve the strength to the stress generated with a bonding pad. In the semiconductor device concerning the present invention, a plurality of bonding pads are formed on a semiconductor chip. In each bonding pad, a plurality of second line-like metals are formed under the first metal formed using the wiring layer of the top layer. And a bonding pad is put in order and located along the long-side direction of a second metal to achieve the above objects. That is, a bonding pad is put in order and located so that the long-side direction of a second metal and the arrangement direction of a bonding pad may become in the same direction. | 06-24-2010 |
20100164114 | Wire Structure of Semiconductor Device and Method for Manufacturing the Same - Disclosed herein are a wire structure of a semiconductor device and a method of making the same. The method includes obtaining a layout of an active region in a semiconductor substrate, the layout extending in a direction diagonally intersecting a layout of a bit line. The method also includes forming an isolation layer that delimits the active region, | 07-01-2010 |
20100164115 | SEMICONDUCTOR CHIP PACKAGE - A device and/or method relating to semiconductor technology. A semiconductor chip package may include dual line type input/output (I/O) pads. A semiconductor chip package may include a core area. A semiconductor chip package may include input/output (I/O) pads arranged on and/or over an outside of a core area, which may signal input/output to and/or from a core area. A semiconductor chip package may have input/output (I/O) pads including dual lines. | 07-01-2010 |
20100171223 | Through-Silicon Via With Scalloped Sidewalls - A semiconductor device having one or more through-silicon vias (TSVs) is provided. The TSVs are formed such that sidewalls of the TSVs have a scalloped surface. In an embodiment, the sidewalls of the TSVs are sloped wherein a top and bottom of the TSVs have different dimensions. The TSVs may have a V-shape wherein the TSVs have a wider dimension on a circuit side of the substrate, or an inverted V-shape wherein the TSVs have a wider dimension on a backside of the substrate. The scalloped surfaces of the sidewalls and/or sloped sidewalls allow the TSVs to be more easily filled with a conductive material such as copper. | 07-08-2010 |
20100171224 | Three dimensional structure memory - A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques. | 07-08-2010 |
20100171225 | Three dimensional structure memory - A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques. | 07-08-2010 |
20100181677 | STRUCTURE WITH SELF ALIGNED RESIST LAYER ON AN INSULATING SURFACE AND METHOD OF MAKING SAME - A structure is provided with a self-aligned resist layer on an insulator surface and non-lithographic method of fabricating the same. The non-lithographic method includes applying a resist on a structure comprising at least one of interconnects formed in an insulator material. The method further comprises exposing the resist to energy and developing the resist to expose surfaces of the interconnects. The method further comprises depositing metal cap material on the exposed surfaces of the interconnects. | 07-22-2010 |
20100181678 | STRUCTURE WITH SELF ALIGNED RESIST LAYER ON AN INTERCONNECT SURFACE AND METHOD OF MAKING SAME - A structure is provided with a self-aligned resist layer on a surface of metal interconnects for use in forming air gaps in an insulator material and method of fabricating the same. The non-lithographic method includes applying a resist on a structure comprising at least one metal interconnect formed in an insulator material. The method further includes blanket-exposing the resist to energy and developing the resist to expose surfaces of the insulator material while protecting the metal interconnects. The method further includes forming air gaps in the insulator material by an etching process, while the metal interconnects remain protected by the resist. | 07-22-2010 |
20100181679 | 3D INTEGRATION OF VERTICAL COMPONENTS IN RECONSTITUTED SUBSTRATES - A reconstituted electronic device including: a first face and a second face; a plurality of individual chips placed perpendicular to the faces, each individual chip carrying, on one of its surfaces, at least one component, tracks, and a connection mechanism that are flush with one or other of the faces of the reconstituted electronic device; and an encapsulant that encapsulates the individual chips. | 07-22-2010 |
20100181680 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device includes: a mounted body in which a wiring pattern is formed on a first main surface; a semiconductor chip mounted on the surface of the mounted body on which the wiring pattern is formed; an underfill material which is filled between the mounted body and the semiconductor chip and forms a fillet on an outer peripheral part of the semiconductor chip; and an injection section which is disposed on the mounted body and on an outside of a side section, on which the fillet is formed to be longest, of four side sections defining a chip mount area on which the semiconductor chip is mounted, and guides the underfill material to between the mounted body and the semiconductor chip. | 07-22-2010 |
20100181681 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - With a recent shrinking semiconductor process, insulating layers formed between interconnect layers are becoming thin. To avoid parasitic capacitance between them, materials of a low dielectric constant have been used for an insulating layer in a multilevel interconnect. Low-k materials, however, have low strength compared with the conventional insulating layers. Porous low-k materials are structurally fragile. The invention therefore provides a manufacturing method of a semiconductor device having a multilevel interconnect layer including a low-k layer. According to the method, in a two-step cutting system dicing in which after formation of a groove in a semiconductor water with a tapered blade, the groove is divided with a straight blade thinner than the groove width, the multilevel interconnect layer portion is cut while being covered with a tapered face and then the wafer is separated with a thin blade which is not brought into contact with the multilevel interconnect layer portion. The wafer can be diced without damaging a relatively fragile low-k layer. | 07-22-2010 |
20100187696 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component that includes a contact landing pad and a method for manufacturing the semiconductor component. A trench having sidewalls is formed in a semiconductor material and a dielectric material is formed on the sidewalls of the trench. An electrically conductive material is formed on the sidewalls and fills the trench. A multi-layer dielectric structure is formed over the electrically conductive material in the trench, where the multi-layer dielectric material is comprised of a dielectric material of one type sandwiched between dielectric materials of a different type such that an etch rate of the middle layer of dielectric material is different from those of the outer layers of dielectric material. Portions of the middle layer of dielectric material are removed and replaced with electrically conductive material that, in combination with portions of the electrically conductive material in the trench, form a contact landing pad. | 07-29-2010 |
20100187697 | ELECTRONIC DEVICE PACKAGE AND METHOD FOR FABRICATING THE SAME - An embodiment of the present invention provides an electronic device package, which includes a chip having a first surface and an opposite second surface and a trench extending into a body of the chip along a direction from the second surface to the first surface, wherein a bottom portion of the trench includes at least two contact holes. | 07-29-2010 |
20100193959 | Redistribution Layer Power Grid - An integrated circuit package including a first metal layer coupled to a bonding pad, a first redistribution layer coupled to the bonding pad, and a RDL to Metal (RTM) via coupled to a first surface of the metal layer and further coupled to a first surface of the first RDL is described. The IC package may further include additional metal layers and redistribution layers. | 08-05-2010 |
20100193960 | Semiconductor device, method for making pattern layout, method for making mask pattern, method for making layout, method for manufacturing photo mask, photo mask, and method for manufacturing semiconductor device - A semiconductor device includes a semiconductor substrate, and a circuit pattern group comprising at least N (≧2) circuit pattern on the semiconductor substrate, at least one vicinity of end portion among the at least of N circuit patterns including a connection area to electrically connect to a circuit pattern in another circuit pattern group different from the circuit pattern group, the at least N wirings pattern including a circuit pattern N1 and at least one circuit pattern Ni (i≧2) arranged in one direction different from longitudinal direction of the circuit pattern N1, the at least one circuit patterns Ni having larger i being arranged at further position away from the circuit pattern N1, and in terms of a pattern including the connection area among the at least of Ni circuit patterns, the larger the i, the connection area being arranged at a further position in longitudinal direction. | 08-05-2010 |
20100193961 | ADHESIVE COMPOSITION FOR ELECTRONIC COMPONENTS, AND ADHESIVE SHEET FOR ELECTRONIC COMPONENTS USING THE SAME - In order to provide an adhesive composition for electronic components that is excellent in adhesion durability under long-term high temperature conditions, thermal cyclability, and insulation reliability, designed is an adhesive composition for electronic components containing a thermoplastic resin (a), an epoxy resin (b), a hardener (c), and an organopolysiloxane (d), wherein the glass transition temperature (Tg) after curing is −10° C. to 50° C. and the rate of change of Tg after heat-treating the composition at 175° C. for 1000 hours is 15% or less. | 08-05-2010 |
20100193962 | SEMICONDUCTOR DEVICE - A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups. | 08-05-2010 |
20100200994 | Semiconductor Device and Method of Manufacturing the Same - A semiconductor device comprises insulating layer including damascene patterns and formed over a semiconductor substrate, conductive line formed higher than the insulating layer within the respective damascene patterns, and interference-prevention grooves formed within the damascene patterns between sidewalls of the conductive line and the insulating layer. | 08-12-2010 |
20100200995 | COUPLING LAYER COMPOSITION FOR A SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, METHOD OF FORMING THE COUPLING LAYER, AND APPARATUS FOR THE MANUFACTURE OF A SEMICONDUCTOR DEVICE - Molecules of a coupling layer composition in a semiconductor device are bidimensionally polymerized in order to provide enhanced moisture blocking effect, particularly when the coupling layer is formed on a porous layer, such as a porous dielectric layer. The deposition of the coupling layer on the underlying structure and/or the cross-polymerization of the coupling layer composition and/or a final metallization can be photo-activated, especially, but not only, using an ultraviolet light. | 08-12-2010 |
20100207275 | HYBRID INTEGRATED CIRCUIT DEVICE, AND METHOD FOR FABRICATING THE SAME, AND ELECTRONIC DEVICE - A hybrid integrated circuit device having high mount reliability comprises a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid out on the rear surface of the module substrate, and a cap which is fixed to the module substrate to cover the main surface of the module substrate. The electrode terminals include a plurality of electrode terminals which are aligned along the edges of the module substrate and power voltage supply terminals which are located inner than these electrode terminals. The electrode terminals aligned along the substrate edges are coated, at least in their portions close to the substrate edge, with a protection film having a thickness of several tens micrometers or less. Connection reinforcing terminals consist of a plurality of divided terminals which are independent of each other, and are ground terminals. | 08-19-2010 |
20100207276 | SPIN-ON ANTIREFLECTIVE COATING FOR INTEGRATION OF PATTERNABLE DIELECTRIC MATERIALS AND INTERCONNECT STRUCTURES - The present invention provides a method of fabricating an interconnect structure in which a patternable low-k material replaces the need for utilizing a separate photoresist and a dielectric material. Specifically, this invention relates to a simplified method of fabricating single-damascene and dual-damascene low-k interconnect structures with at least one patternable low-k dielectric and at least one inorganic antireflective coating. In general terms, a method is provided that includes providing at least one patternable low-k material on a surface of an inorganic antireflective coating that is located atop a substrate. The inorganic ARC is liquid deposited and comprises a polymer that has at least one monomer unit comprising the formula M-R | 08-19-2010 |
20100213615 | Semiconductor device - One wiring width of upper and lower wiring paths formed facing each other sandwiching an interlayer insulating film is large, and another wiring width is small; and the wiring widths of mutually adjacent wiring paths are formed to be large and small in alternating fashion on the same wiring layer. | 08-26-2010 |
20100213616 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME, AND AN ELECTRONIC DEVICE - A semiconductor device includes an electronic component having an electrode pad provided on an electrode pad forming face, and a rear face positioned on a side opposite to the electrode pad forming face; an insulating member provided to seal a periphery of the electronic component, and having a first face exposing the electrode pad forming face of the electronic component and a second face exposing the rear face of the electronic component; a multi-layer wiring structure body provided to cover the first face of the insulating member, the electrode pad, and the electrode pad forming face, and including a plurality of insulating layers laminated on each other, and a wiring pattern; and a piercing electrode piercing the insulating member from the first face to the second face. The wiring pattern is directly connected to the electrode pad and the piercing electrode. | 08-26-2010 |
20100213617 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes cylinder type bottom electrodes connected to a contact plug formed over a semiconductor substrate, and a supporting pattern formed between the cylinder type bottom electrodes, wherein a portion of sidewalls of the bottom electrodes is higher than the supporting pattern and the other portion of the sidewalls of the bottom electrode is lower than the supporting pattern. | 08-26-2010 |
20100219532 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor chip having an upper face on which at least one first electrode pad is formed; a second semiconductor chip provided above the first semiconductor chip and having an upper face on which at least one second electrode pad is formed; a conductive film external to the first semiconductor chip and the second semiconductor chip; and a wire. The wire electrically connects the first electrode pad and the second electrode pad to each other via the conductive film. | 09-02-2010 |
20100219533 | MULTILAYERED WIRING STRUCTURE, AND METHOD FOR MANUFACTURING MULTILAYERED WIRING - Provided is a wiring of the Damascene structure for preventing the TDDB withstand voltage degradation and for keeping the planarity to prevent the degradation of a focus margin. A trench wiring ( | 09-02-2010 |
20100219534 | MICROSTRUCTURE DEVICE INCLUDING A METALLIZATION STRUCTURE WITH SELF-ALIGNED AIR GAPS AND REFILLED AIR GAP EXCLUSION ZONES - In a sophisticated metallization system, self-aligned air gaps may be provided in a locally selective manner by using a radiation sensitive material for filling recesses or for forming therein the metal regions. Consequently, upon selectively exposing the radiation sensitive material, a selective removal of exposed or non-exposed portions may be accomplished, thereby resulting in a highly efficient overall manufacturing flow. | 09-02-2010 |
20100219535 | METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT - A method for producing a semiconductor component with an easily solderable contact structure comprising the provision of a semiconductor substrate of a planar design with a first side, a second side, a surface normal standing vertically thereon, a dielectric passivation layer arranged on at least one of the sides and a first contact layer arranged on passivation layer, the application, at least in some areas, of at least one second contact layer onto the first contact layer, the at least one second contact layer comprising at least a partial layer made of an easily solderable metal, especially of nickel and/or silver and/or tin and/or a compound thereof, and the making of an electrically conductive contact between the second contact layer and the semiconductor substrate. | 09-02-2010 |
20100219536 | CONNECTING TERMINAL, SEMICONDUCTOR PACKAGE, WIRING BOARD, CONNECTOR, AND MICROCONTACTOR - A connecting terminal, a semiconductor package, a wiring board, a connector, and a microcontactor that can achieve a stable contact with a contact target are provided. To achieve the object and to establish an electrical connection to a contact target by making a physical contact with the contact target, there are provided a plurality of conductive terminal-forming members each having a terminal portion, which is extended in a band shape and at least a part of a surface of which forms a curved surface. Each terminal portion is configured so that a part of which is laminated on a part of at least one terminal portion in a thickness direction. All the terminal portions may be laminated at respective tip portions in the thickness direction. | 09-02-2010 |
20100225000 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate including a wiring layer; electrode pads that are not provided on, above and below with the semiconductor substrate and are provided to be electrically connected with wiring lines included in the wiring layer; and a resin layer that is fixed to the semiconductor substrate and supports the electrode pads. | 09-09-2010 |
20100225001 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE - In a method for manufacturing a semiconductor device having a plate-shaped member, a semiconductor element, and a wiring board, the manufacturing method for the semiconductor device includes: a concave portion forming step (S | 09-09-2010 |
20100230821 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED WITH SUCH A METHOD - The invention relates to a method of manufacturing a semiconductor device ( | 09-16-2010 |
20100230822 | Semiconductor Die and Method of Forming Noise Absorbing Regions Between THVS in Peripheral Region of the Die - A semiconductor wafer has a plurality of semiconductor die. A peripheral region is formed around the die. An insulating material is formed in the peripheral region. A portion of the insulating material is removed to form a through hole via (THV). A conductive material is deposited in the THV to form a conductive THV. A conductive layer is formed between the conductive THV and contact pads of the semiconductor die. A noise absorbing material is deposited in the peripheral region between the conductive THV to isolate the semiconductor die from intra-device interference. The noise absorbing material extends through the peripheral region from a first side of the semiconductor die to a second side of the semiconductor die. The noise absorbing material has an angular, semi-circular, or rectangular shape. The noise absorbing material can be dispersed in the peripheral region between the conductive THV. | 09-16-2010 |
20100230823 | SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: an electronic component including an electrode pad forming face on which electrode pads are formed, a back face opposite to the electrode pad forming face; a sealing resin including a first face provided on the electrode pad forming face side and a second face provided on the back face side, and provided around the electronic component to seal up a side face of the electrode component; a multilayer wiring structure which is provided on the first face, and in which insulating layers, a wiring pattern and external connecting pads are stacked on each other; and a conductive member which is provided in a through-hole passing through the sealing resin and the insulating layer. The wiring pattern is directly connected to the electrode pads and the external connecting pads, and includes a wiring provided in the insulating layers. The conductive member is connected to the wiring. | 09-16-2010 |
20100237506 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and manufacturing method. One embodiment provides a device including a semiconductor chip. A first conductor line is placed over the semiconductor chip. An external contact pad is placed over the first conductor line. At least a portion of the first conductor line lies within a projection of the external contact pad on the semiconductor chip. | 09-23-2010 |
20100237507 | POWER MODULE - A power module includes a pair of power devices that are stacked with a plate-shaped output electrode arranged therebetween, and an N-electrode and a P-electrode that are stacked with the pair of power devices arranged therebetween. The output electrode is anisotropic such that the thermal conductivity in a direction orthogonal to the stacking direction is greater than the thermal conductivity in the stacking direction. Also, the output electrode extends in the orthogonal direction from a stacked area where the pair of power devices are stacked. The N-electrode and the P-electrode extend in the orthogonal direction while maintaining an opposing positional relationship. | 09-23-2010 |
20100244268 | APPARATUS, SYSTEM, AND METHOD FOR WIRELESS CONNECTION IN INTEGRATED CIRCUIT PACKAGES - Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of die bond pads on a surface of the die. The connecting structure includes a plurality of via and groove combinations. Conductive material is formed in the via and groove combinations to provide connection between the die bond pads and bond pads on the support. Other embodiments are described and claimed. | 09-30-2010 |
20100244269 | Semiconductor device having integral structure of contact pad and conductive line - Provided are a semiconductor device and a method of forming a semiconductor device in which a plurality of patterns are simultaneously formed to have different widths and the pattern densities of some regions are increased using a double patterning. The semiconductor device includes a plurality of conductive lines each including a first line portion and a second line portion, where the first line portion extends on a substrate in a first direction, the second line portion extends from one end of the first line portion in a second direction different from the first direction; a plurality of contact pads each of which is connected with a respective conductive line of the plurality of conductive lines and a respective second line portion of a respective conductive line of the plurality of conductive lines; and a plurality of dummy conductive lines each including a first dummy portion extending from a respective contact pad of the plurality of contact pads, in parallel with the corresponding second line portion in the second direction. | 09-30-2010 |
20100244270 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A semiconductor device includes: a component substrate of a semiconductor device; electrode pads provided on one surface of the component substrate; a support plate material reinforcing the component substrate; via holes made in the support plate material; a conducting material filled in the via holes; and a joining member interposed between the electrode pads and the conducting material and joining the component substrate and the support plate material. | 09-30-2010 |
20100244271 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device has a first insulation film defining a plurality of contact holes arranged along a predetermined direction. A plurality of first contact plugs is respectively formed in the contact holes. A second insulation film is formed on the first insulation film and defining an opening to expose a predetermined region of the first insulation film including a region where the first contact plugs are formed. A plurality of interconnections are formed to extend across the opening and to be in contact with top surfaces of the first contact plugs, respectively. | 09-30-2010 |
20100244272 | PACKAGED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING PACKAGED MICROELECTRONIC DEVICES - Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member, a first die attached to the support member, and a second die attached to the first die in a stacked configuration. The device can also include an attachment feature between the first and second dies. The attachment feature can be composed of a dielectric adhesive material. The attachment feature includes (a) a single, unitary structure covering at least approximately all of the back side of the second die, and (b) a plurality of interconnect structures electrically coupled to internal active features of both the first die and the second die. | 09-30-2010 |
20100244273 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE DEVICE UNITS AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing an integrated circuit package system includes: forming a first device unit, having first external interconnects arranged along a perimeter of the first device unit, and a second device unit, having second external interconnects arranged along a perimeter of the second device unit, in an array configuration; mounting an integrated circuit die over the first device unit; connecting the integrated circuit die and the first external interconnects; encapsulating with an encapsulation covering the integrated circuit die, the first device unit, and the second device unit with both the first external interconnects and the second external interconnects partially exposed; and forming a partial encapsulation cut in the encapsulation electrically isolating the first external interconnects and the second electrical interconnects. | 09-30-2010 |
20100252931 | FLASH MEMORY STORAGE APPARATUS - A flash memory storage apparatus is provided. The flash memory storage apparatus includes a substrate, a control and storage circuit unit, a ground lead, at least a signal lead, and a power lead. The control and storage circuit unit, the power lead, the signal lead, and the ground lead are disposed on the substrate, in which the power lead, the signal lead, and the ground lead respectively electrically connect to the control and storage circuit unit. Moreover, the flash memory storage apparatus further includes an extra ground lead electrically connected to the ground lead or a protrusion on the substrate, such that the ground lead first electrically connects to a host when the flash memory storage apparatus is plugged into the host. | 10-07-2010 |
20100252932 | SENSOR DEVICE AND METHOD OF MANUFACTURING THE SENSOR DEVICE - A sensor device includes a substrate which includes an element forming region, a plurality of sensor elements formed in the element forming region, a plurality of connection pads formed on a region of the substrate other than the element forming region, a plurality of first wiring formed on the substrate and electrically connected with the plurality of sensor elements, a plurality of second wiring formed on the substrate and electrically connected with the plurality of connection pads, a plurality of third wiring formed on a different layer to the plurality of first wiring and the plurality of second wiring and formed to intersect with the plurality of first wiring and the plurality of second wiring, and an insulation layer formed between the plurality of first wiring, the plurality of second wiring and the plurality of third wiring. | 10-07-2010 |
20100252933 | SEMICONDUCTOR DEVICE - As etch-stop films or Cu-diffusion barrier films used in insulation films constituting conductor layers of a stacked structure, films having smaller dielectric constant than silicon nitride films are used, and an insulation film at a lower-layer part of the stacked structure is made to have smaller dielectric constant than that at an upper-layer part thereof, and further this insulation film is a silicon oxide (SiO) film and has, in the interior thereof, nano-pores of from 0.05 nm or more to 4 nm or less in diameter as chief construction. This makes it possible to dramatically reduce effective dielectric constant while keeping the mechanical strength of the conductor layers themselves, and can materialize a highly reliable and high-performance semiconductor device having mitigated the wiring delay of signals which pass through wirings. | 10-07-2010 |
20100258942 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING USING THE SAME - A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a plurality of bit lines having a uniform width on a semiconductor substrate, an active region obliquely arranged to have a predetermined angle with respect to the bit lines, a spacer arranged around the bit lines connected to a center part of the active region. A contact pad is connected to a lower part of the bit lines. The spacer is formed not only at an upper part of sidewalls of the contact pad but also at sidewalls of the bit lines. As a result, a CD of the bit line contact increases, so that a bit line contact patterning margin also increases. A bit line pattern having a uniform width is formed so that a patterning margin increases. A storage electrode contact self-alignment margin increases so that a line-type storage electrode contact margin increases. | 10-14-2010 |
20100258943 | SEMICONDUCTOR DEVICE - A technique for expanding an effective area in which a semiconductor structure required for a semiconductor device to function is desired. With the semiconductor device | 10-14-2010 |
20100258944 | ELECTRONIC APPARATUS AND FABRICATION METHOD OF THE SAME - A first semiconductor component and a second semiconductor component are attached together via an adhesion layer so that the first semiconductor component and the second semiconductor component are electrically connected with each other via a through electrode. The through electrode is formed to fill a through hole formed in the second semiconductor component and a through hole formed in a portion the adhesion layer. The through hole formed in the portion the adhesion layer is positioned between the through hole formed in the second semiconductor component and a second connection surface of a first semiconductor component through electrode. | 10-14-2010 |
20100258945 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a method for manufacturing a semiconductor device involving the step of bonding a metallic ribbon to a pad of a semiconductor chip, breakage of the metallic ribbon is to be prevented while ensuring the bonding strength even when the metallic ribbon becomes thin with reduction in size of the semiconductor chip. In bonding an Al ribbon to a pad of a semiconductor chip by bringing a pressure bonding surface of a wedge tool into pressure contact with the Al ribbon while applying ultrasonic vibration to the ribbon positioned over the pad, recesses | 10-14-2010 |
20100264545 | Metal Fill Structures for Reducing Parasitic Capacitance - Vertically-staggered-level metal fill structures include inner contiguous metal fill structures and outer contiguous metal fill structures. A dielectric material portion is provided between each contiguous metal fill structure. Vertical extent of each contiguous metal fill structure is limited up to three vertically adjoining metal interconnect levels, thereby limiting the capacitance of each contiguous metal fill structure. Capacitive coupling between the contiguous metal fill structures and the metal interconnect structures is minimized due to the fragmented structure of contiguous metal fill structures. | 10-21-2010 |
20100264546 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention provides a semiconductor device and manufacturing method of the semiconductor device which can prevent breaks in an interlayer insulation film ( | 10-21-2010 |
20100264547 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING - A first region having a first metal wiring, the first metal wiring being buried into an insulation film with a first minimum dimension, and a second region having a second metal wiring, the second metal wiring being buried in the insulation film with a second minimum dimension which is larger than the first minimum dimension, the second region being arranged adjacent to the first region, wherein a thickness of the first metal wiring and a thickness of the second metal wiring are different. | 10-21-2010 |
20100270676 | ADAPTIVE INTERCONNECT STRUCTURE - An array of contact pads on a semiconductor structure has a pitch less than twice an overlay tolerance of a bonding process employed to vertically stack semiconductor structures. A set of contact pads within the area of overlay variation for a matching contact pin may be electrically connected to an array of programmable contacts such that one programmable contact is connected to each contact pad within the area of overlay variation. One contact pad may be provided with a plurality of programmable contacts. The variability of contacts between contact pins and contact pads is accommodated by connecting or disconnecting programmable contacts after the stacking of semiconductor structures. Since the pitch of the array of contact pins may be less than twice the overlay variation of the bonding process, a high density of interconnections is provided in the vertically stacked structure. | 10-28-2010 |
20100270677 | Semiconductor device and method of manufacturing semiconductor device - An interconnect is provided in a first insulating layer and the upper surface of the interconnect is higher than the upper surface of the first insulating layer. An air gap is disposed between the interconnect and the first insulating layer. A second insulating layer is formed at least over the first insulating layer and the air gap. The second insulating layer does not cover the interconnect. An etching stopper film is formed at least over the second insulating layer. The etching stopper film is formed over the second insulating layer and the interconnect. A third insulating layer is formed over the etching stopper film. A via is provided in the third insulating layer so as to be connected to the interconnect. | 10-28-2010 |
20100270678 | SEMICONDUCTOR DEVICE - A semiconductor device including a plurality of circuits that includes a transistor, where a semiconductor layer forming the transistor includes a first contact pad, a first part that is connected to the first contact pad and that extends in a direction intersecting a short direction of a pitch with which the circuits are arranged, a second part that extends from the first part in the short direction, and a second contact pad including the first part and the second part that are provided between the first contact pad and the second contact pad, where the second part overlaps an electrode layer across an insulating layer. | 10-28-2010 |
20100270679 | MICROELECTRONIC PACKAGES FABRICATED AT THE WAFER LEVEL AND METHODS THEREFOR - A method of making microelectronic packages includes making a subassembly by providing a plate having a top surface, a bottom surface and openings extending between the top and bottom surfaces, attaching a compliant layer to the top surface of the plate, the compliant layer having openings that are aligned with the openings extending through the plate, and providing electrically conductive features on the compliant layer. After making the subassembly, the bottom surface of the plate is attached with the top surface of a semiconductor wafer so that the openings extending through the plate are aligned with contacts on the wafer. At least some of the electrically conductive features on the compliant layer are electrically interconnected with the contacts on the semiconductor wafer. | 10-28-2010 |
20100270680 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OFFSET STACKING AND ANTI-FLASH STRUCTURE - An integrated circuit package system includes: a carrier; a device structure in an offset location over the carrier with the device structure having a bond pad and a contact pad; an electrical interconnect between the bond pad and the carrier; an anti-flash structure over the device structure with the anti-flash structure exposing the contact pad; and a package encapsulation adjacent to the anti-flash structure and over the carrier. | 10-28-2010 |
20100270681 | OPTIMIZING APPLICATION SPECIFIC INTEGRATED CIRCUIT PINOUTS FOR HIGH DENSITY INTERCONNECT PRINTED CIRCUIT BOARDS - Techniques for optimizing application specific integrated circuit (ASIC) and other IC pin assignment corresponding to a high density interconnect (HDI) printed circuit board (PCB) layout are provided. Applying the techniques described herein, pin assignments may be systematically and strategically planned, for example, in an effort to reduce the PCB layer count and associated cost, increase signal integrity and speed, reduce the surface area used by an ASIC and its support circuitry, reduce plane perforations, and reduce via crosstalk when compared to conventional designs with an ASIC mounted on a multilayered PCB. | 10-28-2010 |
20100276809 | T-CONNECTIONS, METHODOLOGY FOR DESIGNING T-CONNECTIONS, AND COMPACT MODELING OF T-CONNECTIONS - T-connections, methodology for designing T-connections, and compact modeling of T-connections. The T-connections include an electrically conductive T-junction comprising a body and first, second and third integral arms projecting from mutually perpendicular sides of the body, each arm of the three integral arms having a same first width abutting the body and a same length extending away from the body; an electrically conductive step-junction comprising a first section having the first width and an integral and abutting second section having a second width, the second width different from the first width, the first section smoothly abutting and integral with the first arm of the T-junction; and wherein top surfaces of the T-junction and the step-junction are coplanar. | 11-04-2010 |
20100276810 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device is provided. A substrate is provided. A buried layer is formed in the substrate. The buried layer comprises an insulating region. A deep trench contact structure is formed in the substrate. The deep trench contact structure comprises a conductive material and a liner layer formed on a side wall of the conductive material. The conductive material is electrically connected with the substrate. | 11-04-2010 |
20100276811 | Semiconductor Component with Terminal Contact Surface - At least one terminal contact surface ( | 11-04-2010 |
20100276812 | EPITAXIAL WAFER AND MANUFACTURING METHOD THEREOF - A semiconductor device comprises a substrate, a conductive layer deposited on a substrate and an epitaxial layer deposited on the conductive layer. The conductive layer is patterned to include a first pattern. The first pattern includes a major surface and a plurality of grids defined in the major surface. The major surface includes a plurality of first lines and a connecting portion. The connecting portion is connected to an electrode. The epitaxial layer covers the grids and the first lines between the adjacent grids. | 11-04-2010 |
20100276813 | INJECTION MOLDED SOLDERING PROCESS AND ARRANGEMENT FOR THREE-DIMENSIONAL STRUCTURES - A method of implementing an injection molded soldering process for three-dimensional structures, particularly, such as directed to three-dimensional semiconductor chip stacking. Also provide is an arrangement for implementing the injection molded soldering (IMS) process. Pursuant to an embodiment of the invention, the joining of the semiconductor chip layers with a substrate is implemented, rather than by means of currently known wire bond stacking, through the intermediary of columns of solder material formed by the IMS process, thereby providing electrical advantages imparted by the flip chip interconnect structures. In this connection, various diversely dimensioned solder column interconnects allow for simple and dependable connections to a substrate by a plurality of superimposed layers or stacked arrays of semiconductor components, such as semiconductor chips. In accordance with a further aspect, it is possible to derive a unique design for an IMS mold structure, which contains cavities for forming the columnar fill of solder, and which also incorporates further cavities acting as cutouts for dies or the positioning of other electronic packages or modules. | 11-04-2010 |
20100283155 | Methods Of Forming A Plurality Of Conductive Lines In The Fabrication Of Integrated Circuitry, Methods Of Forming An Array Of Conductive Lines, And Integrated Circuitry - A method of forming a pair of conductive lines in the fabrication of integrated circuitry includes forming a trench into a damascene material received over a substrate. Conductive material is deposited over the damascene material and to within the trench to overfill the trench. The conductive material is removed back at least to the damascene material to leave at least some of the conductive material remaining in the trench. Etching is conducted longitudinally through the conductive material within the trench to form first and second conductive lines within the trench which are mirror images of one another in lateral cross section along at least a majority of length of the first and second conductive lines. Other implementations are contemplated. | 11-11-2010 |
20100283156 | SEMICONDUCTOR DEVICE - A semiconductor device in which size reduction is possible without functional devices below pads being damaged by stress. The semiconductor device has a plurality of pads above a semiconductor substrate as terminals for external connection. A plurality of dual use pads which are used in both a probing test and assembly are provided in a first area above a main surface of the semiconductor substrate, an application of pressure by a probe during the probing test being permitted in the first area, and a plurality of assembly pads which are not used in the probing test are provided in a second area above the main surface of the semiconductor substrate, the application of pressure by the probe during the probing test being not permitted in the second area. | 11-11-2010 |
20100283157 | INTERCONNECT STRUCTURES WITH PATTERNABLE LOW-K DIELECTRICS AND METHOD OF FABRICATING SAME - The present invention provides an interconnect structure in which a patternable low-k material is employed as an interconnect dielectric material. Specifically, this invention relates to single-damascene and dual-damascene low-k interconnect structures with at least one patternable low-k dielectric. In general terms, the interconnect structure includes at least one patterned and cured low-k dielectric material located on a surface of a substrate. The at least one cured and patterned low-k material has conductively filled regions embedded therein and typically, but not always, includes Si atoms bonded to cyclic rings via oxygen atoms. The present invention also provides a method of forming such interconnect structures in which no separate photoresist is employed in patterning the patterned low-k material. | 11-11-2010 |
20100283158 | STRUCTURE AND METHOD FOR FORMING A CAPACITIVELY COUPLED CHIP-TO-CHIP SIGNALING INTERFACE - A system and method for providing capacitively-coupled signaling in a system-in-package (SiP) device is disclosed. In one embodiment, the system includes a first semiconductor device and an opposing second semiconductor device spaced apart from the first device, a dielectric layer interposed between the first device and the second device, a first conductive pad positioned in the first device, and a second conductive pad positioned in the second device that capacitively communicate signals from the second device to the first device. In another embodiment, a method of forming a SiP device includes forming a first pad on a surface of a first semiconductor device, forming a second pad on a surface of a second semiconductor device, and interposing a dielectric layer between the first semiconductor device and the second semiconductor device that separates the first conductive signal pad and the second conductive signal pad. | 11-11-2010 |
20100289149 | SEMICONDUCTOR COMPONENT AND ASSUMBLY WITH PROJECTING ELECTRODE - A semiconductor component has a substrate and a projecting electrode on the substrate. The projecting electrode is configured suitably for electrically and mechanically connecting the semiconductor component to an external substrate. Furthermore, the projecting electrode is formed by a one-dimensional or two-dimensional array of projecting sub-electrodes, which are separated from each other by an electrically insulating fluid beginning from a substrate surface. The semiconductor component has an improved projecting-electrode. It provides the projecting electrode with a sub-structure, which achieves sufficient flexibility without introducing much constructive complexity and processing complexity during fabrication. | 11-18-2010 |
20100289150 | Semiconductor device, designing method for semiconductor device, computer-readable medium, and manufacturing method for semiconductor device - A designing method for a semiconductor device includes: determining a placement of metal wirings to be connected to contact holes and a placement of through-holes for preparing the contact holes. The determining step includes: specifying areas in one of the metal wirings to be exposed by the through-holes, specifying a capacitance of the metal wirings, and determining the placement of the metal wirings such that damage to the areas is suppressed in a case where electric charges accumulated in the capacitance are transferred from one of the metal wirings to a polar solvent through the areas. | 11-18-2010 |
20100289151 | SEMICONDUCTOR DEVICE - A semiconductor device includes a lower-layer wire, an upper-layer wire including a wire portion and a first wide portion whose wire width is greater than the wire portion, and a contact formation portion in which a contact portion for connecting the lower-layer wire and the first wide portion with each other is provided. The contact formation portion has a planar shape of which a length L1 in a direction parallel to a wire width direction of the first wide portion is greater than a length L2 in a direction parallel to a wire length direction of the first wide portion. | 11-18-2010 |
20100289152 | Strip conductor structure for minimizing thermomechanocal loads - A semiconductor chip device including a surface on which at least one electrical contact surface is provided. A foil from an electrically insulating material is applied, especially by vacuum, to the surface and rests closely to the surface and adheres to the surface. The foil, in the area of the contact surface, is provided with a window in which the contact surface is devoid of the foil and is contacted across a large area to at least one layer from an electroconductive material. In at least one embodiment, the layer from the electroconductive material is part of a flexible contact for electrically connecting the contact surface to at least one external connecting conductor. | 11-18-2010 |
20100289153 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor chip is provided comprising a semiconductor substrate on which an integrated circuit is formed. The semiconductor chip, which is provided on the semiconductor substrate in an area array, further comprises a plurality of electrodes electrically coupled with the inside of the semiconductor substrate, wherein the electrodes are arranged into a plurality of first groups respectively lined along a plurality of paralleling first straight lines and, further, into a plurality of second groups respectively lined along a plurality of second straight lines which extend so as to intersect with the first straight lines. | 11-18-2010 |
20100295183 | METHOD FOR PROVIDING ELECTRICAL CONNECTIONS TO SPACED CONDUCTIVE LINES - An integrated circuit and a method of formation provide a contact area formed at an angled end of at least one linearly extending conductive line. In an embodiment, conductive lines with contact landing pads are formed by patterning lines in a mask material, cutting at least one of the material lines to form an angle relative to the extending direction of the material lines, forming extensions from the angled end faces of the mask material, and patterning an underlying conductor by etching using said material lines and extension as a mask. In another embodiment, at least one conductive line is cut at an angle relative to the extending direction of the conductive line to produce an angled end face, and an electrical contact landing pad is formed in contact with the angled end face. | 11-25-2010 |
20100295184 | Method Of Manufacturing Semiconductor Device Including Wiring Layout And Semiconductor Device - A method of manufacturing a semiconductor device having a first wiring layer, a first interlayer insulating film, a second interlayer insulating film, a third interlayer insulating film, and a second wiring layer, in which the method includes depositing the second wiring layer on the third interlayer insulating film and, where the widths of first wiring layer and the second wiring layer are 10.0 μm or greater, executing one of etching the second wiring layer to set a width of 1.0 μm or greater in a portion where the first wiring layer and the second wiring layer overlap and etching the second wiring layer to seta horizontal distance of 2.0 μm or greater between adjacent portions of the first wiring layer and the second wiring layer. | 11-25-2010 |
20100295185 | Nonvolatile Memory Device and Method of Manufacturing the Same - A nonvolatile memory device comprises a semiconductor substrate comprising alternating, parallel active regions and isolation regions; first and second selection lines intersecting the active regions and the isolation regions; first junctions formed in the active regions between the first and second selection lines; spacers formed on sidewalls of the first and second selection lines; second junctions deeper than the first junctions formed in the first junctions, respectively; contact plugs coupled to one side of the respective second junctions; and dummy plugs coupled second sides of the respective second junctions. | 11-25-2010 |
20100295186 | SEMICONDUCTOR MODULE FOR STACKING AND STACKED SEMICONDUCTOR MODULE | 11-25-2010 |
20100295187 | Semiconductor device and method for fabricating the same - A semiconductor device which can prevent a deterioration in the electrical properties by preventing sputters generated by laser welding from adhering to a circuit pattern or a semiconductor chip and a method for fabricating such a semiconductor device are provided. A connection conductor is bonded to a copper foil formed over a ceramic by a solder and resin is injected to a level lower than a top of the connection conductor. Laser welding is then performed. After that, resin is injected. This prevents sputters generated by the laser welding from adhering to a circuit pattern or a semiconductor chip. As a result, a deterioration in the electrical properties can be prevented. | 11-25-2010 |
20100301487 | IMPROVEMENTS IN OR RELATING TO INTEGRATED CIRCUIT RELIABILITY - A method of manufacturing an integrated circuit having minimized electromigration effect, wherein the integrated circuit comprises one or more interconnect, said the or each interconnect comprising a dielectric layer having an intrinsic parameter at a first defined value, characterized in that said method comprises: identifying one or more characteristics of the or each interconnect; determining a minimal process distance from the or each interconnect for the application of one or more first metal elements; calculating a required correction parameter which can correct the intrinsic parameter at said first defined value; calculating a required number of the first metal elements which have the intrinsic parameter at a second defined value, such that the second defined value provides the required correction parameter for the first defined value; applying a plurality of said first metal elements around the interconnect at said minimum process distance to overcome the problem of electromigration caused by the intrinsic parameter at the first defined value. | 12-02-2010 |
20100301488 | Semiconductor device - In a semiconductor device, a lower multi-layered interconnect structure, an intermediate via-level insulating interlayer, and an upper multi-layered interconnect structure are stacked in this order in a region overlapped with a bonding pad in a plan view; upper interconnects and vias of the upper multi-layered interconnect structure are formed so as to be connected to the bonding pad in the pad placement region; the intermediate via-level insulating interlayer has no electro-conductive material layer, which connect the interconnects or vias in the upper multi-layered interconnect structure with interconnects or vias in the lower multi-layered interconnect structure, formed therein; and the ratio of area occupied by the vias in the via-level insulating interlayers contained in the lower multi-layered interconnect structure is smaller than the ratio of area occupied by the vias in the via-level insulating interlayers contained in the upper multi-layered interconnect structure. | 12-02-2010 |
20100301489 | MICROSTRUCTURE DEVICE INCLUDING A METALLIZATION STRUCTURE WITH SELF-ALIGNED AIR GAPS FORMED BASED ON A SACRIFICIAL MATERIAL - In a sophisticated metallization system of a semiconductor device, air gaps may be formed in a self-aligned manner on the basis of a sacrificial material, such as a carbon material, which is deposited after the patterning of a dielectric material for forming therein a via opening. Consequently, superior process conditions during the patterning of the via opening and the sacrificial material in combination with a high degree of flexibility in selecting appropriate materials for the dielectric layer and the sacrificial layer may provide superior uniformity and device characteristics. | 12-02-2010 |
20100301490 | PROFILED CONTACT FOR SEMICONDUCTOR DEVICE - A profiled contact for a device, such as a high power semiconductor device is provided. The contact is profiled in both a direction substantially parallel to a surface of a semiconductor structure of the device and a direction substantially perpendicular to the surface of the semiconductor structure. The profiling can limit the peak electric field between two electrodes to approximately the same as the average electrical field between the electrodes, as well as limit the electric field perpendicular to the semiconductor structure both within and outside the semiconductor structure. | 12-02-2010 |
20100301491 | HIGH YIELD AND HIGH THROUGHPUT METHOD FOR THE MANUFACTURE OF INTEGRATED CIRCUIT DEVICES OF IMPROVED INTEGRITY, PERFORMANCE AND RELIABILITY - A method for forming a contact opening, such as a via hole, is provided. In the method, a sacrificial layer is deposited over a damascene feature prior to exposing a conductor formed in a substrate at a bottom of the opening. The sacrificial layer is provided to prevent damage or contamination of materials used. Even after the conductor has been exposed once or more times, the sacrificial layer can be deposited over the damascene feature to protect it from further damage or contamination by a subsequent process that will further expose the conductor at the contact opening bottom. The exposing step may form a recess in the conductor. By further forming a trench feature over the contact opening, a dual damascene feature can be fabricated. By performing further damascene process steps over already formed damascene interconnect features, various interconnect systems, such as a single damascene planar via, a single damascene embedded via and a dual damascene interconnect system having either a planar via or an embedded via, can be fabricated. Dual damascene interconnect structures having either a sacrificial layer incorporated in them or having no sacrificial layer incorporated in them are also provided. | 12-02-2010 |
20100301492 | METHOD OF STIFFENING CORELESS PACKAGE SUBSTRATE - Embodiments of the present invention relate to a method of stiffening a semiconductor coreless package substrate to improve rigidity and resistance against warpage. An embodiment of the method comprises disposing a sacrificial mask on a plurality of contact pads on a second level interconnect (package-to-board interconnect) side of a coreless package substrate, forming a molded stiffener around the sacrificial mask without increasing the effective thickness of the substrate, and removing the sacrificial mask to form a plurality of cavities in the molded stiffener corresponding to the contact pads. Embodiments also include plating the surface of the contact pads and the sidewalls of the cavities in the molded cavities with an electrically conductive material. | 12-02-2010 |
20100308466 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate; first and second semiconductor pillars; a first insulator; and a first wiring layer. The first and second semiconductor pillars are disposed over the substrate. The first and second semiconductor pillars may be aligned in a first direction. The first insulator may eclectically isolate the first and second semiconductor pillars from each other. The first wiring layer may continuously extend inside a first continuing groove that extends through the first and second semiconductor pillars and the first insulator. The first continuing groove extends in a first direction along which the first and second semiconductor pillars are aligned. | 12-09-2010 |
20100308467 | Semiconductor Device and Method of Forming Through Hole Vias in Die Extension Region Around Periphery of Die - A semiconductor wafer contains a plurality of semiconductor die. The semiconductor wafer is diced to separate the semiconductor die. The semiconductor die are transferred onto a carrier. A die extension region is formed around a periphery of the semiconductor die on the carrier. The carrier is removed. A plurality of through hole vias (THV) is formed in first and second offset rows in the die extension region. A conductive material is deposited in the THVs. A first RDL is formed between contact pads on the semiconductor die and the THVs. A second RDL is formed on a backside of the semiconductor die in electrical contact with the THVs. An under bump metallization is formed in electrical contact with the second RDL. Solder bumps are formed on the under bump metallization. The die extension region is singulated to separate the semiconductor die. | 12-09-2010 |
20100308468 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATION METHOD - In a semiconductor device made of a plurality of materials, if the device is fabricated through a step of cutting the bonded plurality of materials, a boundary line of the plurality of materials is exposed on a cutting plane. Internal stress in the cutting remains at this boundary line to allow moisture and corrosive gas to easily enter into the device. In order to reduce the entrance of the moisture, the gas, and the like, the boundary appearing on the cutting plane is covered by a covering layer. At this time, partial cutting exposing the boundary line and not separating semiconductor devices are performed so that the covering layer can be formed with the plurality of semiconductor devices attached to the substrate. | 12-09-2010 |
20100314770 | Mounting Substrate and Electronic Apparatus - A mounting substrate having a structure allowing reduction of the cost and an electronic apparatus formed by surface-mounting a semiconductor device thereon are provided. The mounting substrate is a mounting substrate mounted with a semiconductor device having external terminals alignedly arrayed in the form of a matrix, and includes junctions arrayed on a surface to which the semiconductor device is opposed so that the external terminals are bonded thereto respectively and wires connected to the junctions respectively and extracted out of a region to which the semiconductor device is bonded. The wires connected to inwardly arrayed 4 rows by | 12-16-2010 |
20100314771 | SEMICONDUCTOR DEVICE INCLUDING AN IMPROVED LITHOGRAPHIC MARGIN - A semiconductor device includes first to third lines. The second line has a width equal to the first line. The second line is arranged with a space equal to the width from the first line, and partially has a gap. The third line is connected to one end of the first line and to a side of one end of the second line. | 12-16-2010 |
20100314772 | Stacked Layer Type Semiconductor Device and Semiconductor System Including the Same - A stacked layer type semiconductor device includes N memories each including at least one main via and (N−1) sub vias, the N memories being sequentially stacked on one-another so that central axes of the N memories face each other crosswise, and a plurality of connection units electrically connecting the N memories. Here, N is a natural number greater than 1. | 12-16-2010 |
20100314773 | Semiconductor device - A semiconductor device has: a radiator plate that is maintained at a predetermined potential; an SOI (Silicon On Insulator) chip mounted on the radiator plate; and thermal grease applied to an interface between the radiator plate and the SOI chip. The SOI chip has: a first silicon substrate forming a circuit element part; a second silicon substrate facing the radiator plate; and an insulating film formed between the first silicon substrate and the second silicon substrate. The first silicon substrate and the second silicon substrate are electrically connected to each other. The thermal grease is conductive and electrically connects the second silicon substrate and the radiator plate. | 12-16-2010 |
20100314774 | RELIABLE INTERCONNECTS - A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with a dielectric layer formed thereon. The dielectric layer having a conductive line disposed in an upper portion of the dielectric layer. The substrate is processed to produce a top surface of the dielectric layer that is not coplanar with a top surface of the conductive line to form a stepped topography. | 12-16-2010 |
20100320609 | WETTING PRETREATMENT FOR ENHANCED DAMASCENE METAL FILLING - Disclosed are pre-wetting apparatus designs and methods. These apparatus designs and methods are used to pre-wet a wafer prior to plating a metal on the surface of the wafer. Disclosed compositions of the pre-wetting fluid prevent corrosion of a seed layer on the wafer and also improve the filling rates of features on the wafer. | 12-23-2010 |
20100320610 | SEMICONDUCTOR PACKAGE WITH SUBSTRATE HAVING SINGLE METAL LAYER AND MANUFACTURING METHODS THEREOF - A semiconductor package includes a substrate, a die, and a package body. The substrate includes: (a) a core including a resin reinforced with fibers; (b) a plurality of openings extending through the core; (c) a dielectric layer; and (d) a single conductive layer disposed between the dielectric layer and the core. Portions of a lower surface of the single conductive layer cover the plurality of openings to form a plurality of first contact pads for electrical connection external to the semiconductor package. Exposed portions of an upper surface of the single conductive layer form a plurality of second contact pads. The die is electrically connected to the plurality of second contact pads, and the package body encapsulates the die. | 12-23-2010 |
20100320611 | Method for manufacturing a semiconductor device, semiconductor chip and semiconductor wafer - A method for manufacturing a semiconductor device includes forming a semiconductor wafer including a plurality of interconnect layers, the semiconductor wafer including: a plurality of chip-composing portions; a dicing region separating the chip-composing portions from each other; and a plurality of inter-chip interconnects electrically connecting adjacent ones of the chip-composing portions and formed in one of the interconnect layers and in the dicing region; a dummy metal pattern comprising a plurality of dummy metals, the dummy metal pattern being formed in at least one of the interconnect layers over or below the inter-chip interconnects only in an area corresponded to a region where the inter-chip interconnects are arranged and corresponded to a region therearound; and forming semiconductor chips by dicing the dicing region so as to divide the chip-composing portions. | 12-23-2010 |
20100320612 | Method for manufacturing semiconductor device, semiconductor chip, and semiconductor wafer - A method for manufacturing a semiconductor device includes forming a semiconductor wafer including a plurality of interconnect layers, the semiconductor wafer including: a plurality of chip-composing portions; a dicing region separating the chip-composing portions from each other; and a plurality of inter-chip interconnects formed in the dicing region and electrically connecting adjacent ones of the chip-composing portions; and forming semiconductor chips by dicing the dicing region so as to divide the chip-composing portions, wherein each of the inter-chip interconnects has a width of an intermediate portion narrower than widths of connection end portions connected to the adjacent ones of the chip-composing portions. | 12-23-2010 |
20100320613 | INTEGRATED CIRCUIT ARRANGEMENT WITH AN AUXILIARY INDENTATION, PARTICULARLY WITH ALIGNING MARKS - An integrated circuit arrangement is disclosed having a wiring indentation and an auxiliary indentation in a dielectric layer. The wiring indentation contains a metal through which current flows during operation of the circuit arrangement. The auxiliary indentation contains a metal through which an electric current does not flow during operation of the circuit arrangement. The auxiliary indentation serves as an alignment mark during the production of the integrated circuit arrangement. | 12-23-2010 |
20100320614 | SEMICONDUCTOR PACKAGE AND PRODUCTION METHOD THEREOF, AND SEMICONDUCTOR DEVICE - A semiconductor package production method includes the step of die-cutting part of a lead side portion of a seal formed by molding and dam bars using a pedestal and punch. The pedestal has an outer surface at a position retreating from a side surface of an upper seal portion as far as possible and an inner surface generally near a side surface of a lower seal portion. Width Wa of the upper surface of the pedestal is smaller than the overhang size of the upper seal portion. Tip region Ra of the lead side portion which is present right under the overhang portion of the upper seal portion has a slanted surface Fa | 12-23-2010 |
20100320615 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device, includes: mounting a semiconductor chip having an electrode on a wiring substrate having a base substrate and a wiring formed on the base substrate; forming a eutectic alloy by contacting the wiring with the electrode and by heating and pressurizing, and; forming the eutectic alloy so as a part of the eutectic alloy enters between the wiring and the base substrate. | 12-23-2010 |
20100327452 | MOUNTING STRUCTURE AND METHOD OF MANUFACTURING THE SAME - To provide a mounting structure having a substrate and a semiconductor package mounted thereon which enables suppression of unnecessary electromagnetic radiation and improvement of drop impact resistance, and a method of manufacturing the same. A substrate | 12-30-2010 |
20100327453 | Semiconductor Device and Method of Manufacturing the Same - A semiconductor device comprises a first substrate in which a first memory cell array is formed, a second substrate in which a second memory cell array, a page buffer, and decoders are formed, and a coupling structure formed on the first and second substrates and configured to have the page buffer and the decoders operated in conjunction with the first and second memory cell arrays. The second substrate is adhered over the first substrate. | 12-30-2010 |
20100327454 | SEMICONDUCTOR DEVICE, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - There is provided a semiconductor device including: an insulating layer provided on a substrate and formed with plural cavities; wiring lines provided on the insulating layer; plural branched wiring lines that branch from the wiring lines so as to respectively overlap with the plural cavities when seen in plan view; a conductive portion formed on the wiring lines; an external terminal formed on the conductive portion; and a sealing resin layer that seals the wiring lines and the conductive portion. | 12-30-2010 |
20100327455 | Semiconductor device including two heat sinks and method of manufacturing the same - A semiconductor device includes a semiconductor element, a first heat sink, a second heat sink, and a resin member. The semiconductor element has first and second surfaces. The first heat sink has a first heat radiation surface and a first end surface. The first end surface is coupled with the first surface. The second heat sink has a second heat radiation surface, the second end surface being opposite the second heat radiation surface, and a depressed section depressed toward the second heat radiation surface. The second surface of the semiconductor element is coupled with a bottom surface of the depressed section. The resin member is disposed in the depressed section and seals the semiconductor element, the first heat sink, and the second heat sink in such a manner that the first heat radiation surface is exposed outside the resin member. | 12-30-2010 |
20100327456 | Process for Improving the Reliability of Interconnect Structures and Resulting Structure - An interconnect structure of an integrated circuit having improved reliability and a method for forming the same are provided. The method includes providing a substrate, forming a dielectric layer overlying the substrate, performing a first shrinking process, wherein the dielectric layer shrinks and has a first shrinkage rate, forming a conductive feature in the dielectric layer after the step of performing the first shrinking process, and performing a second shrinking process after the step of forming the conductive feature, wherein the dielectric layer substantially shrinks and has a second shrinkage rate. | 12-30-2010 |
20100327457 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE - To provide a semiconductor chip whose number of electrodes are minimized while the horizontal position between the semiconductor chip and the mounted substrate is maintained in implementation to avoid any connection problem, as well as to prevent the damage to the semiconductor circuit of such chip. | 12-30-2010 |
20110001243 | SEMICONDUCTOR DEVICE INCLUDING DUMMY - A semiconductor device or a memory which includes the same have a line pattern, and a contact plug, the line pattern including a first linear feature to which the contact plug is connected by design, and a second linear feature having a connecting portion and a dummy portion adjacent the location at which the contact plug is electrically connected to the first linear feature. A second contact plug is electrically connected to the connecting portion of the second linear feature of the line pattern. In the case of a misalignment error or the like, the first contact plug may also be electrically connected to the second linear feature of the line pattern but at the dummy portion thereof so as to not create a short circuit in that case. The dummy portion thus allows a sufficiently large process margin to be secured for the contact plug. | 01-06-2011 |
20110001244 | Method for Producing a Power Semiconductor Module, and Power Semiconductor Module Comprising a Connection Device - A method for making a power semiconductor module and a module produced by that method, wherein the module includes a substrate, a connection device and load terminal elements, wherein power semiconductor components are arranged on a conductor track of the substrate and connected to one of the load terminal element by the connection device. The power semiconductor module has auxiliary contact pads which can be connected to an external printed circuit board. The primary production step in this case is cohesively connecting respective first contact areas of the first conductor tracks to at least one second contact area of a power semiconductor component and at least one third contact area of a load terminal element; afterwards, the assemblage composed of at least one power semiconductor component of a connection device and load terminal elements is arranged to form a housing of the power semiconductor module. | 01-06-2011 |
20110001245 | SEMICONDUCTOR DEVICE INCLUDING SEALING FILM FOR ENCAPSULATING SEMICONDUCTOR CHIP AND PROJECTION ELECTRODES AND MANUFACTURING METHOD THEREOF - Disclosed in a semiconductor device including a semiconductor chip including an electrode, a projection electrode, an sealing film for encapsulating the semiconductor chip and the projection electrode, a first wiring lines provided on one surface of the sealing film, which is electrically connected with the electrode and the projection electrode, a second wiring lines provided on the other surface of the sealing film, which is electrically connected with the projection electrode and at least one of a first via hole conductor for electrically connecting the first wiring lines and the projection electrode or a second via hole conductor for electrically connecting the second wiring lines and the projection electrode, and an area of the projection electrode in an interface where the projection electrode and the first via hole conductor contact each other is greater than an area of the first via hole conductor in the interface and an area of the projection electrode in an interface where the projection electrode and the second via hole conductor contact each other is greater than an area of the second via hole conductor in the interface. | 01-06-2011 |
20110001246 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The reliability of a semiconductor device having an embedded wire in the lowest layer wire is improved. In a main surface of a semiconductor substrate, MISFETs are formed and over the main surface, insulating films | 01-06-2011 |
20110006432 | RECONSTITUTED WAFER STACK PACKAGING WITH AFTER-APPLIED PAD EXTENSIONS - A stacked microelectronic unit is provided which can include a plurality of vertically stacked microelectronic elements ( | 01-13-2011 |
20110006433 | ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREFOR - An electronic device includes the electronic element, the interposer substrate, on one surface of which the electronic element is mounted, and the interconnection substrate, on one surface of which the interposer substrate is mounted. One portion of the connection parts is an electrical connection part that electrically interconnects the interposer substrate and the interconnection substrate. The remaining portion is a dummy connection part that produces no functional deficiency even when the dummy connection part does not electrically interconnect the interposer substrate with the interconnection substrate. The dummy connection part includes at least one of the connection parts that at least partially overlap with the electronic element in a plan projection and are preferably arranged along an outer rim of the plan projection of the electronic element. | 01-13-2011 |
20110006434 | UNDER LAND ROUTING - An electronic component comprising an integrated device and a plurality of packaging layers in which routing between locations on the device and lands on the surface of the component is provided by a redistribution layer. The redistribution layer may be routed below the extent of a contact pad on the surface by providing a channel through the via and redistribution layers underneath that land. | 01-13-2011 |
20110006435 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment of the present invention includes a substrate, isolation layers and active regions formed in the substrate, and arranged alternately along a first direction parallel to a surface of the substrate, an inter layer dielectric formed on the isolation layers and the active regions, and having holes for respective contact plugs on the respective active regions, barrier layers formed in the holes, each of the barrier layers being formed on a top surface of an active region exposed in a hole and on one of two side surfaces of the hole, the two side surfaces of the hole being perpendicular to the first direction, and plug material layers formed on the barrier layers in the holes. | 01-13-2011 |
20110012264 | OPTOELECTRONIC DEVICE WITH HEAT SPREADER UNIT - Optoelectronic devices with heat spreader units are described. An optoelectronic device includes a back-contact optoelectronic cell including a plurality of back-contact metallization regions. One or more heat spreader units are disposed above the plurality of back-contact metallization regions. A heat sink is disposed above the one or more heat spreader units. | 01-20-2011 |
20110012265 | Semiconductor device - A semiconductor device includes a wiring board that has a conductive pattern formed on at least one principal surface, and an IC chip that is mounted on the wiring board. The IC chip includes a plurality of electrodes to make conductor connection with the wiring board. The conductive pattern includes a lead line pattern and a heat dissipation pattern. The lead line pattern is connected with at least one of the plurality of electrodes through a conductor. The heat dissipation pattern is physically spaced from the IC chip and the lead line pattern and has a larger surface area than the lead line pattern. Further, the lead line pattern and the heat dissipation pattern are placed opposite to each other with a gap therebetween, and their opposite parts respectively have interdigitated shapes and are arranged with the respective interdigitated shapes engaging with each other with the gap therebetween. | 01-20-2011 |
20110012266 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In a semiconductor device, a substrate includes a plurality of line conductors which penetrate the substrate from a top surface to a bottom surface of the substrate. A semiconductor chip is secured in a hole of the substrate. A first insulating layer is formed on the top surfaces of the substrate and the semiconductor chip. A first wiring layer is formed on the first insulating layer and electrically connected via through holes of the first insulating layer to the semiconductor chip and some line conductors exposed to one of the through holes. A second insulating layer is formed on the bottom surfaces of the substrate and the semiconductor chip. A second wiring layer is formed on the second insulating layer and electrically connected via a through hole of the second insulating layer to some line conductors exposed to the through hole. | 01-20-2011 |
20110012267 | SEMICONDUCTOR INTEGRATED DEVICE HAVING A CONTACT STRUCTURE, AND CORRESPONDING MANUFACTURING PROCESS - An integrated device, including: a first conductive region; a second conductive region set at a distance from the first conductive region; an etch-stop layer, made of a first dielectric material, at least partially overlapped on the first and second conductive regions; an insulating layer, made of a second dielectric material, different from the first, overlapped on the first and second conductive regions and on the etch-stop layer; at least one through opening extending through the insulating layer and the etch-stop layer; and a barrier layer, made of a third dielectric material, different from the first, set between the first conductive region and the etch-stop layer and between the second conductive region and the etch-stop layer. | 01-20-2011 |
20110018136 | APPARATUS AND METHOD FOR FORMING ELECTONIC DEVICES - A method of forming at least one electronic device on a substrate comprising creating a depository and an attached capillary; providing a liquid containing particles in the range 1 nanometer to 1 millimeter for deposit into the depository; the liquid flowing into the at least one capillary by capillary action; evaporating the liquid such that the particles form an agglomerate beginning at the end of the at least one capillary with a substantially uniform distribution of the particles within the agglomerate; whereby the agglomerate is used to form a part of the at least one electronic device. An microelectronic integrated circuit device comprising a substrate; a depository coupled to said substrate formed by at least one wall, a capillary channel coupled to said depository adapted to be filled with liquid comprising nanoparticles by capillary action, whereby as the liquid evaporates, an agglomerate forms in the capillary channel having a substantially uniform distribution of the particles. | 01-27-2011 |
20110018137 | Method of manufacturing semiconductor device, semiconductor device thus manufactured, and semiconductor manufacturing apparatus - A plurality of projections, respectively given later as cores of a plurality of external connection terminals, are formed first by selectively forming a curable resin layer over a protective insulating film; flat portions are then formed respectively on the top surfaces of the plurality of projections, by pressing a molding jig having a flat opposing surface onto the top surfaces of the plurality of projections, before the projections are cured; the plurality of projections are cured; and the plurality of external connection terminals, and the plurality of interconnects are formed, by selectively forming an electro-conductive film over the plurality of projections, the protective insulating film, and the plurality of electrode pads. | 01-27-2011 |
20110024911 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An electrical characteristics test for a semiconductor integrated circuit using a Kelvin contact method can be conducted in a pre-process without obstructing the reduction in size of a semiconductor chip or without complicating the circuit design. A probe card in a testing apparatus includes probes for Kelvin contact, the probes for Kelvin contact including a coil probe and a POGO pin probe disposed inside the coil probe, and a probe for two-terminal measurement. Electrode pads formed in each chip area over a wafer are in a relation of A=B<2A, given that the area of one of the electrode pads with which the probe for Kelvin contact comes into contact is B and the area of the other electrode pad with which the probe for two-terminal measurement comes into contact is A. | 02-03-2011 |
20110024912 | CMOS DEVICE INCLUDING MOLECULAR STORAGE ELEMENTS IN A VIA LEVEL - Memory cells in integrated circuit devices may be formed on the basis of functional molecules which may be positioned within via openings on the basis of appropriate patterning techniques, which may also be used for forming semiconductor-based integrated circuits. Consequently, memory cells may be formed on a “molecular” level without requiring extremely sophisticated patterning regimes, such as electron beam lithography and the like. | 02-03-2011 |
20110024913 | SEMICONDUCTOR DEVICE - A semiconductor device includes first and second semiconductor chips. The first semiconductor chip includes a first engaging portion. The first engaging portion includes a first conductor. The second semiconductor chip includes a second engaging portion engaged with the first engaging portion. The second engaging portion includes a second conductor being electrically in contact with the first conductor. | 02-03-2011 |
20110031627 | Reducing Crosstalk In The Design Of Module Nets - A method, a system and a computer program product for reducing coupling noise in low loss on-module wires used for connecting module components in electrical circuits/devices. During the design stage, an Enhanced Crosstalk Reduction (ECR) utility identifies interconnect wires as driven/aggressor traces or receiver traces. The ECR utility substantially avoids forward crosstalk in a victim trace by specially arranging driver traces adjacent to the receiver victim trace in order to provide a lower level and saturated level of backward crosstalk. In particular, the ECR utility provided a configuration of wire/trace layers based on one or more of: (a) the crosstalk impact of a trace when positioned in a particular location; (b) the crosstalk impact of the trace upon remaining components based on placement in the particular location; and (c) system component specifications. In addition, the ECR utility reduces crosstalk by providing a configuration of receiver wires and transmitter wires without the use of isolation layers. | 02-10-2011 |
20110031628 | SEMICONDUCTOR DEVICE MODULE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE MODULE - A semiconductor device module includes a first substrate layer on which a first semiconductor device is surface-mounted, a second substrate layer that is a layer laminated on a side of the first substrate layer on which the first semiconductor device is not surface-mounted, a second semiconductor device being surface-mounted on a surface of the second substrate layer and not on a side of the first substrate layer, and a hollow section that is a space sandwiched between the first substrate layer and the second substrate layer and formed on back sides of areas on which the first semiconductor device and the second semiconductor device are surface-mounted. | 02-10-2011 |
20110031629 | EDGE CONNECT WAFER LEVEL STACKING - In accordance with an aspect of the invention, a stacked microelectronic package is provided which may include a plurality of subassemblies, e.g., a first subassembly and a second subassembly underlying the first subassembly. A front face of the second subassembly may confront the rear face of the first subassembly. Each of the first and second subassemblies may include a plurality of front contacts exposed at the front face, at least one edge and a plurality of front traces extending about the respective at least one edge. The second subassembly may have a plurality of rear contacts exposed at the rear face. The second subassembly may also have a plurality of rear traces extending from the rear contacts about the at least one edge. The rear traces may extend to at least some of the plurality of front contacts of at least one of the first or second subassemblies. | 02-10-2011 |
20110037175 | INTERCONNECTION BETWEEN SUBLITHOGRAPHIC-PITCHED STRUCTURES AND LITHOGRAPHIC-PITCHED STRUCTURES - An interconnection between a sublithographic-pitched structure and a lithographic pitched structure is formed. A plurality of conductive lines having a sublithographic pitch may be lithographically patterned and cut along a line at an angle less than 45 degrees from the lengthwise direction of the plurality of conductive lines. Alternately, a copolymer mixed with homopolymer may be placed into a recessed area and self-aligned to form a plurality of conductive lines having a sublithographic pitch in the constant width region and a lithographic dimension between adjacent lines at a trapezoidal region. Yet alternately, a first plurality of conductive lines with the sublithographic pitch and a second plurality of conductive lines with the lithographic pitch may be formed at the same level or at different. | 02-17-2011 |
20110037176 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE MODULE, SEMICONDUCTOR DEVICE CONNECTING DEVICE, SEMICONDUCTOR DEVICE MODULE MANUFACTURING DEVICE, SEMICONDUCTOR DEVICE MODULE - A method of forming a semiconductor device module including a number of n semiconductor devices is provided, n being an integer ≧2, the method including: providing a substrate coated with a first contact layer, having a semiconductor layer formed on the first contact layer, and having a second contact layer formed on the semiconductor layer; and forming a connection of the first contact layer and the second contact layer by forming a number of n-1 conductive paths in a material of the semiconductor layer for connecting the n semiconductor devices. | 02-17-2011 |
20110037177 | DEVICE UNDER BONDING PAD USING SINGLE METALLIZATION - An integrated circuit device comprising an improved bonding pad structure. The device has a semiconductor substrate. A plurality of active MOS devices are formed on the semiconductor substrate. The device has an interlayer dielectric layer overlying the plurality of active MOS devices and at least one single metal bonding pad formed on the interlayer dielectric layer and directly over at least one of the active devices. At least four edge regions are formed on a square shape of the at least one single metal bonding pad. An angled cut region is formed on each of the four edge regions. Preferably, the angled cut region is within a periphery of the square shape of the at least one single metal bonding pad. A passivation layer having an opening is formed over the at least single metal bonding pad. The device has a buffer metal layer free region between the plurality of active MOS devices and the at least one single metal bonding pad. The buffer metal layer free region is within an entirety of the interlayer dielectric layer. The passivation is substantially free from the buffer metal layer underlying the single metal bonding pad. | 02-17-2011 |
20110037178 | INTEGRATED CIRCUIT - An integrated circuit connection is disclosed. The integrated circuit connection comprises a substrate | 02-17-2011 |
20110042818 | Adding Symmetrical Filling Material In An Integrated Circuit Layout - In one embodiment, an integrated circuit has a conductive layer, where the conductive layer has a first set of regions and a second set of fill material regions, and the second set of fill material regions has a line of symmetry. Other embodiments are described and claimed. | 02-24-2011 |
20110042819 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - According to an embodiment of the invention, a chip package is provided. The chip package includes a semiconductor substrate having an upper surface and an opposite lower surface, a through-hole penetrating the upper surface and the lower surface of the semiconductor substrate, a chip disposed overlying the upper surface of the semiconductor substrate, a conducting layer overlying a sidewall of the through-hole and electrically connecting the chip, a first insulating layer overlying the upper surface of the semiconductor substrate, a second insulating layer overlying the lower surface of the semiconductor substrate, and a bonding structure disposed overlying the lower surface of the semiconductor substrate, wherein a material of the second insulating layer is different from that of the first insulating layer. | 02-24-2011 |
20110049721 | METAL DENSITY AWARE SIGNAL ROUTING - Methods and apparatus for routing signal paths in an integrated circuit. One or more signal routing paths for transferring signals of the integrated circuit may be determined. A dummy fill pattern for the integrated circuit may be determined based on the one or more metal density specifications and at least one design rule for reducing cross coupling capacitance between the dummy fill pattern and the routing paths. The signal routing paths and/or the dummy fill pattern may be incrementally optimized to meet one or more timing requirements of the integrated circuit. | 03-03-2011 |
20110049722 | Semiconductor Circuit Structure and Layout Method thereof - A semiconductor circuit structure includes a substrate and an interconnect structure. The interconnect structure is disposed on the substrate and includes a plurality of circuit patterns and at least one closed loop pattern. The closed loop pattern is in a same layer with the circuit patterns, surrounds between the circuit patterns and is insulated from the circuit patterns. The closed loop pattern can protect the circuit patterns from being damaged by stresses, for improving a mechanical strength of the semiconductor circuit structure. | 03-03-2011 |
20110049723 | METHODS AND STRUCTURES FOR CONTROLLING WAFER CURVATURE - Methods and structures for controlling wafer curvature during fabrication of integrated circuits caused by stressed films. The methods include controlling the conductor density of wiring levels, adding compensating stressed film layers and disturbing the continuity of stress films with the immediately lower layer. The structure includes integrated circuits having compensating stressed film layers. | 03-03-2011 |
20110049724 | BEOL INTERCONNECT STRUCTURES AND RELATED FABRICATION METHODS - Methods for forming voids in BEOL interconnect structures and BEOL interconnect structures. The methods include forming a temporary feature on a top surface of a first dielectric layer and depositing a second dielectric layer on the top surface of the first dielectric layer. The temporary feature is removed from the second dielectric layer to define a void in the second dielectric layer that is laterally adjacent to a conductive feature in the second dielectric layer. The void operates to reduce the effective dielectric constant of the second dielectric layer, which reduces parasitic capacitance between the conductive feature and other conductors in the BEOL interconnect structure. | 03-03-2011 |
20110049725 | Semiconductor Chip with Contoured Solder Structure Opening - Methods and apparatus to inhibit cracks and delaminations in a semiconductor chip solder bump are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first dielectric layer over a first conductor structure of a semiconductor chip and forming a first opening in the first dielectric layer to expose at least a portion of the conductor structure. The first opening defines an interior wall that includes plural protrusions. A solder structure is coupled to the first conductor structure such that a portion of the solder structure is positioned in the first opening. | 03-03-2011 |
20110049726 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR PACKAGE - A semiconductor package includes a semiconductor chip; a resin part configured to cover a side surface of the semiconductor chip; and a wiring structure formed on a circuit forming surface of the semiconductor chip and a surface of the resin part being situated at the same side as the circuit forming surface, the wiring structure being electrically connected to the semiconductor chip, wherein the resin part is formed so as to cover a part of a surface of the semiconductor chip situated at an opposite side to the circuit forming surface of the semiconductor chip. | 03-03-2011 |
20110049727 | RECESSED INTERLAYER DIELECTRIC IN A METALLIZATION STRUCTURE OF A SEMICONDUCTOR DEVICE - In a complex metallization system, the probability of dielectric breakdown may be reduced by vertically separating a critical area of high electric field strength and an area of reduced dielectric strength of the interlayer dielectric material. For this purpose, the interlayer dielectric material may be recessed after forming the metal regions and/or the metal regions may be increased in height and the corresponding recess may be refilled with an appropriate dielectric material. | 03-03-2011 |
20110049728 | METHOD TO PERFORM ELECTRICAL TESTING AND ASSEMBLY OF ELECTRONIC DEVICES - A method performs electrical testing and assembly of an electronic device on a wafer and comprising a pad made in an oxide layer covered by a passivation layer. The method includes connecting the electronic device to a testing apparatus; providing said electronic device with a metallization layer extending on the passivation layer from the pad to a non-active area of said wafer. The method comprises-performing the electrical testing on wafer of the electronic device by placing a probe of on a portion of the extended metallization layer; performing the cut of said wafer, reducing the extension of the metallization layer to the edge of the electronic device; embedding the device inside a package, forming on the metallization layer an electrical connection configured to connect the metallization layer to a circuit in said package. | 03-03-2011 |
20110057318 | Die Package - A die is packaged. The package of the die has a line groove filled with a conductive material. A metal pad is exposed out of a solder mask. And the metal pad is connected with a die pad on the die through the line groove in a deflective way. In this way, a wiring space of a wafer is efficiently used; and a manufacturing yield of the wafer is enhanced. | 03-10-2011 |
20110057319 | ARRANGING THROUGH SILICON VIAS IN IC LAYOUT - A portion of an IC layout that includes a plurality of through silicon vias (TSVs) is evaluated to identify linearly aligned TSVs. The portion of the IC layout is modified to reduce a number of the linearly aligned TSVs, resulting in less wafer breakage. | 03-10-2011 |
20110057320 | SEMICONDUCTOR INTEGRATED CIRCUIT AND DESIGN METHOD THEREOF - In a layout process of a semiconductor integrated circuit, a power supply is initially formed in an arrangement in which the current threshold value is not exceeded. In a case where the excess over the current threshold value occurs after the power supply is formed, the power supply arrangement is changed according to the current threshold value, design rule data base, and power supply wiring density so as not to exceed the current threshold value. | 03-10-2011 |
20110062590 | Chip Stacking Device Having Re-Distribution Layer - A chip stacking device uses nano particle silver paste for re-distribution interconnection to form a structure having low resistance through trench filling or printing. Thus, due to its low resistance, it can effectively reduce the electrical instability due to voltage drop after current flows. Furthermore, power consumption is reduced too, with energy saved. With its stable electrical signal, its utilization scope can be further expanded to high frequency product. | 03-17-2011 |
20110062591 | INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING THROUGH SILICON VIA WITH DIRECT INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a through silicon via die having an interconnect through a silicon substrate; depositing a re-distribution layer on the through silicon via die and connected to the interconnects; mounting a structure over the through silicon via die; connecting the structure to the interconnect of the through silicon via die with a direct interconnect; and encapsulating the through silicon via die and partially encapsulating the structure with an encapsulation. | 03-17-2011 |
20110068473 | Lead pin for package substrate - There is provided a lead pin for a package substrate including: a connection pin being inserted into a hole formed in an external substrate; a head part formed on one end of the connection pin; and a barrier part formed on one surface of the head part in order to block the path of a solder paste so that the solder paste is prevented from flowing so as to cover the upper portion of the head part when the head part is mounted on the package substrate. | 03-24-2011 |
20110068474 | SEMICONDUCTOR DEVICE HAVING METAL LINES WITH SLITS - A semiconductor device including a semiconductor substrate, an integrated circuit on the semiconductor substrate, an insulation layer covering the integrated circuit, and a plurality of metal line patterns on the insulation layer. First and second adjacent metal line patterns of the plurality of metal line patterns are spaced apart from each other by a space, and each of the first and second adjacent metal line patterns has at least one slit. | 03-24-2011 |
20110074035 | SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor memory apparatus is provided to minimize failure of the semiconductor memory apparatus and to secure a processing margin. The method also provides for minimizing the deterioration of an operating speed and the operational stability, and minimizing the increase of resistance occurring as a result of a reduced processing margin when forming a gate pattern in a peripheral region of the semiconductor memory apparatus. The method includes forming a connection pad in a peripheral region while forming a buried word line in a cell region, and forming a gate pattern in the peripheral region while forming a bit line in the cell region. | 03-31-2011 |
20110074036 | VIA CONTACT STRUCTURES AND METHODS FOR INTEGRATED CIRCUITS - A method for fabricating an integrated circuit device includes providing a semiconductor substrate having a first region and a second region, e.g., peripheral region. The method forms a stop layer overlying the first and second regions and a low k dielectric layer (e.g., k<2.9) overlying the stop layer in the first and second regions. The method forms a cap layer overlying the low k dielectric layer. In an embodiment, the method initiates formation of a plurality of via structures within a first portion of the low k dielectric layer overlying the first region and simultaneously initiates formation of an isolated via structure for in the second region of the semiconductor substrate, using one or more etching processes. The method includes ceasing formation of the plurality of via structures within the first portion and ceasing formation of the isolated via structure in the second region when one or more portions of stop layer have been exposed. | 03-31-2011 |
20110074037 | SEMICONDUCTOR DEVICE - A device has a semiconductor chip, a wiring board, a support which supports the semiconductor chip on the wiring board and forms a gap between the semiconductor chip and the wiring board, and a sealing resin injected into the gap and covering the semiconductor chip. | 03-31-2011 |
20110074038 | METHODS FOR FORMING INTERCONNECT STRUCTURES THAT INCLUDE FORMING AIR GAPS BETWEEN CONDUCTIVE STRUCTURES - A method for forming a semiconductor structure includes forming a sacrificial layer over a substrate. A first dielectric layer is formed over the sacrificial layer. A plurality of conductive structures are formed within the sacrificial layer and the first dielectric layer. The sacrificial layer is treated through the first dielectric layer, at least partially removing the sacrificial layer and forming at least one air gap between two of the conductive structures. A surface of the first dielectric layer is treated, forming a second dielectric layer over the first dielectric layer, after the formation of the air gap. A third dielectric layer is formed over the second dielectric layer. At least one opening is formed within the third dielectric layer such that the second dielectric layer substantially protects the first dielectric layer from damage by the step of forming the opening. | 03-31-2011 |
20110079912 | Connection for Off-Chip Electrostatic Discharge Protection - A method and apparatus for off-chip ESD protection, the apparatus includes an unprotected IC | 04-07-2011 |
20110079913 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device, includes temporarily fixing a semiconductor chip to a supporting member to direct a connection electrode toward the supporting member side, forming an insulating layer for preventing resin-permeation covering the semiconductor chip, on the supporting member and the semiconductor chip, forming a resin substrate sealing a periphery and a back surface side of the semiconductor chip, on the insulating layer, and removing the supporting member to expose the connection electrode of the semiconductor chip. A build-up wiring is connected directly to the connection electrode of the semiconductor chip. | 04-07-2011 |
20110079914 | STANDARD CELL AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire. | 04-07-2011 |
20110079915 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor chip is provided comprising a semiconductor substrate on which an integrated circuit is formed. The semiconductor chip, which is provided on the semiconductor substrate in an area array, further comprises a plurality of electrodes electrically coupled with the inside of the semiconductor substrate, wherein the electrodes are arranged into a plurality of first groups respectively lined along a plurality of paralleling first straight lines and, further, into a plurality of second groups respectively lined along a plurality of second straight lines which extend so as to intersect with the first straight lines. | 04-07-2011 |
20110084394 | Semiconductor Structure - A semiconductor structure is provided. The semiconductor structure includes a substrate, a dielectric layer, a pad structure and a protection structure. The dielectric layer is disposed on the substrate. The pad structure is disposed in the dielectric layer. The pad structure includes a plurality of first metal layers and a plurality of plugs which are electrically connected to each other vertically. There is no contact plug disposed between the pad structure and the substrate. The protection structure is disposed in the dielectric layer and encompasses the pad structure. | 04-14-2011 |
20110084395 | Semiconductor package substrate and semiconductor device having the same - A semiconductor device includes a semiconductor chip and a package substrate on which the semiconductor chip is mounted. The package substrate has internal terminals connected to the semiconductor chip, front surface wirings connected to the internal terminals, rear surface wirings connected to external electrodes, and contacts connecting the front surface wiring and rear surface wiring. Out of the plurality of contact, some contacts included in the wirings for signal transmission are disposed near the internal terminals. Thus, a signal led out from the semiconductor chip is immediately taken away from the chip mounting surface of the package substrate. This reduces the floating capacitance between the wirings on the package substrate and chip, thereby improving the signal quality. | 04-14-2011 |
20110084396 | ELECTRICAL CONNECTION FOR MULTICHIP MODULES - A semiconductor package includes a first semiconductor chip mounted on a substrate and a second semiconductor chip mounted on top of the first semiconductor chip. A plurality of metal lines is deposited on the top of the first chip, and the metal lines are isolated from circuitry in the first chip. Wire bonds connect pads on the second chip to metal lines on the first chip. Additional wired bonds connect the metal lines on the first chip to terminals on the substrate. Conductive through-silicon vias or solder bumps may replace the wire bonds, and additional chips may be included in the package. | 04-14-2011 |
20110089569 | Multilayer wiring, method for placing dummy wiring in multilayer wiring, semiconductor device, and semiconductor device manufacturing method - A multilayer wiring in which plural metal wirings and plural interlayer insulating films are layered, each interlayer insulating film being planarized each time formed, is divided into plural regions. The percentage of an area occupied by each of the metal wirings within each region is obtained for each of the metal wirings. An integral percentage is obtained per region by integrating, the percentages. The integral percentages are used to calculate the relative positional relationship of upper surfaces of the interlayer insulating films of plural regions, from the relative values of the integral percentages obtained beforehand and relative positions of the upper surfaces. In regions where the upper surface is of a height lower than a predetermined value, a dummy wiring is disposed, and in regions where the upper surface is of a height equal to or greater than the predetermined value, a dummy wiring is not disposed. | 04-21-2011 |
20110095433 | CONDUCTIVE FILM, METHOD OF MANUFACTURING THE SAME, SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - There is provided a method of manufacturing a conductive film. The method includes: (a) providing an anodized layer having a plurality of through holes extending therethrough in its thickness direction; (b) forming a plurality of linear conductors by filling each of the through holes with a conductive material; (c) forming protection layers on both surfaces of the anodized layer; (d) removing the anodized layer to form a plurality of gaps between the linear conductors; (e) forming an organic insulation layer between the protection layers to fill the gaps with the organic insulation layer; and (f) removing the protection layers. | 04-28-2011 |
20110095434 | APPARATUS AND METHODS OF FORMING MEMORY LINES AND STRUCTURES USING DOUBLE SIDEWALL PATTERNING FOR FOUR TIMES HALF PITCH RELIEF PATTERNING - The present invention provides apparatus, methods, and systems for fabricating memory lines and structures using double sidewall patterning for four times half pitch relief patterning. The invention includes forming features from a first template layer disposed above a substrate, forming half-pitch sidewall spacers adjacent the features, forming smaller features in a second template layer by using the half-pitch sidewall spacers as a hardmask, forming quarter-pitch sidewall spacers adjacent the smaller features, and forming conductor features from a conductor layer by using the quarter-pitch sidewall spacers as a hardmask. Numerous additional aspects are disclosed. | 04-28-2011 |
20110101534 | AUTOMATED SHORT LENGTH WIRE SHAPE STRAPPING AND METHODS OF FABRICTING THE SAME - An automatic short length wire shape generation and strapping and method of fabricating such wires is provided. The method of manufacturing includes breaking of a wiring into adjacent short length wires which are below a maximum short length effect length. The adjacent short length wires are formed in a same wiring level of an integrated circuit. The method further includes forming a conductive strap in a single deposition process which overlaps and is in contact with the adjacent short length wires. | 05-05-2011 |
20110101535 | MICROELECTRONIC ASSEMBLY WITH IMPEDANCE CONTROLLED WIREBOND AND CONDUCTIVE REFERENCE ELEMENT - A microelectronic assembly can include a microelectronic device having device contacts exposed at a surface thereof and an interconnection element having element contacts and having a face adjacent to the microelectronic device. Conductive elements, e.g., wirebonds connect the device contacts with the element contacts and have portions extending in runs above the surface of the microelectronic device. A conductive layer has a conductive surface disposed at least a substantially uniform distance above or below the plurality of the runs of the conductive elements. In some cases, the conductive material can have first and second dimensions in first and second horizontal directions which are smaller than first and second corresponding dimensions of the microelectronic device. The conductive material is connectable to a source of reference potential so as to achieve a desired impedance for the conductive elements. | 05-05-2011 |
20110101536 | Methods For Discretized Formation of Masking and Capping Layers on a Substrate - The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate. | 05-05-2011 |
20110108991 | CIRCUIT LAYOUT STRUCTURE - A circuit layout structure includes a metal interlayer dielectric layer surrounding a metal interconnect and a metal pattern within a scrub line. The scrub line is in the vicinity of the metal interlayer dielectric layer and the metal interconnect. The metal pattern or the metal interconnect are suitably segregated to reduce a capacitance charging effect. | 05-12-2011 |
20110108992 | AIR GAP INTERCONNECT STRUCTURES AND METHODS FOR FORMING THE SAME - A metal interconnect structure includes at least a pair of metal lines, a cavity therebetween, and a dielectric metal-diffusion barrier layer located on at least one portion of walls of the cavity. After formation of a cavity between the pair of metal lines, the dielectric metal-diffusion barrier layer is formed on the exposed surfaces of the cavity. A dielectric material layer is formed above the pair of metal lines to encapsulate the cavity. The dielectric metal-diffusion barrier layer prevents diffusion of metal and impurities from one metal line to another metal line and vice versa, thereby preventing electrical shorts between the pair of metal lines. | 05-12-2011 |
20110108993 | Semiconductor package and manufacturing method thereof - There is provided a semiconductor package including: a circuit board having a receiving space formed therein; a semiconductor chip inserted into the receiving space of the circuit board; and an electrode pattern portion having a pattern shape on one surface of the semiconductor chip, and directly contacting a via portion of the circuit board so as to be electrically connected thereto. | 05-12-2011 |
20110115093 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a semiconductor substrate including a cell region and a core region adjacent to the cell region, active regions in the cell region and the core region, an interlayer insulating layer covering the active regions, upper cell contacts penetrating the interlayer insulating layer in the cell region, the upper cell contacts being adjacent to each other along a first direction and being electrically connected to the active regions, and core contacts penetrating the interlayer insulating layer in the active regions of the core region, the core contacts being adjacent to each other along the first direction and including upper connection core contacts electrically connected to the active regions, and dummy contacts adjacent to the upper connection core contacts, the dummy contacts being insulated from the active regions. | 05-19-2011 |
20110121461 | SEMICONDUCTOR DEVICE AND METHOD OF PACKAGING A SEMICONDUCTOR DEVICE WITH A CLIP - A method and apparatus of packaging a semiconductor device with a clip is disclosed. The clip defines a first contact region and a second contact region on a same face of the at least one clip. The chip defines a first face, and a second face opposite to the first face, the first contact region being attached to the first face of the chip and the second contact region being located within a same plane with the second face of the clip. | 05-26-2011 |
20110127675 | LAMINATE ELECTRONIC DEVICE - A method of manufacturing a laminate electronic device is disclosed. One embodiment provides a carrier, the carrier defining a first main surface and a second main surface opposite to the first main surface. The carrier has a recess pattern formed in the first main surface. A first semiconductor chip is attached on one of the first and second main surface. A first insulating layer overlying the main surface of the carrier on which the first semiconductor chip is attached and the first semiconductor chip is formed. The carrier is then separated into a plurality of parts along the recess pattern. | 06-02-2011 |
20110127676 | Lead pin for semiconductor package and semiconductor package - Disclosed is a lead pin for a semiconductor package. The lead pin includes a coupling pin inserted into a hole formed in an external device, a head portion disposed at one end of the coupling pin, and a step portion formed in a stepped manner between the coupling pin and the head portion, the step portion having a smaller size than the head portion. | 06-02-2011 |
20110127677 | Method of manufacturing semiconductor device, and semiconductor device - A semiconductor device including a substrate, and an insulating film formed over the substrate, wherein the insulating film has a first contact having a rectangular geometry in a plan view, and second to fifth contacts provided respectively adjacent to the individual edges of the rectangular first contact, formed therein. | 06-02-2011 |
20110127678 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED CIRCUITRY AND POST - An integrated circuit packaging system includes: an integrated circuit device; a conductive post adjacent the integrated circuit device, the conductive post with a contact surface having characteristics of a shaped platform removed; and an encapsulant around the conductive post and the integrated circuit device with the conductive post extending through the encapsulant and each end of the conductive post exposed from the encapsulant. | 06-02-2011 |
20110133339 | Semiconductor Structure and Method for Making the Same - The present invention relates to a semiconductor structure and a method for making the same. The method includes the following steps: (a) providing a first wafer and a second wafer; (b) disposing the first wafer on the second wafer; (c) removing part of the first wafer, so as to form a groove; (d) forming a through via in the groove; and (e) forming at least one electrical connecting element on the first wafer. Therefore, the wafers are penetrated and electrically connected by forming only one conductive via, which leads to a simplified process and a low manufacturing cost. | 06-09-2011 |
20110133340 | Package substrate and semiconductor apparatus - A package substrate includes: a plurality of electrodes configured to be electrically connected to a semiconductor chip; a plurality of wiring layers configured to be stacked; and a plurality of vias configured to electrically connect a plurality of planes formed in the plurality of wiring layers. A power supply via included in the plurality of vias electrically connects a power supply plane included in the plurality of planes to a power supply electrode included in the plurality of electrodes. The power supply plane is supplied with a power supply voltage. A passing wiring layer included in the plurality of wiring layers, through which the power supply via passes, includes: grid ground planes configured to surround the power supply via. The grid ground planes are electrically connected to a ground plane included in the plurality of planes through a ground via included in the plurality of vias. The ground plane is grounded. | 06-09-2011 |
20110133341 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - There is provided a method of manufacturing a semiconductor package. The method includes: (a) providing a semiconductor chip having a first surface and a second surface opposite to the first surface, wherein a pad is formed on the first surface; (b) disposing the semiconductor chip on a supporting substrate such that the first surface is directed upward; (c) forming an encapsulation resin layer on the supporting substrate so as to cover the semiconductor chip; and (d) polishing the encapsulation resin layer to expose a top surface of the pad. | 06-09-2011 |
20110140278 | OPTICAL PROXIMITY CORRECTION AWARE INTEGRATED CIRCUIT DESIGN OPTIMIZATION - An EDA method is implemented for modifying a layout file after place and route. The method includes storing a library of shape modifications for cells in the design library used for implementation of the circuit. The library of shape modifications includes the results of process-specific calibration of the shape modifications which indicate adjustment of a circuit parameter caused by applying the shape modifications to the cells. The layout file is analyzed to identify a cell for adjustment of the circuit parameter. A shape modification calibrated to achieve the desired adjustment is selected from the library. The shape modification is applied to the identified cell in the layout file to produce a modified layout file. The modified layout file can be used for tape out, and subsequently for manufacturing of an improved integrated circuit. | 06-16-2011 |
20110147942 | METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE - A method of manufacturing a semiconductor memory device of an embodiment includes: after forming a first interconnection layer and a memory cell layer above a semiconductor substrate, forming first lines by forming first grooves extending in first direction; forming a thin film on the side walls of the first grooves; forming a stack structure by filling an interlayer insulating film in the first grooves; forming a second interconnection layer above the stack structure; forming second lines by forming second grooves extending in second direction; removing the thin film exposed at bottom of the second grooves; and forming columnar memory cells by removing the memory cell layer exposed at bottom of the second grooves. The thin film has higher etching rate than the interlayer insulating film, and is removed prior to portions of the memory cell layer adjoining the thin film. | 06-23-2011 |
20110147943 | WAFER LEVEL SURFACE PASSIVATION OF STACKABLE INTEGRATED CIRCUIT CHIPS - An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board). | 06-23-2011 |
20110156261 | INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING SAME - An integrated circuit package includes a first dielectric layer comprising a dielectric film having a first side and a second side, the first side having a plurality of contact locations and a plurality of non-contact locations. The package includes a plurality of components, each component having a first surface and a second surface, wherein the first surface of each of the plurality of components is affixed to a corresponding one of the plurality of contact locations of the dielectric film absent a layer of adhesive therebetween that is distinct from a material of the dielectric film. | 06-30-2011 |
20110156262 | SEMICONDUCTOR DEVICE WITH BURIED GATE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming landing plugs over a substrate, forming a trench by etching the substrate between the landing plugs, forming a buried gate to partially fill the trench, forming a gap-fill layer to gap-fill an upper side of the buried gate, forming protruding portions of the landing plugs, and trimming the protruding portions of the landing plugs. | 06-30-2011 |
20110156263 | SEMICONDUCTOR DEVICE - A semiconductor device may include, but is not limited to: a semiconductor substrate having an element formation region and a dicing region; an element layer over the element formation region and the dicing region; and a multi-layered wiring structure over the dicing region. The multi-layered wiring structure extends upwardly from the element layer. The multi-layered wiring structure has a groove penetrating the multi-layered wiring structure. | 06-30-2011 |
20110156264 | SEMICONDUCTOR ELEMENT BUILT-IN DEVICE - A semiconductor element built-in device includes: a first substrate having a first pad thereon; a semiconductor element on the first substrate; a second substrate having a second pad thereon and mounted on the first substrate via a solder terminal having a solder coated thereon; a resin layer provided between the first substrate and the second substrate such that the solder terminal and the semiconductor element are embedded in the resin layer; and a dam provided at least partially around at least one of the first and second pads, the dam being configured to restrain the solder flowing from the solder terminal. | 06-30-2011 |
20110156265 | ELECTRONIC COMPONENT AND METHOD OF MANUFACTURING THE SAME - An electronic component includes a substrate, a functional element formed on the substrate, a plurality of terminals including a first terminal electrode connected to the functional element and a second terminal electrode layered on the first terminal electrode, and a feed line, one end of which is electrically connected to the first terminal electrode and the other end of which reaches an edge of the substrate, wherein the feed line includes a first portion directly reaching the edge, and a second portion branching from the first portion and then reaching the edge. | 06-30-2011 |
20110156266 | METHODS FOR FORMING THROUGH-SUBSTRATE CONDUCTOR FILLED VIAS, AND ELECTRONIC ASSEMBLIES FORMED USING SUCH METHODS - Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming desired device regions with contacts on the front surface of an initially relatively thick wafer; etching via cavities partly through the wafer in the desired locations; filling the via cavities with a conductive material coupled to some device region contacts; mounting the wafer with its front side facing a support structure; thinning the wafer from the back side to expose internal ends of the conductive material filled vias; applying any desired back-side interconnect region coupled to the exposed ends of the filled vias; removing the support structure and separating the individual device or IC assemblies so as to be available for mounting on a further circuit board, tape or larger circuit. | 06-30-2011 |
20110163455 | Tunnel Junction Via - A method for forming a tunnel junction (TJ) circuit, the method includes forming a bottom wiring layer; forming a plurality of TJs contacting the bottom wiring layer; forming a plurality of tunnel junction vias (TJVs) simultaneously with the formation of the plurality of TJs, the TJVs contacting the bottom wiring layer; and forming a top wiring layer contacting the plurality of TJs and the plurality of TJVs. A circuit comprising a plurality of tunnel junctions (TJs) includes a bottom wiring layer contacting the plurality of TJs, the bottom wiring layer further contacting a plurality of tunnel junction vias (TJVs), wherein the plurality of TJs and the plurality of TJVs comprise the same material; and a top wiring layer contacting the plurality of TJs and the plurality of TJVs. | 07-07-2011 |
20110163456 | ELECTRONIC DEVICE SUBSTRATE, ELECTRONIC DEVICE, METHOD OF MANUFACTURING ELECTRONIC DEVICE SUBSTRATE, METHOD OF MANUFACTURING ELECTRONIC DEVICE, AND ELECTRONIC APPARATUS - An electronic device substrate includes a resin layer, a semiconductor layer disposed in a first region on the resin layer, a plurality of insulating films disposed in the first region on the resin layer, and connection terminals disposed in a second region on the resin layer, the connection terminals being used for connection to an external component to be connected. The connection terminals in plan view do not overlap with any insulating films composed of an inorganic material among the plurality of insulating films. | 07-07-2011 |
20110169169 | Method for providing and connecting two contact areas of a semiconductor component or a substrate, and a substrate having two such connected contact areas - A method for providing and connecting a first contact area to at least one second contact area on a substrate, in particular in the case of a semiconductor component, which includes providing at least one insulation layer on the substrate, forming an opening in the at least one insulation layer over at least one insulation trench of a first contact area, applying at least one metal layer to the insulation layer, forming the first and second contact areas in the at least one metal layer and at least one printed conductor between the two contact areas, and forming the insulation trench. | 07-14-2011 |
20110175229 | Semiconductor Device and Semiconductor Module Including the Same - Integrated circuit devices include a semiconductor substrate having a plurality of trench isolation regions therein that define respective semiconductor active regions therebetween. A trench is provided in the semiconductor substrate. The trench has first and second opposing sidewalls that define opposing interfaces with a first trench isolation region and a first active region, respectively. A first electrical interconnect is provided at a bottom of the trench. An electrically insulating capping pattern is provided, which extends between the first electrical interconnect and a top of the trench. An interconnect insulating layer is also provided, which lines the first and second sidewalls and bottom of the trench. The interconnect insulating layer extends between the first electrical interconnect and the first active region. A recess is provided in the first active region. The recess has a sidewall that defines an interface with the interconnect insulating layer. A second electrical interconnect is also provided, which extends on: (i) an upper surface of the first trench isolation region, (ii) the electrically insulating capping pattern; and (iii) the sidewall of the recess. The first and second electrical interconnects extend across the semiconductor substrate in first and second orthogonal directions, respectively. | 07-21-2011 |
20110175230 | Forming Compliant Contact Pads for Semiconductor Packages - In one embodiment, the present invention includes a semiconductor package having a substrate with a first surface to support a semiconductor die. A second surface of the substrate includes compliant conductive pads to provide electrical connections to the semiconductor die. In this way, improved connection between the semiconductor package and a socket is provided. Other embodiments are described and claimed. | 07-21-2011 |
20110175231 | Semiconductor Device Having Electrode and Manufacturing Method Thereof - A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film. | 07-21-2011 |
20110180930 | WIRING BOARD, MANUFACTURING METHOD OF THE WIRING BOARD, AND SEMICONDUCTOR PACKAGE - A wiring board includes a ceramic substrate including a plurality of stacked ceramic layers, an internal wiring, and an electrode electrically connected to the internal wiring, the electrode being exposed from a first surface of the ceramic substrate; and a silicon substrate including a wiring layer, the wiring layer including a wiring pattern and a via-fill, the wiring pattern being formed on a main surface of the silicon substrate, an end of the via-fill being electrically connected to the wiring pattern, another end of the via-fill being exposed from a rear surface of the silicon substrate positioned opposite to the main surface, wherein the another end of the via-fill is bonded to the electrode of the ceramic substrate via a metal layer. | 07-28-2011 |
20110180931 | ROBUST HIGH ASPECT RATIO SEMICONDUCTOR DEVICE - The invention relates to an semi-conductor device comprising a first surface and neighboring first and second electric elements arranged on the first surface, in which each of the first and second elements extends from the first surface in a first direction, the first element having a cross section substantially perpendicular to the first direction and a sidewall surface extending at least partially in the first direction, wherein the sidewall surface comprises a first section and a second section adjoining the first section along a line extending substantially parallel to the first direction, wherein the first and second sections are placed at an angle with respect to each other for providing an inner corner wherein the sidewall surface at the inner corner is, at least partially, arranged at a constant distance R from a facing part of the second element for providing a mechanical reinforcement structure at the inner corner. | 07-28-2011 |
20110187001 | SEMICONDUCTOR DEVICE INCLUDING PROCESS MONITORING PATTERN AND METHODS OF FABRICATING THE SAME - The semiconductor device includes a process monitoring pattern and an input/output (I/O) pad array area, the process monitoring pattern including a lower layer having a peripheral area surrounding a first internal area, the first internal area exposed by an internal open area, an external structure on the peripheral area of the lower layer, and a first dam disposed in the peripheral area spaced apart from the external structure by an external open area, the first dam defining the first internal area. The peripheral area overlaps the input/output (I/O) pad array area of the semiconductor device. | 08-04-2011 |
20110187002 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURE METHOD - A support substrate includes a first surface and a second surface located above the level of the first surface. Chips are mounted on the first surface. A first insulating film is disposed over each chip. First conductive plugs are connected to the chip extending through each first insulating film. Filler material made of resin filling a space between chips. Wirings are disposed over the first insulating film and the filler material for interconnecting different chips. The second surface, an upper surface of the first insulating film and an upper surface of the filler material are located at the same level. | 08-04-2011 |
20110187003 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device includes power semiconductor elements joined to wiring patterns of a circuit substrate, cylindrical external terminal communication sections, and wiring means for forming electrical connection between, for example, the power semiconductor elements and the cylindrical external terminal communication sections. The power semiconductor elements, the cylindrical external terminal communication sections, and the wiring means are sealed with transfer molding resin. The cylindrical external terminal communication sections are arranged on the wiring patterns so as to be substantially perpendicular to the wiring patterns, such that external terminals are insertable and connectable to the cylindrical external terminal communication sections, and such that a plurality of cylindrical external terminal communication sections among the cylindrical external terminal communication sections are arranged two-dimensionally on each of wiring patterns that act as main circuits. | 08-04-2011 |
20110193233 | INTERCONNECT PATTERN FOR TRANSCEIVER PACKAGE - In one embodiment, signaling and ground contacts are located in at least two parallel, rectilinear rows along at least one edge of an interconnect package such as a BGA package. In one row, each of a plurality of ground contacts is located between two pairs of contacts for receiving differential signals. In the second row, each of a plurality of ground contacts is located between two pairs of contacts for transmitting differential signals and the ground contacts in the second row are offset by one column from the ground contacts in the first row. As a result, the ratio of signaling pairs to ground contacts is 2:2. Additional pairs of rows may also be used. In other embodiments, signaling and ground contacts are located in three parallel, rectilinear rows along at least one edge of the package. In the first row, ground contacts alternate with contacts for receiving differential signals and in the second row ground contacts alternate with contacts for transmitting differential signals. The third row of contacts is located between the first and second rows and contains contacts for receiving differential signals that alternate with contacts for transmitting differential signals. The ground contacts in the second row are offset by one column from the ground contacts in the first row. In a second embodiment, the receiving contacts in the third row are in the same column as the receiving contacts in the first row; and the transmitting contacts in the third row are in the same column as the transmitting contacts in the second row. In a third embodiment, the contacts in the third row are offset by one column from the corresponding contacts in the first or second rows. Each pair of contacts for receiving differential signals is formed by a contact in the first row and an adjacent contact in the third row; and each pair of contacts for transmitting differential signals is formed by a contact in the second row and an adjacent contact in the third row. | 08-11-2011 |
20110193234 | Methods for Double-Patterning-Compliant Standard Cell Design - A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells. | 08-11-2011 |
20110193235 | 3DIC Architecture with Die Inside Interposer - A device is formed to include an interposer having a top surface, and a bump on the top surface of the interposer. An opening extends from the top surface into the interposer. A first die is bonded to the bump. A second die is located in the opening of the interposer and bonded to the first die. | 08-11-2011 |
20110193236 | SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHODS THEREOF - The present invention provides a method of manufacturing a gallium nitride (GaN) substrate on a heterogeneous substrate at low cost while realizing performance improvement and long operational lifespan of semiconductor devices, such as LEDs or laser diodes, which are manufactured using the GaN substrate. The semiconductor substrate includes a substrate, a first semiconductor layer arranged on the substrate, a mask arranged on a first region of the first semiconductor layer, a metallic material layer arranged on the first semiconductor layer and the mask, the metallic material layer being arranged in a direction intersecting the mask, a second semiconductor layer arranged on the first semiconductor layer and the metallic material layer, and a cavity in the first semiconductor layer and arranged under the metallic material layer. | 08-11-2011 |
20110193237 | METHOD FOR MAKING SEMICONDUCTOR PACKAGE - A method for assembling a semiconductor package includes a rapid cooling step after post mold curing of an encapsulation material. The rapid cooling step includes blowing chilled, compressed air over the package for about two minutes. The rapid cooling step does not require any clamping pressure be simultaneously applied to the package. The rapid cooling step reduces a temperature of the encapsulation material from a curing temperature to the cooled temperature within a maximum period of less than five minutes. By using rapid cooling, as opposed to cooling the package under a clamping pressure with ambient air, package warpage due to CTE mismatches is prevented. | 08-11-2011 |
20110193238 | SILICON WAFER FOR SEMICONDUCTOR WITH POWERSUPPLY SYSTEM ON THE BACKSIDE OF WAFER - A battery mounted semiconductor device is provided. A battery mounted semiconductor device comprises a semiconductor silicon wafer, an electric power supply formed on a backside of the semiconductor silicon wafer and a circuit pattern formed on a front side of the semiconductor silicon wafer. | 08-11-2011 |
20110193239 | SEMICONDUCTOR ELEMENT AND DISPLAY DEVICE PROVIDED WITH THE SAME - Provided is a semiconductor element in which decrease in reliability of wiring is suppressed. A driver IC ( | 08-11-2011 |
20110204523 | METHOD OF FABRICATING DUAL DAMASCENE STRUCTURES USING A MULTILEVEL MULTIPLE EXPOSURE PATTERNING SCHEME - A method for fabricating a dual damascene structure includes providing a first photoresist layer coated on an underlying dielectric stack, exposing said first photoresist layer to a first predetermined pattern of light, coating a second photoresist layer onto the pre-exposed first photoresist layer, exposing said second photoresist layer to a second predetermined pattern of light, optionally post-exposure baking the multi-tiered photoresist layers and developing said photoresist layers to form a multi-tiered dual damascene structure in the photoresist layers. | 08-25-2011 |
20110215477 | INTEGRATED CIRCUITS INCLUDING AIR GAPS AROUND INTERCONNECT STRUCTURES, AND FABRICATION METHODS THEREOF - An integrated circuit includes an interconnect structure at least partially disposed in at least one opening of a dielectric layer that is disposed over a substrate. At least one air gap is disposed between the dielectric layer and the interconnect structure. At least one first liner material is disposed under the at least one air gap. At least one second liner material is disposed around the interconnect structure. The at least one first liner material is disposed between the dielectric layer and at least one second liner material. | 09-08-2011 |
20110215478 | SEMICONDUCTOR ELEMENT-EMBEDDED WIRING SUBSTRATE - In a wiring substrate containing a semiconductor element, the wiring substrate includes a supporting substrate; a semiconductor element provided on the supporting substrate; a peripheral insulating layer covering at least an outer circumferential side surface of the semiconductor element; and upper surface-side wiring provided on the upper surface side of the wiring substrate. The semiconductor element includes a semiconductor substrate; a first wiring-structure layer including first wiring and a first insulating layer alternately formed on the semiconductor substrate; and a second wiring-structure layer including second wiring and a second insulating layer alternately formed on the first wiring-structure layer. The upper surface-side wiring includes fan-out wiring led out from immediately above the semiconductor element to a peripheral region external to an outer edge of the semiconductor element. The fan-out wiring is electrically connected to the first wiring through the second wiring. The second wiring is thicker than the first wiring but thinner than the upper surface-side wiring. The second insulating layer is formed of a resin material and is thicker than the first insulating layer. | 09-08-2011 |
20110215479 | Feature Patterning Methods and Structures Thereof - Methods of patterning features, methods of manufacturing semiconductor devices, and semiconductor devices are disclosed. In one embodiment, a method of patterning a feature includes forming a first portion of the feature in a first material layer. A second portion of the feature is formed in the first material layer, and a third portion of the feature is formed in a second material layer. | 09-08-2011 |
20110221065 | METHODS OF FORMING SEMICONDUCTOR CHIP UNDERFILL ANCHORS - Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in an insulating layer applied to a side of a semiconductor chip. The first opening does not extend through to the side. A second opening is formed in the insulating layer that exposes a portion of the side. | 09-15-2011 |
20110221066 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device according to an aspect of the present invention includes the steps of: forming a metallic film; forming plural connecting conductors including engaging portions on the metallic film; forming a first resin; curing a second resin; forming a wiring pattern; forming a second external electrode; and cutting the second resin. The step of forming the first resin is the step of inserting and bringing a projected first external electrode provided in each of plural semiconductor chips in and into contact with each of the engaging portions of the plural connecting conductors, and forming a first resin between the plural semiconductor chips and the metallic film. The step of curing the second resin is the step of covering the plural semiconductor chips with the second resin to cure the second resin. | 09-15-2011 |
20110221067 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A layout structure of a semiconductor integrated circuit is provided with which narrowing and breaking of metal interconnects near a cell boundary can be prevented without increasing the data amount and processing time for OPC. A cell A and a cell B are adjacent to each other along a cell boundary. The interconnect regions of metal interconnects from which to the cell boundary no other interconnect region exists are placed to be substantially axisymmetric with respect to the cell boundary, while sides of diffusion regions facing the cell boundary are asymmetric with respect to the cell boundary. | 09-15-2011 |
20110227229 | SEMICONDUCTOR WAFER PROCESSING - A method of processing a semiconductor wafer is provided which comprises treating a metallisation layer provided on a backside of the wafer to form a plurality of channels therein, such that at least some of the channels along substantially the length thereof extend through the thickness of the metallisation layer to the backside of the wafer, thereby exposing the material of the backside of the wafer. When the semiconductor wafer is separated into dies, each die is provided with a plurality of channels, which extend to an edge of the die. On attaching the die to a die attach flag by solder, the solder does not stick to the exposed material of the backside of the die, and channels are thereby formed in the solder. This allows venting of gases formed in the solder, and decreases void formation in the solder. | 09-22-2011 |
20110227230 | THROUGH-SILICON VIA FABRICATION WITH ETCH STOP FILM - For a semiconductor wafer substrate having an inter layer dielectric, a through-silicon via may be formed in the substrate by first depositing an etch stop film on top of the inter layer dielectric, followed by etching an opening through the etch stop film, the interlayer dielectric, and into the substrate. A dielectric liner is then deposited over the etch stop film and into the opening. For some embodiments, the dielectric liner may be etched away except for those portions adhering to the sidewall of the opening. Then a conductive material may be deposited into the opening and on the etch stop film. The excess conductive material may then be removed, and for some embodiments the etch stop film may also be removed. | 09-22-2011 |
20110227231 | SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING THE SAME - A semiconductor device may include plugs disposed in a zigzag pattern, interconnections electrically connected to the plugs and a protection pattern which is interposed between the plugs and the interconnections to selectively expose the plugs. The interconnections may include a connection portion which is in contact with plugs selectively exposed by the protection pattern. A method of manufacturing a semiconductor device includes, after forming a molding pattern and a mask pattern, selectively etching a protection layer using the mask pattern to form a protection pattern exposing a plug. | 09-22-2011 |
20110233785 | BACKSIDE DUMMY PLUGS FOR 3D INTEGRATION - A semiconductor structure includes backside dummy plugs embedded in a substrate. The backside dummy plugs can be a conductive structure that enhances vertical thermal conductivity of the semiconductor structure and provides electrical decoupling of signals in through-substrate vias (TSVs) in the substrate. The backside dummy plug can include a cavity to accommodate volume changes in other components in the substrate, thereby alleviating mechanical stress in the substrate during thermal cycling and operation of the semiconductor chip. The backside dummy plug including the cavity can be composed of an insulator material or a conductive material. The inventive structures can be employed to form three-dimensional structures having vertical chip integration, in which inter-wafer thermal conductivity is enhanced, cross-talk between signals through TSVs is reduced, and/or mechanical stress to the TSVs is reduced. | 09-29-2011 |
20110233786 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to an embodiment, a separation layer and a wiring layer having an organic insulating film formed of a resin material and a metal wiring are sequentially formed on a support substrate. Regions of the organic insulating film corresponding to dicing regions are removed. Plural semiconductor chips are mounted on the wiring layer. A sealing resin layer is formed on the separation layer. The sealing resin layer is formed to cover edge surfaces of the device forming regions. The support substrate is separated from a resin sealing body having the wiring layer, the plural semiconductor chips and the sealing resin layer. The resin sealing body is cut according to the dicing regions to cingulate a structure configuring a semiconductor device. | 09-29-2011 |
20110233787 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE - Disclosed is a semiconductor structure including a semiconductor substrate including an electronic circuit, which is provided in a predetermined region of the semiconductor substrate; a wall which is formed to encircle the predetermined region of the semiconductor substrate; a wiring provided in a region of the semiconductor substrate outside of the predetermined region of the semiconductor substrate; an external connection electrode provided on the wiring; a sealing resin which seals the wiring, the sealing resin being filled in the region of the semiconductor substrate outside of the wall; and a transparent resin to seal the predetermined region of the semiconductor substrate, the transparent resin being filled inside of the wall. | 09-29-2011 |
20110233788 | SEMICONDUCTOR DEVICE - A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card. | 09-29-2011 |
20110241214 | Virtually Substrate-less Composite Power Semiconductor Device and Method - A virtually substrate-less composite power semiconductor device (VSLCPSD) and method are disclosed. The VSLCPSD has a power semiconductor device (PSD), a front-face device carrier (FDC) made out of a carrier material and an intervening bonding layer (IBL). Both carrier and IBL material can be conductive or non-conductive. The PSD has back substrate portion, front semiconductor device portion with patterned front-face device metallization pads and a virtually diminishing thickness T | 10-06-2011 |
20110241215 | EMBEDDED SEMICONDUCTIVE CHIPS IN RECONSTITUTED WAFERS, AND SYSTEMS CONTAINING SAME - A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer. | 10-06-2011 |
20110241216 | Semiconductor device - A semiconductor device includes a substrate over which a circuit is formed, a multi-layer wiring layer having a plurality of wiring layers formed over the substrate and a pad formed in a predetermined location of an uppermost layer of the wiring layers, a new pad provided in an appropriate location over the multi-layer wiring layer, and a redistribution layer provided with a redistribution line coupling the new pad and the pad. In the semiconductor device: the multi-layer wiring layer includes a signal line for transmitting an electric signal to the circuit and a ground line provided in a wiring layer between the redistribution line or the new pad and the circuit; the ground line is formed to correspond to a location where the new pad is assumed to be located and a route along which the redistribution line is assumed to be formed; and the redistribution line is formed along at least a portion of the ground line. | 10-06-2011 |
20110248404 | Dummy Pattern in Wafer Backside Routing - A device includes a semiconductor substrate including a front side and a backside. A through-substrate via (TSV) penetrates the semiconductor substrate. A dummy metal line is formed on the backside of the semiconductor substrate, and may be connected to the dummy TSV. | 10-13-2011 |
20110248405 | Selective Patterning for Low Cost through Vias - A block layer deposited on a substrate before deposition of metal lines and etching of a through via enables low cost fabrication of through vias in a substrate using isotropic etching processes. For example, wet etching of a glass substrate may be used to fabricate through glass vias without undercut from the wet etching shorting metal lines on the glass substrate. The block layer prevents contact between a conductive layer lining the through via with more than one metal line on the substrate. The manufacturing process allows stacking of devices on substrates such as glass substrates and connecting the devices with through vias. | 10-13-2011 |
20110248406 | Method of Manufacturing Semiconductor Device - In connection with a semiconductor device in which a conductive member is coupled to the surface of a bonding pad exposed from an opening formed in a passivation film, there is provided a technique able to suppress the occurrence of a crack in the passivation film. A second planar distance between a first end of an electrode layer and a first end of a pad is greater than a first planar distance between the first end of the electrode layer and a first end of an opening. Since the second planar distance between the first end of the electrode layer and the first end of the pad is long, even when a coupled position of wire is deviated to the first end side of the electrode layer, stress caused by coupling of the wire to a stepped portion of the electrode layer can be prevented from being transmitted to the first end portion of the pad. | 10-13-2011 |
20110248407 | Process For Making a Semiconductor System - Multiple devices, including a first device and a second device, have operational circuitry and opposing first and second surfaces. First and second electrical contacts are formed at the first surface, while a third electrical contact is formed at the second surface opposite the first electrical contact. The first electrical contact is electrically connected to the operational circuitry, and the second electrical contact is electrically connected to the third electrical contact. The first device and the second device are subsequently stacked such that the first surface of the second device is located adjacent the second surface of the first device such that the first electrical contact of the second device is aligned with the third electrical contact of the first device. The first electrical contact of the second device is electrically connected to the third electrical contact of the first device. | 10-13-2011 |
20110254166 | Chip Area Optimized Pads - An optimized semiconductor chip pad configuration. The pad includes a pad circuit area Ap, a first dimension x and a second dimension y, in a chip having N number of pins on each side. The pins include a longitudinal axis, and the chip includes a chip core of length Lc. The method includes determining the first dimension x by dividing the length Lc by the N, determining the second dimension y by dividing the pad circuit area Ap by a result of a division of the length Lc by the N, and creating a semiconductor area pad that includes pins with the longitudinal axis positioned parallel to the chip core. A stack of circuits is designed in the chip to fit in the pad based on the first dimension x and the second dimension y. | 10-20-2011 |
20110254167 | STACK PACKAGE HAVING FLEXIBLE CONDUCTORS - A stack package includes a first package having a first semiconductor chip and a first encapsulation member which seals the first semiconductor chip. A second package is stacked on the first package, and includes a second semiconductor chip and a second encapsulation member which seals the second semiconductor chip. Flexible conductors are disposed within the first encapsulation member of the first package in such a way as to electrically connect the first package and the second package. | 10-20-2011 |
20110260327 | CHIP PACKAGE - A quad flat non-leaded package including a first patterned conductive layer, a second patterned conductive layer, a chip, bonding wires and a molding compound is provided. The first patterned conductive layer defines a first space, and the second patterned conductive layer defines a second space, wherein the first space overlaps the second space and a part of the second patterned conductive layer surrounding the second space. The chip is disposed on the second patterned conductive layer. The bonding wires are connected between the chip and the second patterned conductive layer. The molding compound encapsulates the second patterned conductive layers, the chip and the bonding wires. In addition, a method of manufacturing a quad flat non-leaded package is also provided. | 10-27-2011 |
20110260328 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING USING THE SAME - A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a plurality of bit lines having a uniform width on a semiconductor substrate, an active region obliquely arranged to have a predetermined angle with respect to the bit lines, a spacer arranged around the bit lines connected to a center part of the active region. A contact pad is connected to a lower part of the bit lines. The spacer is formed not only at an upper part of sidewalls of the contact pad but also at sidewalls of the bit lines. As a result, a CD of the bit line contact increases, so that a bit line contact patterning margin also increases. A bit line pattern having a uniform width is formed so that a patterning margin increases. A storage electrode contact self-alignment margin increases so that a line-type storage electrode contact margin increases. | 10-27-2011 |
20110266682 | MICROELECTRONIC STRUCTURE INCLUDING AIR GAP - A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure. | 11-03-2011 |
20110266683 | Stackable Power MOSFET, Power MOSFET Stack, and Process of Manufacture - A thin and stackable power MOSFET (SP-MOSFET) and method are proposed. The SVP-MOSFET includes semiconductor substrate with bottom drain metal layer. Formed atop the semiconductor substrate are trenched gate regions and source-body regions. A patterned gate metal layer and source-body metal layer respectively contact trenched gate regions and source-body regions. At least one of through substrate drain via (TSDV), through substrate gate via (TSGV), through substrate source via (TSSV) is provided. The TSDV, formed through semiconductor substrate and in contact with drain metal layer, has top drain contacting pad and bottom drain contacting pad for making top and bottom contacts thereto. Similarly the TSGV, formed through semiconductor substrate and in contact with gate metal layer, has top gate contacting pad and bottom gate contacting pad. Likewise the TSSV, formed through semiconductor substrate and in contact with source-body metal layer, has top source contacting pad and bottom source contacting pad. | 11-03-2011 |
20110266684 | Selective Die Electrical Insulation By Additive Process - Additive processes are employed for electrically insulating selected surface regions on a stack of die; and methods for electrically interconnecting die in a stack of die, include additive processes for electrically insulating selected surface regions of the die. Regions that are not insulated according to the invention are available for electrical connection using electrically conductive material applied in flowable form to make electrically conductive traces. | 11-03-2011 |
20110266685 | Semiconductor Device Comprising Sophisticated Conductive Elements in a Dielectric Material System Formed by Using a Barrier Layer - An efficient patterning strategy may be applied when etching through a dielectric material system on the basis of two different etch chemistries. To this end, a conductive etch stop or barrier material may be formed in the opening prior to etching through the further dielectric layer of the material system, thereby substantially preserving the initial critical dimensions and avoiding etch damage. Thus, superior contact openings, via openings and the like may be formed on the basis of well-established etch chemistries. | 11-03-2011 |
20110266686 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate having a conductor; a semiconductor chip disposed on the substrate and electrically connected to the conductor; a tubular electrode having one end electrically connected to the conductor; and a sealing resin sealing the substrate, the semiconductor chip and the electrode. The electrode is configured to be extendable and contractible in the stacking direction in which the substrate and the semiconductor chip are stacked in the state before sealing of the sealing resin. The edge of the other end of the electrode is exposed from the sealing resin. The electrode has a hollow space opened at the edge of the other end. Therefore, a semiconductor device reduced in size and a method of manufacturing this semiconductor device can be provided. | 11-03-2011 |
20110266687 | ELECTRONIC ELEMENTS AND DEVICES WITH TRENCH UNDER BOND PAD FEATURE - Electronic elements having an active device region and bonding pad (BP) region on a common substrate desirably include a dielectric region underlying the BP to reduce the parasitic impedance of the BP and its interconnection as the electronic elements are scaled to higher power and/or operating frequency. Mechanical stress created by plain (e.g., oxide only) dielectric regions can adversely affect performance, manufacturing yield, pad-to-device proximity and occupied area. This can be avoided by providing a composite dielectric region having electrically isolated inclusions of a thermal expansion coefficient (TEC) less than that of the dielectric material in which they are embedded and/or closer to the substrate TEC. For silicon substrates, poly or amorphous silicon is suitable for the inclusions and silicon oxide for the dielectric material. The inclusions preferably have a blade-like shape separated by and enclosed within the dielectric material. | 11-03-2011 |
20110266688 | PLANARIZED PASSIVATION LAYER FOR SEMICONDUCTOR DEVICES - A semiconductor device includes a substrate having a dielectric layer and a device layer on the substrate. The device layer has an opening. First and second sublayers are disposed on the device layer and line the opening. The second sublayer serves as a stop layer for planarization to provide a substantially planarized top surface for the semiconductor device. | 11-03-2011 |
20110266689 | Methods Of Forming A Plurality Of Conductive Lines In The Fabrication Of Integrated Circuitry, Methods Of Forming An Array Of Conductive Lines, And Integrated Circuitry - A method of forming a pair of conductive lines in the fabrication of integrated circuitry includes forming a trench into a damascene material received over a substrate. Conductive material is deposited over the damascene material and to within the trench to overfill the trench. The conductive material is removed back at least to the damascene material to leave at least some of the conductive material remaining in the trench. Etching is conducted longitudinally through the conductive material within the trench to form first and second conductive lines within the trench which are mirror images of one another in lateral cross section along at least a majority of length of the first and second conductive lines. Other implementations are contemplated. | 11-03-2011 |
20110266690 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, CIRCUIT SUBSTRATE, AND ELECTRONIC APPARATUS - A semiconductor device includes: a semiconductor substrate including a first face and a second face on a side opposite to the first face; an external connection terminal formed on the first face of the semiconductor substrate; a first electrode formed on the first face of the semiconductor substrate and electrically connected to the external connection terminal; an electronic element formed on or above the second face of the semiconductor substrate; a second electrode electrically connected to the electronic element and having a top face and a rear face; a groove portion formed on the second face of the semiconductor substrate and having a bottom face including at least part of the rear face of the second electrode; and a conductive portion formed in the groove portion and electrically connected to the rear face of the second electrode. | 11-03-2011 |
20110272814 | METHOD FOR ATTACHING WIDE BUS MEMORY AND SERIAL MEMORY TO A PROCESSOR WITHIN A CHIP SCALE PACKAGE FOOTPRINT - A semiconductor device including a first memory die having a first memory type, a second memory die having a second memory type different from the first memory type, and a logic die such as a microprocessor. The first memory die can be electrically connected to the logic die using a first type of electrical connection preferred for the first memory type. The second memory die can be electrically connected to the logic die using a second type of electrical connection different from the first type of electrical connection which is preferred for the second memory type. Other devices can include dies all of the same type, or two or more dies of a first type and two or more dies of a second type different from the first type. | 11-10-2011 |
20110272815 | SEMICONDUCTOR DEVICE AND LAYOUT DESIGN METHOD FOR THE SAME - A semiconductor device includes: a plurality of line features including at least one real feature which includes a gate electrode portion, and at least one dummy feature. Two of multiple ones of the dummy feature, and at least one of the line features interposed between the two dummy features and including the at least one real feature form parallel running line features which are evenly spaced. The parallel running line features have an identical width, and line end portions of the parallel running line features are substantially flush. Line end portion uniformization dummy features are formed on extensions of the line end portions of the parallel running line features. The line end portion uniformization dummy features include a plurality of linear features each having a same width as each of the line features and spaced at intervals equal to an interval between each adjacent pair of the line features. | 11-10-2011 |
20110272816 | WIRING OVER SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHODS FOR MANUFACTURING THEREOF - A wiring over a substrate capable of reducing particles between wirings and a method for manufacturing the wiring is disclosed. A wiring over a substrate capable of preventing short-circuiting between wirings due to big difference in projection and depression between wirings and a method for manufacturing the wiring is also disclosed. Further, a wiring over a substrate capable of preventing cracks in the insulating layer due to stress at the edge of a wiring or particles and a method for manufacturing the wiring is also disclosed. According to the present invention, a method for manufacturing a wiring over a substrate is provided that comprises the steps of: forming a first conductive layer over an insulating surface; forming a first mask pattern over the first conductive layer; forming a second mask pattern by etching the first mask pattern under a first condition, simultaneously, forming a second conductive layer having a side having an angle of inclination cross-sectionally by etching the first conductive layer; and forming a third conductive layer and a third mask pattern by etching the second conductive layer and the second mask pattern under a second condition; wherein a selective ratio under the first condition of the first conductive layer to the first mask pattern is in a range of 0.25 to 4, and a selective ratio under the second condition of the second conductive layer to the second mask pattern is larger than that under the first condition. | 11-10-2011 |
20110272817 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - According to an aspect of the present invention, there is provided a semiconductor device, including a semiconductor chip including a first electrode and a second electrode of a semiconductor element, the first electrode and the second electrode being configured on a first surface and a second surface of the semiconductor chip, an encapsulating material encapsulating the semiconductor chip, the surface portion being other than regions, each of the regions connecting with the first second electrodes, each of inner electrodes being connected with the first or the second electrodes, a thickness of the inner electrode from the first surface or the second surface being the same thickness as the encapsulating material from the first surface or the second surface, respectively, outer electrodes, each of the outer electrodes being formed on the encapsulating material and connected with the inner electrode, a width of the outer electrode being at least wider than a width of the semiconductor chip, and outer plating materials, each of the outer plating materials covering five surfaces of the outer electrode other than one surface of the outer electrode being connected with the inner electrode. | 11-10-2011 |
20110278728 | Chip Packaging - An electronic device package comprising: a block of insulating material; an electronic device housed within the insulating material and having a set of contact pads thereon; and a set of electrically conductive contact members at least partially housed within the insulating material, each contact member extending between a respective external contact point at which it is exposed at the surface of the block and an internal contact point from which it is electrically coupled to a respective contact pad on the electronic device, each internal contact point being outside the footprint of the electronic device, the set of contact members including: at least one contact member of a first type whose external contact point is located at least partially within the footprint of the electronic device; and at least one contact member of a second type that is wholly outside the footprint of the device. | 11-17-2011 |
20110278729 | Extendable Network Structure - Disclosed herein is an extendable network structure, which includes a first device portion, a second device portion and at least three connectors. The three connectors are connected to the first device portion. The second device portion is electrically connected to the first device portion through one of the three connectors. The first and second device portions respectively have a first and a second center. Each of the connectors may be extendable from an initial state to an extended state, such that a first distance between the first and second centers in the extended state is at least 1.1 fold of a second distance between the first and second centers in the initial state. | 11-17-2011 |
20110278730 | Semiconductor Devices and Structures Thereof - A structure having air gaps between interconnects is disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region. | 11-17-2011 |
20110285023 | Substrate Interconnections having Different Sizes - A bump structure that may be used to interconnect one substrate to another substrate is provided. A conductive pillar is formed on a first substrate such that the conductive pillar has a width different than a contact surface on a second substrate. In an embodiment the conductive pillar of the first substrate has a trapezoidal shape or a shape having tapered sidewalls, thereby providing a conductive pillar having base portion wider than a tip portion. The substrates may each be an integrated circuit die, an interposer, a printed circuit board, a high-density interconnect, or the like. | 11-24-2011 |
20110285024 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor structure having a cap layer formed over a metalized dielectric layer is formed by depositing manganese on the surface of the metalized dielectric layer. The deposited manganese serves as a first cap layer to remove oxidation on the surface of the metalized dielectric layer. The presence of oxidation on the surface of the metalized dielectric layer can be delirious for performance of a device constructed out of the semiconductor structure. A second cap layer is then formed by depositing silicon carbide or nitrogen enriched silicon carbide over the first cap layer. | 11-24-2011 |
20110285025 | Wafer Level Chip Scale Package Method Using Clip Array - A method for wafer level chip scale package comprises providing a wafer with semiconductor chips formed thereon, forming a groove alongside each chip, providing a wafer size clip array with a plurality of clip contact areas each extending to a down set connecting bar, connecting the plurality of clip contact areas to a plurality of the electrodes disposed on a top surface of the chips with down set connecting bars disposed inside the grooves, encapsulating top of wafer in molding compound, thinning the bottom portion of the wafer and dicing the thin wafer into single chip packages. The chip has source and gate electrodes on a top surface connected to a first and second clip contact areas extending to a first a second down set connecting bars respectively, with the bottom surfaces of the down set connecting bars substantially coplanar to a drain electrode located at the chip bottom surface. | 11-24-2011 |
20110285026 | Process For Improving Package Warpage and Connection Reliability Through Use Of A Backside Mold Configuration (BSMC) - A backside mold configuration (BSMC) process for manufacturing packaged integrated circuits includes applying a mold compound to a side of a packaging substrate opposite an attached die. The mold compound is deposited on a dielectric (such as photo resist). The mold compound and dielectric are patterned after coupling a die to the packaging substrate to expose a contact pad of the packaging substrate. After patterning the mold compound and dielectric, a packaging connection is coupled to contact pads through the mold compound and dielectric. The mold compound surrounding the packaging connection reduces warpage of the packaging substrate during processing. Additionally, patterning the dielectric after attaching the die improves reliability of the packaging connection. | 11-24-2011 |
20110291283 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH EMBEDDED DIE SUPERSTRUCTURE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit package system includes: providing a through-silicon-via die having conductive vias therethrough; forming a first redistribution layer on a bottom of the through-silicon-via die coupled to the conductive vias; forming a second redistribution layer on the top of the through-silicon-via die coupled to the conductive vias; fabricating an embedded die superstructure on the second redistribution layer including: mounting an integrated circuit die to the second redistribution layer, forming a core material layer on the second redistribution layer to be coplanar with the integrated circuit die, forming a first build-up layer, having contact links coupled to the integrated circuit die, on the core material layer, and coupling component interconnect pads to the contact links; and forming system interconnects on the first redistribution layer for coupling the through-silicon-via die, the integrated circuit die, the component interconnect pads, or a combination thereof. | 12-01-2011 |
20110291284 | INTERCONNECT STRUCTURE WITH AN OXYGEN-DOPED SiC ANTIREFLECTIVE COATING AND METHOD OF FABRICATION - An interconnect structure is provided that includes at least one patterned and cured photo-patternable low k material located on a surface of a patterned and cured oxygen-doped SiC antireflective coating (ARC). A conductively filled region is located within the at least one patterned and cured photo-patternable low k material and the patterned and cured oxygen-doped SiC ARC. The oxygen-doped SiC ARC, which is a thin layer (i.e., less than 400 angstroms), does not produce standing waves that may degrade the diffusion barrier and the electrically conductive feature that are embedded within the patterned and cured photo-patternable low k dielectric material and, as such, structural integrity is maintained. Furthermore, since a thin oxygen-doped SiC ARC is employed, the plasma etch process time used to open the material stack of the ARC/dielectric cap can be reduced, thus reducing potential plasma damage to the patterned and cured photo-patternable low k material. Also, the oxygen-doped SiC ARC can withstand current BEOL processing conditions. | 12-01-2011 |
20110291285 | Semiconductor Device Comprising a Die Seal with Graded Pattern Density - A die seal of a semiconductor device may be provided with a varying pattern density such that a gradient between the die region and the die seal may be reduced. Consequently, for a given width of the die seal, a required mechanical stability may be achieved, while at the same time differences in topography between the die region and the die seal may be reduced, thereby contributing to superior process conditions for sophisticated lithography processes. | 12-01-2011 |
20110291286 | ELECTRONIC DEVICE AND METHOD FOR CONNECTING A DIE TO A CONNECTION TERMINAL - An electronic device including a die-pad area, a die fixed to the die-pad area, a connection terminal, and a ribbon of conductive material. The ribbon is electrically connected to the die and to the connection terminal, and has a prevalent dimension along a first axis, a width, measured along a second axis, which is transverse to the first axis, and a thickness, which is negligible with respect to the width; the ribbon moreover has a cross section that defines a concave geometrical shape. | 12-01-2011 |
20110298137 | Semiconductor Device and Method of Forming Sacrificial Adhesive Over Contact Pads of Semiconductor Die - A semiconductor wafer contains a plurality of semiconductor die each having a plurality of contact pads. A sacrificial adhesive is deposited over the contact pads. Alternatively, the sacrificial adhesive is deposited over the carrier. An underfill material can be formed between the contact pads. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier such that the sacrificial adhesive is disposed between the contact pads and temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and sacrificial adhesive is removed to leave a via over the contact pads. An interconnect structure is formed over the encapsulant. The interconnect structure includes a conductive layer which extends into the via for electrical connection to the contact pads. The semiconductor die is offset from the interconnect structure by a height of the sacrificial adhesive. | 12-08-2011 |
20110298138 | STANDARD CELL AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire. | 12-08-2011 |
20110304052 | POWER GRID OPTIMIZATION - A global power distribution network in an integrated circuit comprising a first layer of conductive material and a second layer of conductive material. The first layer of conductive material may be (i) coupled to one or more power supplies and (ii) configured to form a plurality of first rails of a mesh. The first rails may (a) supply power to one or more components of a core logic of the integrated circuit, (b) be aligned with a first axis of the integrated circuit, and (c) have one or more parameters configured such that the mesh has a uniform voltage gradient from a perimeter of the integrated circuit to a center of the integrated circuit along the first axis. The second layer of conductive material may be (i) coupled to the one or more power supplies and (ii) configured to form a plurality of second rails of the mesh. The second rails may (a) supply power to one or more components of the core logic, (b) be aligned with a second axis of the integrated circuit, and (c) have one or more parameters configured such that the mesh comprises a uniform voltage gradient from the perimeter of the integrated circuit to the center of the integrated circuit along the second axis. | 12-15-2011 |
20110309513 | BURIED THERMALLY CONDUCTIVE LAYERS FOR HEAT EXTRACTION AND SHIELDING - An embodiment is a method and apparatus for heat extraction and shielding in multi-block semiconductor devices. A plurality of blocks stacked on each other is interconnected by vertical vias filled with thermally conducting material and separated by buried thermally conductive layers. A thermally conductive layer is bonded to bottom or top of the plurality of blocks as a ground plane or a heat extraction layer. The thermally conductive layer has a high thermal conductivity. | 12-22-2011 |
20110309514 | PACKAGED SEMICONDUCTOR DEVICE HAVING IMPROVED LOCKING PROPERTIES - The invention relates to a method of manufacturing a semiconductor device ( | 12-22-2011 |
20110309515 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR DESIGNING THE SAME - A semiconductor integrated circuit device includes a semiconductor chip including input/output cells, pads formed on a surface of the semiconductor chip, and interconnects formed on the surface of the semiconductor chip to electrically connect at least some of the plurality of input/output cells and at least some of the plurality of pads. A first plurality of the pads located in a center portion of the semiconductor chip are arranged in a rectangular dot grid pattern, and a second plurality of the pads located in at least one of four corner portions of the semiconductor chip are arranged in a staggered dot pattern. | 12-22-2011 |
20110316162 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TRENCHES AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate with a material layer including grooves in a fillet region that are substantially parallel and adjacent an integrated circuit; and forming a resin between the substrate and the integrated circuit that contacts a trench trace exposed by the grooves. | 12-29-2011 |
20110316163 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit device; forming package interconnects adjacent the integrated circuit device, the package interconnects having an internal interconnect side with a lock structure; applying an encapsulation over the integrated circuit device and the package interconnects, the lock structure conformally filled with the encapsulation; and forming a base cavity with sides formed by the encapsulation and an external interconnect side of each of an adjacent pair of package interconnects facing one another, the base cavity having a cross-sectional length at least two times a cross-sectional width. | 12-29-2011 |
20110316164 | CORRUGATED DIE EDGE FOR STACKED DIE SEMICONDUCTOR PACKAGE - A semiconductor die and semiconductor package formed therefrom, and methods of fabricating the semiconductor die and package, are disclosed. The semiconductor die includes an edge formed with a plurality of corrugations defined by protrusions between recesses. Bond pads may be formed on the protrusions. The semiconductor die formed in this manner may be stacked in the semiconductor package in staggered pairs so that the die bond pads on the protrusions of a lower die are positioned in the recesses of the upper die. | 12-29-2011 |
20110316165 | Semiconductor Device and Method of Fabricating the Same - A semiconductor device includes first, second, and third conductive lines, each with a respective line portion formed over a substrate and extending in a first direction and with a respective branch portion extending from an end of the respective line portion in a direction different from the first direction. The branch portion of a middle conductive line is disposed between and shorter than the respective branch portions of the outer conductive lines such that contact pads may be formed integral with such branch portions of the conductive lines. | 12-29-2011 |
20120001339 | BUMPLESS BUILD-UP LAYER PACKAGE DESIGN WITH AN INTERPOSER - The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein an interposer, such as a through-silicon via interposer, may be used in a bumpless build-up layer package to facilitate stacked microelectronic components. | 01-05-2012 |
20120001340 | METHOD AND SYSTEM FOR ALIGNMENT OF INTEGRATED CIRCUITS - Alignment for electronic devices using a template having holes to align the protrusions of one or more integrated circuits. There are least one integrated circuit having a plurality of protrusions arranged in a protrusion pattern. There is a template with holes disposed on the integrated circuit, wherein at least some of the holes are arranged in the protrusion pattern and the holes are disposed onto the protrusions such that a portion of the protrusions extends from the template. There is an interconnect disposed on the template, wherein the interconnect has a plurality of electric contacts, wherein at least some of the electrical contacts are arranged in the protrusion pattern, and wherein at least some of the electrical contacts are electrically coupled to at least some of the protrusions. | 01-05-2012 |
20120001341 | SEMICONDUCTOR DEVICE - The semiconductor device has a unit stack body including a plurality of units stacked on one another. Each unit includes a power terminal constituted of a lead part and a connection part. The connection part is formed with a projection and a recess. When the units are stacked on one another, the projection of one unit is fitted to the recess of the adjacent unit, so that the power terminals of the respective unit are connected to one another. | 01-05-2012 |
20120001342 | SEMICONDUCTOR DEVICE - The reliability of a semiconductor device is improved. | 01-05-2012 |
20120007248 | MULTI-CHIP PACKAGE INCLUDING CHIP ADDRESS CIRCUIT - A multi-chip package according to an aspect of this disclosure includes a plurality of multi-chips. Each of the multi-chips includes a lead configured to receive an external power supply voltage, and a pad circuit configured to reset an internal node to the level of a ground voltage and to generate chip address information by controlling the potential of the internal node based on the state of a connection between the pad circuit and the lead. | 01-12-2012 |
20120013012 | METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES, AND SEMICONDUCTOR STRUCTURES FORMED BY SUCH METHODS - Methods of forming bonded semiconductor structures include temporarily, directly bonding together semiconductor structures, thinning at least one of the semiconductor structures, and subsequently permanently bonding the thinned semiconductor structure to another semiconductor structure. The temporary, direct bond may be established without the use of an adhesive. Bonded semiconductor structures are fabricated in accordance with such methods. | 01-19-2012 |
20120013013 | TEMPORARY SEMICONDUCTOR STRUCTURE BONDING METHODS AND RELATED BONDED SEMICONDUCTOR STRUCTURES - Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods. | 01-19-2012 |
20120013014 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - The semiconductor device comprises a metal line configured to be buried in an interlayer insulation layer formed over a semiconductor substrate, a first insulating pattern configured to be formed over the interlayer insulating layer and the first metal line so that the first metal line is exposed, a second insulating pattern configured to be buried between the first insulating patterns so that the first metal line is exposed, and a third insulating pattern configured to be formed over the first insulating pattern and the second insulating pattern so that the first metal line is exposed, thereby reducing the resistance of a contact plug, such that it operates at high speed and requires low power consumption. | 01-19-2012 |
20120013015 | Interconnection architecture for semiconductor device - An interconnection architecture, for a semiconductor device (having regions arranged to include at least an inner region, an intermediate region located at least aside the inner region, and an outer region located at least on a side of the intermediate region opposite to the inner region, includes: one or more pairs of first and second signal lines, each pair extending from the inner region into the intermediate region; first portions and second portions of the first and second signal lines being parallel, respectively, the first portions being located in the inner region; the first and second portion of at least the first signal line not being collinear; and an intra-pair line-spacing, d(i), for each pair including the following magnitudes, d | 01-19-2012 |
20120013016 | FLEXIBLE SEMICONDUCTOR PACKAGE APPARATUS HAVING A RESPONSIVE BENDABLE CONDUCTIVE WIRE MEMBER AND A MANUFACTURING THE SAME - A flexible semiconductor package apparatus having a responsive bendable conductive wire member is presented. The apparatus includes a flexible substrate, semiconductor chips, and conductive wires. The semiconductor chips are disposed on the flexible substrate and spaced apart from each other on the flexible substrate. Each semiconductor chip has bonding pads. The conductive wires are electrically connected to the bonding pads of the semiconductor chip. Each conductive wire has at least one elastic portion. One preferred configuration is that part of the conductive wire is wound to form a coil spring shape so that the coil spring shape of the conductive wire aid in preventing the conductive wire from being separated from the corresponding bonding pad of the semiconductor chip when the flexible substrate on which the semiconductor chips are mounted are bent, expanded or twisted. | 01-19-2012 |
20120018891 | METHODS TO FORM SELF-ALIGNED PERMANENT ON-CHIP INTERCONNECT STRUCTURES - Methods of fabricating a self-aligned permanent on-chip interconnect structure are provided. In one embodiment, the method includes forming a patterned photoresist having at least one opening on a surface of a substrate. A dielectric sidewall structure is then formed on each sidewall of the patterned photoresist and within the at least one opening. A narrowed width opening is present between neighboring dielectric sidewall structures. The patterned photoresist is then removed and thereafter each dielectric sidewall structure is converted into a permanent patterned dielectric structure which is self-aligned and double patterned. At least an electrically conductive material is formed within the narrowed width openings. | 01-26-2012 |
20120018892 | SEMICONDUCTOR DEVICE WITH INDUCTOR AND FLIP-CHIP - Semiconductor devices comprising a flip-chip having vias to connect front and back surfaces and a bondwire connected to the via or the back surface. | 01-26-2012 |
20120018893 | METHODS OF FORMING SEMICONDUCTOR ELEMENTS USING MICRO-ABRASIVE PARTICLE STREAM - A method of fabricating a microelectronic unit includes providing a semiconductor element having a front surface and a rear surface remote from the front surface, forming at least one first opening extending from the rear surface partially through the semiconductor element towards the front surface by directing a jet of fine abrasive particles towards the semiconductor element, and forming at least one conductive contact and at least one conductive interconnect coupled thereto. The semiconductor element can include a plurality of active semiconductor devices therein. The semiconductor element can include a plurality of conductive pads exposed at the front surface. Each conductive interconnect can extend within one or more of the first openings and can be coupled directly or indirectly to at least one of the conductive pads. Each of the conductive contacts can be exposed at the rear surface of the semiconductor element for electrical connection to an external device. | 01-26-2012 |
20120018894 | NON-LITHOGRAPHIC FORMATION OF THREE-DIMENSIONAL CONDUCTIVE ELEMENTS - A method of forming a conductive element on a substrate and the resulting assembly are provided. The method includes forming a groove in a sacrificial layer overlying a dielectric region disposed on a substrate. The groove preferably extends along a sloped surface of the substrate. The sacrificial layer is preferably removed by a non-photolithographic method, such as ablating with a laser, mechanical milling, or sandblasting. A conductive element is formed in the groove. The grooves may be formed. The grooves and conductive elements may be formed along any surface of the substrate, including within trenches and vias formed therein, and may connect to conductive pads on the front and/or rear surface of the substrate. The conductive elements are preferably formed by plating and may or may not conform to the surface of the substrate. | 01-26-2012 |
20120018895 | ACTIVE CHIP ON CARRIER OR LAMINATED CHIP HAVING MICROELECTRONIC ELEMENT EMBEDDED THEREIN - A structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within the cavity. The first chip may have vias extending from the cavity to the front surface and via conductors within these vias serving to connect the additional microelectronic element to the active elements of the first chip. The structure may have a volume comparable to that of the first chip alone and yet provide the functionality of a multi-chip assembly. A composite chip incorporating a body and a layer of semiconductor material mounted on a front surface of the body similarly may have a cavity extending into the body from the rear surface and may have an additional microelectronic element mounted in such cavity. | 01-26-2012 |
20120018896 | SEMICONDUCTOR DEVICE - The semiconductor device according to the present invention includes a semiconductor chip, an island having an upper surface to which the semiconductor chip is bonded, a lead arranged around the island, a bonding wire extended between the surface of the semiconductor chip and the upper surface of the lead, and a resin package collectively sealing the semiconductor chip, the island, the lead and the bonding wire, while the lower surface of the island and the lower surface of the lead are exposed on the rear surface of the resin package, and the lead is provided with a recess concaved from the lower surface side and opened on a side surface thereof. | 01-26-2012 |
20120025387 | CHIP PACKAGE AND FABRICATING METHOD THEREOF - A chip package and a fabrication method thereof are provided. The chip package includes a substrate and a chip disposed over the substrate. A solder layer is disposed between the chip and the substrate. A conductive pad is disposed between the solder layer and the substrate, wherein the conductive pad includes a first portion disposed under the solder layer, a second portion disposed away from the first portion and a connective portion disposed between the first portion and the second portion. The connective portion has a width which is narrower than a width of the first portion along a first direction perpendicular to a second direction extending from the first portion to the connective portion. | 02-02-2012 |
20120025388 | THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURE HAVING IMPROVED POWER AND THERMAL MANAGEMENT - A three dimensional (3D) integrated circuit (IC) structure having improved power and thermal management is described. The 3D IC structure includes at least first and second dies. Each of the first and second dies has at least one power through silicon via (TSV) and one signal TSV. The at least one power and signal TSVs of the first die are connected to the at least one power and signal TSVs of the second die, respectively. The 3D IC structure also includes one or more peripheral TSV structures disposed adjacent to one or more sides of the first and/or the second die. The peripheral TSV structures supply at least power and/or signals. | 02-02-2012 |
20120025389 | Hermetic Wafer Level Packaging - Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum-based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers. | 02-02-2012 |
20120025390 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a plurality of storage node contact plugs passing through a first interlayer dielectric layer, a plurality of storage nodes in contact with the storage node contact plugs, each including a first electrode having a pillar shape and a second electrode spaced apart from the first electrode by a certain distance and surrounding the first electrode, and a second interlayer dielectric layer filling a gap between the second electrodes of neighboring storage nodes. | 02-02-2012 |
20120025391 | Semiconductor device and multilayer semiconductor device - Disclosed herein is a semiconductor device including: an input terminal receiving, if a preceding-stage semiconductor device is layered on a predetermined one of an upper layer and a lower layer, a bit train outputted from the preceding-stage semiconductor device; a semiconductor device identifier hold block holding a semiconductor device identifier for uniquely identifying the semiconductor device; a semiconductor device identifier computation block executing computation by using the semiconductor device identifier to update the semiconductor device identifier held in the semiconductor device identifier hold block according to a result of the computation; a control block once holding data of a bit train entered from the input terminal to control updating of the semiconductor device identifier executed by the semiconductor device identifier computation block based on the held data; and an output terminal outputting the bit train held in the control block to a succeeding-stage semiconductor device layered on another layer. | 02-02-2012 |
20120025392 | Increased Stability of a Complex Material Stack in a Semiconductor Device by Providing Fluorine Enriched Interfaces - When forming complex metallization systems, a sensitive material, such as a ULK material, may be deposited on a silicon-containing dielectric material, such as an etch stop material, with superior adhesion by performing a surface treatment on the basis of fluorine radicals. Due to the fluorine treatment, silicon-fluorine bonds are generated, which are then broken up upon interacting with the chemically active component during the further deposition process. Consequently, the subsequent material layer is chemically bonded to the underlying material, thereby imparting superior stability to the interface, which in turn may result in superior robustness and reliability of the metallization system upon performing reflowing processes and operating complex packaged semiconductor devices. | 02-02-2012 |
20120025393 | Power Semiconductor Module, Method for Producing a Power Semiconductor Module and a Housing Element for a Power Semiconductor Module - A power semiconductor module includes a housing element into which one or more connecting lugs are inserted. Each connecting lug has a foot region on the topside of which one or more bonding connections can be produced. In order to fix the foot regions, press-on elements are provided, which press against the end of the connecting lug. | 02-02-2012 |
20120032336 | SELF-ALIGNED PERMANENT ON-CHIP INTERCONNECT STRUCTURE FORMED BY PITCH SPLITTING - A method of fabricating an interconnect structure is provided. The method includes forming a hybrid photo-patternable dielectric material atop a substrate. The hybrid photo-patternable dielectric material has dual-tone properties with a parabola like dissolution response to radiation. The hybrid photo-patternable dielectric material is then image-wise exposed to radiation such that a self-aligned pitch split pattern forms. A portion of the self-aligned split pattern is removed to provide a patterned hybrid photo-patternable dielectric material having at least one opening therein. The patterned hybrid photo-patternable dielectric material is then converted into a cured and patterned dielectric material having the at least one opening therein. The at least one opening within the cured and patterned dielectric material is then filed with at least an electrically conductive material. Also provided are a hybrid photo-patternable dielectric composition and an interconnect structure. | 02-09-2012 |
20120032337 | Flip Chip Substrate Package Assembly and Process for Making Same - Apparatus and methods for providing a package substrate and assembly for a flip chip integrated circuit. A substrate is provided having a solder mask layer, openings in the solder mask layer for conductive bump pads, and openings in the solder mask layer between the conductive bump pads exposing a dielectric layer underneath the solder mask layer. A flip chip integrated circuit is attached to the substrate using a thermal reflow to reflow conductive solder bumps on the integrated circuit to the conductive bump pads. An underfill material is dispensed beneath the integrated circuit and physically contacting the dielectric layer of the substrate. In additional embodiments, one or more integrated circuits are flip chip mounted to the substrate. The resulting assembly has improved thermal characteristics over the assemblies of the prior art. | 02-09-2012 |
20120032338 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Disclosed is a semiconductor device which includes a base substrate; a lower electrode formed on a main surface of the base substrate; and an insulating film formed over the lower electrode and the main surface of the base substrate. The insulating film has a contact hole defined by a wall extending upwardly from the top surface of the lower electrode. The insulating film has a film density distribution in which a film density decreases with increasing distance from the main surface of the base substrate in the thickness direction. A width of the contact hole increases as the film density decreases. | 02-09-2012 |
20120038053 | Semiconductor Device and Method of Forming FO-WLCSP Having Conductive Layers and Conductive Vias Separated by Polymer Layers - A Fo-WLCSP has a first polymer layer formed around a semiconductor die. First conductive vias are formed through the first polymer layer around a perimeter of the semiconductor die. A first interconnect structure is formed over a first surface of the first polymer layer and electrically connected to the first conductive vias. The first interconnect structure has a second polymer layer and a plurality of second vias formed through the second polymer layer. A second interconnect structure is formed over a second surface of the first polymer layer and electrically connected to the first conductive vias. The second interconnect structure has a third polymer layer and a plurality of third vias formed through the third polymer layer. A semiconductor package can be mounted to the WLCSP in a PoP arrangement. The semiconductor package is electrically connected to the WLCSP through the first interconnect structure or second interconnect structure. | 02-16-2012 |
20120038054 | IMPEDANCE CONTROLLED ELECTRICAL INTERCONNECTION EMPLOYING META-MATERIALS - A method of improving electrical interconnections between two electrical elements is made available by providing a meta-material overlay in conjunction with the electrical interconnection. The meta-material overlay is designed to make the electrical signal propagating via the electrical interconnection to act as though the permittivity and permeability of the dielectric medium within which the electrical interconnection is formed are different than the real component permittivity and permeability of the dielectric medium surrounding the electrical interconnection. In some instances the permittivity and permeability resulting from the meta-material cause the signal to propagate as if the permittivity and permeability have negative values. Accordingly the method provides for electrical interconnections possessing enhanced control and stability of impedance, reduced noise, and reduced loss. Alternative embodiments of the meta-material overlay provide, the enhancements for conventional discrete wire bonds whilst also facilitating single integrated designs compatible with tape implementation. | 02-16-2012 |
20120038055 | POWER AND GROUND ROUTING OF INTEGRATED CIRCUIT DEVICES WITH IMPROVED IR DROP AND CHIP PERFORMANCE - An integrated circuit chip includes a semiconductor substrate having thereon a plurality of IMD layers and first conductive layers embedded in the IMD layers; a first insulating layer overlying the IMD layers and the first conductive layers; a plurality of first power/ground mesh wiring lines, in a second conductive layer overlying the first Insulating layer, for distributing power signal or ground signal; and a second insulating layer covering the second conductive layer and the first insulating layer. | 02-16-2012 |
20120043660 | THIN FOIL SEMICONDUCTOR PACKAGE - One aspect of the present invention involves a foil-based method for packaging integrated circuits. Initially, a metallic foil and a photoresist layer are attached with a carrier. The photoresist layer is exposed and patterned. Afterward, multiple integrated circuit dice are connected to the foil. The dice and portions of the foil are encapsulated in a molding material. The foil is then etched based on the patterned photoresist layer to define multiple device areas in the foil, where each device area supports at least one of the integrated circuit dice. Some aspects of the present invention relate to panel arrangements that are involved in the aforementioned method. | 02-23-2012 |
20120043661 | INTEGRATED CIRCUITS AND METHODS OF FORMING CONDUCTIVE LINES AND CONDUCTIVE PADS THEREFOR - Integrated circuits and methods for forming conductive lines and conductive pads of integrated circuits are disclosed. One such integrated circuit includes circuitry, a first conductor coupled to the circuitry, a conductive pad coupled to the first conductor, and a second conductor spaced apart from the first conductor and coupled to the conductive pad. The second conductor would be floating but for its coupling to the conductive pad. | 02-23-2012 |
20120043662 | SEMICONDUCTOR DEVICE PRODUCTION METHOD AND SEMICONDUCTOR DEVICE - A purpose of the application is to provide a semiconductor device production method capable of reducing complexity of production operations and keeping production costs low, and enhancing reliability, and a semiconductor device. One aspect of the invention provides a method of producing a semiconductor device, the method including a first bonding step of bonding a first electrode plate and a semiconductor device portion, and a second bonding step of bonding the semiconductor device portion and a second electrode plate. The method includes a sealing step of forming a sealed composite body by covering target surfaces of a composite body formed by the first bonding step with resin, the target surfaces being surfaces other than a second surface of the first electrode plate and the second surface of the semiconductor device portion. The second bonding step is performed after the sealing step. | 02-23-2012 |
20120043663 | POWER AND GROUND ROUTING OF INTEGRATED CIRCUIT DEVICES WITH IMPROVED IR DROP AND CHIP PERFORMANCE - An integrated circuit chip includes a semiconductor substrate having thereon a plurality of IMD layers and a plurality of first conductive layers; a first passivation layer overlying the plurality of IMD layers and the first conductive layers; at least a first power/ground mesh wiring line in a first aluminum layer overlying the first Insulating layer; and at least a second power/ground mesh wiring line in a second aluminum layer overlying the first aluminum layer. | 02-23-2012 |
20120056327 | RAMP-STACK CHIP PACKAGE WITH STATIC BENDS - A ramp-stack chip package is described. This chip package includes a vertical stack of semiconductor dies or chips that are offset from each other in a horizontal direction, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, is electrically and mechanically coupled to the exposed pads. For example, the ramp component may be coupled to the semiconductor dies using: solder, microsprings and/or an anisotropic conducting film. Furthermore, each of the semiconductor dies includes a static bend so that an end segment of each of the semiconductor dies is parallel to the direction and is mechanically coupled to the ramp component. These end segments may facilitate high-bandwidth communication of signals between the chips and the ramp component, for example, via proximity communication. | 03-08-2012 |
20120061845 | Methods for filling a contact hole in a chip package arrangement and chip package arrangements - In various embodiments, a method for filling a contact hole in a chip package arrangement is provided. The method may include introducing electrically conductive discrete particles into a contact hole of a chip package; and forming an electrical contact between the electrically conductive particles and a contact terminal of the front side and/or the back side of the chip. | 03-15-2012 |
20120061846 | COMPLIANT PRINTED CIRCUIT AREA ARRAY SEMICONDUCTOR DEVICE PACKAGE - An integrated circuit (IC) package for an IC device, and a method of making the same. The IC package includes an interconnect assembly with at least one printed compliant layer, a plurality of first contact members located along a first major surface, a plurality of second contact members located along a second major surface, and a plurality of printed conductive traces electrically coupling a plurality of the first and second contact members. The compliant layer is positioned to bias at least the first contact members against terminals on the IC device. Packaging substantially surrounds the IC device and the interconnect assembly. The second contact members are accessible from outside the packaging. | 03-15-2012 |
20120061847 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and manufacturing method thereof improving moisture resistance of a FeRAM. After a probe test using a pad, a metal film is formed to cover the pad in an opening of a protective film and a region from the pad to an opening outer periphery of the protective film. On the metal film, a metal bump is formed. The metal film is formed to have a two-layer structure of the first and second metal films. Materials of the lower and upper layers are selected mainly in consideration of adhesion to the protective film and adhesion to the metal bump, respectively. Film formation conditions thereof are set to provide metal films with a desired quality and thickness. Thus, penetration of moisture from the pad or the periphery into a ferroelectric capacitor can be prevented and therefore, occurrence of potential inversion abnormalities due to penetrated moisture can be effectively suppressed. | 03-15-2012 |
20120068346 | STRUCTURE FOR NANO-SCALE METALLIZATION AND METHOD FOR FABRICATING SAME - A method for forming structure aligned with features underlying an opaque layer is provided for an interconnect structure, such as an integrated circuit. In one embodiment, the method includes forming an opaque layer over a first layer, the first layer having a surface topography that maps to at least one feature therein, wherein the opaque layer is formed such that the surface topography is visible over the opaque layer. A second feature is positioned and formed in the opaque layer by reference to such surface topography. | 03-22-2012 |
20120068347 | METHOD FOR PROCESSING SEMICONDUCTOR STRUCTURE AND DEVICE BASED ON THE SAME - Methods for fabricating a device and related device structures are provided herein. According to one embodiment, a method for fabricating a device includes the acts of producing a substrate; forming a structure on the substrate having a lower dielectric layer, a metal layer, an upper dielectric layer, a planarizing layer, and a layer of photoresist material; developing the photoresist material according to a mask pattern; etching the planarizing layer and the upper dielectric layer according to the mask pattern; removing the photoresist material and the planarizing layer upon etching of the planarizing layer and the upper dielectric layer; applying a selective metal growth or metal/organic film to respective exposed portions of the metal layer following etching of the upper dielectric layer, thereby obtaining an inverted mask pattern; and etching at least the metal layer and the lower dielectric layer according to the inverted mask pattern. | 03-22-2012 |
20120068348 | Interconnect Regions - Some embodiments include interconnect regions. The regions may contain, along a cross section, a closed-shape interior region having an electrically conductive material therein, a first dielectric material configured as a liner extending entirely around a lateral periphery of the interior region, and at least two dielectric projections joining to the dielectric material liner and being laterally outward of the interior region. The dielectric projections may have an outer dielectric ring surrounding an inner dielectric region. The outer ring may consist of the first dielectric material and the inner dielectric region may be a composition different from a composition of the first dielectric material, and in some embodiments the composition within the inner dielectric region may be gaseous. | 03-22-2012 |
20120068349 | TAPE PACKAGE - A tape package providing a plurality of input and output portions each having a minimum pitch. The tape package includes a tape wiring substrate including first and second wirings, and a semiconductor chip mounted on the tape wiring substrate, and including a first edge, a first pad disposed adjacent to the first edge, and a second pad disposed to be farther spaced apart from the first edge than the first pad, where the first wiring is connected to a portion of the first pad that is spaced from the first edge by a first distance, and where the second wiring is connected to a portion of the second pad that is spaced from the first edge by a second distance that is greater than the first distance. | 03-22-2012 |
20120068350 | SEMICONDUCTOR PACKAGES, ELECTRONIC DEVICES AND ELECTRONIC SYSTEMS EMPLOYING THE SAME - A semiconductor package, an electronic device, and an electronic system employing the same are provided. The semiconductor package includes a printed circuit board (PCB) and a semiconductor chip structure. A first PCB land region is provided on a first surface of the PCB. A plurality of first chip land regions are provided on a first surface of the semiconductor chip structure which faces the first surface of the PCB. A first connection structure for electrically connecting the first PCB land region to the plurality of first chip land regions is provided. | 03-22-2012 |
20120074576 | INTERCONNECT FOR AN OPTOELECTRONIC DEVICE - Interconnects for optoelectronic devices are described. An interconnect may include a stress relief feature. An interconnect may include an L-shaped feature. | 03-29-2012 |
20120074577 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING OF SEMICONDUCTOR DEVICE, AND SWITCHING CIRCUIT - It is an objective to provide a semiconductor device with low leak current. The semiconductor device includes a plurality of ground side electrodes and a plurality of signal side electrodes arranged on a semiconductor substrate in an alternating manner; a plurality of control electrodes arranged respectively between each pair of a ground side electrode and a signal side electrode; a ground side electrode connecting section that connects the ground side electrodes to each other; a signal side electrode connecting section that connects the signal side electrodes to each other; and ground side lead wiring and signal side lead wiring that extend respectively from a region near one end and a region near another end of an arranged electrode section, in which the ground side electrodes and the signal side electrodes are arranged in an arrangement direction, away from the arranged electrode group in the arrangement direction. | 03-29-2012 |
20120074578 | SEMICONDUCTOR ELEMENT, SEMICONDUCTOR ELEMENT MOUNTED BOARD, AND METHOD OF MANUFACTURING SEMICONDUCTOR ELEMENT - A semiconductor element includes connection terminals. The connection terminals are each shaped in such a manner that the transverse cross-sectional area in a portion near the leading end thereof decreases toward the leading end. Specifically, the shape of each of the connection terminals is columnar except for the portion near the leading end, and the side surface in the portion near the leading end of the connection terminal is shaped in a tapered form. Furthermore, a metal layer for improving a solder wettability may be formed at least on the side surface shaped in the tapered form, of the connection terminal. | 03-29-2012 |
20120080800 | POWER MODULE AND METHOD FOR MANUFACTURING THE SAME - Provided is a power module that prevents a deterioration of reliability of bonded portions of aluminum wires, and enables a high-temperature operation of a Si or SiC device. A power module according to the present invention includes: insulating substrates arranged in a case; power elements bonded on the insulating substrates; wiring members as first wiring members which are rectangular tube-like metal, and have first side surfaces bonded to surface electrodes of the power elements; aluminum wires as wires connected to second side surfaces of the wiring members, which are opposite to the first side surfaces, and a sealing material filled into the case while covering the insulating substrates, the power elements, the wiring members and the aluminum wires. | 04-05-2012 |
20120080801 | SEMICONDUCTOR DEVICE AND ELECTRONIC COMPONENT MODULE USING THE SAME - A semiconductor device includes a circuit board having an element mounting area, connecting pads positioned in the same surface side as the element mounting area and external connectors to be connected with the connecting pads, respectively; and a semiconductor element mounted on the element mounting area of the circuit board and having electrode pads to be electrically connected with the connecting pads, respectively. The external connectors are detachably configured through a combination of convex portions and concave portions which are mechanically and electrically connected with one another. | 04-05-2012 |
20120086126 | PACKAGE SYSTEMS AND MANUFACTURING METHODS THEREOF - A package system includes a first substrate and a second substrate. The second substrate is electrically coupled with the first substrate. The second substrate includes at least one first opening. At least one electrical bonding material is disposed between the first substrate and the second substrate. A first portion of the at least one electrical bonding material is at least partially filled in the at least one first opening. | 04-12-2012 |
20120086127 | PACKAGE SYSTEMS AND MANUFACTURING METHODS THEREOF - A package system includes a first substrate. A second substrate is electrically coupled with the first substrate. At least one electrical bonding material is disposed between the first substrate and the second substrate. The at least one electrical bonding material includes a eutectic bonding material. The eutectic bonding material includes a metallic material and a semiconductor material. The metallic material is disposed adjacent to a surface of the first substrate. The metallic material includes a first pad and at least one first guard ring around the first pad. | 04-12-2012 |
20120091592 | Double Patterning Technology Using Single-Patterning-Spacer-Technique - A method of forming an integrated circuit structure includes forming a first and a second plurality of tracks parallel to a first direction and on a wafer representation. The first and the second plurality of tracks are allocated in an alternating pattern. A first plurality of patterns is laid out on the first plurality of tracks and not on the second plurality of tracks. A second plurality of patterns is laid out on the second plurality of tracks and not on the first plurality of tracks. The first plurality of patterns is extended in the first direction and in a second direction perpendicular to the first direction, so that each of the second plurality of patterns is surrounded by portions of the first plurality of patterns, and substantially none of neighboring ones of the first plurality of patterns on the wafer representation have spacings greater than a pre-determined spacing. | 04-19-2012 |
20120098138 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device of the present invention has the power semiconductor elements having back surfaces bonded to the wiring patterns and surface electrodes on surfaces, the cylindrical communication parts having bottom surfaces bonded on the surface electrodes of the power semiconductor elements and/or on the wiring patterns, the transfer mold resin having concave parts which expose the upper surfaces of the communication parts and covering surfaces other than the upper surfaces of the communication parts, the insulating layer, the wiring patterns, and the power semiconductor elements, and the external terminals having one ends inserted in the upper surfaces of the communication parts and the other ends guided upward, and at least one external terminal has, between both end parts, the bent area which is bent in an L shape and the bent area is embedded in the concave part of the transfer mold resin. | 04-26-2012 |
20120098139 | Vertical Memory Devices And Methods Of Manufacturing The Same - A vertical memory device includes a channel, a ground selection line (GSL), word lines, a string selection line (SSL), and a contact. The channel includes a vertical portion and a horizontal portion. The vertical portion extends in a first direction substantially perpendicular to a top surface of a substrate, and the horizontal portion is connected to the vertical portion and parallel to the top surface of the substrate. The GSL, the word lines and the SSL are formed on a sidewall of the vertical portion of the channel sequentially in the first direction, and are spaced apart from each other. The contact is on the substrate and electrically connected to the horizontal portion of the channel. | 04-26-2012 |
20120104619 | SUBLITHOGRAPHIC PATTERNING EMPLOYING IMAGE TRANSFER OF A CONTROLLABLY DAMAGED DIELECTRIC SIDEWALL - A first low dielectric constant (low-k) dielectric material layer is lithographically patterned to form a recessed region having expose substantially vertical sidewalls, which are subsequently damaged to de-carbonize a surface portion at the sidewalls having a sublithographic width. A second low-k dielectric material layer is deposited to fill the recessed region and planarized to exposed top surfaces of the damaged low-k dielectric material portion. The damaged low-k dielectric material portion is removed selective to the first and second low-k dielectric material layers to form a trench with a sublithographic width. A portion of the pattern of the sublithographic-width trench is transferred into a metallic layer and optionally to an underlying dielectric masking material layer to define a trench with a sublithographic width, which can be employed as a template to confine the widths of via holes and line trenches to be subsequently formed in an interconnect-level dielectric material layer. | 05-03-2012 |
20120104620 | CONTACT PAD ARRAY - A contact pad array is provided. The contact pad array includes a plurality of first contact pads and a plurality of second contact pads. The first contact pads are arranged along the first direction. Each first contact pad includes two first lengthwise sides and two widthwise sides. The second contact pads are arranged along the first direction. Each second contact pad includes two second lengthwise sides and two second widthwise sides. The length of the second lengthwise side is substantially shorter than that of the first lengthwise side, and the width of the second widthwise side is substantially larger than that of the first widthwise side. The projection of the first widthwise side of each first contact pad on the first direction is completely within the projection of the second widthwise side of the corresponding second contact pad on the first direction. | 05-03-2012 |
20120104621 | POWER PACKAGE MODULE AND METHOD FOR FABRICATING THE SAME - Disclosed herein are a power package module and a method for fabricating the same, including: a base substrate; a plurality of high power chips and a plurality of low power chips electrically connected to the base substrate; and a plurality of metal lead plates electrically connecting the plurality of high power chips and the plurality of low power chips to the base substrate. | 05-03-2012 |
20120112352 | INTEGRATED CIRCUIT SYSTEM WITH DISTRIBUTED POWER SUPPLY - An integrated circuit system having an interposer and an integrated circuit with first and second bond pads, the integrated circuit die bonded to the interposer using the first bond pads. The integrated circuit having circuit blocks, that operate at different operating voltages and voltage regulator modules die bonded to the second bond pads of the integrated circuit. The voltage regulator modules converting a power supply voltage to the operating voltage of a respective circuit block and supply the respective operating voltage to the circuit block via the second bond pads. | 05-10-2012 |
20120112353 | ORGANIC ELECTRONIC CIRCUIT - A multi-layer film body comprises a plastic substrate strip conveyed in a first direction in a roll-to-roll process for printing electronic organic components on the substrate. A first electrically conducting layer is on the substrate, a semiconductor layer is on the first layer, an insulator layer is on the semiconductor layer and a second electrically conducting layer is on the insulator layer, the layers comprising a first interconnection assembly portion and a second electronic assembly portion successively positioned in the first direction, each portion comprising a central zone and a respective conductor tract input zone and conductor tract output zone bordering the respective central zones, the input, central and output zones of each portion each comprising parallel conductor tracts in the first conducting layer. Electrical connectors in the second conducting layer interconnect selected ones of the conductor tracts in the two portions. Regions of the semiconductor and insulating layers in the second portion are juxtaposed with electrodes formed from the first and second conducting layers in the central zone, forming organic electronic components comprising one or more of transistors, diodes, resistors and capacitors. The conductive tracts of the input zone of the first portion and the conductive tracts of the output zone of the second portion form the component inputs and outputs. | 05-10-2012 |
20120112354 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first interconnect layer and a second interconnect layer provided above or under the first interconnect layer. The first interconnect layer includes a plurality of first interconnect blocks, and in each of the first interconnect blocks, a first interconnect has a first potential, and extends in at least two or more directions, and a second interconnect has a second potential, and extends in at least two or more directions. The second interconnect layer includes a third interconnect which electrically connects the first interconnect of one of a pair of adjacent first interconnect blocks and the first interconnect of the other of the pair of adjacent first interconnect blocks, and a fourth interconnect which electrically connects the second interconnect of one of the pair of adjacent first interconnect blocks and the second interconnect of the other of the pair of adjacent first interconnect blocks. | 05-10-2012 |
20120112355 | Semiconductor Device and Method of Forming Stepped Interconnect Layer for Stacked Semiconductor Die - A semiconductor die has a first semiconductor die mounted to a carrier. A plurality of conductive pillars is formed over the carrier around the first die. An encapsulant is deposited over the first die and conductive pillars. A first stepped interconnect layer is formed over a first surface of the encapsulant and first die. The first stepped interconnect layer has a first opening. A second stepped interconnect layer is formed over the first stepped interconnect layer. The second stepped interconnect layer has a second opening. The carrier is removed. A build-up interconnect structure is formed over a second surface of the encapsulant and first die. A second semiconductor die over the first semiconductor die and partially within the first opening. A third semiconductor die is mounted over the second die and partially within the second opening. A fourth semiconductor die is mounted over the second stepped interconnect layer. | 05-10-2012 |
20120119367 | CONDUCTIVE PADS DEFINED BY EMBEDDED TRACES - An assembly and method of making same are provided. The assembly can include a first component including a dielectric region having an exposed surface, a conductive pad at the surface defined by a conductive element having at least a portion extending in an oscillating or spiral path along the surface, and a an electrically conductive bonding material joined to the conductive pad and bridging an exposed portion of the dielectric surface between adjacent segments. The conductive pad can permit electrical interconnection of the first component with a second component having a terminal joined to the pad through the electrically conductive bonding material. The path of the conductive element may or may not overlap or cross itself. | 05-17-2012 |
20120119368 | SEMICONDUCTOR MEMORY DEVICE - In one embodiment, a semiconductor memory device includes a substrate, and device regions formed in the substrate to extend in a first direction which is parallel to a principal plane of the substrate. The device further includes select gates disposed on the substrate to extend in a second direction which is perpendicular to the first direction, and a contact region provided between the select gates on the substrate and including contact plugs disposed on the respective device regions. Further, the contact region includes partial regions, in each of which N contact plugs are disposed on N successive device regions to be arranged on a straight line being non-parallel to the first and second directions, where N is an integer of 2 or more. Further, the contact region includes the partial regions of at least two types whose values of N are different. | 05-17-2012 |
20120119369 | SEMICONDUCTOR DEVICE - A semiconductor device includes a main current external electrode for connecting a high-voltage main current electrode of a power semiconductor element to the outside, and a resin case into which the main current external electrode is press fitted. The main current external electrode has a press-fitted fixing portion and a claw fixing portion for fixation to the resin case. The claw fixing portion includes a projection passing through a through hole defined in the resin case, and having a bendable claw portion at its tip end. | 05-17-2012 |
20120119370 | SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - Provided are a semiconductor package and a semiconductor system including the semiconductor package. The semiconductor package includes a semiconductor device and an interconnect structure electrically connected to the semiconductor device and delivering a signal from the semiconductor device, wherein the interconnect structure includes an anodized insulation region and an interconnect adjacent to and defined by the anodized insulation region. | 05-17-2012 |
20120119371 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - There is provided a method of fabricating a semiconductor device including: forming an insulating film on a semiconductor substrate; forming a pad electrode on the insulating film; forming a protective film on the pad electrode; forming, on the protective film, a resist equipped with an open portion in a first region corresponding to part of the pad electrode; by using the resist as a mask, etching the protective film and etching the first region of part of the pad electrode to a predetermined depth; etching the protective film on a second region that surrounds the first region of the pad electrode; and removing the resist. | 05-17-2012 |
20120119372 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a substrate including an electrode pad on a surface; a semiconductor chip placed on the substrate so as to be electrically connected to the electrode pad; a first resin layer which is formed on the substrate and is also filled between the substrate and the semiconductor chip; and a second resin layer, laminated on the first resin layer, which has an elastic modulus larger than that of the first resin layer. | 05-17-2012 |
20120126412 | INTEGRATED CIRCUIT DEVICE AND METHOD OF FORMING THE SAME - An integrated circuit device includes a semiconductor substrate having a first region and second region, a conductive via positioned in the first region of the semiconductor substrate, at least one active element positioned in the second region of the semiconductor substrate, a conductive layer extending from the first region to the second region and electrically connecting the conductive via to the active element, and an auxiliary structure positioned in the first region of the semiconductor substrate and proximate to the conductive via. The auxiliary structure can be a stress-absorbing structure, and the volume of the stress-absorbing structure decreases as the volume of the conductive via increases. The auxiliary structure can be a heat-evacuating structure, and the heat-evacuating structure is configured to transfer the operating heat generated by the active element from the first region of the semiconductor substrate to the conductive via through the conductive layer. | 05-24-2012 |
20120126413 | METHOD OF SEALING AN AIR GAP IN A LAYER OF A SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE - Providing a first layer of a semiconductor structure having at least one air gap between conductive lines formed in the first layer. The air gap extends into the first layer from a first surface of the first layer. A barrier dielectric material over the first surface and the air gap is selected to have a dielectric constant less than 3.5 and to provide a barrier to prevent chemicals entering the at least one air gap. An air gap can extend from a first surface of the first layer to at least a portion of side surfaces of the at least two conductive lines to expose at least a portion of the side surfaces. | 05-24-2012 |
20120126414 | Semiconductor Device and Manufacturing Method Thereof - A method of manufacturing a semiconductor device, includes forming an insulating film of a material having a low relative dielectric constant on a substrate, forming an SiOCH film on the insulating film in a chamber, forming an SiO | 05-24-2012 |
20120133045 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. | 05-31-2012 |
20120139120 | Semiconductor Device and Method of Forming Openings Through Encapsulant to Reduce Warpage and Stress on Semiconductor Package - A semiconductor device has a plurality of semiconductor die mounted active surface to a carrier. An encapsulant is deposited over semiconductor die and carrier. Openings are formed through a surface of the encapsulant to divide the encapsulant into discontinuous segments. The openings have straight or beveled sidewalls. The openings can be formed partially through the surface of the encapsulant in an area between the semiconductor die. The openings can be formed partially through the surface of the encapsulant over the semiconductor die. The openings can be formed through the encapsulant in an area between the semiconductor die. A portion of the surface of the encapsulant is removed down to a bottom of the openings. The carrier is removed. An interconnect structure is formed over the encapsulant and the semiconductor die. The encapsulant is cured prior to or after forming the openings. | 06-07-2012 |
20120139121 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD CONNECTION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a lead having a horizontal ridge at a lead top side; forming a connection layer having an inner pad and an outer pad directly on the lead top side, the inner pad having an inner pad bottom surface; mounting an integrated circuit over the inner pad; applying a molding compound, having a molding bottom surface, over the integrated circuit, the inner pad, and the outer pad; and applying a dielectric directly on the molding bottom surface and the inner pad bottom surface. | 06-07-2012 |
20120139122 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device which includes a substrate, a semiconductor chip which is mounted on the substrate, a package in which an upper surface of the substrate and the semiconductor chip are sealed using an insulating material, and a molding material which is exposed to the upper surface of the package. In addition, the device includes a lead of which one end is connected to the mold material and the other end is electrically connected to the substrate, which is integrally formed of the same material as from a connection portion with the mold material to a connection portion with the substrate, and of which the connection portion with the mold material is exposed to the upper surface of the package. | 06-07-2012 |
20120146229 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a package substrate bottom side, a package substrate top side, and a package substrate window; mounting a base integrated circuit over the package substrate, the base integrated circuit having a base inactive side and a base active side facing the package substrate top side; attaching a lower internal connector to the base active side and the package substrate bottom side, the lower internal connector through the package substrate window; forming an upper insulation conformal to the base integrated circuit and the package substrate top side, the upper insulation having an upper insulation top side; and forming a peripheral through-insulation connector through the upper insulation, the peripheral through-insulation connector having a peripheral connector bottom side directly on the package substrate top side and a peripheral connector top side coplanar with the upper insulation top side. | 06-14-2012 |
20120146230 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a carrier having a contact pad; forming a first resist layer, having a first resist opening, over the carrier and the contact pad, the first resist opening partially exposing the first contact pad; forming a second resist layer, having a second resist opening over the first resist opening, the second resist opening partially exposing the first resist layer; mounting an integrated circuit over the carrier; and forming an internal interconnect between the integrated circuit and the carrier, the internal interconnect filling the second resist opening with no space between the second resist layer in the second resist opening. | 06-14-2012 |
20120146231 | Semiconductor Device and Method of Manufacture Thereof - A semiconductor device and a method of making a semiconductor device are disclosed. The semiconductor device comprises a redistribution layer arranged over a chip, the redistribution layer comprising a first redistribution line. The semiconductor further comprises an isolation layer disposed over the redistribution layer, the isolation layer having a first opening forming a first pad area and a first interconnect located in the first opening and in contact with the first redistribution line. The redistribution line in the first pad area is arranged orthogonal to a first direction to a neutral point of the semiconductor device. | 06-14-2012 |
20120146232 | ELECTRONIC DEVICE AND METHOD OF MANUFACTURING ELECTRONIC DEVICE - An electronic device in which a metal wire ( | 06-14-2012 |
20120146233 | SEMICONDUCTOR DEVICE AND SUBSTRATE - A semiconductor device of the invention include a rectangular semiconductor element mounted on a substrate formed with an external input terminal, an external output terminal, and a plurality of wiring patterns connected to each of the external input terminal and the external output terminal. The semiconductor element comprises, a plurality of first electrodes formed along a first edge of a surface thereof, a plurality of second electrodes formed along an edge opposite to the first edge of the surface, a plurality of third electrodes formed in the neighborhood of a functional block, and an internal wiring for connecting the first electrodes and the third electrodes. The substrate comprises, a first wiring pattern for connecting the external input terminal and the first electrodes, a second wiring pattern for connecting the external output terminal and the second electrodes, and a third wiring pattern for connecting the first electrodes and the third electrodes. | 06-14-2012 |
20120153489 | SEMICONDUCTOR PACKAGE HAVING PROXIMITY COMMUNICATION SIGNAL INPUT TERMINALS AND MANUFACTURING METHODS THEREOF - A semiconductor package includes a semiconductor structure. The semiconductor structure includes a plurality of dielectric layers and a plurality of conductive interconnects embedded in the semiconductor structure. The semiconductor structure also includes a plurality of proximity communication signal input terminals. At least one of the plurality of proximity communication signal input terminals includes a first electrode and a second electrode. The first electrode and the second electrode are spaced apart so as to be configured to provide proximity communication through capacitive coupling. The first electrode is exposed proximate to a surface of the semiconductor structure. | 06-21-2012 |
20120153490 | INTERCONNECTION STRUCTURE FOR AN INTEGRATED CIRCUIT - The disclosure relates to a method of fabricating an interconnection structure of an integrated circuit, comprising the steps of: forming a first conductive element within a first dielectric layer; depositing a first etch stop layer above the first conductive element and the first dielectric layer; forming an opening in the first etch stop layer above the first conductive element, to form a first connection area; depositing a second dielectric layer above the etch stop layer and above the first conductive element in the connection area; etching the second dielectric layer to form at least one hole which is at least partially aligned with the connection area; and filling the hole with a conductive material to form a second conductive element in electrical contact with the first conductive element. | 06-21-2012 |
20120153491 | SEMICONDUCTOR DEVICE - A first transistor group, a second transistor group, and an electrode pad are formed on a semiconductor substrate. A first protective film is formed so as to cover the semiconductor substrate except for an upper region of the electrode pad. The second protective film which generates a stress in a projecting direction is formed so as to cover the first protective film except for an upper region of the first transistor group. A transistor ability of the first transistor group is varied to be relatively higher due to a presence of the second protective film, based on a transistor ability of the second transistor group, as a reference. | 06-21-2012 |
20120161327 | Shrinkage of Contact Elements and Vias in a Semiconductor Device by Incorporating Additional Tapering Material - Vertical contact structures, such as contact elements connected to semiconductor-based contact regions in device areas comprising densely-spaced gate electrode structures, are formed for given lithography and patterning capabilities by incorporating at least one additional dielectric layer of superior tapering behavior into the dielectric material system. | 06-28-2012 |
20120161328 | RETICLE SET MODIFICATION TO PRODUCE MULTI-CORE DIES - A first reticle set designed for manufacturing dies with a limited number of cores is modified into a second reticle set suitable for manufacturing at least some dies with at least twice as many cores. The first reticle set defines scribe lines to separate the originally defined dies. At least one scribe line is removed from pairs of adjacent but originally distinctly defined dies. Inter-core communication wires are defined to connect the adjacent cores, which are configured to enable the adjacent cores to communicate during operation without connecting to any physical input/output landing pads of the resulting more numerously cored die, which will not carry signals through the inter-core communication wires off the P-core die. The inter-core communication wires may be used for power management coordination purposes or to bypass the external processor bus. | 06-28-2012 |
20120161329 | MULTI-LEVEL INTEGRATED CIRCUIT, DEVICE AND METHOD FOR MODELING MULTI-LEVEL INTEGRATED CIRCUITS - A multi-level integrated circuit comprising a superposition of a first stack and a second stack of layers, and including:
| 06-28-2012 |
20120168955 | Integrated Circuit Pattern and Method - An integrated circuit pattern comprises a set of lines of material having X and Y direction portions. The X and Y direction portions have first and second pitches, the second pitch being larger, such as at least 3 times larger, than the first pitch. The X direction portions are parallel and the Y direction portions are parallel. The end regions of the Y direction portions comprise main line portions and offset portions. The offset portions comprise offset elements spaced apart from and electrically connected to the main line portions. The offset portions define contact areas for subsequent pattern transferring procedures. A multiple patterning method, for use during integrated circuit processing procedures, provides contact areas for subsequent pattern transferring procedures. | 07-05-2012 |
20120168956 | CONTROLLING DENSITY OF PARTICLES WITHIN UNDERFILL SURROUNDING SOLDER BUMP CONTACTS - A method forms an integrated circuit structure, using a manufacturing device, to have kerf regions and external contacts, and to have conductive structures in the kerf regions. The method also forms an underfill material on a surface of the integrated circuit structure, using the manufacturing device, that contacts the kerf regions and the external contacts. The underfill material comprises electrically attracted filler particles that affect the coefficient of thermal expansion and elastic modulus of the underfill material. When forming the underfill material, the method applies an electrical charge to the conductive structures and the external contacts. | 07-05-2012 |
20120175779 | Semiconductor Device and Method of Forming Integrated Passive Device - An IPD semiconductor device has a capacitor formed over and electrically connected to a semiconductor die. An encapsulant is deposited over the capacitor and around the semiconductor die. A first interconnect structure is formed over a first surface of the encapsulant by forming a first conductive layer, forming a first insulating layer over the first conductive layer, and forming a second conductive layer over the first insulating layer. The second conductive layer has a portion formed over the encapsulant at least 50 micrometer away from a footprint of the semiconductor die and wound to operate as an inductor. The portion of the second conductive layer is electrically connected to the capacitor by the first conductive layer. A second interconnect structure is formed over a second surface of the encapsulant. A conductive pillar is formed within the encapsulant between the first and second interconnect structures. | 07-12-2012 |
20120175780 | SEMICONDUCTOR COMPONENT AND METHOD OF MAKING THE SAME - One embodiment provides a semiconductor chip including a semiconductor body and a power semiconductor component integrated therein. The power semiconductor component includes a load electrode zone arranged on a first surface of the semiconductor body, a control electrode zone arranged on the first surface, the control electrode zone being electrically insulated from the load electrode zone, and a resistance track arranged on the load electrode zone and the control electrode zone. The resistance track ensures an electrical connection between the load electrode zone and the control electrode zone. | 07-12-2012 |
20120181699 | Semiconductor Structure and Manufacturing Method of the Same - A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a first stacked structure, a second stacked structure, a dielectric element, and a conductive line. The first stacked structure and the second stacked structure are disposed on the substrate. Each of the first stacked structure and the second stacked structure includes conductive strips and insulating strips stacked alternately. The conductive strips are separated from each other by the insulating strips. The dielectric element is disposed on the first stacked structure and the second stacked structure and includes a second dielectric portion. The first stacked structure and the second stacked structure are separated from each other by only the second dielectric portion. The conductive line is disposed on the stack sidewalls of the first stacked structure and the second stacked structure far from the second dielectric portion. | 07-19-2012 |
20120187564 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE PACKAGE - A semiconductor device or semiconductor device package for transmitting a plurality of differential signals, the reliability of which hardly deteriorates. The semiconductor device is an area array semiconductor device in which a plurality of lands (external terminals) including a plurality of lands for transmitting a plurality of differential signals are arrayed in a matrix pattern in the back surface of a wiring substrate. Some of the lands are located in the outermost periphery of the matrix pattern. Some others of the lands are located inward of the outermost periphery of the matrix pattern and in rows next to the outermost periphery. The spacing between lands in a second region between the lands located in the rows next to the outermost periphery and the side surface of the wiring substrate is larger than in a first region in the outermost periphery. | 07-26-2012 |
20120193802 | GLOB TOP SEMICONDUCTOR PACKAGE - A semiconductor package is disclosed including a substrate, a solder mask layer, one or more semiconductor die mounted to the solder mask layer and electrically coupled to the substrate, and a glob top cover over the semiconductor die. The solder mask further includes a dam protruding above surrounding areas of the solder mask layer and a cavity recessed into the solder mask layer for limiting flow of the glob top cover when the glob top material is applied. | 08-02-2012 |
20120193803 | SEMICONDUCTOR DEVICE, METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, AND DISPLAY - It is desired to enhance reliability of thermal coupling between a semiconductor chip and a radiating member. A driver assembly has a sheetlike wiring sheet on which lead wires are provided, a driver chip that is mounted over the wiring sheet and is electrically coupled to the lead wire, and a radiator plate in which a housing part for partially housing the driver chip is provided and that is thermally coupled to the driver chip, wherein the wiring sheet and the radiator plate are adhered to each other so as to sandwich the driver chip housed in the housing part between them, and a depth profile of the housing part is set so that the wiring sheet may approach toward the radiator plate side as the wiring sheet extends in such a direction that so as to separate from the driver chip. | 08-02-2012 |
20120193804 | OHMIC CONNECTION USING WIDENED CONNECTION ZONES IN A PORTABLE ELECTRONIC OBJECT - The invention relates to portable electronic objects comprising an integrated circuit chip, and a mounting having two connection terminals for a circuit, as well as to a method for manufacturing such objects. The invention is characterized in that the chip is provided, on the active surface thereof, with two widened connection zones, in particular connection plates, said connection plates being positioned opposite said terminals and electrically connected, by ohmic contact, to the latter, and in that the surface defined by the connection plates, at the surface of the active integrated circuit having said plates, is greater than ½ of the surface of said surface. The invention can be used, in particular, for RFID objects. | 08-02-2012 |
20120193805 | DUAL MOLDED MULTI-CHIP PACKAGE SYSTEM - A dual molded multi-chip package system is provided including forming an embedded integrated circuit package system having a first encapsulation partially covering a first integrated circuit die and a lead connected thereto, mounting a semiconductor device over the first encapsulation and connected to the lead, and forming a second encapsulation over the semiconductor device and the embedded integrated circuit package system. | 08-02-2012 |
20120199978 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR WAFER - In a method for manufacturing a semiconductor device, a process of providing a semiconductor wafer having a wiring layer having conductive patterns and a plurality of insulation films containing a first insulation film surrounding side surfaces of the conductive patterns are provided. After the process of providing the semiconductor wafer, a process of removing some regions of the plurality of insulation films to form openings is provided. Herein, the first insulation film is disposed to a position closer to the circumference of the semiconductor wafer than a position closest to the outermost circumference of the wafer among the arrangement positions of the conductive patterns. | 08-09-2012 |
20120199979 | METHOD OF PROCESSING DUMMY PATTERN BASED ON BOUNDARY LENGTH AND DENSITY OF WIRING PATTERN, SEMICONDUCTOR DESIGN APPARATUS AND SEMICONDUCTOR DEVICE - A semiconductor device, includes a first wiring pattern in a first region, a second wiring pattern in a second region, and at least one first dummy pattern formed in the first region and at least one second dummy pattern formed in the second region. A total area of the at least one first dummy pattern is the same as a total area of the at least one second dummy pattern and a total length of pattern periphery of the at least one second dummy pattern is longer than a total length of pattern periphery of the at least one first dummy pattern. The first region and the second region have same area. | 08-09-2012 |
20120205810 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A method for fabricating a semiconductor device includes forming an interlayer dielectric layer including contact holes on a semiconductor substrate, forming contact patterns by filling the contact holes with a conductive material, removing the interlayer dielectric layer to expose the contact patterns, forming a spacer which has a first thickness and surrounds at least a portion of sidewalls of the contact patterns, forming a bit line extending in one direction of the contact pattern provided with the spacer, and removing the spacer to form an air gap in between the contact pattern and the bit line. | 08-16-2012 |
20120205811 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TERMINAL LOCKS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a terminal having a cornered dimple formed therein as a simple concave polygon; mounting an integrated circuit above and coupled to the terminal; and forming an encapsulation encapsulating the integrated circuit and portions of the terminal. | 08-16-2012 |
20120205812 | PATTERNS OF PASSIVATION MATERIAL ON BOND PADS AND METHODS OF MANUFACTURE THEREOF - A method includes forming a pad on an electronic component. The pad comprises conductive material. The method further includes providing passivation material on a surface of the conductive material and removing passivation material from the surface to expose portions of the conductive material to form a bond pad comprising conductive material and passivation material. | 08-16-2012 |
20120205813 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH POST-PASSIVATION INTERCONNECTION AND INTEGRATION - An integrated circuit package system including: providing an integrated circuit die, forming a first layer over the integrated circuit die, forming a bridge on and in the first layer, forming a second layer on the first layer, and forming bump pads on and in the second layer, the bump pads connected to ends of the bridge. | 08-16-2012 |
20120211891 | Anchoring Structure and Intermeshing Structure - An anchoring structure for a metal structure of a semiconductor device includes an anchoring recess structure having at least one overhanging side wall, the metal structure being at least partly arranged within the anchoring recess structure. | 08-23-2012 |
20120217642 | SEMICONDUCTOR DEVICE PACKAGES HAVING A SIDE-BY-SIDE DEVICE ARRANGEMENT AND STACKING FUNCTIONALITY - A semiconductor device package including a substrate, a first device module, a second device module, and an package body. The first device module and the second device module are disposed side-by-side on a carrier surface of the substrate. The first device module includes first connecting elements provided with a first pitch. The second device module includes second connecting elements provided with a second pitch. The first pitch is different from the second pitch. The package body is disposed on the carrier surface and covers the first chip module and the second chip module. The package body includes first openings exposing the first connecting elements and second openings exposing the second connecting elements. | 08-30-2012 |
20120223435 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a base package having a base integrated circuit over a base substrate; stacking a mountable device over the base package with a flow channel between the mountable device and the base package; and forming an external lead having a lead platform and a lead leg, the lead platform extending from the mountable device and the lead leg parallel to the base package. | 09-06-2012 |
20120223436 | SEMICONDUCTOR DEVICE AND STRUCTURE FOR HEAT REMOVAL - A semiconductor device comprising power distribution wires wherein; a portion of said wires have thermal connection to the semiconductor layer and said thermal connection designed to conduct heat but to not conduct electricity. | 09-06-2012 |
20120228776 | SEMICONDUCTOR DEVICE - A semiconductor device is formed by molding using a resin with a semiconductor element and one or two heat dissipating plates contained therein, said one or two heat dissipating plates being disposed to face one surface or both the surfaces of the semiconductor element. An intermediate layer is formed by spraying a metal powder to the semiconductor element and to one of or both of the heat dissipating plates using a cold spray method, and the semiconductor element and the heat dissipating plate are bonded together using a solder with the intermediate layer therebetween. | 09-13-2012 |
20120235303 | REINFORCEMENT STRUCTURE FOR FLIP-CHIP PACKAGING - The present disclosure provides a carrier substrate, a device including the carrier substrate, and a method of bonding the carrier substrate to a chip. An exemplary device includes a carrier substrate having a chip region and a periphery region, and a chip bonded to the chip region of the carrier substrate. The carrier substrate includes a reinforcement structure embedded within the periphery region. | 09-20-2012 |
20120235304 | ULTRAVIOLET (UV)-REFLECTING FILM FOR BEOL PROCESSING - Semiconductor devices are formed with a dielectric stack by forming an UV reflecting layer between cured and uncured ULK layers during BEOL processing. Embodiments include forming a first ultra low-k (ULK) layer on a semiconductor element, curing the first ULK layer, forming an ultraviolet (UV) reflecting layer on the first ULK layer, forming a second ULK layer on the UV reflecting layer, and irradiating the second ULK layer with UV light. | 09-20-2012 |
20120241964 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package carrier having a carrier top side; mounting an integrated circuit over the carrier top side; attaching a bottom attachment directly on the integrated circuit; dragging a sandwich connector from the bottom attachment, the sandwich connector having a connector diameter; and attaching a top attachment directly on the sandwich connector, the top attachment wider than the bottom attachment. | 09-27-2012 |
20120241965 | SOLDER IN CAVITY INTERCONNECTION STRUCTURES - The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate. | 09-27-2012 |
20120241966 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PLATED LEADS AND METHOD OF MANUFACTURE THEREOF - An integrated circuit packaging system and method of manufacture thereof includes: an L-plated lead; a die conductively connected to the L-plated lead; and an encapsulant encapsulating the L-plated lead and the die. | 09-27-2012 |
20120241967 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED CONDUCTIVE STRUCTURE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package carrier; mounting an integrated circuit device to the package carrier; mounting an embeddable conductive structure, having a non-horizontal portion between a lower portion and an elevated portion and a hole, to the integrated circuit device with the lower portion over the integrated circuit device; mounting an interposer to the lower portion and below the elevated portion; and forming an encapsulation having a recess exposing the interposer and the elevated portion. | 09-27-2012 |
20120241968 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a post of multiple plating layers having a base end with an inward protrusion, a connect riser, and a top end opposite the base end; positioning an integrated circuit device having a perimeter end facing the connect riser and the inward protrusion; attaching a bond wire directly on the inward protrusion and the integrated circuit device; and applying an encapsulation over the integrated circuit device, the bond wire, the inward protrusion, and around the post, the encapsulation exposing a portion of the base end and the top end of the post. | 09-27-2012 |
20120241969 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes: a rectangular shaped semiconductor substrate; a metal wiring layer formed on or over the semiconductor substrate; and a passivation layer covering the metal wiring layer. A corner non-wiring region where no portion of the metal wiring layer is formed is disposed in a corner of the semiconductor substrate. A slit is formed in a portion of the metal wiring layer which is close to the corner of the semiconductor substrate. The passivation layer includes a first passivation layer which is formed on the metal wiring layer and a second passivation layer which is formed on the first passivation layer. The first passivation layer is formed of a material that is softer than a material of the second passivation layer. | 09-27-2012 |
20120241970 | SEMICONDUCTOR DEVICE - Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex. | 09-27-2012 |
20120241971 | SEMICONDUCTOR DEVICE - A semiconductor device, includes a substrate, a multi-layer wiring layer formed on the substrate, and including a signal line and ground lines extending above the signal line, one of the ground lines extending toward a direction in a predetermined layer and another one of the ground lines extending from the one of the ground lines toward another direction in the predetermined layer, a first pad on the multi-layer wiring layer, a redistribution layer formed on the multi-layer wiring layer, including a second pad, a redistribution line coupling the first and second pads, and an insulation film covering the redistribution line, the redistribution line extending above the ground lines along the one of the ground lines and not extending along the another one of the ground lines. The insulation film includes a hole exposing the second pad above an end portion of the one of the ground lines. | 09-27-2012 |
20120248617 | MULTILAYERED LOW k CAP WITH CONFORMAL GAP FILL AND UV STABLE COMPRESSIVE STRESS PROPERTIES - The present disclosure provides a multilayered cap (i.e., migration barrier) that conforms to the substrate (i.e., interconnect structure) below. The multilayered cap, which can be located atop at least one interconnect level of an interconnect structure, includes, from bottom to top, a first layer comprising silicon nitride and a second layer comprising at least one of boron nitride and carbon boron nitride. | 10-04-2012 |
20120248618 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor device includes: a semiconductor substrate; an insulating film provided on a surface of the semiconductor substrate; a porous metal film provided on the insulating film; a protective film provided on the porous metal film, and having an opening portion for defining a pad region; and a wire wire-bonded to the porous metal film in the pad region. The stress generated by the impact of wire-bonding is mostly absorbed in the porous metal film owing to the distortion of the porous metal film, preventing generation of cracks in the insulating film. | 10-04-2012 |
20120248619 | CHIP PACKAGING STRUCTURE - A chip packaging structure includes a flexible plate, a chip, and a plurality of leads. The chip is disposed on the flexible plate. A first boundary and a second boundary are defined on the flexible plate. The first boundary is located between the chip and the second boundary. A first area is formed between the first boundary and the chip. A second area is formed between the first boundary and the second boundary. The chip includes a plurality of signal conducting points and a plurality of non-signal conducting points. The plurality of leads are disposed on the flexible plate and include a plurality of signal leads and a plurality of non-signal leads. The width of the non-signal lead is smaller than the width of the signal lead extending out of the second boundary. | 10-04-2012 |
20120248620 | SEMICONDUCTOR DEVICE - The semiconductor device | 10-04-2012 |
20120256318 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor substrate and a second semiconductor substrate laminated with an insulating layer, a first transmission line formed on the first semiconductor substrate, the first transmission line including a signal line and a ground, a second transmission line formed on the second semiconductor substrate, the second transmission line including a signal line and a ground, a first via layer for the signal lines, the first via layer for the signal lines being formed of a conductor layer formed within a via hole, a first via layer for the grounds, the first via layer for the grounds being formed of a conductor layer formed within a via hole, and a second via layer for the grounds, the second via layer for the grounds being formed of a conductor layer formed within a via hole. | 10-11-2012 |
20120261824 | METAL DENSITY AWARE SIGNAL ROUTING - Methods and apparatus for routing signal paths in an integrated circuit. One or more signal routing paths for transferring signals of the integrated circuit may be determined. A dummy fill pattern for the integrated circuit may be determined based on the one or more metal density specifications and at least one design rule for reducing cross coupling capacitance between the dummy fill pattern and the routing paths. The signal routing paths and/or the dummy fill pattern may be incrementally optimized to meet one or more timing requirements of the integrated circuit. | 10-18-2012 |
20120261825 | SEMICONDUCTOR DEVICE - It is made for the layout of the mounting wiring at the time of mounting to become efficient by changing the structure of a semiconductor device. | 10-18-2012 |
20120267787 | Wafer Level Chip Scale Package Method Using Clip Array - A method for wafer level chip scale package comprises providing a wafer with semiconductor chips formed thereon, forming a groove alongside each chip, providing a wafer size clip array with a plurality of clip contact areas each extending to a down set connecting bar, connecting the plurality of clip contact areas to a plurality of the electrodes disposed on a top surface of the chips with down set connecting bars disposed inside the grooves, encapsulating top of wafer in molding compound, thinning the bottom portion of the wafer and dicing the thin wafer into single chip packages. The chip has source and gate electrodes on a top surface connected to a first and second clip contact areas extending to a first a second down set connecting bars respectively, with the bottom surfaces of the down set connecting bars substantially coplanar to a drain electrode located at the chip bottom surface. | 10-25-2012 |
20120273957 | CHIP-PACKAGING MODULE FOR A CHIP AND A METHOD FOR FORMING A CHIP-PACKAGING MODULE - A chip-packaging module for a chip is provided, the chip-packaging module including an isolation material configured to cover a chip on at least one side, the isolation material having a first surface proximate to a first side of a chip, and said isolation material having a second surface facing an opposite direction to the first surface; and at least one layer in connection with the chip first side, the at least one layer further configured to extend from the chip first side to the second surface of the isolation material. | 11-01-2012 |
20120292775 | MOUNTING METHOD AND MOUNTING DEVICE - A mounting method of sequentially mounting elements on a substrate includes a mounting process of mounting one element, which is taken out by a take-out part from an accommodating part in which the elements are accommodated, on a first contact region of the surface of the substrate where a liquid is coated. The method further includes a coating process of coating a liquid, by a coating part movably provided together with the take-out part, on a contact region of the surface of the substrate different from the first contact region when the one element is mounted on the first region. | 11-22-2012 |
20120292776 | PAD LAYOUT STRUCTURE OF SEMICONDUCTOR CHIP - Provided is a pad layout structure of a semiconductor chip capable of preventing lead-broken problems when packaging the semiconductor chip with a high aspect ratio in a tape carrier package (TCP). In the pad layout structure of the semiconductor chip, a plurality pads are arranged along upper, lower, left and right sides of the semiconductor chip with a high aspect ratio, and a longitudinal width of pads arranged at the left and right sides and a transverse width of pads arranged at both edges of the upper and lower sides are greater than a transverse width of pads arranged at centers of the upper and lower sides. | 11-22-2012 |
20120299188 | WIRING STRUCTURE AND METHOD OF FORMING THE STRUCTURE - Disclosed is a wiring structure and method of forming the structure with a conductive diffusion barrier layer having a thick upper portion and thin lower portion. The thicker upper portion is located at the junction between the wiring structure and the adjacent dielectric materials. The thicker upper portion: (1) minimizes metal ion diffusion and, thereby TDDB; (2) allows a wire width to dielectric space width ratio that is optimal for low TDDB to be achieved at the top of the wiring structure; and (3) provides a greater surface area for via landing. The thinner lower portion: (1) allows a different wire width to dielectric space width ratio to be maintained in the rest of the wiring structure in order to balance other competing factors; (2) allows a larger cross-section of wire to reduce current density and, thereby reduce EM; and (3) avoids an increase in wiring structure resistivity. | 11-29-2012 |
20120299189 | SEMICONDUCTOR MEMORY DEVICE, METHOD OF MANUFACTURING THE SAME AND METHOD OF FORMING CONTACT STRUCTURE - When a first wiring and/or a second wiring is formed, a connection portion is formed in the first wiring and/or the second wiring which covers a part of a lower electrode layer outside the memory cell array. An etching suppressing portion is formed above the connection portion. A contact hole is formed in which a portion under the etching suppressing portion reaches up to a connection potion, and the other portion reaches up to the lower electrode layer by performing etching to a laminated body in a range including the etching suppressing portion. The laminated body includes the insulating layer, the first wiring, a memory cell layer, the second wiring, and the etching suppressing portion. The contact layer is formed by burying a conductive material in the contact hole. | 11-29-2012 |
20120306088 | METHOD AND SYSTEM FOR INTERNAL LAYER-LAYER THERMAL ENHANCEMENT - The exemplary embodiments of the present invention provide a method and apparatus for enhancing the cooling of a chip stack of semiconductor chips. The method includes creating a first chip with circuitry on a first side and creating a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The method further includes creating a cavity in a second side of the first chip between the connectors and filling the cavity with a thermal material. The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes wherein portions of a second side of the first chip between the connectors is removed to provide a cavity in which a thermal material is placed. | 12-06-2012 |
20120306089 | APPARATUSES INCLUDING STAIR-STEP STRUCTURES AND METHODS OF FORMING THE SAME - Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from of the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. Apparatuses such as memory devices including laterally adjacent first and second regions each including contact regions of a different portion of a plurality of conductive materials and related methods of forming such devices are also disclosed. | 12-06-2012 |
20120306090 | CONDUCTIVE STRUCTURES, SYSTEMS AND DEVICES INCLUDING CONDUCTIVE STRUCTURES AND RELATED METHODS - Conductive structures include a plurality of conductive steps and a contact extending at least partially therethrough in communication with at least one of the plurality of conductive steps and insulated from at least another one of the conductive steps. Devices may include such conductive structures. Systems may include a semiconductor device and a stair step conductive structure having a plurality of contacts extending through a step of the stair step conductive structure. Methods of forming conductive structures include forming contacts in contact holes formed through at least one conductive step of a conductive structure. Methods of forming electrical connections in stair step conductive structures include forming contacts in contact holes formed through each step of the stair step conductive structure. | 12-06-2012 |
20120306091 | Connecting System for Electrically Connecting Electronic Devices and Method for Connecting an Electrically Conductive First Connector and Electrically Conductive Second Connector - A semiconductor module system includes a substrate, at least one semiconductor chip, and a number of at least two electrically conductive first connecting elements. The substrate has a bottom side and a top side spaced apart from the bottom side in a vertical direction. The at least one semiconductor chip is arranged on the top side. Each one of the first connecting elements has a first end which protrudes away from an insulation carrier of the substrate in a direction perpendicular to the vertical direction. The semiconductor system further includes a connecting system with a number of N≧1 connectors. A first one of the connectors includes at least two electrically conductive second connecting elements. Each one of the second connecting elements has a first end. The first end of each one of the first connecting elements is electrically conductively connectable to the first end of one of the second connecting elements. | 12-06-2012 |
20120306092 | CONDUCTIVE PADS DEFINED BY EMBEDDED TRACES - An assembly and method of making same are provided. The assembly can include a first component including a dielectric region having an exposed surface, a conductive pad at the surface defined by a conductive element having at least a portion extending in an oscillating or spiral path along the surface, and a an electrically conductive bonding material joined to the conductive pad and bridging an exposed portion of the dielectric surface between adjacent segments. The conductive pad can permit electrical interconnection of the first component with a second component having a terminal joined to the pad through the electrically conductive bonding material. The path of the conductive element may or may not overlap or cross itself. | 12-06-2012 |
20120313250 | Forming Features on a Substrate Having Varying Feature Densities - A method includes forming a cavity in a substrate, depositing a layer of conductive material in the cavity and over exposed portions of the substrate, removing portions of the conductive material to expose portions of the substrate using a planarizing process, and removing residual portions of the conductive material disposed on the substrate using a reactive ion etch (RIE) process. | 12-13-2012 |
20120313251 | INTERCONNECT STRUCTURE WITH IMPROVED ALIGNMENT FOR SEMICONDUCTOR DEVICES - Methods and structure are provided for creating and utilizing hard masks to facilitate creation of a grating effect to control an anisotropic etching process for the creation of an opening, and subsequent formation of a interconnect structure (e.g., a via) in a multilayered semiconductor device. A first hard mask can be patterned to control etching in a first dimension, and a second hard mask can be patterned to control etching in a second dimension, wherein the second hard mask is patterned orthogonally opposed to the first hard mask. A resist can be patterned by inverting the pattern of a metal line patterning. Interconnects can be formed with critical dimension(s) and also self-aligned. | 12-13-2012 |
20120313252 | SEMICONDUCTOR DEVICE - A semiconductor device includes a base plate having one main surface joined to an insulating substrate on which a semiconductor chip and the like are mounted and a transfer mold resin which is so provided as to cover the one main surface of the base plate, the insulating substrate, the semiconductor chip, and the like and expose the other main surface of the base plate. The coefficient of linear expansion of the base plate is lower than that of copper and the coefficient of linear expansion of the transfer mold resin is not higher than 16 ppm/° C. The transfer mold resin has such scooped shapes as to expose opposed short-side centers and the vicinity of the base plate, respectively. The base plate has mounting holes in portions exposed by the scooped shapes of the transfer mold resin. | 12-13-2012 |
20120319284 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE ON PACKAGE SUPPORT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated packaging system includes: providing a substrate; mounting a die over the substrate; mounting an interposer having a slot over the die; covering a first encapsulant over the die and the interposer, a central region of the interposer exposed from the first encapsulant; and forming a hole through the first encapsulant to expose a peripheral portion of the interposer. | 12-20-2012 |
20120319285 | INTEGRATED CIRCUITS INCLUDING BARRIER POLISH STOP LAYERS AND METHODS FOR THE MANUFACTURE THEREOF - Embodiments of a method for fabricating integrated circuits are provided, as are embodiments of an integrated circuit. In one embodiment, the method includes the steps of depositing an interlayer dielectric (“ILD”) layer over a semiconductor device, depositing a barrier polish stop layer over the ILD layer, and patterning at least the barrier polish stop layer and the ILD layer to create a plurality of etch features therein. Copper is plated over the barrier polish stop layer and into the plurality of etch features to produce a copper overburden overlying the barrier polish stop layer and a plurality of conductive interconnect features in the ILD layer and barrier polish stop layer. The integrated circuit is polished to remove the copper overburden and expose the barrier polish stop layer. | 12-20-2012 |
20120319286 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUPPORT STRUCTURE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a connection post on the substrate, the connection post having a post top and a post side; mounting an integrated circuit die on the substrate, the integrated circuit die having a top die surface; molding an encapsulation on the integrated circuit die and the connection post; and forming a connector recess in the encapsulation by removing the encapsulation around the connection post exposing a portion of the post side. | 12-20-2012 |
20120319287 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING SEMICONDUCTOR LAYOUT - A method for fabricating a semiconductor layout includes providing a first layout having a plurality of line patterns and a second layout having a plurality of connection patterns, defining at least a first to-be-split pattern overlapping with the connection pattern among the line patterns, splitting the first to-be-split pattern at where the first to-be-split pattern overlapping with the connection pattern, decomposing the first layout to form a third layout and a fourth layout, and outputting the third layout and the further layout to a first mask and a second mask respectively. | 12-20-2012 |
20120319288 | Semiconductor Package - A semiconductor package and a carrier for a semiconductor package are provided, the carrier having a top surface and a bottom surface separated by side walls. The carrier includes a seat for a component, and at least one terminal region for electrically connecting the component to the carrier when mounted to the seat, wherein a test portal is arranged at an outer surface of the carrier, and wherein one or more routing paths are arranged in the carrier for routing one or more electrical contacts arranged at the carrier to the test portal. | 12-20-2012 |
20120319289 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a semiconductor chip having plural electrode pads, and a wiring substrate having plural electrode pads to mount the semiconductor chip on the wiring substrate, wherein the plural electrode pads of the semiconductor chip include a first electrode pad, and a second electrode pad arranged on an outer periphery side of the first electrode pad, the plural electrode pads of the wiring substrate include a third electrode pad, and a fourth electrode pad arranged on an outer periphery side of the third electrode pad, the first electrode pad and the third electrode pad are connected via a first connecting portion, and the second electrode pad and the fourth electrode pad are connected via a second connecting portion including a pin. | 12-20-2012 |
20120319290 | ELECTRICAL CONNECTION FOR MULTICHIP MODULES - A semiconductor chip is provided. The semiconductor chip includes a semiconductor substrate, a circuit on the substrate, an insulating layer formed on the circuit, and a plurality of electrically floating conductor lines formed on the insulating layer, at a major surface of the semiconductor chip. | 12-20-2012 |
20120326322 | CHIP PACKAGE WITH REINFORCED POSITIVE ALIGNMENT FEATURES - A chip package includes a substrate having a positive feature, which is defined on a surface of the substrate and which protrudes above a region on the surface proximate to the positive feature. Furthermore, the chip package includes a mechanical reinforcement mechanism defined on the substrate proximate to the positive feature that increases a lateral shear strength of the positive feature relative to the substrate. In this way, the chip package may facilitate increased reliability of a multi-chip module (MCM) that includes the chip package. | 12-27-2012 |
20120326323 | HIGH VOLTAGE HIGH PACKAGE PRESSURE SEMICONDUCTOR PACKAGE - A hermetically sealed integrated circuit package that includes a cavity housing a semiconductor die, whereby the cavity is pressurized during assembly and when formed. The invention prevents the stress on a package created when the package is subject to high temperatures at atmospheric pressure and then cooled from reducing the performance of the die at high voltages. By packaging a die at a high pressure, such as up to 60 PSIG or more, in an atmosphere with an inert gas, and providing a large pressure in the completed package, the dies are significantly less likely to arc at higher voltages, allowing the realization of single die packages operable up to at least 1200 volts or more. Moreover, the present invention is configured to employ brazed elements compatible with Silicon Carbide dies which can be processed at higher temperatures. | 12-27-2012 |
20130001790 | SYSTEM ON A CHIP WITH INTERLEAVED SETS OF PADS - A system on a chip (SOC) includes a physical interface having first and second sets of interface pads. Interface pads from the first set are interleaved with interface pads from the second set. Additionally, the SOC is arranged for operation with a superset die having first and second personalities and has a physical interface with interface pads. The SOC uses a first number of interface pads in the first personality and a second number of interface pads in the second personality, where the first number is greater than the second number. A switch switches signals between the superset die and the physical interface and, in the second personality, switches signals to the physical interface so that interface pads in the second number of interface pads are interleaved with interface pads not in use in the second personality. | 01-03-2013 |
20130001791 | Method and Apparatuses for Integrated Circuit Substrate Manufacture - Embodiments described herein provide a method of manufacturing integrated circuit (IC) devices. The method includes coupling a first surface of a first intermediate substrate to a first surface of a second intermediate substrate, forming a first plurality of patterned metal layers on a second surface of the first intermediate substrate to form a first substrate and a second plurality of patterned metal layers on a second surface of the second intermediate substrate to form a second substrate, and separating the first and second substrates. Each of the first substrate and the second substrate is configured to facilitate electrical interconnection between a respective IC die and a respective printed circuit board (PCB). | 01-03-2013 |
20130001792 | SEMICONDUCTOR DEVICE - A power MOSFET for switching and a sense MOSFET having an area smaller than that of the power MOSFET and configured to detect an electric current flowing through the power MOSFET are formed within one semiconductor chip CPH and the semiconductor chip CPH is mounted over a chip mounting part via an electrically conductive joining material and sealed with a resin. In a main surface of the semiconductor chip CPH, a sense MOSFET region in which the sense MOSFET is formed is located more internally than a source pad PDHS | 01-03-2013 |
20130009313 | SEMICONDUCTOR DEVICE PACKAGES WITH SOLDER JOINT ENHANCEMENT ELEMENT AND RELATED METHODS - A semiconductor device package including a substrate, first and second solder joints, a die pad, leads and enhancement elements surrounding the die pad, a chip electrically connected to the leads, and a package body encapsulating the chip, portions of the leads, and portions of the enhancement elements, but leaving exposed at least a side surface of each enhancement element. Side surfaces of the enhancement elements and the package body are coplanar. The substrate includes first pads corresponding to the leads and second pads corresponding to the enhancement elements. The first solder joints are disposed between the first pads and the leads. The second solder joints are disposed between the second pads and the enhancement elements. The second solder joints contact side surfaces of the enhancement elements. The surface area of the second pads is greater than the surface area of the corresponding enhancement elements. | 01-10-2013 |
20130009314 | TEST CIRCUIT, INTEGRATED CIRCUIT, AND TEST CIRCUIT LAYOUT METHOD - A test circuit includes a substrate, a wiring section having a plurality of pieces of wiring, and a device-under-test section formed on the substrate, and having a device-under-test main body and a plurality of connecting electrodes for establishing connection between the main body and the plurality of pieces of wiring, an extending direction of a straight line connecting a position of a center of rotation in a plane of pattern formation of the main body and each electrodes being inclined at a predetermined angle to an extending direction of the pieces of wiring, and the connecting electrodes being arranged at positions such that connection relation between the electrodes and the plurality of pieces of wiring is maintained even when the main body and the electrodes are rotated about the position of the center of rotation by 90 degrees relative to the wiring section in the plane of the pattern formation. | 01-10-2013 |
20130015583 | Chip Comprising an Integrated Circuit, Fabrication Method and Method for Locally Rendering a Carbonic Layer ConductiveAANM Hoeckele; UweAACI RegensburgAACO DEAAGP Hoeckele; Uwe Regensburg DE - A chip includes an integrated circuit and a carbonic layer. The carbonic layer includes a graphite-like carbon, wherein a lateral conducting path through the graphite-like carbon electrically connects two circuit elements of the integrated circuit. | 01-17-2013 |
20130015584 | OPTOELECTRONIC SEMICONDUCTOR DEVICE - An optoelectronic semiconductor device includes a substrate, a semiconductor system having an active layer formed on the substrate and an electrode structure formed on the semiconductor system, wherein the layout of the electrode structure having at least a first conductivity type contact zone or a first conductivity type bonding pad, a second conductivity type bonding pad, a first conductivity type extension electrode, and a second conductivity type extension electrode wherein the first conductivity type extension electrode and the second conductivity type extension electrode have three-dimensional crossover, and partial of the first conductivity type extension electrode and the first conductivity type contact zone or the first conductivity type bonding pad are on the opposite sides of the active layer. | 01-17-2013 |
20130020711 | Interconnect Pillars with Directed Compliance Geometry - Pillars having a directed compliance geometry are arranged to couple a semiconductor die to a substrate. The direction of maximum compliance of each pillar may be aligned with the direction of maximum stress caused by unequal thermal expansion and contraction of the semiconductor die and substrate. Pillars may be designed and constructed with various shapes having particular compliance characteristics and particular directions of maximum compliance. The shape and orientation of the pillars may be selected as a function of their location on a die to accommodate the direction and magnitude of stress at their location. A method includes fabricating pillars with particular shapes by patterning to increase surface of materials upon which the pillar is plated or deposited. | 01-24-2013 |
20130020712 | IMPLEMENTING INTEGRATED CIRCUIT MIXED DOUBLE DENSITY AND HIGH PERFORMANCE WIRE STRUCTURE - A method and structures are provided for implementing an integrated circuit with an enhanced wiring structure of mixed double density and high performance wires in a common plane. A wiring structure includes a first wire having a first plane and a first via to a second wire in a second plane having a second via and a third wire having the first plane with height equal to the first wire and the first via, and a third via having a height equal to the second wire and the second via. | 01-24-2013 |
20130020713 | Wafer Level Package and a Method of Forming a Wafer Level Package - In an embodiment, a wafer level package may be provided. The wafer level package may include a device wafer including a MEMS device, a cap wafer disposed over the device wafer, at least one first interconnect disposed between the device wafer and the cap wafer and configured to provide an electrical connection between the device wafer and the cap wafer, and a conformal sealing ring disposed between the device wafer and the cap wafer and configured to surround the at least one first interconnect and the MEMS device so as to provide a conformally sealed environment for the at least one first interconnect and the MEMS device, wherein the conformal sealing ring may be configured to conform to a respective suitable surface of the device wafer and the cap wafer when the device wafer may be bonded to the cap wafer. A method of forming a wafer level package may also be provided. | 01-24-2013 |
20130020714 | CONTACT PAD - A contact pad for an electronic device integrated in a semiconductor material chip is formed from a succession of protruding elements. Each protruding element extends transversally to a main surface of the chip and has a rounded terminal portion. Adjacent pairs protruding elements define an opening which is partially filled with a first conductive material to form a contact structure that is in electrical contact with an integrated electronic device formed in the chip. A layer of a second conductive material is deposited to cover said protruding elements and the contact structures so as to form the contact pad. | 01-24-2013 |
20130020715 | Semiconductor Device - A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad. | 01-24-2013 |
20130026639 | Method of fabricating dual damascene structures using a multilevel multiple exposure patterning scheme - A method for fabricating a dual damascene structure includes providing a first photoresist layer coated on an underlying dielectric stack, exposing said first photoresist layer to a first predetermined pattern of light, coating a second photoresist layer onto the pre-exposed first photoresist layer, exposing said second photoresist layer to a second predetermined pattern of light, optionally post-exposure baking the multi-tiered photoresist layers and developing said photoresist layers to form a multi-tiered dual damascene structure in the photoresist layers. | 01-31-2013 |
20130026640 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, CIRCUIT SUBSTRATE, AND ELECTRONIC APPARATUS - A semiconductor device includes: a semiconductor substrate including a first face and a second face on a side opposite to the first face; an external connection terminal formed on the first face of the semiconductor substrate; a first electrode formed on the first face of the semiconductor substrate and electrically connected to the external connection terminal; an electronic element formed on or above the second face of the semiconductor substrate; a second electrode electrically connected to the electronic element and having a top face and a rear face; a groove portion formed on the second face of the semiconductor substrate and having a bottom face including at least part of the rear face of the second electrode; and a conductive portion formed in the groove portion and electrically connected to the rear face of the second electrode. | 01-31-2013 |
20130032943 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip which includes a first circuit and a second circuit that are spaced apart from each other, without internal wirings electrically connecting the first circuit and the second circuit to each other, a substrate on which the semiconductor chip is disposed, and substrate wirings that are arranged on the substrate and electrically connect the first circuit and the second circuit to each other. | 02-07-2013 |
20130037958 | CMOS Image Sensor and Method for Forming the Same - An integrated circuit structure includes an interconnect structure that includes a plurality of metal layers, wherein the interconnect structure is under a semiconductor substrate. A metal pad is formed in one of the plurality of metal layers. A dielectric pad extends from a bottom surface of the semiconductor substrate up into the semiconductor substrate. An opening extends from a top surface of the semiconductor substrate down to penetrate through the semiconductor substrate and the dielectric pad. An edge of the semiconductor substrate in the opening is vertically aligned to an edge of the dielectric pad in the opening. The opening stops on a top surface of the metal pad. A dielectric spacer is disposed in the opening, wherein the dielectric spacer is formed on the edge of the semiconductor substrate and the edge of the dielectric pad. | 02-14-2013 |
20130043595 | Semiconductor Package Containing Silicon-On-Insulator Die Mounted In Bump-On-Leadframe Manner To Provide Low Thermal Resistance - Thermal transfer from a silicon-on-insulator (SOI) die is improved by mounting the die in a bump-on-leadframe manner in a semiconductor package, with solder or other metal bumps connecting the active layer of the SOI die to metal leads used to mount the package on a printed circuit board or other support structure. | 02-21-2013 |
20130043596 | SEMICONDUCTOR DEVICE - A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern. | 02-21-2013 |
20130049205 | Semiconductor Device and Method of Manufacturing a Semiconductor Device Including Grinding Steps - A method of manufacturing a device includes providing a semiconductor chip having a first face and a second face opposite to the first face with a contact pad arranged on the first face. The semiconductor chip is placed on a carrier with the first face facing the carrier. The semiconductor chip is encapsulated with an encapsulation material. The carrier is removed and the semiconductor material is removed from the second face of the first semiconductor chip without removing encapsulation material at the same time. | 02-28-2013 |
20130049206 | Bond Pad Configurations for Controlling Semiconductor Chip Package Interactions - Generally, the subject matter disclosed herein relates to sophisticated semiconductor chips that may be less susceptible to the occurrence of white bumps during semiconductor chip packaging operations, such as flip-chip or 3D-chip assembly, and the like. One illustrative semiconductor chip disclosed herein includes at least one integrated circuit device and a bond pad that is electrically connected to the at least one integrated circuit device. Furthermore, the bond pad has an irregular overall configuration when viewed from above that corresponds to a first area portion that is defined by a first substantially regular geometric shape when viewed from above and a second area portion adjacent to the first area portion. Additionally, the second area portion is located at a greater distance from a centerline of the semiconductor chip than any part of the first area portion when viewed from above, and the bond pad is electrically connected to the at least one integrated circuit device. | 02-28-2013 |
20130049207 | MULTIPLE STEP ANNEAL METHOD AND SEMICONDUCTOR FORMED BY MULTIPLE STEP ANNEAL - A method of annealing a semiconductor and a semiconductor. The method of annealing including heating the semiconductor to a first temperature for a first period of time sufficient to remove physically-adsorbed water from the semiconductor and heating the semiconductor to a second temperature, the second temperature being greater than the first temperature, for a period of time sufficient to remove chemically-adsorbed water from the semiconductor. A semiconductor device including a plurality of metal conductors, and a dielectric including regions separating the plurality of metal conductors, the regions including an upper interface and a lower bulk region, the upper interface having a density greater than a density of the lower bulk region. | 02-28-2013 |
20130049208 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH REDISTRIBUTION LAYER AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a peripheral interconnect having a bond finger and a contact pad with a trace in direct contact with the bond finger and the contact pad, the bond finger vertically offset from the contact pad; connecting an integrated circuit die and the bond finger; and forming a module encapsulation on the integrated circuit die, the bond finger and the trace exposed from the module encapsulation. | 02-28-2013 |
20130049209 | SEMICONDUCTOR DEVICE WITH DAMASCENE BIT LINE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes first conductive patterns adjacent to each other and isolated by a trench including first and second trenches, a second conductive pattern formed in the first trench, and an insulating pattern partially filling the second trench under the second conductive pattern and formed between the first conductive patterns and the second conductive pattern. | 02-28-2013 |
20130049210 | SEMICONDUCTOR WAFER AND LAMINATE STRUCTURE INCLUDING THE SAME - According to one embodiment, a semiconductor wafer includes a semiconductor substrate and an interconnect layer formed on the semiconductor substrate. In the semiconductor wafer, the semiconductor substrate includes a first region that is located on the outer periphery side of the semiconductor substrate and that is not covered with the interconnect layer. The interconnect layer includes a second region where the upper surface of the interconnect layer is substantially flat. A first insulating film is formed in the first region. The upper surface of the interconnect layer within the second region and the upper surface of the first insulating film substantially flush with each other. | 02-28-2013 |
20130056874 | Protection of intermetal dielectric layers in multilevel wiring structures - A semiconductor device is accepted at a stage of its fabrication, at which stage the device includes a diffusion-barrier cap-material (DBCM) layer and an intermetal dielectric layer covering the DBCM layer. The DBCM layer is exposed and it is suitable for removal by an etching procedure in a portion of a pattern contained in the intermetal dielectric layer. A silylation treatment is performed on the semiconductor device prior to the etching procedure for removing the DBCM layer. The intermetal dielectric layer of the completed device has surfaces in contact with metal interconnects and metal vias, and it may have an excess of carbon content near at least a portion of the these surfaces. | 03-07-2013 |
20130056875 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor substrate having a main surface; an electrode in a device region on the main surface; a metal wiring on the main surface and having a first end connected to the electrode; an electrode pad outside the device region and spaced from the metal wiring; an air gap between the main surface and an air gap forming film on the main surface, enveloping the first end of the metal wiring and the electrode, and having a first opening; a resin closing the first opening and covering a second end of the metal wiring; a liquid repellent film facing the air gap and increasing contact angle of the resin, when liquid, relative to contact angles on the semiconductor substrate and the air gap forming film; and a metal film connecting the metal wiring to the electrode pad through a second opening located in the resin. | 03-07-2013 |
20130056876 | COMPOSITE ELECTRODE AND METHOD OF MANUFACTURE THEREOF - The present invention provides a composite electrode and method of manufacturing such a composite electrode, the method comprising the steps of: providing a first substrate layer with an electrically conducting surface; providing a non-conducting curable material; providing a second substrate layer which has a surface relief pattern defining at least one retaining feature corresponding to a desired metal track pattern; forming a line of contact between the conducting carrier layer and at least a part of the surface relief pattern; depositing curable material onto at least part of the surface relief pattern or the electrically conducting surface along the line of contact; advancing the line of contact and curing the curable material through the second substrate layer; releasing the cured material from the surface relief pattern feature so as to leave behind a surface relief pattern on the conducting carrier layer; depositing a first metal layer onto the exposed regions of the electrically conducting surface of the conducting carrier layer and optionally deposition further metal layers on the first metal layer. | 03-07-2013 |
20130062771 | DESIGN METHOD OF WIRING LAYOUT, SEMICONDUCTOR DEVICE, PROGRAM FOR SUPPORTING DESIGN OF WIRING LAYOUT, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a design method of layout formed by a sidewall method is provided. The method includes: preparing a base pattern on which a plurality of first patterns extending in a first direction and arranged at a first space in a second direction intersecting the first direction and a plurality of second patterns extending in the first direction and arranged at a center between the first patterns, respectively, are provided; and drawing a connecting portion which extends in the second direction and connects two neighboring first patterns sandwiching one of the second patterns, and separating the one of the second patterns into two patterns not contacting the connecting portion. | 03-14-2013 |
20130062772 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - In a method for fabricating a semiconductor device, first, a first metal interconnect is formed in an interconnect formation region, and a second metal interconnect is formed in a seal ring region. Subsequently, by chemical mechanical polishing or etching, the upper portions of the first metal interconnect and the second metal interconnect are recessed to form recesses. A second insulating film filling the recesses is then formed above a substrate, and the upper portion of the second insulating film is planarized. Next, a hole and a trench are formed to extend halfway through the second insulating film, and ashing and polymer removal are performed. Subsequently to this, the hole and the trench are allowed to reach the first metal interconnect and the second metal interconnect. | 03-14-2013 |
20130075915 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CHIP STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a first substrate; mounting an integrated circuit structure on the first substrate; mounting a second substrate on the integrated circuit structure; coupling a vertical chip to the first substrate and to the second substrate; and forming a package body for encapsulating the integrated circuit structure, the vertical chip, and a portion of the second substrate. | 03-28-2013 |
20130075916 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EXTERNAL WIRE CONNECTION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package carrier; mounting an integrated circuit to the package carrier; forming an external wire on the package carrier and adjacent to the integrated circuit; forming an encapsulation on the package carrier over the external wire; and forming a hole in the encapsulation with the external wire and a portion of the package carrier exposed from the encapsulation. | 03-28-2013 |
20130075917 | Multi-Chip and Multi-Substrate Reconstitution Based Packaging - Embodiments for multi-chip and multi-substrate reconstitution based packaging are provided. Example packages are formed using substrates from a reconstitution. substrate panel or strip. The reconstitution substrate panel or strip may include known good substrates of same or different material types and/or same of different layer counts and sizes. As such, different combinations of reconstitution substrates and chips can be used within the same package, thereby allowing substrate customization according to semiconductor chip block(s) and types contained in the package. | 03-28-2013 |
20130075918 | SHIFT REGISTER MEMORY - In one embodiment, a shift register memory includes a substrate, and a channel layer provided on the substrate, and having a helical shape rotating around an axis which is perpendicular to a surface of the substrate. The memory further includes at least three control electrodes provided on the substrate, extending in a direction parallel to the axis, and to be used to transfer charges in the channel layer. | 03-28-2013 |
20130075919 | Semiconductor Device and Method of Forming FO-WLCSP Having Conductive Layers and Conductive Vias Separated by Polymer Layers - A Fo-WLCSP has a first polymer layer formed around a semiconductor die. First conductive vias are formed through the first polymer layer around a perimeter of the semiconductor die. A first interconnect structure is formed over a first surface of the first polymer layer and electrically connected to the first conductive vias. The first interconnect structure has a second polymer layer and a plurality of second vias formed through the second polymer layer. A second interconnect structure is formed over a second surface of the first polymer layer and electrically connected to the first conductive vias. The second interconnect structure has a third polymer layer and a plurality of third vias formed through the third polymer layer. A semiconductor package can be mounted to the WLCSP in a PoP arrangement. The semiconductor package is electrically connected to the WLCSP through the first interconnect structure or second interconnect structure. | 03-28-2013 |
20130082388 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - According to one embodiment, a first core pattern is formed in a wiring portion on a process target film and a second core pattern, which is led out from the first core pattern and includes an opening, is formed in a leading portion on the process target film, a sidewall pattern is formed along an outer periphery of the first core pattern and the second core pattern and a sidewall dummy pattern is formed along an inner periphery of the opening of the second core pattern, the first core pattern and the second core pattern are removed, and the process target film is processed to transfer the sidewall pattern and the sidewall dummy pattern. | 04-04-2013 |
20130082389 | STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE - A microelectronic package can include a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are joined to corresponding contacts on a surface of the substrate. An axial plane may intersect the face along a line in the first direction and centered relative to the columns of element contacts. Columns of package terminals can extend in the first direction. First terminals in a central region of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between the columns of package terminals. The axial plane can intersect the central region. | 04-04-2013 |
20130082390 | STUB MINIMIZATION USING DUPLICATE SETS OF TERMINALS FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS - A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face facing away from a substrate of the package, and electrically connected with the substrate through conductive structure extending above the front face. First terminals provided in first and second parallel grids or in first and second individual columns can be configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid can have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid. | 04-04-2013 |
20130082391 | STUB MINIMIZATION FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS - A microelectronic assembly can include a circuit panel having first and second surfaces and panel contacts at each surface, and first and second microelectronic packages having terminals mounted to the panel contacts at the first and second surfaces, respectively. The circuit panel can electrically interconnect terminals of the first package with corresponding terminals of the second package. Each package can include a substrate having first and second surfaces, a microelectronic element, conductive structure extending above a front face of the microelectronic element, and parallel columns of terminals at the second surface. The terminals of each package can include first terminals in a central region of the respective second surface and configured to carry address information usable by circuitry within the package to determine an addressable memory location within the respective microelectronic element. Each central region can have a width within three and one-half times a minimum pitch between adjacent terminals. | 04-04-2013 |
20130082392 | DEVICE WITH CONTACT ELEMENTS - A device with contact elements. One embodiment provides an electrical device including a structure defining a main face. The structure includes an array of cavities and an array of overhang regions, each overhang region defining an opening to one of the cavities. The electrical device further includes an array of contact elements, each contact element only partially filling one of the cavities and protruding from the structure over the main face. | 04-04-2013 |
20130082393 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An upper surface of a plug (PL | 04-04-2013 |
20130087920 | Integrated Circuit Structure Having Dies with Connectors of Different Sizes - An embodiment is a structure comprising a substrate, a first die, and a second die. The substrate has a first surface. The first die is attached to the first surface of the substrate by first electrical connectors. The second die is attached to the first surface of the substrate by second electrical connectors. A size of one of the second electrical connectors is smaller than a size of one of the first electrical connectors. | 04-11-2013 |
20130087921 | Semiconductor Arrangement for Galvanically Isolated Signal Transmission and Method for Producing Such an Arrangement - A semiconductor arrangement includes an artificial chip having a semiconductor chip and an electrically insulating molding compound. The semiconductor chip has circuit structures and is embedded into the molding compound at all sides other than at a base area of the semiconductor chip in such a way that a base area of the artificial chip is enlarged by the molding compound relative to the base area of the semiconductor chip. A thin-film substrate is applied to the enlarged base area and extends beyond the base area of the semiconductor chip into the enlarged base area. The substrate has at least two layers composed of nonconductive material between which a structured metallization is disposed. A first coil is formed by one or a plurality of structured metallization layers in the substrate. A second coil is magnetically and/or capacitively coupled to the first coil and galvanically isolated from the first coil. | 04-11-2013 |
20130087922 | Semiconductor Resistance Element, Semiconductor Module Including The Same, And Processor-Based System Including The Semiconductor Module - Provided may be a semiconductor resistance element including resistance patterns disposed on an insulating substrate. The substrate may have first and second planer surfaces disposed in a first direction, third and fourth planar surfaces at least between the first and second planar surfaces in a second direction and fifth and sixth planar surfaces at least between the first and second planar surfaces in a third direction. The semiconductor resistance element may include a first resistance pattern configured to cover a selected one of the first and second planar surfaces and a second resistance pattern on at least one of the third through sixth planar surfaces. | 04-11-2013 |
20130087923 | MULTI COMPONENT DIELECTRIC LAYER - An in-situ process is described incorporating plasma enhanced chemical vapor deposition comprising flowing at least one of a Si, Si═C, B, Si═B, Si═B═C, and B═C containing precursor, and a N containing precursors at first times and removing the N precursor at second times and starting the flow of an oxidant gas and a porogen gas into the chamber. A dielectric layer is described comprising a network having inorganic random three dimensional covalent bonding throughout the network which contains at least one SiCN, SiCNH, SiN, SiNH, BN, BNH, CBN, CBNH, BSiN, BSiNH, SiCBN and SiCBNH as a first component and a low k dielectric as a second component adjacent thereto. | 04-11-2013 |
20130087924 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - Disclosed is a semiconductor device provided with: lower-layer wiring formed on a substrate, an interlayer insulating film covering the lower-layer wiring, and a first upper-layer wiring line ( | 04-11-2013 |
20130093094 | Method and Apparatus for Die Assembly - Methods and apparatus for die assembly. A method includes forming a trench extending from an active surface of a semiconductor substrate comprising a plurality of integrated circuit dies having connector terminals extending from the active surface, the trench extending into, but not through, the semiconductor substrate; forming a protective layer overlying the active surface of the semiconductor substrate and the trench, and covering the lower portion of the connector terminals; opening a pre-dicing opening in the protective layer and within the trench; applying a tape over the active surface of the semiconductor wafer, the protective layer and the connector terminals; and performing an operation on a backside of the semiconductor substrate to remove material until the pre-dicing opening is exposed on the backside of the semiconductor wafer. An apparatus includes a semiconductor substrate with integrated circuits and a protective layer surrounding connector terminals of integrated circuits. | 04-18-2013 |
20130093095 | SEMICONDUCTOR MODULE - A semiconductor module includes a semiconductor having a semiconductor substrate, a first electrode formed on one surface of the semiconductor substrate, and a second electrode formed on an opposite surface of the semiconductor substrate. A first conductive member is in contact with the first electrode. A second conductive member is in contact with the second electrode. A third conductive member is in contact with the second conductive member and extends along the first conductive member. An insulating member provides insulation between the first conductive member and the third conductive member. The third conductive member is fixed to the first conductive member and the second conductive member by being sandwiched between the first conductive member and the second conductive member. The semiconductor device is fixed to the first conductive member and the second conductive member by being sandwiched between the first conductive member and the second conductive member. | 04-18-2013 |
20130093096 | SEMICONDUCTOR DEVICE - A semiconductor device with a transistor region has a first conductor pattern formed within a multilayer interconnect structure positioned under a signal line and above the transistor region. The first conductor pattern is coupled to ground or a power supply and overlaps the transistor region. The signal line overlaps the first conductor pattern. | 04-18-2013 |
20130099385 | Packages and Methods for Forming the Same - A device includes a package component having conductive features on a top surface, and a polymer region molded over the top surface of the first package component. A plurality of openings extends from a top surface of the polymer region into the polymer region, wherein each of the conductive features is exposed through one of the plurality of openings. The plurality of openings includes a first opening having a first horizontal size, and a second opening having a second horizontal size different from the first horizontal size. | 04-25-2013 |
20130099386 | SEMICONDUCTOR MEMORY DEVICE HAVING CELL PATTERNS ON INTERCONNECTION AND FABRICATION METHOD THEREOF - A semiconductor memory device having a cell pattern formed on an interconnection and capable of reducing an interconnection resistance and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate in which a cell area, a core area, and a peripheral area are defined and a bottom structure is formed, a conductive line formed on an entire structure of the semiconductor substrate, a memory cell pattern formed on the conductive line in the cell area, and a dummy conductive pattern formed on any one of the conductive line in the core area and the peripheral area. | 04-25-2013 |
20130105981 | FLATTENED SUBSTRATE SURFACE FOR SUBSTRATE BONDING | 05-02-2013 |
20130105982 | LAND GRID ARRAY SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURE | 05-02-2013 |
20130105983 | SEMICONDUCTOR DEVICE AND METHOD FORMING PATTERNS WITH SPACED PADS IN TRIM REGION | 05-02-2013 |
20130105984 | SEMICONDUCTOR DEVICE PACKAGE ADAPTER | 05-02-2013 |
20130105985 | SEMICONDUCTOR DEVICE | 05-02-2013 |
20130113109 | WIRING STRUCTURE, THIN FILM TRANSISTOR ARRAY SUBSTRATE INCLUDING THE SAME, AND DISPLAY DEVICE - On a wiring conversion part connected to a first conductive film and a second conductive film each functioning as a wiring, a hollow portion is formed inside the second conductive film. A first transparent conductive film provided on the second conductive film is formed so as to cover an upper surface of the second conductive film and an end surface thereof exposed on the hollow portion, and so as not to cover an outer peripheral end surface of the second conductive film. A second transparent conductive film which is a layer above the first transparent conductive film is connected to the second conductive film and the first conductive film, so that the first conductive film and the second conductive film are electrically connected. | 05-09-2013 |
20130119550 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a method of manufacturing a semiconductor device includes sequentially forming a first insulator, a second insulator, and a sacrificial layer on a semiconductor substrate, and forming plural core materials from the sacrificial layer and the second insulator. The method further includes forming first and second interconnects on side surfaces of each core material to form plural first interconnects and plural second interconnects alternately, each first interconnect having a first side surface in contact with a core material and a second side surface positioned on an opposite side of the first side surface, and each second interconnect having a third side surface in contact with a core material and a fourth side surface positioned on an opposite side of the third side surface. The method further includes removing the sacrificial layer so that the second insulator remains, after the first and second interconnects are formed. | 05-16-2013 |
20130119551 | SEMICONDUCTOR ELEMENT AND FABRICATION METHOD THEREOF - A semiconductor element includes: a transparent substrate; a stack structure formed on the transparent substrate and having a metal oxide layer partially exposed through sidewalls of the stack structure; a plurality of leads spacingly formed on the stack structure and extending to the sidewalls of the stack structure; an insulating film covering the exposed portions of the metal oxide layer; a metal film formed on the leads; and a solder mask layer disposed on the metal film, the stack structure and the insulating film. As such, the insulating film prevents short circuits from occurring between adjacent leads so as to improve the product yield. | 05-16-2013 |
20130127059 | Adjusting Sizes of Connectors of Package Components - A device includes a plurality of connectors on a top surface of a package component. The plurality of connectors includes a first connector having a first lateral dimension, and a second connector having a second lateral dimension. The second lateral dimension is greater than the first lateral dimension. The first and the second lateral dimensions are measured in directions parallel to a major surface of the package component. | 05-23-2013 |
20130127060 | UNDER BUMP PASSIVES IN WAFER LEVEL PACKAGING - Under bump passive structures in wafer level packaging and methods of fabricating these structures are described. In an embodiment, a packaged semiconductor device is described which includes an under-bump capacitor formed in semiconductor device post-processing layers. As part of the post-processing a first dielectric layer is deposited on the active face of a semiconductor die and then in sequence a first metal layer, second dielectric layer and second metal layer are deposited. The under-bump capacitor is formed from a lower plate in the first metal layer and an upper plate in the second metal layer, the plates being separated by the second dielectric layer. In order to increase capacitance, the capacitor may be formed over one or more openings in the first dielectric layer, such that the layers forming the capacitor are no longer planar but follow the underlying topology. | 05-23-2013 |
20130127061 | INTEGRATED CIRCUIT PACKAGE SYSTEM - An integrated circuit package system is provided forming a first I/O cell having a first circuitry area and a first bond pad with the first circuitry area partitioned along a cell length and on opposing perimeter segment of the first bond pad, forming an I/O ring having the first I/O cell, forming an integrated circuit die having the I/O ring, and connecting an external interconnect and the first bond pad. | 05-23-2013 |
20130127062 | MULTIPLE DIE FACE-DOWN STACKING FOR TWO OR MORE DIE - A microelectronic assembly can include a substrate having first and second surfaces each extending in first and second transverse directions, a peripheral edge extending in the second direction, first and second openings extending between the first and second surfaces, and a peripheral region of the second surface extending between the peripheral edge and one of the openings. The assembly can also include a first microelectronic element having a front surface facing the first surface, a rear surface opposite therefrom, and an edge extending between the front and rear surfaces. The assembly can also include a second microelectronic element having a front surface facing the rear surface of the first microelectronic element and projecting beyond the edge of the first microelectronic element. The assembly can also include a plurality of terminals exposed at the second surface, at least one of the terminals being disposed at least partially within the peripheral region. | 05-23-2013 |
20130127063 | SEMICONDUCTOR DEVICE HEAT DISSIPATION STRUCTURE - A heat generating component of a semiconductor device is located between two heavily doped semiconductor regions in a semiconductor substrate. The heat generating component may be a middle portion of a diode having a light doping, a lightly doped p-n junction between a cathode and anode of a silicon controlled rectifier, or a resistive portion of a doped semiconductor resistor. At least one thermally conductive via comprising a metal or a non-metallic conductive material is place directly on the heat generating component. Alternatively, a thin dielectric layer may be formed between the heat generating component and the at least one thermally conductive via. The at least one thermally conductive via may, or may not, be connected to a back-end-of-line metal wire, which may be connected to higher level of metal wiring or to a handle substrate through a buried insulator layer. | 05-23-2013 |
20130134595 | METHODS AND APPARATUS TO IMPROVE RELIABILITY OF ISOLATED VIAS - A method for increasing metal density around selected vias in a semiconductor device is provided. The semiconductor device includes a plurality of vias. The method includes: generating a layout database for the semiconductor device; identifying isolated vias of the plurality of vias; selecting the isolated vias; defining a zone around each of the selected isolated vias; and increasing area of a metal layer which is above the selected isolated via and which encloses the selected isolated via within each zone to achieve a target metal density within the zone. The method improves reliability of the semiconductor device by allowing moisture to vent from around the vias. | 05-30-2013 |
20130134596 | Wafer Level Semiconductor Package - There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process. | 05-30-2013 |
20130134597 | CHIP ON FILM, AND METHOD OF MANUFACTURE THEREOF - A chip on film includes a plastic film approximately rectangular in flat view, a designated wiring pattern having approximately rectangular electrodes arrayed longitudinally formed on a mounting surface of the plastic film, and an LSI chip mounted on the mounting surface of the plastic film and connected to the designated wiring pattern. At least one cutout part is formed on each short side of the approximate rectangle of the plastic film. | 05-30-2013 |
20130134598 | Semiconductor Device and Method of Forming a Power MOSFET With Interconnect Structure to Achieve Lower RDSON - A semiconductor device has a substrate and gate structure over the substrate. A source region is formed in the substrate adjacent to the gate structure. A drain region in the substrate adjacent to the gate structure opposite the source region. An interconnect structure is formed over the substrate by forming a conductive plane electrically connected to the source region, and forming a conductive layer within openings of the conductive plane and electrically connected to the drain region. The interconnect structure can be formed as stacked conductive layers laid out in alternating strips. The conductive plane extends under a gate terminal of the semiconductor device. An insulating layer is formed over the substrate and a field plate is formed in the insulating layer. The field plate is electrically connected the source terminal. A stress relief layer is formed over a surface of the substrate opposite the gate structure. | 05-30-2013 |
20130134599 | METHOD AND STRUCTURE OF INTEGRATED MICRO ELECTRO-MECHANICAL SYSTEMS AND ELECTRONIC DEVICES USING EDGE BOND PADS - A monolithic integrated electronic device includes a substrate having a surface region and one or more integrated micro electro-mechanical systems and electronic devices provided on a first region overlying the surface region. Each of the integrated micro electro-mechanical systems and electronic devices has one or more contact regions. The first region has a first surface region. One or more trench structures are disposed within one or more portions of the first region. A passivation material overlies the first region and the one or more trench structures. A conduction material overlies the passivation material, the one or more trench structures, and one or more of the contact regions. The device also has one or more edge bond pad structures within a vicinity of the one or more bond pad structures, which are formed by a singulation process within a vicinity of the one or more bond pad structures. | 05-30-2013 |
20130140704 | Low Frequency CMUT with Thick Oxide - A capacitive micromachined ultrasonic transducer (CMUT), which has a conductive structure that can vibrate over a cavity, utilizes a thick oxide layer to substantially increase the volume of the cavity which, in turn, allows the CMUT to receive and transmit low frequency ultrasonic waves. In addition, the CMUT can include a back side bond pad structure that eliminates the need for and cost of one patterned photoresist layer. | 06-06-2013 |
20130140705 | Circuit connector apparatus and method therefor - Aspects of the present invention are directed to circuits, circuit packages and related methods. In accordance with various example embodiments, respective electrodes are implemented to facilitate contact to a semiconductor device via different surfaces and/or sidewalls, as may be useful in connecting the device to an external package having a plurality of semiconductor devices in which same-surface connections to the devices are spatially restricted. The semiconductor device has opposing surfaces and sidewalls connecting the surfaces, and contacts to respective different regions in the device. Respective electrodes are coupled to the respective contacts and extend along/around the device to provide access to the contacts via different surfaces. | 06-06-2013 |
20130140706 | UBM Structures for Wafer Level Chip Scale Packaging - A wafer level chip scale semiconductor device comprises a semiconductor die, a first under bump metal structure and a second under bump metal structure. The first under bump metal structure having a first enclosure is formed on a corner region or an edge region of the semiconductor die. A second under bump metal structure having a second enclosure is formed on an inner region of the semiconductor die. The first enclosure is greater than the second enclosure. | 06-06-2013 |
20130140707 | SEMICONDUCTOR DEVICE AND LAYOUT DESIGN METHOD FOR THE SAME - A semiconductor device includes: a plurality of line features including at least one real feature which includes a gate electrode portion, and at least one dummy feature. Two of multiple ones of the dummy feature, and at least one of the line features interposed between the two dummy features and including the at least one real feature form parallel running line features which are evenly spaced. The parallel running line features have an identical width, and line end portions of the parallel running line features are substantially flush. Line end portion uniformization dummy features are formed on extensions of the line end portions of the parallel running line features. The line end portion uniformization dummy features include a plurality of linear features each having a same width as each of the line features and spaced at intervals equal to an interval between each adjacent pair of the line features. | 06-06-2013 |
20130147049 | Circuit Probing Structures and Methods for Probing the Same - A package component includes a stack-probe unit, which includes a first-type connector, and a second-type connector connected to the first-type connector. The first-type connector and the second-type connector are exposed through a surface of the package component. | 06-13-2013 |
20130147050 | SEMICONDUCTOR HAVING INTEGRALLY-FORMED ENHANCED THERMAL MANAGEMENT - A semiconductor structure and method of manufacturing that has integrally-formed enhanced thermal management. During operation of a semiconductor device, electron flow between the source and the drain creates localized heat generation. A containment gap is formed by selectively removing a portion of the back side of the semiconductor device substrate directly adjacent to a localized heat generation area. A thermal management material is filled in the containment gap. This thermal management material enhances the thermal management of the semiconductor device by thermally coupling the localized heat generation area to a heat sink. The thermal management material may be a Phase Change Material (PCM) having a heat of fusion effective for absorbing heat generated in the localized heat generation area by the operation of the semiconductor device for reducing a peak operating temperature of the semiconductor device. | 06-13-2013 |
20130154101 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed. In the semiconductor device, an upper part of a storage node contact plug is increased in size, and an area of overlap between a storage node formed in a subsequent process and a storage node contact plug is increased, such that resistance of the storage node contact plug is increased and device characteristics are improved. The semiconductor device includes at least one bit line formed over a semiconductor substrate, a first storage node contact plug formed between the bit lines and coupled to an upper part of the semiconductor substrate, and a second storage node contact plug formed over the first storage node contact plug, wherein a width of a lower part of the second storage node contact plug is larger than a width of an upper part thereof. | 06-20-2013 |
20130154102 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURE METHOD - A support substrate includes a first surface and a second surface located above the level of the first surface. Chips are mounted on the first surface. A first insulating film is disposed over each chip. First conductive plugs are connected to the chip extending through each first insulating film. Filler material made of resin filling a space between chips. Wirings are disposed over the first insulating film and the filler material for interconnecting different chips. The second surface, an upper surface of the first insulating film and an upper surface of the filler material are located at the same level. | 06-20-2013 |
20130154103 | SEMICONDUCTOR PACKAGE HAVING MULTI PITCH BALL LAND - A semiconductor device having a printed circuit board and a semiconductor chip. The printed circuit board includes a chip region, a plurality of first ball lands adjacent to the chip region, and at least one second ball land adjacent to the first ball lands. The semiconductor chip is mounted on the chip region. The first ball lands are arranged to have a first pitch. One of the first ball lands which is nearest to the second ball land, and the second ball land have a second pitch greater than the first pitch. | 06-20-2013 |
20130154104 | INTEGRATED CIRCUITS AND METHODS OF FORMING CONDUCTIVE LINES AND CONDUCTIVE PADS THEREFOR - An integrated circuit includes circuitry, a first conductor coupled to the circuitry, a conductive pad coupled to the first conductor, and a second conductor coupled to the conductive pad. The second conductor would be floating but for its coupling to the conductive pad. The second conductor may be spaced apart from the first conductor by a distance that is substantially equal to a width of a merged spacer that was formed from a merging of single sidewall spacers over a conductive material from which the first and second conductors were formed. | 06-20-2013 |
20130161821 | NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile memory device includes a substrate including a cell region, contact regions and dummy contact regions. The contact regions and the dummy contact regions alternately are disposed. A plurality of word lines stacked at the cell region of the substrate and contact groups stacked at the contact regions and the dummy contact regions of the substrate. The contact groups include a plurality of pad layers being coupled to the word lines, and each of the contact groups has stepped structure disposed at a corresponding contact region. | 06-27-2013 |
20130161822 | CONTROLLING DENSITY OF PARTICLES WITHIN UNDERFILL SURROUNDING SOLDER BUMP CONTACTS - A method forms an integrated circuit structure, using a manufacturing device, to have kerf regions and external contacts, and to have conductive structures in the kerf regions. The method also forms an underfill material on a surface of the integrated circuit structure, using the manufacturing device, that contacts the kerf regions and the external contacts. The underfill material comprises electrically attracted filler particles that affect the coefficient of thermal expansion and elastic modulus of the underfill material. When forming the underfill material, the method applies an electrical charge to the conductive structures and the external contacts. | 06-27-2013 |
20130161823 | Semiconductor Device and Method of Manufacturing the Same - A semiconductor device capable of realizing highly reliable three-dimensional mounting, and a method of manufacturing the same, are provided. A projected electrode | 06-27-2013 |
20130168866 | CHIP-ON-LEAD PACKAGE AND METHOD OF FORMING - In one embodiment, a chip-on-lead package structures includes an electronic chip having opposing major surfaces. One major surface of the electronic chip is attached to first and second leads. The one major surface is electrically connected to the first lead, and electrically isolated from the second lead. The other major surface where active device are formed may be electrically connected to the second lead. | 07-04-2013 |
20130168867 | METHOD FOR FORMING METAL LINE IN SEMICONDUCTOR DEVICE - A method for forming a metal line in a semiconductor device and an associated apparatus. The method includes at least one of (1) Depositing a metal line layer and a metal contact layer over a semiconductor substrate. (2) Patterning the metal contact layer and the metal line layer to form a primarily formed contact portion and a lower metal line. (3) Patterning the primarily formed contact portion to form a secondarily formed contact portion. (4) Forming an insulating film on the semiconductor substrate including the secondarily formed contact portion and the lower metal line. (5) Planarizing the insulating film such that the secondarily formed contact portion is exposed. (6) Forming an upper metal line over the planarized insulating film to be in electrical contact with the secondarily formed contact portion. | 07-04-2013 |
20130168868 | SEMICONDUCTOR STACK STRUCTURE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor stack structure mainly includes: singulating a wafer of a first specification into a plurality of chips; rearranging the chips into a second specification of a wafer so as to stack the chips on a substrate of the second specification through a plurality of blocks; forming a redistribution layer on the chips; and performing a cutting process to obtain a plurality of semiconductor stack structures. Therefore, the present invention allows a wafer of a new specification to be processed by using conventional equipment without the need of new factory buildings or equipment. As such, chip packages can be timely supplied to meet the replacement speed of electronic products. | 07-04-2013 |
20130175694 | Packages and Method of Forming the Same - A method includes forming a dielectric layer over a substrate, forming an interconnect structure over the dielectric layer, and bonding a die to the interconnect structure. The substrate is then removed, and the dielectric layer is patterned. Connectors are formed at a surface of the dielectric layer, wherein the connectors are electrically coupled to the die. | 07-11-2013 |
20130175695 | SEMICONDUCTOR DEVICE STRUCTURES AND MEMORY DEVICES INCLUDING A UNIFORM PATTERN OF CONDUCTIVE MATERIAL - Methods of forming semiconductor device structures are disclosed. One method comprises forming a plurality of loops of a conductive material. Each loop of the plurality of loops comprises a uniform pattern. In one embodiment, a portion of the conductive material is removed from at least one location in each loop of the plurality of loops. Contacts are formed to the conductive material. A semiconductor device structure is also disclosed. | 07-11-2013 |
20130175696 | Semiconductor Device and Method of Forming Insulating Layer Disposed Over The Semiconductor Die For Stress Relief - A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure. | 07-11-2013 |
20130181352 | Method of Growing Carbon Nanotubes Laterally, and Lateral Interconnections and Effect Transistor Using the Same - Provided are a method of growing carbon nanotubes laterally, including forming catalyst dots to grow carbon nanotubes on a substrate, forming a sacrificial layer including a plurality of nanochannels including regions having the catalyst dots formed therein, and growing carbon nanotubes through the nanochannels, and a field effect transistor using the method. | 07-18-2013 |
20130181353 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package includes a semiconductor device and a substrate, the semiconductor device including a straight line portion on an outer periphery and the substrate supporting the semiconductor device. A foil positioning pattern is formed on a front surface of the substrate, the positioning pattern touching the straight line portion of the semiconductor device to regulate a position of the semiconductor device. | 07-18-2013 |
20130187279 | SEMICONDUCTOR DEVICE STRUCTURES INCLUDING BURIED DIGIT LINES AND RELATED METHODS - Methods of forming semiconductor device structures include forming trenches in an array region and in a buried digit line end region, forming a metal material in the trenches, filling the trenches with a mask material, removing mask material in the trenches to expose a portion of the metal material, and removing the exposed portion of the metal material. A plurality of conductive contacts are formed in direct contact with the metal material in the buried digit line end region. Methods of forming a buried digit line contact include forming conductive contacts physically contacting metal material in trenches in a buried digit line end region. Vertical memory devices and apparatuses include metallic connections disposed between a buried digit line and a conductive contact in a buried digit line end region. | 07-25-2013 |
20130187280 | Crack-Arresting Structure for Through-Silicon Vias - The subject matter disclosed herein relates to structures formed on semiconductor chips that are used for at least partially addressing the thermally induced stresses and metallization system cracking problems in a semiconductor chip that may be caused by the presence of through-silicon vias (TSV's), and which may be due primarily to the significant differences in thermal expansion between the materials of the TSV's and the semiconductor-based materials that generally make up the remainder of the semiconductor chip. One device disclosed herein includes a substrate and a crack-arresting structure positioned above the substrate, the crack-arresting structure comprising a plurality of crack-arresting elements and having a perimeter when viewed from above. The device also includes a conductive structure positioned at least partially within the perimeter of the crack-arresting structure, and a conductive element extending through an opening in the crack-arresting structure, wherein the conductive element is conductively coupled to the conductive structure. | 07-25-2013 |
20130187281 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING OF SAME - A method for manufacturing a semiconductor device, includes: forming a first metal layer on a semiconductor substrate, the semiconductor substrate including a diffusion layer; forming an insulating layer having an opening on the first metal layer; forming a second metal layer on the first metal layer in the opening of the insulating layer; removing the insulating layer; covering an exposed surface of the second metal layer with a third metal layer, the third metal layer including a metal having an ionization tendency lower than that of the second metal layer; and forming an electrode interconnect including the first metal layer, the second metal layer, and the third metal layer by removing the first metal layer using the third metal layer as a mask. | 07-25-2013 |
20130187282 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, METHOD FOR GENERATING MASK DATA, MASK AND COMPUTER READABLE RECORDING MEDIUM - A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines. | 07-25-2013 |
20130187283 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a semiconductor device of a multilayer wiring structure that comprises a CF | 07-25-2013 |
20130193581 | PACKAGED MICRODEVICES AND METHODS FOR MANUFACTURING PACKAGED MICRODEVICES - Microdevices and methods for packaging microdevices. One embodiment of a packaged microdevice includes a substrate having a mounting area, contacts in the mounting area, and external connectors electrically coupled to corresponding contacts. The microdevice also includes a die located across from the mounting area and spaced apart from the substrate by a gap. The die has an integrated circuit and pads electrically coupled to the integrated circuit. The microdevice further includes first and second conductive elements in the gap that form interconnects between the contacts of the substrate and corresponding pads of the die. The first conductive elements are electrically connected to contacts on the substrate, and the second conductive elements are electrically coupled to corresponding pads of the die. The first conductive elements are attached to the second conductive elements at corresponding interfaces such that the interconnects connect the contacts of the substrate directly to corresponding pads on the die within the gap. | 08-01-2013 |
20130193582 | METHOD AND APPARATUS FOR CONNECTING MEMORY DIES TO FORM A MEMORY SYSTEM - A method, system and apparatus for connecting multiple memory device dies | 08-01-2013 |
20130193583 | SEMICONDUCTOR DEVICE HAVING METAL LINES WITH SLITS - A semiconductor device including a semiconductor substrate, an integrated circuit on the semiconductor substrate, an insulation layer covering the integrated circuit, and a plurality of metal line patterns on the insulation layer. First and second adjacent metal line patterns of the plurality of metal line patterns are spaced apart from each other by a space, and each of the first and second adjacent metal line patterns has at least one slit. | 08-01-2013 |
20130200522 | METHOD OF MOUNTING SEMICONDUCTOR CHIPS, SEMICONDUCTOR DEVICE OBTAINED USING THE METHOD, METHOD OF CONNECTING SEMICONDUCTOR CHIPS, THREE-DIMENSIONAL STRUCTURE IN WHICH WIRING IS PROVIDED ON ITS SURFACE, AND METHOD OF PRODUCING THE SAME - A method of mounting a semiconductor chip includes: forming a resin coating on a surface of a path connecting a bonding pad on a surface of a semiconductor chip and an electrode pad formed on a surface of an insulating base material; forming, by laser beam machining, a wiring gutter having a depth that is equal to or greater than a thickness of the resin coating along the path for connecting the bonding pad and the electrode pad; depositing a plating catalyst on a surface of the wiring gutter; removing the resin coating; and forming an electroless plating coating only at a site where the plating catalyst remains. | 08-08-2013 |
20130214419 | SEMICONDUCTOR PACKAGING METHOD AND STRUCTURE THEREOF - A semiconductor packaging method includes providing a substrate having a plurality of connection pads; mounting a chip on the substrate, wherein the chip comprises a plurality of copper-containing bumps directly coupled to the connection pads, and each of the copper-containing bumps comprises a ring surface; forming an anti-dissociation gel between the substrate and the chip, wherein the anti-dissociation gel comprises a plurality of anti-dissociation substances, and the ring surfaces of the copper-containing bumps are covered by the anti-dissociation substances. | 08-22-2013 |
20130214420 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including first and second semiconductor pillars formed on a surface of a semiconductor substrate and aligning in a first direction; a first interconnect extending in a second direction intersecting with the first direction and provided between the first and second semiconductor pillars; and a first contact pad located over the first interconnect, the first contact pad being in contact with and electrically connected to the first semiconductor pillar at a side surface thereof, while being electrically isolated from the second semiconductor pillar. | 08-22-2013 |
20130214421 | DISABLING ELECTRICAL CONNECTIONS USING PASS-THROUGH 3D INTERCONNECTS AND ASSOCIATED SYSTEMS AND METHODS - Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect. | 08-22-2013 |
20130214422 | CIRCUIT SUBSTRATE STRUCTURE - A circuit substrate structure including a substrate, a dielectric stack layer, a first plating layer and a second plating layer is provided. The substrate has a pad. The dielectric stack layer is disposed on the substrate and has an opening exposing the pad, wherein the dielectric stack layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer located between the first dielectric layer and the second dielectric layer, and there is a gap between the portion of the first dielectric layer surrounding the opening and the portion of the second dielectric layer surrounding the opening. The first plating layer is disposed at the dielectric stack layer. The second plating layer is disposed at the pad, wherein the gap isolates the first plating layer from the second plating layer. | 08-22-2013 |
20130221531 | SEMICONDUCTOR DEVICE, MEMORY SYSTEM AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device includes first pads having centers offset in a first direction, wherein the first pads are arranged in a second direction crossing the first direction; second pads separated in the first direction from the first pads and arranged in the second direction, wherein centers of the second pads are offset in the first direction; first gate lines coupled to the first pads, respectively; and second gate lines coupled to the second pads, respectively. | 08-29-2013 |
20130221532 | SEMICONDUCTOR MODULE WITH SWITCHING ELEMENTS - In a semiconductor module, an upper arm switching element is integrated to a high-potential conductor coupled to a high-potential electrode of a power source, and a lower arm switching element is integrated to a load conductor coupled to a load. A first connecting conductor has a first end connected to the upper arm switching element and a second end connected to the load conductor. A second connecting conductor has a first end connected to the lower arm switching element and a second end connected to a low-potential conductor coupled to a low-potential electrode of the power source. At least one of the first connecting conductor and the second connecting conductor serves as a shunt resistor for detecting an electric current flowing in the at least one. | 08-29-2013 |
20130221533 | HIGH SPEED, HIGH DENSITY, LOW POWER DIE INTERCONNECT SYSTEM - A system for interconnecting at least two die each die having a plurality of conducting layers and dielectric layers disposed upon a substrate which may include active and passive elements. In one embodiment there is at least one interconnect coupling at least one conducting layer on a side of one die to at least one conducting layer on a side of the other die. Another interconnect embodiment is a slug having conducting and dielectric layers disposed between two or more die to interconnect between the die. Other interconnect techniques include direct coupling such as rod, ball, dual balls, bar, cylinder, bump, slug, and carbon nanotube, as well as indirect coupling such as inductive coupling, capacitive coupling, and wireless communications. The die may have features to facilitate placement of the interconnects such as dogleg cuts, grooves, notches, enlarged contact pads, tapered side edges and stepped vias. | 08-29-2013 |
20130241071 | Semiconductor Device and Method of Forming Compliant Conductive Interconnect Structure in Flipchip Package - A semiconductor device has a semiconductor die. The semiconductor die has a contact pad. A first conductive layer is formed over the contact pad. A conductive shell having a hollow core is formed over the first conductive layer. A compliant material is deposited in the hollow core. The semiconductor die is mounted over a substrate with the conductive shell electrically connected to a conductive trace on the substrate. A second conductive layer is formed over the conductive shell. The compliant material is an insulating material. A bump material is deposited around the conductive shell. A pre-solder material is deposited over the conductive trace. The conductive shell has a cross-sectional width less than 7 micrometers. The second conductive layer is a conductive lip. Mounting the semiconductor die over the substrate further includes mounting the semiconductor die over the substrate in a bump on lead (BOL) configuration. | 09-19-2013 |
20130241072 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device has 3n, 3n+1, and 3n+2 connector lines that are formed together. The 3n+1 connector line is located between the 3n connector line and the 3n+2 connector line. The first fringe pattern pad is located at the terminus of the 3n connector line and is formed with a wider space than the width of the 3n connector line. The second fringe pattern pad is located at the terminus of the 3n+1 connector line and is formed with a wider width than the width of the 3n+1 connector line. The third fringe pattern pad is located at the terminus of the 3n+2 connector line and is formed with a wider width than the width of the 3n+2 connector line. The second fringe pattern pad is positioned closer to a memory array as compared with the terminus of each connector line with the first and third fringe pattern pads. | 09-19-2013 |
20130241073 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a plurality of wires arranged in parallel at a predetermined pitch, a plurality at first contacts that are each connected to an odd-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to a wiring direction of the wires, and a plurality of second contacts that are each connected to an even-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to the wiring direction of the wires in such a way as to be offset from the first contacts in the wiring direction of the wires, in which the first contacts are offset from the second contacts by a pitch of the wires in an orthogonal direction with respect to the wiring direction of the wires. | 09-19-2013 |
20130241074 | ADAPTIVE PATTERNING FOR PANELIZED PACKAGING - An adaptive patterning method and system for fabricating panel based package structures is described. Misalignment for individual device units in a panel or reticulated wafer may be adjusted for by measuring the position of each individual device unit and forming a unit-specific pattern over each of the respective device units. | 09-19-2013 |
20130249101 | Semiconductor Method of Device of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units - A semiconductor device has a carrier with a die attach area. A semiconductor die is mounted to the die attach area with a back surface opposite the carrier. A modular interconnect unit is mounted over the carrier and around or in a peripheral region around the semiconductor die such that the modular interconnect unit is offset from the back surface of the semiconductor die. An encapsulant is deposited over the carrier, semiconductor die, and modular interconnect unit. A first portion of the encapsulant is removed to expose the semiconductor die and a second portion is removed to expose the modular interconnect unit. The carrier is removed. An interconnect structure is formed over the semiconductor die and modular interconnect unit. The modular interconnect unit includes a vertical interconnect structures or bumps through the semiconductor device. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die. | 09-26-2013 |
20130249102 | SEMICONDUCTOR DEVICE WITH STRENGTHENED INTER-WIRE AIR GAP STRUCTURES - A semiconductor device with a plurality of wires wherein at least some of the regions between wires (inter-wire regions) contain an air gap region formed by capping the wires and inter-wire regions with an insulator film using a film coating process, for example chemical vapor deposition. The existence, size, and shape of the air gap depend upon the film coating parameters and the spacing between wires. | 09-26-2013 |
20130249103 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip, a first electrode terminal, a second electrode terminal, and a connector. The semiconductor chip is carried on the first electrode terminal. The second electrode terminal is separated from the first electrode terminal. The connector includes first through third structural parts. The first structural part is connected to an electrode of the semiconductor chip via the first connecting part; the third structural part is connected to a second electrode terminal via the second connecting part; the second structural part connects the first and third structural parts; and holes are formed on at least one of the first through third structural parts. Additionally, laser ablated recesses may be formed in the first electrode terminal to align the semiconductor chip therewith. | 09-26-2013 |
20130256895 | STACKED SEMICONDUCTOR COMPONENTS WITH UNIVERSAL INTERCONNECT FOOTPRINT - A method of manufacturing is provided that includes fabricating a first set of interconnect structures on a side of a first semiconductor substrate. The first semiconductor substrate is operable to have at least one of plural semiconductor substrates stacked on the side. The first set of interconnect structures is arranged in a pattern. Each of the plural semiconductor substrates has a second set of interconnect structures arranged in the pattern, one of the plural semiconductor substrates has a smallest footprint of the plural semiconductor substrates. The pattern has a footprint smaller than the smallest footprint of the plural semiconductor substrates. | 10-03-2013 |
20130256896 | VERTICAL MOUNT PACKAGE AND WAFER LEVEL PACKAGING THEREFOR - Vertical mount packages and methods for making the same are disclosed. A method for manufacturing a vertical mount package includes providing a device substrate with a plurality of device regions on a front surface, and a plurality of through-wafer vias. MEMS devices or integrated circuits are formed or mounted onto the device regions. A capping substrate having recesses is mounted over the device substrate, enclosing the device regions within cavities defined by the recesses. A plurality of aligned through-wafer contacts extend through the capping substrate and the device substrate. The device substrate and capping substrate can be singulated by cutting through the aligned through-wafer contacts, with the severed through-wafer contacts forming vertical mount leads. A vertical mount package includes a device sealed between a device substrate and a capping substrate. At least of the side edges of the package includes exposed conductive elements for vertical mount leads. | 10-03-2013 |
20130256897 | SUBSTRATE AND SEMICONDUCTOR DEVICE - A substrate may include: a base material having a predetermined thickness; an electrode section formed on one side surface in a thickness direction of the base material, and having a plurality of electrodes; and a concave section formed on at least a part of the surface on which the electrode section is formed, on the base material. | 10-03-2013 |
20130256898 | Optimizing Layout of Irregular Structures in Regular Layout Context - A plurality of regular wires are formed within a given chip level, each having a linear-shape with a length extending in a first direction and a width extending in a second direction perpendicular to the first direction. The plurality of regular wires are positioned according to a fixed pitch such that a distance as measured in the second direction between lengthwise centerlines of any two regular wires is an integer multiple of the fixed pitch. At least one irregular wire is formed within the given chip level and within a region bounded by the plurality of regular wires. Each irregular wire has a linear-shape with a length extending in the first direction and a width extending in the second direction. A distance as measured in the second direction between lengthwise centerlines of any irregular wire and any regular wire is not equal to an integer multiple of the fixed pitch. | 10-03-2013 |
20130256899 | METHODS AND APPARATUSES TO FORM SELF-ALIGNED CAPS - At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line. | 10-03-2013 |
20130264714 | SEMICONDUCTOR DEVICE AND METHOD OF ASSEMBLING SAME - A semiconductor die has interface electrodes on an interface surface and an electrically conductive layer on a mounting surface that is opposite to the interface surface. The electrically conductive layer extends onto side regions of the semiconductor die. Electrical conductors couple the interface electrodes to external connector pads. A solder alloy joins the semiconductor die to a flag. The solder alloy is disposed between the flag and the electrically conductive layer and provides a joint between the flag and both the mounting surface and the side regions. | 10-10-2013 |
20130264715 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To provide a semiconductor device comprising a first layer that is provided on a semiconductor substrate and includes a first wiring pattern planarized by CMP and a plurality of first dummy patterns made of a same material as the first wiring pattern and a second layer that is provided above the semiconductor substrate and includes a second wiring pattern planarized by CMP and a plurality of second dummy patterns made of a same material as the second wiring pattern. A central axis of each of the second dummy patterns coincides with that of a corresponding one of the first dummy patterns in a direction perpendicular to the semiconductor substrate. | 10-10-2013 |
20130264716 | System-In-Package Having Integrated Passive Devices and Method Therefor - A semiconductor device has a substrate, first passivation layer formed over the substrate, and integrated passive device formed over the substrate. The integrated passive device can include an inductor, capacitor, and resistor. A second passivation layer is formed over the integrated passive device. System components are mounted to the second passivation layer and electrically connect to the second conductive layer. A mold compound is formed over the integrated passive device. A coefficient of thermal expansion of the mold compound is approximately equal to a coefficient of thermal expansion of the system component. The substrate is removed. An opening is etched into the first passivation layer and solder bumps are deposited over the opening in the first passivation layer to electrically connect to the integrated passive device. A metal layer can be formed over the molding compound or first passivation layer for shielding. | 10-10-2013 |
20130270705 | Semiconductor Device Packages and Methods - Semiconductor devices packages and methods are disclosed. In one embodiment, a package for a semiconductor device includes a substrate and a contact pad disposed on a first surface of the substrate. The contact pad has a first side and a second side opposite the first side. A conductive trace is coupled to the first side of the contact pad, and an extension of the conductive trace is coupled to the second side of the contact pad. A plurality of bond pads is disposed on a second surface of the substrate. | 10-17-2013 |
20130270706 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes: first and second semiconductor chips, each including a first electrode and a second electrode opposite to each other in a predetermined direction; a chip-mount substrate on which the first and second semiconductor chips are mounted; and a first wiring terminal to which the second electrodes of the first and second semiconductor chips are connected. The second semiconductor chip lies over the first semiconductor chip in the predetermined direction such that the second electrode of the first semiconductor chip and the second electrode of the second semiconductor chip face each other across the first wiring terminal, and the chip-mount substrate is bent such that the first electrode of the first semiconductor chip is connected to the first electrode of the second semiconductor chip. | 10-17-2013 |
20130270707 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS - A semiconductor device includes a base substrate and first and second semiconductor wires which are arranged side by side on the base substrate, and the base substrate is provided with an opening (inter-wire grove, slit) in an extending direction of the first and second semiconductor wires between the first semiconductor wire and the second semiconductor wire. | 10-17-2013 |
20130277848 | METHOD OF FORMING CONTACT AND SEMICONDUCTOR DEVICE MANUFACTURED BY USING THE METHOD - A method of forming a contact includes forming an inter-layer dielectric layer to cover a gate formed on a semiconductor substrate; and forming a first hole which passes through the inter-layer dielectric layer to expose the gate, a second hole which exposes an active region of the semiconductor substrate, and a third hole which exposes the semiconductor substrate at a preset depth. Further, the method includes forming a shielding layer on the semiconductor substrate including the bottom and sidewalls of the first hole, the second hole, and the third hole; and removing the shielding layer at the bottom of the first hole and the second hole to expose the gate and the active region. Furthermore, the method includes filling the first hole, the second hole, and the third hole with a conductive material. | 10-24-2013 |
20130277849 | INTERNAL WIRING STRUCTURE OF SEMICONDUCTOR DEVICE - Aspects of the invention provide an internal wiring structure of a power semiconductor device, which is capable of reducing a mutual inductance between two wiring conductors and improving the heat dissipation effect, the two wiring conductors being disposed so as to oppose each other and having currents flowing in the same direction. In some aspects, notches can be formed alternately from side walls of two flat plates, on the flat plates, to obtain two wiring conductors. The two wiring conductors can be disposed so as to oppose each other and in parallel to each other so that currents flow along the notches in directions opposite to each other. Accordingly, in some circumstances, the mutual inductance can be reduced. Further, in some circumstances, the dimensions of the planes of the wiring conductors obtained by forming the notches can be increased to improve the heat dissipation. | 10-24-2013 |
20130277850 | ELECTRONIC DEVICE - An electronic device includes a substrate and an electronic component. The substrate has a metallization trace. The metallization trace has a metallization layer and a synthetic resin layer. The metallization layer has a high-melting-point metallic component and a low-melting-point metallic component. The high-melting-point metallic component and the low-melting-point metallic component are diffusion bonded together and adhered to a surface of the substrate. The synthetic resin layer is formed simultaneously with the metallization layer to cover a surface of the metallization layer with a thickness in the range of 5 nm to 1000 nm. The electronic component is electrically connected to the metallization layer. | 10-24-2013 |
20130277851 | Semiconductor Method and Device of Forming a Fan-Out Device with PWB Vertical Interconnect Units - A semiconductor device has a modular interconnect unit or interconnect structure disposed in a peripheral region of the semiconductor die. An encapsulant is deposited over the semiconductor die and interconnect structure. A first insulating layer is formed over the semiconductor die and interconnect structure. A plurality of openings is formed in the first insulating layer over the interconnect structure. The openings have a pitch of 40 micrometers. The openings include a circular shape, ring shape, cross shape, or lattice shape. A conductive layer is deposited over the first insulating layer. The conductive layer includes a planar surface. A second insulating layer is formed over the conductive layer. A portion of the encapsulant is removed to expose the semiconductor die and the interconnect structure. The modular interconnect unit includes a vertical interconnect structure. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die. | 10-24-2013 |
20130285249 | SEMICONDUCTOR DEVICE AND METHOD OF PACKAGING A SEMICONDUCTOR DEVICE WITH A CLIP - A method and apparatus of packaging a semiconductor device with a clip is disclosed. The clip defines a first contact region and a second contact region on a same face of the at least one clip. The chip defines a first face, and a second face opposite to the first face, the first contact region being attached to the first face of the chip and the second contact region being located within a same plane with the second face of the clip. | 10-31-2013 |
20130285250 | SEMICONDUCTOR DEVICE - The semiconductor device according to the present invention includes a semiconductor chip, an island having an upper surface to which the semiconductor chip is bonded, a lead arranged around the island, a bonding wire extended between the surface of the semiconductor chip and the upper surface of the lead, and a resin package collectively sealing the semiconductor chip, the island, the lead and the bonding wire, while the lower surface of the island and the lower surface of the lead are exposed on the rear surface of the resin package, and the lead is provided with a recess concaved from the lower surface side and opened on a side surface thereof. | 10-31-2013 |
20130292836 | VIA-FREE INTERCONNECT STRUCTURE WITH SELF-ALIGNED METAL LINE INTERCONNECTIONS - The present disclosure provides a semiconductor device. The semiconductor device includes a first conductive line disposed over a substrate. The first conductive line is located in a first interconnect layer and extends along a first direction. The semiconductor device includes a second conductive line and a third conductive line each extending along a second direction different from the first direction. The second and third conductive lines are located in a second interconnect layer that is different from the first interconnect layer. The second and third conductive lines are separated by a gap that is located over or below the first conductive line. The semiconductor device includes a fourth conductive line electrically coupling the second and third conductive lines together. The fourth conductive line is located in a third interconnect layer that is different from the first interconnect layer and the second interconnect layer. | 11-07-2013 |
20130292837 | PASSIVATION FOR WAFER LEVEL - CHIP-SCALE PACKAGE DEVICES - Aspects of the disclosure are directed towards an efficient wafer level chip-scale package, and methods or producing the packages. Various aspects are directed to protecting against humidity, contamination, mechanical damage, and current leakage while maintaining isolation and manufacturability of the plastic package and a ratio of active die size to package size. | 11-07-2013 |
20130292838 | PACKAGE-ON-PACKAGE INTERCONNECT STIFFENER - Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package. | 11-07-2013 |
20130292839 | POROUS SILICON MATERIAL - Provided are a method for producing a porous silicon material filled with a metal, the method including the steps of rendering hydrophobic a porous silicon substrate having pores from 1 to 5 nm in diameter, and depositing a metal into the pores of the porous silicon substrate by the electrodeposition of the porous silicon substrate; a method for producing a metallic nanoparticle or a nanofiber, the method including the steps of producing a porous silicon material filled with a metal, dissolving the silicon contained in the porous silicon material filled with a metal; a metallic nanoparticle or a nanofiber obtained by using the method for producing a metallic nanoparticle or a nanofiber: and a porous silicon material formed from a porous silicon substrate having pores from 1 to 5 nm in diameter and a resistivity of 5 to 20 Ω·cm, the pores of which are filled with a metal. | 11-07-2013 |
20130292840 | STACKED MEMORY ALLOWING VARIANCE IN DEVICE INTERCONNECTS - A stacked memory allowing variance in device interconnects. An embodiment of a memory device includes a system element for the memory device, the system element including multiple pads, and a memory stack connected with the system element, the memory stack having one or more memory die layers, a connection of the system element and the memory stack including interconnects for connecting a first memory die layer and the plurality of pads of the system element. For a single memory die layer in the memory stack, a first subset of the plurality of pads is utilized for a first group of interconnects for the connection of the system element and the memory stack, and for two or more memory die layers, the first subset and an additional second subset of the plurality of pads are utilized for the first group of interconnects and a second group of interconnects for the connection of the system element and the memory stack. | 11-07-2013 |
20130307158 | CURVILINEAR WIRING STRUCTURE TO REDUCE AREAS OF HIGH FIELD DENSITY IN AN INTEGRATED CIRCUIT - A method for reducing areas of high field density in an integrated circuit is disclosed. In one embodiment, the method includes forming a first curvilinear wiring structure in a first interconnect layer of an integrated circuit. A second curvilinear wiring structure may be formed in a second interconnect layer of the integrated circuit, such that the first and second curvilinear wiring structures are substantially vertically aligned. The first curvilinear wiring structure may then be electrically connected to the second curvilinear wiring structure. A corresponding apparatus and design structure are also described. | 11-21-2013 |
20130313712 | Multi-Chip Package and Method of Manufacturing Thereof - A multi-chip package comprises a first chip accommodated in a first housing and a second chip accommodated in a second housing. The first housing and the second housing are arranged in a laterally spaced-apart relationship defining a gap between the first housing and the second housing. An interconnecting structure is configured to span the gap and to electrically couple the first chip and the second chip. | 11-28-2013 |
20130313713 | EXTREMELY STRETCHABLE ELECTRONICS - In embodiments, the present invention may attach at least two isolated electronic components to an elastomeric substrate, and arrange an electrical interconnection between the components in a boustrophedonic pattern interconnecting the two isolated electronic components with the electrical interconnection. The elastomeric substrate may then be stretched such that the components separate relative to one another, where the electrical interconnection maintains substantially identical electrical performance characteristics during stretching, and where the stretching may extend the separation distance between the electrical components to many times that of the un-stretched distance. | 11-28-2013 |
20130313714 | SEMICONDUCTOR DEVICE HAVING ENHANCED SIGNAL INTEGRITY - A semiconductor includes a first signal line commonly connected to a plurality of semiconductor devices and a second signal line commonly connected to one or more of the plurality of semiconductor devices. The first signal line has a first impedance per unit length, the second signal line has a second impedance per unit length, the second impedance per unit length is greater than the first impedance per unit length, and the first signal line has a longer routing length than the first signal line. Widths of the signal lines may be set to reduce a difference in the impedances. | 11-28-2013 |
20130313715 | Component Leg Arrangement - An electronic component including one or more legs for attachment to a circuit board, wherein at least one of said legs includes a spring-acting kink, arranged so as to offers resilience to relative displacement between the end of said leg and the body of said component. The kink may be substantially S-shaped, Z-shaped, U-shaped, wave-shaped or coil-shaped. | 11-28-2013 |
20130320549 | SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming, over a substrate, a plurality of first conductive structures which are separated from one another; forming multi-layered dielectric patterns including a first dielectric layer which covers upper ends and both sidewalls of the first conductive structures; removing portions of the first dielectric layer starting from lower end portions of the first conductive structures to define air gaps, and forming second conductive structures which are filled between the first conductive structures. | 12-05-2013 |
20130320550 | SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a plurality of bit line structures over a substrate, forming multiple layers of spacer layers with a capping layer interposed therebetween over the bit line structures, exposing a surface of the substrate by selectively etching the spacer layers, forming air gaps and capping spacers for covering upper portions of the air gaps by selectively etching the capping layer, and forming storage node contact plugs between the bit line structures. | 12-05-2013 |
20130320551 | DISCRETE SEMICONDUCTOR DEVICE PACKAGE AND MANUFACTURING METHOD - Disclosed is a discrete semiconductor device package ( | 12-05-2013 |
20130320552 | INTEGRATED CIRCUIT FABRICATION - A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width. | 12-05-2013 |
20130328205 | INTEGRATED CIRCUITS HAVING A CONTINUOUS ACTIVE AREA AND METHODS FOR FABRICATING SAME - Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes a standard cell having a first boundary, a second boundary opposite the first boundary, a third boundary interconnecting the first and second boundaries, and a fourth boundary opposite the third boundary and interconnecting the first and second boundaries. The standard cell further includes parallel active areas extending from the first boundary to the second boundary. Also, the standard cell has parallel gate strips extending from the third boundary to the fourth boundary and over the active areas. A cut mask overlies the gate strips. An interconnect is positioned overlying the cut mask and forms an electrical connection with a selected gate strip. | 12-12-2013 |
20130328206 | CHIP ARRANGEMENT AND METHOD FOR PRODUCING A CHIP ARRANGEMENT - A chip arrangement includes semiconductor chips coupled to opposing sides of an insulating layer. The arrangement includes a first semiconductor chip having a first chip surface presenting a first chip conductive region. An electrically insulating layer includes a first layer surface presenting a first layer conductive region, and a second, opposing surface presenting a second layer conductive region. The electrically insulating layer is coupled to the first semiconductor chip by applying the first layer conductive region to the first chip conductive region. The electrically insulating layer is then coupled to the second chip conductive region by applying the second layer conductive region to the second chip conductive region. | 12-12-2013 |
20130328207 | EMBEDDED SEMICONDUCTIVE CHIPS IN RECONSTITUTED WAFERS, AND SYSTEMS CONTAINING SAME - A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer. | 12-12-2013 |
20130334694 | PACKAGING SUBSTRATE, SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A packaging substrate is provided, including: a metal board having a first surface and a second surface opposite to the first surface, wherein the first surface has a plurality of first openings for defining a first core circuit layer therebetween, the second surface has a plurality of second openings for defining a second core circuit layer therebetween, each of the first and second openings has a wide outer portion and a narrow inner portion, and the inner portion of each of the second openings is in communication with the inner portion of a corresponding one of the first openings; a first encapsulant formed in the first openings; a second encapsulant formed in the second openings; and a surface circuit layer formed on the first encapsulant and the first core circuit layer. The present invention effectively reduces the fabrication cost and increases the product reliability. | 12-19-2013 |
20130334695 | ELECTRONIC DEVICE AND METHOD OF MANUFACTURING SUCH DEVICE - The invention relates to an electronic device ( | 12-19-2013 |
20130334696 | BUMPLESS BUILD-UP LAYER PACKAGE DESIGN WITH AN INTERPOSER - The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein an interposer, such as a through-silicon via interposer, may be used in a bumpless build-up layer package to facilitate stacked microelectronic components. | 12-19-2013 |
20130341795 | Methods of Forming Semiconductor Constructions - Some embodiments include a semiconductor construction having a pair of lines extending primarily along a first direction, and having a pair of contacts between the lines. The contacts are spaced from one another by a lithographic dimension, and are spaced from the lines by sub-lithographic dimensions. Some embodiments include a method of forming a semiconductor construction. Features are formed over a base. Each feature has a first type sidewall and a second type sidewall. The features are spaced from one another by gaps. Some of the gaps are first type gaps between first type sidewalls, and others of the gaps are second type gaps between second type sidewalls. Masking material is formed to selectively fill the first type gaps relative to the second type gaps. Excess masking material is removed to leave a patterned mask. A pattern is transferred from the patterned mask into the base. | 12-26-2013 |
20130341796 | SEMICONDUCTOR DEVICE WITH REDISTRIBUTED CONTACTS - A semiconductor device has external, exposed electrical contacts at an device active face and a semiconductor die, which has internal, electrical contacts at a die active face. The exposed contacts are offset from the internal contacts laterally of the device active face. A redistribution layer includes a layer of insulating material and redistribution interconnectors within the insulating material, the interconnectors connecting with the exposed contacts. A set of conductors connect the internal contacts and the interconnectors. The conductors have oblong, tear drop shaped cross-sections extending laterally of the die active face beyond the respective internal contacts, and contact the interconnectors at positions spaced further apart than the internal contacts. The redistribution layer may be prefabricated using less costly manufacturing techniques such as lamination. | 12-26-2013 |
20130341797 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a substrate including a memory cell region and a contact region, a string structure including conductive layers and first interlayer insulating layers alternately stacked over the substrate and protruded toward a lower layer from the memory cell region toward the contact region, barrier rib patterns spaced apart from one another over the conductive layers in the contact region and configured to open the layers of the conductive layers in the contact region through the spaced spaces, and first contact plugs filled into the space between barrier rib patterns adjacent to each other and coupled to the conductive layers in the contact region. | 12-26-2013 |
20130341798 | APPARATUSES INCLUDING STAIR-STEP STRUCTURES AND METHODS OF FORMING THE SAME - Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from of the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. Apparatuses such as memory devices including laterally adjacent first and second regions each of which including contact regions of a different portion of a plurality of conductive materials and related methods of forming such devices are also disclosed. | 12-26-2013 |
20140001638 | Semiconductor Devices and Methods of Manufacture Thereof | 01-02-2014 |
20140001639 | SEMICONDUCTOR DEVICE HAVING SILICON INTERPOSER ON WHICH SEMICONDUCTOR CHIP IS MOUNTED | 01-02-2014 |
20140001640 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE | 01-02-2014 |
20140008806 | STAIR STEP FORMATION USING AT LEAST TWO MASKS - Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed. | 01-09-2014 |
20140008807 | SEMICONDUCTOR CONSTRUCTIONS AND METHODS OF FORMING SEMICONDUCTOR CONSTRUCTIONS - Some embodiments include methods in which first insulative material is formed across a memory region and a peripheral region of a substrate. An etch stop structure is formed to have a higher portion over the memory region than over the peripheral region. A second insulative material is formed to protect the lower portion of the etch stop structure, and the higher portion is removed. Subsequently, at least some of the first and second insulative materials are removed. Some embodiments include semiconductor constructions having a first region with first features, and a second region with second features. The first features are closer spaced than the second features. A first insulative material is over the second region and an insulative structure is over the first insulative material. The structure has a stem joined to a bench. The bench has an upper surface, and the stem extends to above the upper surface. | 01-09-2014 |
20140015142 | SEMICONDUCTOR DEVICE - In a semiconductor device, a first contact-diffusion-layer is in a first well to be connected to the first well and extends in a channel width direction of a first transistor in a first well. A second contact-diffusion-layer is in the first well so as to be electrically connected to the first well and extends in a channel-length direction of the first transistor. A first contact on the first contact-diffusion-layer has a shape with a diameter in the channel-width direction larger than that in the channel-length direction when viewed from above the substrate. A second contact on the second contact-diffusion-layer has a shape with a diameter in the channel-width direction smaller than that of the first contact and a diameter in the channel-length direction almost equal to that of the first contact when viewed from above the substrate. A wiring is electrically connected to the first transistor through the second contact. | 01-16-2014 |
20140021621 | PACKAGED SEMICONDUCTOR DIE WITH POWER RAIL PADS - A packaged semiconductor die has a die support mounting surface mounted to a die support having external connectors. A die connection pad surface opposite to die supporting mount surface has associated die connection pads that are circuit nodes of the semiconductor die. The die connection pad surface also has a power rail pad. The power rail pad has a surface area larger than surface areas of the die connection pads. Bond wires electrically couple the power rail pad to two or more of the die connection pads. | 01-23-2014 |
20140021622 | OPTIMIZATION METALLIZATION FOR PREVENTION OF DIELECTRIC CRACKING UNDER CONTROLLED COLLAPSE CHIP CONNECTIONS - A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads. | 01-23-2014 |
20140021623 | METHOD OF FORMING ELECTRIC CONTACT INTERFACE REGIONS OF AN ELECTRONIC DEVICE - A method for forming electrical-contact interface regions on a wafer including a silicon-carbide substrate having a surface with at least one conductive region facing the surface. The method includes forming a first and a second resist layer; forming; removing portions of the second resist layer to form a through opening partially aligned to the conductive region; removing, selective portions of the first resist layer to expose the surface of the substrate; removing portions of the first resist layer that extend laterally staggered with respect to the through opening; depositing a nickel layer on the wafer to form a nickel region on the substrate in an area corresponding to the conductive region; removing the first and second resist layers; and carrying out a step of thermal treatment of the wafer to form nickel-silicide regions in electrical contact with the conductive region. | 01-23-2014 |
20140021624 | MOUNTING STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor-device mounting structure includes a first semiconductor device and a plate-shaped second semiconductor device connected to the first semiconductor device. The first semiconductor device includes a flexible board, an electronic component, and a sealing resin. The flexible board includes a bendable flexible portion and a hard portion. The flexible portion is bent at a boundary with the hard portion, along a shape of the electronic component such that the flexible board covers the electronic component. The flexible board and the electronic component are sealed with the sealing resin. The first semiconductor device is provided vertical to the second semiconductor device such that the hard portion is provided parallel to the second semiconductor device. | 01-23-2014 |
20140021625 | WIRING SUBSTRATE, METHOD FOR MANUFACTURING THE WIRING SUBSTRATE, AND SEMICONDUCTOR PACKAGE - A wiring substrate includes an insulating layer including a reinforcement member and having a first surface and a second surface positioned on an opposite side of the first surface, an electrode pad exposed from the first surface, a layered body including first insulating layers and being formed on the second surface, the first insulating layers having a first insulating material as a main component, another layered body including second insulating layers and being formed on the layered body, the second insulating layers having a second insulating material as a main component, and another electrode pad exposed from a surface of the another layered body that is opposite to the layered body. The number of the first insulating layers is equal to that of the second insulating layers. The first insulating layers have a thermal expansion coefficient that is greater than that of the second insulating layers. | 01-23-2014 |
20140021626 | LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF MANUFACTURING A LIQUID CRYSTAL DISPLAY DEVICE - A liquid crystal display device ( | 01-23-2014 |
20140021627 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device is provided with a semiconductor element having a plurality of electrodes, a plurality of terminals electrically connected to the plurality of electrodes, and a sealing resin covering the semiconductor element. The sealing resin covers the plurality of terminals such that a bottom surface of the semiconductor element in a thickness direction is exposed. A first terminal, which is one of the plurality of terminals, is disposed in a position that overlaps a first electrode, which is one of the plurality of electrodes, when viewed in the thickness direction. The semiconductor device is provided with a conductive connection member that contacts both the first terminal and the first electrode. | 01-23-2014 |
20140027916 | SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNEL - A semiconductor device includes: bit lines each extending in a first direction; word lines each extending in a second direction, which crosses the first direction; pillars provided in a region between the bit lines and the word lines, wherein the pillars are each arranged along a third direction; and bit line contacts arranged along the third direction and alternately between the pillars and coupled to alternate bit lines. | 01-30-2014 |
20140027917 | NON-LITHOGRAPHIC LINE PATTERN FORMATION - A metal layer is deposited over an underlying material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation and/or nitridation. A hard mask portion is formed over the metal layer. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. The sequence of a surface pull back of the hard mask portion, trench etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a line pattern having a spacing that is not limited by lithographic minimum dimensions. | 01-30-2014 |
20140027918 | CROSS-COUPLING BASED DESIGN USING DIFFUSION CONTACT STRUCTURES - An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a first gate cut region across the first gate structure, and a second gate cut region across the second gate structure; providing a first gate contact over the first gate structure, and a second gate contact over the second gate structure; and providing a diffusion contact structure between the first and second gate cut regions to couple the first gate contact to the second gate contact. | 01-30-2014 |
20140027919 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device which uses a semiconductor chip originally designed for flip chip bonding and is assembled by a wire bonding process to reduce the cost of assembling a semiconductor product. A second electrode pad group and a fourth electrode pad group are located in the central area of the semiconductor chip and a first electrode pad group and a third electrode pad group are located adjacently to the two long sides of the semiconductor chip. The electrode pads of each electrode group are electrically coupled with a plurality of conductive wires. The layouts of the wiring layers formed in an interconnection substrate are modified so that the wire-bonded semiconductor device is the same as a flip-chip-bonded semiconductor device in terms of the positions of input/output signals. | 01-30-2014 |
20140027920 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first semiconductor chip including a first surface and a plurality of first electrodes disposed on the first surface; a second semiconductor chip including a second surface which faces the first surface, a plurality of second electrodes each of which includes at least one end disposed on the second surface, and a plurality of first protrusions each of which surrounds the one end of each of the second electrodes on an electrode by electrode basis; a plurality of conductive joint materials each of which joins a third electrode included in the first electrodes to the one end of an electrode which faces the third electrode among the second electrodes; and a plurality of first underfill resins each of which is disposed inside one of the first protrusions and covers one of the conductive joint materials on a material by material basis. | 01-30-2014 |
20140027921 | Connection Carrier for Semiconductor Chips and Semiconductor Component - A connection carrier for at least one semiconductor chip is disclosed. The connection carrier has a carrier body having a main surface. A first connection area and a second connection area at a distance from the first connection area are formed on the main surface. The connection carrier has a mechanical decoupling device which is intended to reduce transmission of mechanical forces from the carrier body to at least one region of the first connection area. A semiconductor component having such a connection carrier is also stated. | 01-30-2014 |
20140035151 | INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS USING DOUBLE PATTERNING PROCESSES - Integrated circuits and methods for fabricating integrated circuits are provided. One method includes creating a master pattern layout including first and second adjacent cells. The first adjacent cell has a first border pin with a first routing line. The second adjacent cell has a second border pin with a second routing line. The first and second routing lines overlap to define an edge-edge stitch to couple the first and second border pins. The master pattern layout is decomposed into sub-patterns. | 02-06-2014 |
20140035152 | Methods for Cell Phasing and Placement in Dynamic Array Architecture and Implementation of the Same - A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell. | 02-06-2014 |
20140042632 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The semiconductor device includes a semiconductor substrate including a first region straightly connected to a cell string region and a second region adjacent to the first region, a first conductive pattern having a first pitch in the first region, a second conductive pattern connected to the first conductive pattern in the first region and having a structure in which S shaped characters are continuously connected in a zigzag shape, and a third conductive pattern spaced from the second conductive pattern in the second region and having an essentially oval shape in which a central portion thereof is divided. An exposure process margin is improved in an X-decoder region and a failure such as a bridge is reduced to improve characteristics of the semiconductor device. | 02-13-2014 |
20140042633 | SEMICONDUCTOR DEVICES INCLUDING A NON-PLANAR CONDUCTIVE PATTERN, AND METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING A NON-PLANAR CONDUCTIVE PATTERN - Semiconductor devices are provided. The semiconductor devices may include a non-planar conductive pattern. The non-planar conductive pattern may be on an insulating layer and may contact a connection terminal at a plurality of different heights. Related methods of forming semiconductor devices are also provided. | 02-13-2014 |
20140042634 | METHODS OF MAKING COMPLIANT SEMICONDUCTOR CHIP PACKAGES - A semiconductor chip package is fabricated including providing a compliant layer over a contact bearing face of a semiconductor chip, with a bottom surface of the compliant layer adjacent that chip face, a top surface facing away from the bottom surface, and at least one sloping surface extending between the top and bottom surfaces. Bond ribbons can be formed atop the compliant layer, each bond ribbon electrically coupling one of the contacts with an associated conductive terminal at the top surface of the compliant layer. A bond ribbon can include a strip extending along the sloping surface. The strip may have a substantially constant thickness in a direction away from the sloping surface. | 02-13-2014 |
20140042635 | SEMICONDUCTOR DEVICE - One wiring width of upper and lower wiring paths formed facing each other sandwiching an interlayer insulating film is large, and another wiring width is small; and the wiring widths of mutually adjacent wiring paths are formed to be large and small in alternating fashion on the same wiring layer. | 02-13-2014 |
20140042636 | DUMMY PATTERNS AND METHOD FOR GENERATING DUMMY PATTERNS - A method for generating dummy patterns includes providing a layout region having a layout pattern with a first density, inserting a plurality of first dummy patterns with a second density corresponding to the first density in the layout pattern, dividing the layout region into a plurality of sub-regions with a third density, adjusting a size of the first dummy pattern according to a difference between the second density and the third density, and outputting the layout pattern and the first dummy patterns on a photomask. | 02-13-2014 |
20140048944 | INTERCONNECT SUBSTRATE WITH EMBEDDED SEMICONDUCTOR DEVICE AND BUILT-IN STOPPER AND METHOD OF MAKING THE SAME - The present invention relates to an interconnect substrate with an embedded device, a built-in stopper and dual build-up circuitries and a method of making the same. In accordance with one preferred embodiment of the present invention, the method includes: forming a stopper on a dielectric layer; mounting a semiconductor device on the dielectric layer using the stopper as a placement guide for the semiconductor device; attaching a stiffener to the dielectric layer; forming a first build-up circuitry and a second build-up circuitry that cover the semiconductor device, the stopper and the stiffener at both sides; and providing a plated through-hole that provides an electrical connection between the first and second build-up circuitries. Accordingly, the stopper can accurately confine the placement location of the semiconductor device and avoid the electrical connection failure between the semiconductor device and the build-up circuitry. | 02-20-2014 |
20140048945 | NONVOLATILE MEMORY DEVICE AND A METHOD FOR FABRICATING THE SAME - A nonvolatile memory device including a substrate which includes a cell array region and a connection region, an electrode structure formed on the cell array region and the connection region and including a plurality of laminated electrodes, a first recess formed in the electrode structure on the connection region and disposed between the cell array region and a second recess formed in the electrode structure on the connection region, and a plurality of vertical wirings formed on the plurality of electrodes exposed by the first recess. | 02-20-2014 |
20140054783 | STACKED MICROELECTRONIC PACKAGES HAVING SIDEWALL CONDUCTORS AND METHODS FOR THE FABRICATION THEREOF - Methods for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging a plurality of microelectronic device panels in a panel stack. Each microelectronic device panel contains plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are created in the panel stack exposing the plurality of package edge conductors, and a plurality of sidewall conductors is formed interconnecting different ones of the package edge conductors exposed through the trenches. The panel stack is then separated into a plurality of stacked microelectronic packages each including at least two microelectronic devices electrically interconnected by at least one of the plurality of sidewall conductors included within the stacked microelectronic package. | 02-27-2014 |
20140054784 | Integrated Circuit Connector Access Region and Method for Making - A connector access region of an integrated circuit device includes a set of parallel conductors, extending in a first direction, and interlayer connectors. The conductors comprise a set of electrically conductive contact areas on different conductors which define a contact plane with the conductors extending below the contact plane. A set of the contact areas define a line at an oblique angle, such as less than 45° or 5° to 27°, to the first direction. The interlayer connectors are in electrical contact with the contact areas and extend above the contact plane. At least some of the interlayer connectors overlie but are electrically isolated from the electrical conductors adjacent to the contact areas with which the interlayer connectors are in electrical contact. The set of parallel conductors may include a set of electrically conductive layers with the contact plane being generally perpendicular to the electrically conductive layers. | 02-27-2014 |
20140054785 | CHIP PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING SAME - A chip package structure includes a first wiring layer, a first solder mask layer, a chip and a plurality of third contact pads. The third contact pads are formed on the first wiring layer. The third contact pads and the first wiring layer are unitarily formed. The first solder mask layer is formed on the first wiring layer. The first solder mask layer defines a plurality of first openings to expose portions of the first wiring layers. The portions of the first wiring layers exposed to the first openings serve as first contact pads. The chip is mounted on the first solder mask layer and is electrically connected to the first contact pads. This disclosure further relates to a method of manufacturing the chip package structure. | 02-27-2014 |
20140054786 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package including a semiconductor substrate having a first surface and a second surface opposite thereto. A conducting pad is located on the first surface. A side recess is on at least a first side of the semiconductor substrate, wherein the side recess extends from the first surface toward the second surface and across the entire length of the first side. A conducting layer is located on the first surface and electrically connected to the conducting pad, wherein the conducting layer extends to the side recess. | 02-27-2014 |
20140054787 | METHODS OF FORMING A STACK OF ELECTRODES AND THREE-DIMENSIONAL SEMICONDUCTOR DEVICES FABRICATED THEREBY - Provided are methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby. The device may include electrodes sequentially stacked on a substrate to constitute an electrode structure. each of the electrodes may include a connection portion protruding horizontally and outward from a sidewall of one of the electrodes located thereon and an aligned portion having a sidewall coplanar with that of one of the electrodes located thereon or thereunder. Here, at least two of the electrodes provided vertically adjacent to each other may be provided in such a way that the aligned portions thereof have sidewalls that are substantially aligned to be coplanar with each other. | 02-27-2014 |
20140054788 | METHOD FOR FABRICATING NANOGAP ELECTRODES, NANOGAP ELECTRODES ARRAY, AND NANODEVICE WITH THE SAME - A substrate | 02-27-2014 |
20140061932 | Methods and Apparatus for Package on Package Structures - A package-on-package (“PoP”) structure and a method of forming are provided. The PoP structure may be formed by forming a first set of electrical connections on a first substrate. A first material may be applied to the first set of electrical connections. A second substrate may be provided having a second set of electrical connections formed thereon. The first set of electrical connections of the first substrate having the epoxy flux applied may be contacted to the second electrical connections of the second substrate. A reflow process may be performed to electrically connect the first substrate to the second substrate. The epoxy flux applied to the first electrical connections of the first substrate may prohibit electrical bridges or shorts from forming during the reflow process. | 03-06-2014 |
20140061933 | WIRE BOND SPLASH CONTAINMENT - A splash containment structure for semiconductor structures and associated methods of manufacture are provided. A method includes: forming wire bond pads in an integrated circuit chip and forming at least one passivation layer on the chip. The at least one passivation layer includes first areas having a first thickness and second areas having a second thickness. The second thickness is greater than the first thickness. The first areas having the first thickness extend over a majority of the chip. The second areas having the second thickness are adjacent the wire bond pads. | 03-06-2014 |
20140061934 | SEMICONDUCTOR DEVICE - A semiconductor device with a transistor region has a first conductor pattern formed within a multilayer interconnect structure positioned under a signal line and above the transistor region. The first conductor pattern is coupled to ground or a power supply and overlaps the transistor region. The signal line overlaps the first conductor pattern. | 03-06-2014 |
20140070420 | Chip To Package Interface - In accordance with an embodiment of the present invention, a semiconductor package includes a semiconductor chip disposed within an encapsulant, and a first coil disposed in the semiconductor chip. A dielectric layer is disposed above the encapsulant and the semiconductor chip. A second coil is disposed above the dielectric layer. The first coil is magnetically coupled to the second coil. | 03-13-2014 |
20140070421 | INTEGRATED CIRCUIT PACKAGE - An integrated circuit package has a host integrated circuit with an active front side that is surface-mounted on a support and an inactive backside. Conductive pathways extend between the front and back sides of the integrated circuit. A redistribution layer on the back side of the host integrated circuit provides conductive traces and contact pads. The traces of the redistribution layer establish connection between the conductive pathways and the contact pads. At least one additional component is surface-mounted on the back side of the host integrated circuit by electrical connection to the contact pads of the redistribution layer to provide a compact three-dimensional structure. In an alternative embodiment, the additional components can be mounted on the active side. | 03-13-2014 |
20140077380 | BIT CELL WITH DOUBLE PATTERNED METAL LAYER STRUCTURES - An approach for providing SRAM bit cells with double patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process, a word line structure, a ground line structure, a power line structure, or a combination thereof; and providing, via a second patterning process, a bit line structure proximate the word line structure, the ground line structure, the power line structure, or a combination thereof. Embodiments include: providing a first landing pad as the word line structure, and a second landing pad as the ground line structure; and providing the first landing pad to have a first tip edge and a first side edge, and the second landing pad to have a second tip edge and a second side edge, wherein the first side edge faces the second side edge. | 03-20-2014 |
20140077381 | Semiconductor Device and Method of Forming FO-WLCSP with Multiple Encapsulants - A semiconductor device has a first semiconductor die including TSVs mounted to a carrier with a thermally releasable layer. A first encapsulant having a first coefficient of thermal expansion CTE is deposited over the first semiconductor die. The first encapsulant includes an elevated portion in a periphery of the first encapsulant that reduces warpage. A surface of the TSVs is exposed. A second semiconductor die is mounted to the surface of the TSVs and forms a gap between the first and second semiconductor die. A second encapsulant having a second CTE is deposited over the first and second semiconductor die and within the gap. The first CTE is greater than the second CTE. In one embodiment, the first and second encapsulants are formed in a chase mold. An interconnect structure is formed over the first and second semiconductor die. | 03-20-2014 |
20140077382 | SEMICONDUCTOR PACKAGES HAVING WARPAGE COMPENSATION - A semiconductor package can include a substrate body having a first surface and a second surface. A semiconductor chip can be mounted on the first surface and a plurality of electrode pads can be on the second surface and selectively formed to have progressively smaller or larger sizes extending from a central region of the substrate body toward an outer edge of the substrate body based on a reflow soldering process warpage profile for the semiconductor package. | 03-20-2014 |
20140084475 | SEMICONDUCTOR PACKAGE SUBSTRATES HAVING PILLARS AND RELATED METHODS - The substrate includes a first dielectric layer, a first circuit pattern, a plurality of pillars and a second circuit pattern. The first dielectric layer has opposing first and second dielectric surfaces. The first circuit pattern is embedded in the first dielectric layer and defines a plurality of curved trace surfaces. Each of the pillars has an exterior surface adapted for making external electrical connection and a curved base surface abutting a corresponding one of the trace surfaces. The second circuit pattern is on the second dielectric surface of the first dielectric layer and electrically connected to the first circuit pattern. | 03-27-2014 |
20140091472 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor element includes a plurality of electrodes on a main surface, a sealing resin covering at least a part of a side surface of the semiconductor element, and a first insulating layer formed on the main surface of the semiconductor element, a part of the side surface of the semiconductor element, and the sealing resin. The first insulating layer has first openings formed therein to allow the plural electrodes on the main surface to be exposed through the first openings, and a fillet provided on a part of the side surface. The semiconductor element further includes a wiring layer formed in the first openings in such a manner as to be electrically connected to the plural electrodes, and also formed on the first insulating layer, and a second insulating layer having second openings formed on the first insulating layer and the wiring layer. | 04-03-2014 |
20140097543 | BONDING OF SUBSTRATES INCLUDING METAL-DIELECTRIC PATTERNS WITH METAL RAISED ABOVE DIELECTRIC AND STRUCTURES SO FORMED - Bonding of substrates including metal-dielectric patterns on a surface with the metal raised above the dielectric, as well as related structures, are disclosed. One structure includes: a first substrate having a metal-dielectric pattern on a surface thereof, the metal-dielectric pattern including: a metal having a concave upper surface; and a dielectric having a substantially uniform upper surface, wherein the metal on the first substrate is raised above the dielectric on the first substrate; and a second substrate bonded with the first substrate, the second substrate including: a dielectric; and a metal positioned substantially below the dielectric of the second substrate, wherein the first substrate and the second substrate are bonded only at the metal from the first substrate and the metal from the second substrate. | 04-10-2014 |
20140103532 | CHIP-LEVEL HUMIDITY PROTECTION - An electronic apparatus includes a semiconductor substrate, a device structure supported by the semiconductor substrate, and a guard ring surrounding the device structure. The guard ring includes a plurality of conductive structures spaced apart from one another, supported by the semiconductor substrate, and coupled to a voltage source to establish an operating voltage for the guard ring. | 04-17-2014 |
20140103533 | EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR WITH BACK GATE CONTACT - A structure is provided in which the back gate regions are physically separated from one another as opposed to using reversed biased pn junction diodes. In the present disclosure, the back gate regions can be formed first through a buried dielectric material of an extremely thin semiconductor-on-insulator (ETSOI) substrate. After dopant activation, standard device fabrication processes can be performed. A semiconductor base layer portion of the ETSOI substrate can then be removed from the original ETSOI to expose a surface of the back gates. | 04-17-2014 |
20140103534 | ELECTROCHEMICAL DEPOSITION ON A WORKPIECE HAVING HIGH SHEET RESISTANCE - A method for at least partially filling a feature on a workpiece generally includes obtaining a workpiece including a feature, depositing a first conductive layer in the feature, wherein the sheet resistance of the first conductive layer is greater than 10 ohm/square, depositing a second conductive layer in the feature by electrochemical deposition, wherein the electrical contacts are at least partially immersed in the deposition chemistry. | 04-17-2014 |
20140103535 | STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE - A microelectronic package can include a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are joined to corresponding contacts on a surface of the substrate. An axial plane may intersect the face along a line in the first direction and centered relative to the columns of element contacts. Columns of package terminals can extend in the first direction. First terminals in a central region of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between the columns of package terminals. The axial plane can intersect the central region. | 04-17-2014 |
20140103536 | SEMICONDUCTOR DEVICE - A semiconductor device includes: on an upper surface of a second semiconductor chip on a circuit board, a ring dam section formed at an outer circumference of a mounting region above which a first semiconductor chip is mounted; and an interconnect extending from the dam section to a center section of the first semiconductor chip or the second semiconductor chip in a region in which the first semiconductor chip faces the second semiconductor chip. The interconnect is electrically connected to a connection terminal on a circuit formation surface of the first or second semiconductor chip at the center section of the first or second semiconductor chip. The dam section and the interconnect are power supply interconnects or ground interconnects. | 04-17-2014 |
20140103537 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes first electrode interconnect layers and second electrode interconnect layers formed over a nitride semiconductor layer, a first insulating film formed on the first and second electrode interconnect layers and including first openings, first interconnect layers and second interconnect layers formed on the first insulating film and respectively connected to the first electrode interconnect layers and the second electrode interconnection layers through the first openings, a second insulating film formed on the first and second interconnect layers and including second openings, and a first pad layer and a second pad layer formed on the second insulating film and respectively connected to the first interconnect layers and the second interconnect layers through the second openings. | 04-17-2014 |
20140110850 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a first insulating film formed above a substrate, wires formed on the first insulating film, an air gap formed between the adjacent wires, and a second insulating film formed on the wires and the air gap. Each of the wires has a metal film formed on the first insulating film and a hard mask formed on the metal film, the hard mask has a first layer and a second layer, a second internal angle formed by the under surface and the side surface of the second layer on a cross section of the second layer is smaller than a first internal angle formed by the under surface and the side surface of the first layer on a cross section of the first layer, and the top surface of the air gap is higher than the top surface of the metal film. | 04-24-2014 |
20140110851 | Semiconductor Device - A semiconductor device includes a plurality of bit lines that intersect an active region on a substrate and extend in a first direction, a contact pad formed on the active region between adjacent bit lines, and a plurality of spacers disposed on sidewalls of the plurality of bit lines. An upper portion of the contact pad is interposed between adjacent spacers, and a lower portion of the contact pad has a width greater than a distance between adjacent spacers. | 04-24-2014 |
20140110852 | ACTIVE MATRIX SUBSTRATE, AND DISPLAY DEVICE - An active matrix substrate ( | 04-24-2014 |
20140110853 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, METHOD FOR GENERATING MASK DATA, MASK AND COMPUTER READABLE RECORDING MEDIUM - A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines. | 04-24-2014 |
20140110854 | SEMICONDUCTOR DIES WITH REDUCED AREA CONSUMPTION - The width of scribe lines may be reduced in semiconductor devices by applying a process technique in which trenches may be formed first from the rear side on the basis of a required width of the corresponding trenches, while subsequently it may be cut into the substrate from the front side on the basis of a reduced thickness of the corresponding saw blades, thereby also enabling a reduction of the scribe line width. Furthermore, contamination of the front side, i.e., of the metallization system, may be reduced, for instance, by performing an optional intermediate cleaning process. | 04-24-2014 |
20140117554 | PACKAGED INTEGRATED CIRCUIT HAVING LARGE SOLDER PADS AND METHOD FOR FORMING - A package substrate has a die mounted on a first side. One or more inner solder pads are on an inner portion of a second side. A perimeter of the inner portion is aligned with a perimeter of the die. The one or more inner solder pads are the only solder pads on the inner portion. The one or more inner solder pads number no more than five. A plurality of outer solder pads are on an outer portion of the second side. An average of areas of the one or more inner solder pads is at least five times an average of areas of the one or more inner solder pads. The plurality of outer solder ball pads are for receiving solder ball balls. The outer portion is spaced from the perimeter of the inner portion. The outer portion and the inner portion are coplanar. | 05-01-2014 |
20140117555 | Integrated Circuit Underfill Scheme - An integrated circuit includes a substrate having at least one depression on a top surface. At least one solder bump is disposed over the substrate. A die is disposed over the at least one solder bump and electrically connected with the substrate through the at least one solder bump. An underfill surrounds the at least one solder bump and is formed between the substrate and the die. The at least one depression is disposed around the underfill to keep any spillover from the underfill in the at least one depression. | 05-01-2014 |
20140124938 | STRESS RELIEF FOR PLASTIC ENCAPSULATED DEVICES - A semiconductor integrated circuit includes a semiconductor substrate, one or more devices in or on the semiconductor substrate, and a dielectric layer above the one or more devices, wherein the dielectric layer has openings over at least portions of the one or more devices. The semiconductor integrated circuit also includes plastic packaging material (e.g., plastic granules) on a top surface of the dielectric layer and over the openings. In some implementations, the one or more devices include bi-polar transistors, and the openings in the dielectric layer are located over base-emitter junctions of the bi-polar devices. | 05-08-2014 |
20140124939 | DISCRETE DEVICE MOUNTED ON SUBSTRATE - A method of making an electronic device having a discrete device mounted on a surface of an electronic die with both the discrete device and the die connected by heat cured conductive ink and covered with cured encapsulant including placing the discrete device on the die; and keeping the temperature of each of the discrete device and the die below about 200° C. Also disclosed is a method of electrically attaching a discrete device to a substrate that includes placing the device on the substrate, applying conductive ink that connects at least one terminal on the device to at least one contact on the substrate and curing the conductive ink. Also disclosed is an IC package with a discrete electrical device having electrical terminals; an electrical substrate having contact pads on a surface thereof; and cured conductive ink connecting at least one of the electrical terminals with at least one of the contact pads. | 05-08-2014 |
20140124940 | FLEXIBLE ROUTING FOR CHIP ON BOARD APPLICATIONS - Methods, systems, and apparatuses for semiconductor devices are provided herein. A semiconductor device includes an array of conductive pads for signals. One or more non-linear compliant springs may be present to route signals from the conductive pads to interconnect pads formed on the semiconductor device to attach bump interconnects. Each non-linear compliant spring may include one or more routing segments. The semiconductor device may be mounted to a circuit board by the bump interconnects. When the semiconductor device operates, heat may be generated by the semiconductor device, causing thermal expansion by the semiconductor device and the circuit board. The semiconductor device and circuit board may expand by different amounts due to differences in their thermal coefficients of expansion. The non-linear compliant springs provide for compliance between the conductive pads and bump interconnects to allow for the different rates of expansion. | 05-08-2014 |
20140124941 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first base material having a first surface; a second base material having a coefficient of linear expansion different from that of the first base material, being in contact with the first base material, and having a second surface being adjacent to the first surface; and a first interconnect formed over the first and second surfaces to straddle a borderline between the first and second base materials. The cross-sectional area of the first interconnect along the borderline is greater than the cross-sectional area of at least part of a portion of the first interconnect on the first surface along a width of the first interconnect, or the cross-sectional area of at least part of a portion of the first interconnect on the second surface along the width of the first interconnect. | 05-08-2014 |
20140124942 | Reducing Loadline Impedance in a System - In one embodiment, the present invention includes a method of mounting a semiconductor device to a first side of a circuit board; and mounting at least one voltage regulator device to a second side of the circuit board, the second side opposite to the first side. The voltage regulator devices may be output filters, inductors, capacitors, and the like. In certain embodiments, the devices may be located directly underneath the semiconductor device. | 05-08-2014 |
20140131878 | SEMICONDUCTOR DEVICES WITH ENHANCED ELECTROMIGRATION PERFORMANCE - Semiconductor devices with enhanced electromigration performance and methods of manufacture are disclosed. The method includes forming at least one metal line in electrical contact with a device. The method further includes forming at least one staple structure in electrical contact with the at least one metal line. The at least one staple structure is formed such that electrical current passing through the at least one metal line also passes through the at least staple structure to reduce electromigration issues. | 05-15-2014 |
20140131879 | DESIGN METHOD OF WIRING LAYOUT, SEMICONDUCTOR DEVICE, PROGRAM FOR SUPPORTING DESIGN OF WIRING LAYOUT, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a design method of layout formed by a sidewall method is provided. The method includes: preparing a base pattern on which a plurality of first patterns extending in a first direction and arranged at a first space in a second direction intersecting the first direction and a plurality of second patterns extending in the first direction and arranged at a center between the first patterns, respectively, are provided; and drawing a connecting portion which extends in the second direction and connects two neighboring first patterns sandwiching one of the second patterns, and separating the one of the second patterns into two patterns not contacting the connecting portion. | 05-15-2014 |
20140131880 | METHODS FOR FABRICATION OF AN AIR GAP-CONTAINING INTERCONNECT STRUCTURE - Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures. | 05-15-2014 |
20140138837 | SANDWICHED DIFFUSION BARRIER AND METAL LINER FOR AN INTERCONNECT STRUCTURE - A trench is opened in a dielectric layer. The trench is then lined with a sandwiched diffusion barrier and metal liner structure and a metal seed layer. The sandwiched diffusion barrier and metal liner structure includes a conformal metal liner layer sandwiched between a first diffusion barrier layer and a second diffusion barrier layer. The metal seed layer is at least lightly doped. The lined trench is then filled by electroplating with a metal fill material. A dielectric cap layer is then deposited over the metal filled trench. Dopant from the doped metal seed layer is then migrated to an interface between the metal filled trench and the dielectric cap layer to form a self-aligned metal cap. | 05-22-2014 |
20140138838 | Method of Semiconducotr integrated Circuit Fabrication - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A first dielectric layer is deposited on the substrate. A patterned photoresist layer is formed on the first dielectric layer. The patterned photoresist layer is trimmed. The first dielectric layer is etched through the trimmed patterned photoresist layer to form a dielectric feature. A sacrificing energy decomposable layer (SEDL) is deposited on the dielectric feature and etched to form a SEDL spacer on sides of the dielectric feature. A second dielectric layer is deposited on the SEDL spacer and etched to form a dielectric spacer. The SEDL spacer is decomposed to form a trench. | 05-22-2014 |
20140138839 | POWER SEMICONDUCTOR MODULE - Disclosed herein is a power semiconductor module including a substrate having a first metal conductive track formed on one surface thereof, and a base plate made of a metal and solder-joined to the substrate in the first metal conductive track region, wherein a first uneven pattern is formed in the solder junction region formed between the substrate and the base plate. | 05-22-2014 |
20140138840 | STAIR STEP FORMATION USING AT LEAST TWO MASKS - Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed. | 05-22-2014 |
20140145342 | METAL DENSITY DISTRIBUTION FOR DOUBLE PATTERN LITHOGRAPHY - Methods, a computer readable medium, and an apparatus are provided. A method includes and the computer readable medium is configured for decomposing an overall pattern into a first mask pattern that includes a power rail base pattern and into a second mask pattern, and generating on the second mask pattern a power rail insert pattern that is at least partially aligned with the power rail base pattern of the first mask pattern. The apparatus is produced by photolithography using photolithographic masks generated by the method. | 05-29-2014 |
20140145343 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device comprises: a semiconductor structure formed with openings for exposing pads on an one surface thereof, a first conductive layer formed in the openings to make the one surface of the semiconductor structure more uniform, and conductive patterns formed on portions of the one surface of the semiconductor structure including the first conductive layers. | 05-29-2014 |
20140145344 | Semiconductor Constructions and Methods of Forming Semiconductor Constructions - Some embodiments include methods in which first insulative material is formed across a memory region and a peripheral region of a substrate. An etch stop structure is formed to have a higher portion over the memory region than over the peripheral region. A second insulative material is formed to protect the lower portion of the etch stop structure, and the higher portion is removed. Subsequently, at least some of the first and second insulative materials are removed. Some embodiments include semiconductor constructions having a first region with first features, and a second region with second features. The first features are closer spaced than the second features. A first insulative material is over the second region and an insulative structure is over the first insulative material. The structure has a stem joined to a bench. The bench has an upper surface, and the stem extends to above the upper surface. | 05-29-2014 |
20140151890 | PACKAGE WITH A FAN-OUT STRUCTURE AND METHOD OF FORMING THE SAME - An embodiment is a device comprising a semiconductor die, an adhesive layer on a first side of the semiconductor die, and a molding compound surrounding the semiconductor die and the adhesive layer, wherein the molding compound is at a same level as the adhesive layer. The device further comprises a first post-passivation interconnect (PPI) electrically coupled to a second side of the semiconductor die, and a first connector electrically coupled to the first PPI, wherein the first connector is over and aligned to the molding compound. | 06-05-2014 |
20140151891 | SEMICONDUCTOR PACKAGE - A semiconductor package includes: a first wiring substrate; a first spacer on the first wiring substrate, wherein the first spacer has a rectangular shape; a second spacer on the first wiring substrate to be separated from the first spacer, wherein the second spacer has a rectangular shape; a second wiring substrate on the first spacer and the second spacer and having a first surface and a second surface which is opposite to the first surface, wherein the second wiring substrate has opposed sides; a first semiconductor chip on the first surface of the second wiring substrate; and a second semiconductor chip on the second surface of the second wiring substrate to be disposed between the first spacer and the second spacer. The opposed long sides of the first and second spacers are substantially parallel with the opposed sides of the second wiring substrate. | 06-05-2014 |
20140159244 | Process to Achieve Contact Protrusion for Single Damascene Via - The present disclosure relates to a method of forming a back-end-of-the-line metal contact that eliminates RC opens caused by metal dishing during chemical mechanical polishing. The method is performed by depositing a sacrificial UV/thermal decomposition layer (UTDL) above an inter-level dielectric (ILD) layer. A metal contact is formed that extend through the ILD layer and the sacrificial UTDL. A chemical mechanical polishing (CMP) process is performed to generate a planar surface comprising the sacrificial UTDL. The sacrificial UTDL is then removed through an ultraviolet exposure or a thermal anneal, so that the metal contact protrudes from the ILD layer. | 06-12-2014 |
20140159245 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in a region where an occupation rate of wiring is smaller than those in other regions, a dummy wiring is provided. On the contrary, when the occupation rate of wiring is larger than in other regions, slits are formed in the wiring to control the wiring occupation rate. In the respective wirings layers, the shapes, sizes and intervals of wirings below the respective electrode pads are made similar or equal to one another. | 06-12-2014 |
20140159246 | METHODS OF MANUFACTURING NAND FLASH MEMORY DEVICES - A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction | 06-12-2014 |
20140167272 | Semiconductor Device Having an Identification Mark - A semiconductor device includes a chip, a contact pad arranged over the front side of the chip and an identification mark arranged over the contact pad. The identification mark includes an information about a property of the chip. | 06-19-2014 |
20140167273 | LOW PARASITIC PACKAGE SUBSTRATE HAVING EMBEDDED PASSIVE SUBSTRATE DISCRETE COMPONENTS AND METHOD FOR MAKING SAME - One feature pertains to a multi-layer package substrate of an integrated circuit package that comprises a discrete circuit component (DCC) having at least one electrode. The DCC is embedded within an insulator layer, and a via coupling component electrically couples to the electrode. A first portion of the via coupling component extends beyond a first edge of the electrode, and a plurality of vias each having a first end couple to the first via coupling component. At least a first via of the plurality of vias couples to the first portion of the via coupling component that extends beyond the first edge of the electrode. Moreover, the plurality of vias each have a second end that electrically couple to a first outer metal layer, and at least a second portion of the via coupling component is positioned within a first inner metal layer. | 06-19-2014 |
20140167274 | ARRAY SUBSTRATE AND DISPLAY DEVICE - The embodiments of the present invention disclose an array substrate and a display device. The array substrate comprises a substrate and a first transparent conductive layer, an insulating layer and a second transparent conductive layer sequentially formed on the substrate, wherein the second transparent conductive layer has a plurality of slit structures, the first transparent conductive layer has a plurality of protrusions corresponding to the plurality of slit structures, and a height of the plurality of protrusions is smaller than a distance between the first transparent conductive layer and the second transparent conductive layer. | 06-19-2014 |
20140167275 | EMBEDDED PACKAGE AND METHOD OF MANUFACTURING THE SAME - An embedded package in which active elements, such as semiconductor chips, are embedded within a package substrate. The semiconductor chips, embedded within a dielectric layer, are coupled with circuit wires to ensure electrical and signal continuity. | 06-19-2014 |
20140167276 | SUBSTRATE FOR SEMICONDUCTOR PACKAGE, SEMICONDUCTOR PACKAGE USING THE SUBSTRATE, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A semiconductor package includes a package substrate, semiconductor chips adhered over the package substrate and configured to include bonding pads, one or more dummy patterns disposed at specific intervals in peripheries of the semiconductor chips, an insulating layer formed over the package substrate including the semiconductor chips and the dummy patterns so that the bonding pads are exposed, and wire patterns formed over the insulating layer and coupled with the bonding pads. | 06-19-2014 |
20140167277 | SEMICONDUCTOR WIRING PATTERNS - A semiconductor device includes a rectangular semiconductor element mounted on a substrate formed with an external input terminal, an external output terminal, and a plurality of wiring patterns connected to each of the external input terminal and the external output terminal. The semiconductor element includes, a plurality of first electrodes formed along a first edge of a surface thereof, a plurality of second electrodes formed along an edge opposite to the first edge of the surface, a plurality of third electrodes formed in the neighborhood of a functional block, and an internal wiring for connecting the first electrodes and the third electrodes. The substrate includes, a first wiring pattern for connecting the external input terminal and the first electrodes, a second wiring pattern for connecting the external output terminal and the second electrodes, and a third wiring pattern for connecting the first electrodes and the third electrodes. | 06-19-2014 |
20140167278 | STUB MINIMIZATION USING DUPLICATE SETS OF TERMINALS FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS - A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face facing away from a substrate of the package, and electrically connected with the substrate through conductive structure extending above the front face. First terminals provided in first and second parallel grids or in first and second individual columns can be configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid can have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid. | 06-19-2014 |
20140167279 | STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS IN ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE - A microelectronic assembly can include a circuit panel having first and second panel contacts at respective first and second surfaces thereof, and first and second microelectronic packages each having terminals mounted to the respective panel contacts. Each package can include a microelectronic element having a face and contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. The terminals can include first terminals at positions within first and second parallel grids. The first terminals can be configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. Signal assignments of the first terminals in the first grid can be a mirror image of signal assignments of the first terminals in the second grid. | 06-19-2014 |
20140175657 | METHODS TO IMPROVE LASER MARK CONTRAST ON DIE BACKSIDE FILM IN EMBEDDED DIE PACKAGES - Apparatus including a die including a device side with contact points; and a build-up carrier disposed on the device side of the die; and a film disposed on the back side of the die, the film including a markable material including a mark contrast of at least 20 percent. Method including forming a body of a build-up carrier adjacent a device side of a die; and forming a film on a back side of the die, the film including a markable material including a mark contrast of at least 20 percent. Apparatus including a package including a microprocessor disposed in a carrier; a film on the back side of the microprocessor, the film including a markable material including a mark contrast of at least 20 percent; and a printed circuit board coupled to at least a portion of the plurality of conductive posts of the carrier. | 06-26-2014 |
20140175658 | ANCHORING A TRACE ON A SUBSTRATE TO REDUCE PEELING OF THE TRACE - Sonic implementations pertain to a semiconductor device that includes a packaging substrate, a trace coupled to the packaging substrate, and a solder resist layer that covers part of the trace. The trace includes a first portion having a first width, and a second portion having a second width that is wider than the first width. In some implementations, the second portion having the second width increases the area of the trace coupled to the packaging substrate to reduce the likelihood of the trace peeling from the packaging substrate. In some implementations, the solder resist layer further includes an opening such that the second portion of the trace is exposed. In some implementations, the trace further includes a third portion located between the first portion and second portion of the trace and wherein the third portion of the trace is exposed through an opening in the solder resist layer. | 06-26-2014 |
20140175659 | SEMICONDUCTOR DEVICE INCLUDING AIR GAPS AND METHOD OF FABRICATING THE SAME - This technology provides a semiconductor device and a method of fabricating the same, which may reduce parasitic capacitance between adjacent conductive structures. The method of fabricating a semiconductor device may include forming a plurality of bit line structures over a substrate, forming contact holes between the bit line structures, forming sacrificial spacers over sidewalls of the contact holes, forming first plugs recessed into the respective contact holes, forming air gaps by removing the sacrificial spacers, forming capping structures capping the air gaps while exposing top surfaces of the first plugs, and forming second plugs over the first plugs. | 06-26-2014 |
20140175660 | STACK PACKAGES HAVING TOKEN RING LOOPS - Stack packages are provided. The stack package includes a substrate having first and second bond fingers and a plurality of semiconductor chips stacked on the substrate. Each of the plurality of semiconductor chips has an input bonding pad and an output bonding pad. A first interconnection electrically connects the first bond finger to the input bonding pad of a lowermost semiconductor chip of the plurality of semiconductor chips. A second interconnection electrically connects the output bonding pad of a lower semiconductor chip of the plurality of semiconductor chips to the input bonding pad of an upper semiconductor chip stacked on the lower semiconductor chip. A third interconnection electrically connects the output bonding pad of an uppermost semiconductor chip of the plurality of semiconductor chips to the second bond finger. | 06-26-2014 |
20140175661 | Semiconductor Device and Method of Making Bumpless Flipchip Interconnect Structures - A semiconductor device includes a substrate with contact pads. A mask is disposed over the substrate. Aluminum-wettable conductive paste is printed over the contact pads of the substrate. A semiconductor die is disposed over the aluminum-wettable conductive paste. The aluminum-wettable conductive paste is reflowed to form an interconnect structure over the contact pads of the substrate. The contact pads include aluminum. Contact pads of the semiconductor die are disposed over the aluminum-wettable conductive paste. The aluminum-wettable conductive paste is reflowed to form an interconnect structure between the contact pads of the semiconductor die and the contact pads of the substrate. The interconnect structure is formed directly on the contact pads of the substrate and semiconductor die. The contact pads of the semiconductor die are etched prior to reflowing the aluminum-wettable conductive paste. An epoxy pre-dot to maintain a separation between the semiconductor die and substrate. | 06-26-2014 |
20140175662 | POWER LAYOUT FOR INTEGRATED CIRCUITS - An integrated circuit with a power layout includes at least one power grid cell. Each power grid cell includes a first power layer configured to be electrically coupled to a first power supply voltage, and a second power layer separate from the first power layer and configured to be electrically coupled to a second power supply voltage different from the first power supply voltage. The first power layer has conductive lines configured to surround a conductive element electrically connected to the second power layer. | 06-26-2014 |
20140183747 | MULTI-DIE, HIGH CURRENT WAFER LEVEL PACKAGE - Wafer-level package semiconductor devices for high-current applications are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar. The wafer-level package device also includes an integrated circuit chip device (e.g., small die) configured upon the integrated circuit chip (e.g., large die). In the wafer-level package device, the height of the integrated circuit chip device is less than the height of the pillar and/or less than the combined height of the pillar and the one or more solder contacts. | 07-03-2014 |
20140183748 | Microbump and Sacrificial Pad Pattern - Embodiments described herein generally relate to connections for integrated circuit (IC) dies. For example, in an embodiment an integrated circuit (IC) die is provided. The IC die includes a plurality of clusters of pads formed on a surface of the IC die, each cluster being associated with a respective circuit formed in the IC die. Each cluster includes a plurality of micropads each electrically coupled to the circuit associated with the cluster through a respective via and a sacrificial pad coupled to the circuit through the plurality of micropads, the sacrificial pad being larger than each of the micropads. | 07-03-2014 |
20140183749 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - In a method of fabricating a semiconductor device, sacrificial layer patterns are formed by leaving portions of sacrificial layers, instead of completely removing the sacrificial layers. Thus, the reliability of the semiconductor device may be increased, and the process of manufacturing the same may be simplified. | 07-03-2014 |
20140183750 | ULTRATHIN BURIED DIE MODULE AND METHOD OF MANUFACTURING THEREOF - A method of forming a buried die module includes providing an initial laminate flex layer and forming a die opening through the initial laminate flex layer. A first uncut laminate flex layer is secured to the first surface of the initial laminate flex layer by way of an adhesive material and a die is positioned within the die opening of the initial laminate flex layer and onto the adhesive material. A second uncut laminate flex layer is secured to the second surface of the initial laminate flex layer by way of an adhesive material and the adhesive materials are then cured. Vias and metal interconnects are formed in and on the first and second uncut laminate flex layers, with each of the metal interconnects extending through a respective via and being directly metalized to a metal interconnect on the initial laminate flex layer or a die pad on the die. | 07-03-2014 |
20140183751 | THREE-DIMENSIONAL STRUCTURE IN WHICH WIRING IS PROVIDED ON ITS SURFACE - One aspect of the present invention is a three-dimensional structure in which a wiring is formed on a surface, the three-dimensional structure having an insulating resin layer that contains a filler formed from at least one element selected from typical non-metal elements and typical metal elements, wherein a recessed gutter for wiring is formed on a surface of the insulating resin layer, and at least a part of a wiring conductor is embedded in the recessed gutter for wiring. | 07-03-2014 |
20140191403 | MULTI-DIE SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THEREOF - A multi-die semiconductor package and various methods of manufacturing the same. In one embodiment, the semiconductor package includes: (1) a substrate, (2) a first die coupled to the substrate, the first die having a first set of terminals located along a first edge and bearing a first integrated circuit (IC) that substantially occupies an area of the first die, (3) a second die coupled to the substrate, the second die having a second set of terminals and bearing a second IC that substantially occupies an area of the second die, the first and second ICS being mirror-images of one another and (4) interconnects coupling corresponding terminals of the first and second sets together. | 07-10-2014 |
20140191404 | LOCAL INTERCONNECT STRUCTURE AND FABRICATION METHOD - Local interconnect structures and fabrication methods are provided. A dielectric layer can be formed on a semiconductor substrate. A first film layer can be patterned on the dielectric layer to define a region surrounded by a local interconnect structure to be formed. A sidewall spacer can be formed and patterned surrounding the first film layer on an exposed surface portion of the dielectric layer. A second film layer can be formed on the exposed surface portion of the dielectric layer and can have a top surface substantially flushed with a top surface of the sidewall spacer. The patterned sidewall spacer can be removed to form a first opening. After forming the first opening, the dielectric layer can be etched to form a second opening through the dielectric layer. The second opening can be filled with a conductive material to form the local interconnect structure. | 07-10-2014 |
20140191405 | METHOD OF FORMING PATTERNS FOR SEMICONDUCTOR DEVICE - Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed. The first layer in the first and second regions are simultaneously etched by using the plurality of spacers and the blocking pattern as etch masks in the first region and using the low-density large-width pattern as an etch mask in the second region. | 07-10-2014 |
20140191406 | MANUFACTURING METHOD FOR SEMICONDUCTOR PACKAGE, SEMICONDUCTOR PACKAGE, AND SEMICONDUCTOR DEVICE - One aspect of the present invention resides in a manufacturing method for a semiconductor package, including a covering step of forming a covering insulating layer that covers the surface of a semiconductor element, a film-forming step of forming a resin film on the surface of the covering insulating layer, a circuit pattern-forming step of forming a circuit pattern portion including recesses reaching the surfaces of electrodes of the semiconductor element and a circuit groove having a desired shape and a desired depth, a catalyst-depositing step of depositing a plating catalyst or a precursor thereof on the surface of the circuit pattern portion, a film-separating step of separating the resin film from the covering insulating layer, and a plating processing step of forming a circuit electrically connected to the electrodes, by applying electroless plating to the covering insulating layer, from which the resin film is separated. | 07-10-2014 |
20140197542 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES - Semiconductor devices are provided. A semiconductor device may include a substrate and a plurality of lines on the substrate. The semiconductor device may include a dielectric layer on the substrate and adjacent the plurality of lines. The semiconductor device may include a connection element in the dielectric layer. In some embodiments, the semiconductor device may include a plurality of contacts on the connection element, and a conductive interconnection on one of the plurality of contacts that are on the connection element and on a contact that is spaced apart from the connection element. | 07-17-2014 |
20140197543 | Enforcement of Semiconductor Structure Regularity for Localized Transistors and Interconnect - A global placement grating (GPG) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the GPG is positioned to intersect each contact that interfaces with the chip level. A number of subgratings are defined. Each subgrating is a set of equally spaced virtual lines of the GPG that supports a common layout shape run length thereon. The layout for the chip level is partitioned into subgrating regions. Each subgrating region has any one of the defined subgratings allocated thereto. Layout shapes placed within a given subgrating region in the chip level are placed in accordance with the subgrating allocated to the given subgrating region. Non-standard layout shape spacings at subgrating region boundaries can be mitigated by layout shape stretching, layout shape insertion, and/or subresolution shape insertion, or can be allowed to exist in the final layout. | 07-17-2014 |
20140203440 | MICROELECTRONIC PACKAGE AND METHOD OF MANUFACTURE THEREOF - A microelectronic assembly may include a substrate having an opening extending between first and second oppositely facing surfaces of the substrate, the opening elongated in a first direction; and at least one microelectronic element having a front face facing and attached to the first surface of the substrate and a plurality of contacts at the front face overlying the opening, the microelectronic element having first and second opposite peripheral edges extending away from the front face. The first peripheral edge extends beyond, or is aligned in the first direction with, an inner edge of the opening, and the opening extends beyond the second peripheral edge. | 07-24-2014 |
20140203441 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Possible to form an opening having a sufficient opening diameter in a region sandwiched between a pair of bit lines and thereby provide a semiconductor device in which a high-quality contact using the opening is formed. | 07-24-2014 |
20140203442 | WIRING STRUCTURES FOR THREE-DIMENSIONAL SEMICONDUCTOR DEVICES - Wiring structures of three-dimensional semiconductor devices and methods of forming the same are provided. The wiring structures may include an upper wordline and a lower wordline, each of which extends in a longitudinal direction. The upper wordline may include a recessed portion that extends for only a portion of the upper wordline in a transverse direction and the lower wordline may include a wiring area exposed by the recessed portion of the upper wordline. The wiring structures may also include an upper contact plug contacting the upper wordline and a lower contact plug contacting the wiring area. The upper and lower contact plugs may extend in a vertical direction. | 07-24-2014 |
20140203443 | Semiconductor Device and Method of Providing Z-Interconnect Conductive Pillars with Inner Polymer Core - A semiconductor device is made by providing a sacrificial substrate and depositing an adhesive layer over the sacrificial substrate. A first conductive layer is formed over the adhesive layer. A polymer pillar is formed over the first conductive layer. A second conductive layer is formed over the polymer pillar to create a conductive pillar with inner polymer core. A semiconductor die or component is mounted over the substrate. An encapsulant is deposited over the semiconductor die or component and around the conductive pillar. A first interconnect structure is formed over a first side of the encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The sacrificial substrate and adhesive layers are removed. A second interconnect structure is formed over a second side of the encapsulant opposite the first interconnect structure. The second interconnect structure is electrically connected to the conductive pillar. | 07-24-2014 |
20140203444 | SEMICONDUCTOR DEVICE AND POWER SOURCE DEVICE - A manufacturing of a semiconductor device includes forming one of a layer with a first metal and the layer with a second metal on one of a semiconductor chip mounting area of a support plate and a back surface of the semiconductor chip; forming the other of the layer with the first metal and the layer with the second metal on an area corresponding to a part of the area, in which one of the layer with the first metal and the layer with the second metal, of the other one of the semiconductor chip mounting area and the back surface of the semiconductor chip; and forming a layer which includes an alloy with the first metal and the second metal after positioning the semiconductor chip in the semiconductor chip mounting area to bond the semiconductor chip with the semiconductor chip mounting area. | 07-24-2014 |
20140210093 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a functional block unit, external terminals and, and an external resin sealing body. The functional block unit includes an internal resin sealing body having an edge and an opposite edge. The edge side of the internal resin sealing body covers a first end of an internal terminal, but does not cover a second end of the internal terminal. The edge side of the internal resin sealing body covers a first end of an internal terminal, but does not cover a second end of the internal terminal. The external resin sealing body covers the root portion and a portion of the middle portion of the external terminal, but does not cover the terminal portion of the external terminal. The functional block unit and the external terminals and are integrally connected together and sealed by the external resin sealing body. | 07-31-2014 |
20140210094 | WIRING STRUCTURE, DROPLET DISCHARGE HEAD, AND DROPLET DISCHARGE APPARATUS - A droplet discharge head includes: a vibrating plate on which first and second terminals are formed; a reservoir forming substrate bonded to the vibrating plate and including a first inclined surface as a side surface on which a first wiring electrically connected to the first terminal is formed and that is inclined to a plate surface; and a wiring substrate bonded to the vibrating plate and including a second inclined surface as a side surface on which a second wiring electrically connected to the second terminal is formed and that is inclined to a plate surface along the first inclined surface. | 07-31-2014 |
20140210095 | METHODS OF MANUFACTURING NAND FLASH MEMORY DEVICES - A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction | 07-31-2014 |
20140210096 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE DESIGN METHOD, SEMICONDUCTOR DEVICE DESIGN APPARATUS, AND PROGRAM - A semiconductor device includes a semiconductor chip, the semiconductor chip including a substrate, a multilayer interconnect layer formed over the substrate, an outer peripheral cell column disposed along an edge of the substrate in a plan view, the outer peripheral cell column having at least one first I/O cell, and an inner peripheral cell column formed at an inner peripheral side of the outer peripheral cell column, the inner peripheral cell column having at least one second I/O cell. | 07-31-2014 |
20140217596 | POWER TRANSISTOR ARRANGEMENT AND METHOD FOR MANUFACTURING THE SAME - Various embodiments provide a power transistor arrangement. The power transistor arrangement may include a carrier; a first power transistor having a control electrode and a first power electrode and a second power electrode; and a second power transistor having a control electrode and a first power electrode and a second power electrode. The first power transistor and the second power transistor may be arranged next to each other on the carrier such that the control electrode of the first power transistor and the control electrode of the second power transistor are facing the carrier. | 08-07-2014 |
20140217597 | Semiconductor Device and Method of Forming Stress Relieving Vias for Improved Fan-Out WLCSP Package - A semiconductor device includes a semiconductor die. An encapsulant is disposed around the semiconductor die to form a peripheral area. An interconnect structure is formed over a first surface of the semiconductor die and encapsulant. A plurality of vias is formed partially through the peripheral area of the encapsulant and offset from the semiconductor die. A portion of the encapsulant is disposed over a second surface of the semiconductor die opposite the first surface. The plurality of vias comprises a depth greater than a thickness of the portion of the encapsulant. A first portion of the plurality of vias is formed in a row offset from a side of the semiconductor die. A second portion of the plurality of vias is formed as an array of vias offset from a corner of the semiconductor die. A repair material disposed within the plurality of vias. | 08-07-2014 |
20140217598 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a plurality of interconnects of an nth layer, a plurality of interconnects of a (n+1)th layer, a plurality of stacked films of the nth layer, each of the plurality of stacked films of the nth layer including a memory element, an inter-layer insulating film of the nth layer, a plurality of interconnects of a (n+2)th layer, a plurality of stacked films of the (n+1)th layer, each of the plurality of stacked films of the (n+1)th layer including a memory element, and an inter-layer insulating film of the (n+1)th layer. The inter-layer insulating film of the (n+1)th layer is provided also at a side surface of an end portion in the first direction of the interconnects of the nth layer. | 08-07-2014 |
20140217599 | BBUL MATERIAL INTEGRATION IN-PLANE WITH EMBEDDED DIE FOR WARPAGE CONTROL - An apparatus including a die including a first side and an opposite second side including a device side with contact points and lateral sidewalls defining a thickness of the die; a primary core adjacent at least a pair of the lateral sidewalls of the die; and a build-up carrier coupled to the second side of the die, the build-up carrier including a plurality of alternating layers of conductive material and insulating material, wherein at least one of the layers of conductive material is coupled to one of the contact points of the die. A method of forming a package and an apparatus including a computing device including a package are also disclosed. | 08-07-2014 |
20140217600 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention includes a plate electrode to be a plate-shaped electrode member, an epoxy sheet serving as an integrated insulating sheet and provided on the plate electrode, a double printed board serving as a control board and provided on the epoxy sheet, and a board integrated electrode in which the plate electrode and the double printed board are formed integrally by the epoxy sheet. | 08-07-2014 |
20140217601 | SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device. The semiconductor device comprises: a metal pad and a first specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device. The first specific metal layer routing is formed on a second metal layer of the semiconductor device, and directly under the metal pad. | 08-07-2014 |
20140217602 | SEMICONDUCTOR DEVICE - Provided is a semiconductor package with improved mounting property. A concave portion is provided in an insulating resin between an island for mounting a semiconductor chip thereon and an opposing lead, to thereby prevent contact between solder printed on a circuit board and the insulating resin. Self-alignment property in melting solder is improved to increase an effective bonding area. | 08-07-2014 |
20140232006 | Device and Method for Manufacturing a Device - A device includes a semiconductor chip including a frontside, a backside, and a side surface extending from the backside to the frontside. The side surface includes a first region and a second region, wherein a level of the first region is different from a level of the second region. The device further includes an electrically conductive material arranged over the backside of the semiconductor chip and over the first region of the side surface, wherein the second region of the side surface is uncovered by the electrically conductive material. | 08-21-2014 |
20140232007 | SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS - A semiconductor device that is connected to a wiring substrate includes a semiconductor substrate, a circuit provided on the semiconductor substrate, a connection terminal, and a guard ring that is provided on a peripheral region. In the semiconductor device, the guard ring includes a plurality of wiring layers, and a wiring layer included in the guard ring, which is the farthest from the semiconductor substrate, corresponds to a wiring layer closer to the semiconductor substrate relative to a wiring layer of the connection terminal. | 08-21-2014 |
20140232008 | Semiconductor Constructions and Methods of Forming Semiconductor Constructions - Some embodiments include a semiconductor construction having a pair of lines extending primarily along a first direction, and having a pair of contacts between the lines. The contacts are spaced from one another by a lithographic dimension, and are spaced from the lines by sub-lithographic dimensions. Some embodiments include a method of forming a semiconductor construction. Features are formed over a base. Each feature has a first type sidewall and a second type sidewall. The features are spaced from one another by gaps. Some of the gaps are first type gaps between first type sidewalls, and others of the gaps are second type gaps between second type sidewalls. Masking material is formed to selectively fill the first type gaps relative to the second type gaps. Excess masking material is removed to leave a patterned mask. A pattern is transferred from the patterned mask into the base. | 08-21-2014 |
20140232009 | MEMORY CIRCUITS AND ROUTING OF CONDUCTIVE LAYERS THEREOF - A memory circuit memory circuit comprises at least one memory cell for storing a datum. The memory cell is coupled with a word line, a bit line, a bit line bar, a first voltage line, and a second voltage line. A first conductive layer comprising a first landing pad and a second landing pad is arranged at a first level. A second conductive layer is coupled to the first conductive layer and arranged at a second level different from the first level. The second conductive layer is routed to define the first voltage line and the second voltage line. A third conductive layer is coupled to the second conductive layer and arranged at a third level different from the first level and the second level. The third conductive layer is routed to define the word line. | 08-21-2014 |
20140239503 | INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH CAPPING LAYERS BETWEEN METAL CONTACTS AND INTERCONNECTS - Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes forming a metal contact structure that is electrically connected to a device. A capping layer is selectively formed on the metal contact structure, and an interlayer dielectric material is deposited over the capping layer. A metal hard mask is deposited and patterned over the interlayer dielectric material to define an exposed region of the interlayer dielectric material. The method etches the exposed region of the interlayer dielectric material to expose at least a portion of the capping layer. The method includes removing the metal hard mask with an etchant while the capping layer physically separates the metal contact structure from the etchant. A metal is deposited to form a conductive via electrically connected to the metal contact structure through the capping layer. | 08-28-2014 |
20140239504 | MULTI-LAYER MICRO-WIRE STRUCTURE - A multi-layer micro-wire structure includes a substrate having a surface. A plurality of micro-channels is formed in the substrate. A first material composition is located in a first layer only in each micro-channel and not on the substrate surface. A second material composition different from the first material composition is located in a second layer different from the first layer only in each micro-channel and not on the substrate surface. The first material composition in the first layer and the second material composition in the second layer form an electrically conductive multi-layer micro-wire in each micro-channel. | 08-28-2014 |
20140239505 | Bump-on-Trace Methods and Structures in Packaging - A method and structure for bump-on-trace bonding is provided. In an embodiment traces to be used for bump-on-trace (BOT) bonding are protected during a pre-solder treatment. The pre-solder treatment improves the adhesion between the exposed traces (e.g., the non-BOT traces) and a solder resist layer. | 08-28-2014 |
20140239506 | Semiconductor Device and Manufacturing Method Thereof - To provide a semiconductor device comprising a first layer that is provided on a semiconductor substrate and includes a first wiring pattern planarized by CMP and a plurality of first dummy patterns made of a same material as the first wiring pattern and a second layer that is provided above the semiconductor substrate and includes a second wiring pattern planarized by CMP and a plurality of second dummy patterns made of a same material as the second wiring pattern. A central axis of each of the second dummy patterns coincides with that of a corresponding one of the first dummy patterns in a direction perpendicular to the semiconductor substrate. | 08-28-2014 |
20140246777 | CONTROLLED METAL EXTRUSION OPENING IN SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING - Aspects of the present invention relate to a controlled metal extrusion opening in a semiconductor structure. Various embodiments include a semiconductor structure. The structure includes an aluminum layer. The aluminum layer includes an aluminum island within the aluminum layer, and a lateral extrusion receiving opening extending through the aluminum layer adjacent the aluminum island. The opening includes a lateral extrusion of the aluminum layer of the semiconductor structure. Additional embodiments include a method of forming a semiconductor structure. The method can include forming an aluminum layer over a titanium layer. The aluminum layer includes an aluminum island within the aluminum layer. The method can also include forming an opening extending through the aluminum layer adjacent the aluminum island within the aluminum layer. The opening includes a lateral extrusion of the aluminum layer of the semiconductor layer. | 09-04-2014 |
20140246778 | SEMICONDUCTOR DEVICE, WIRELESS DEVICE, AND STORAGE DEVICE - According to one embodiment, a semiconductor device includes a substrate, a first semiconductor chip, a second semiconductor chip, and a discrete element part. The first semiconductor chip is arranged on the substrate and includes a first electrode group. The second semiconductor chip is arranged on the substrate and includes a second electrode group, at least one of electrodes included in the second electrode group being connected to at least one of electrodes included in the first electrode group via at least one bonding wire. The discrete element part is arranged on the substrate and under the at least one bonding wire. | 09-04-2014 |
20140246779 | Semiconductor Device and Method of Forming Insulating Layer Disposed Over the Semiconductor Die For Stress Relief - A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure. | 09-04-2014 |
20140246780 | SEMICONDUCTOR DEVICE INCLUDING DUMMY PATTERN - A semiconductor device includes a substrate including a circuit region, a dummy region, and a dummy clearance section surrounding the circuit region, and a plurality of dummy patterns formed in the dummy region, the plurality of dummy patterns comprising a first dummy pattern and a second dummy pattern, a distance between the first dummy pattern and the circuit region being less than a distance between the second dummy pattern and the circuit region, and a dummy pattern being absent between the first dummy pattern and the circuit region. The first dummy pattern includes an area which is greater than an area of the second dummy pattern. | 09-04-2014 |
20140252631 | Semiconductor Device and Method of Forming Sacrificial Adhesive Over Contact Pads of Semiconductor Die - A semiconductor wafer contains a plurality of semiconductor die each having a plurality of contact pads. A sacrificial adhesive is deposited over the contact pads. Alternatively, the sacrificial adhesive is deposited over the carrier. An underfill material can be formed between the contact pads. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier such that the sacrificial adhesive is disposed between the contact pads and temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and sacrificial adhesive is removed to leave a via over the contact pads. An interconnect structure is formed over the encapsulant. The interconnect structure includes a conductive layer which extends into the via for electrical connection to the contact pads. The semiconductor die is offset from the interconnect structure by a height of the sacrificial adhesive. | 09-11-2014 |
20140252632 | SEMICONDUCTOR DEVICES - A semiconductor device includes: a semiconductor chip; an extension layer extending laterally from a boundary of the semiconductor chip; a redistribution layer disposed over at least one side of the extension layer and the semiconductor chip, wherein the redistribution layer electrically couples at least one contact of the semiconductor chip to at least one contact of an interface, wherein at least a part of the interface extends laterally beyond the boundary of the semiconductor chip. | 09-11-2014 |
20140252633 | METHOD OF FABRICATING AN AIR GAP USING A DAMASCENE PROCESS AND STRUCTURE OF SAME - The present disclosure provides a method for forming a semiconductor device. The method includes forming first conductive layer structures in a first dielectric layer on a substrate; forming a patterned photoresist layer having portions that are each disposed over a respective one of the first conductive layer structures; forming an energy removable film (ERF) on the sidewalls of each of the portions; forming a second dielectric layer over the ERFs, the portions of the patterned photoresist layer, and the first dielectric layer; removing the portions to leave behind a plurality of openings; filling a conductive material in the openings, the conductive material defining second conductive layer structures; forming a ceiling layer over the second conductive layer structures, the ERFs, and the second dielectric layer; and applying energy to the ERFs to partially remove the ERFs on the sidewalls of the portions thereby forming air gaps. | 09-11-2014 |
20140252634 | Packaging Devices and Methods for Semiconductor Devices - Packaging devices and methods for semiconductor devices are disclosed. In some embodiments, a packaging device for a semiconductor device includes a packaging substrate including a semiconductor device mounting region. The packaging device includes a stress isolation structure (SIS) disposed on the packaging substrate proximate a portion of a perimeter of the semiconductor device mounting region. | 09-11-2014 |
20140252635 | Bonding Structures and Methods of Forming the Same - A package includes a package component and a second package component. A first elongated bond pad is at a surface of the first package component, wherein the first elongated bond pad has a first length in a first longitudinal direction, and a first width smaller than the first length. A second elongated bond pad is at a surface of the second package component. The second elongated bond pad is bonded to the first elongated bond pad. The second elongated bond pad has a second length in a second longitudinal direction, and a second width smaller than the second width. The second longitudinal direction is un-parallel to the first longitudinal direction. | 09-11-2014 |
20140252636 | INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME - An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a middle low-k (LK) dielectric layer over the lower ESL; a supporting layer over the middle LK dielectric layer; an upper LK dielectric layer over the supporting layer; an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature is through the supporting layer; a gap along an interface of the upper conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the upper conductive feature, and the gap. | 09-11-2014 |
20140252637 | HORIZONTAL INTERCONNECTS CROSSTALK OPTIMIZATION - A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus generates a plurality of interconnect patterns for a set of longitudinal channels that are occupied by horizontal interconnects. Each interconnect pattern may be different from the other interconnect patterns. Each interconnect pattern may define relative locations for the set of horizontal interconnects and gap channels. Highest crosstalk is determined for each of the interconnect patterns and the interconnect pattern with the minimum highest crosstalk is selected as a preferred pattern. The highest crosstalk may comprise far-end crosstalk or near-end crosstalk and may be calculated for a range of frequencies or for a plurality of frequencies. The crosstalk may be calculated by modeling the interconnects as transmission lines. | 09-11-2014 |
20140252638 | VERTICAL INTERCONNECTS CROSSTALK OPTIMIZATION - A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus generate a plurality of interconnect patterns for a set of vertical interconnects. Each interconnect pattern may be different from the other interconnect patterns. Each interconnect pattern may define relative locations for the set of vertical interconnects within a predefined area of a substrate in the semiconductor device. Highest crosstalk is determined for each of the interconnect patterns and the interconnect pattern with the minimum highest crosstalk is selected as a preferred pattern. One or more sets of interconnects is formed on a substrate in accordance with the preferred pattern. At least one set of interconnects may be rotated with respect to another set of interconnects on the substrate to minimize crosstalk between the sets of interconnects. | 09-11-2014 |
20140252639 | INTEGRATED CIRCUIT DEVICE, METHOD FOR PRODUCING MASK LAYOUT, AND PROGRAM FOR PRODUCING MASK LAYOUT - According to one embodiment, a method for producing a mask layout of an exposure mask for forming wiring of an integrated circuit device, includes estimating shape of the wiring formed based on an edge of a pattern included in an initial layout of the exposure mask. The method includes modifying shape of the edge if the estimated shape of the wiring does not satisfy a requirement. | 09-11-2014 |
20140252640 | SEMICONDUCTOR PACKAGE HAVING A MULTI-CHANNEL AND A RELATED ELECTRONIC SYSTEM - A substrate including internal interconnections, first and second finger electrodes, and having first to fourth quadrants. External terminals are formed on the substrate and connected to the first and second finger electrodes via the internal interconnections. A first tower including first semiconductor chips is formed on the substrate. First conductive wires are formed between the first semiconductor chips and the first finger electrodes. A second tower including second semiconductor chips is formed on the substrate. Second conductive wires are formed between the second semiconductor chips and the second finger electrodes. The external terminals include a first group connected to the first finger electrodes and configuring a channel, and a second group connected to the second finger electrodes, and configuring another channel. The first finger electrodes are formed on the third quadrant, and the second finger electrodes are formed on the first quadrant. | 09-11-2014 |
20140252641 | Semiconductor Device and Method of Forming Ultra High Density Embedded Semiconductor Die Package - A semiconductor device has a plurality of semiconductor die. A first prefabricated insulating film is disposed over the semiconductor die. A conductive layer is formed over the first prefabricated insulating film. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The first prefabricated insulating film is laminated over the semiconductor die. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The semiconductor die is embedded within the first prefabricated insulating film with the first prefabricated insulating film covering first and side surfaces of the semiconductor die. The interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A portion of the first prefabricated insulating film is removed after disposing the first prefabricated insulating film over the semiconductor die. A second prefabricated insulating film is disposed over the first prefabricated insulating film. | 09-11-2014 |
20140252642 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a semiconductor substrate; a device region formed in the semiconductor substrate; at least a conducting pad disposed over a surface of the semiconductor substrate; a protection plate disposed over the surface of the semiconductor substrate; and a spacer layer disposed between the surface of the semiconductor substrate and the protection plate, wherein the protection plate and the spacer layer surround a cavity over the device region, the spacer layer has an outer side surface away from the cavity, and the outer side surface of the spacer layer is not a cutting surface. | 09-11-2014 |
20140252643 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented. | 09-11-2014 |
20140264888 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package structure includes a chip unit, a package unit and an electrode unit. The chip unit includes at least one semiconductor chip. The semiconductor chip has an upper surface, a lower surface, and a surrounding peripheral surface connected between the upper and the lower surfaces, and the semiconductor chip has a first conductive pad and a second conductive pad disposed on the lower surface thereof. The package unit includes a package body covering the upper surface and the surrounding peripheral surface of the semiconductor chip. The package body has a first lateral portion and a second lateral portion respectively formed on two opposite lateral sides thereof. The electrode unit includes a first electrode structure covering the first lateral portion and a second electrode structure covering the second lateral portion. The first and the second electrode structures respectively electrically contact the first and the second conductive pads. | 09-18-2014 |
20140264889 | SEMICONDUCTOR DEVICE CHANNELS - A semiconductor device and a method of manufacture are provided. The semiconductor device includes one or more layers having channels adapted to carry signals or deliver power. The semiconductor device may include at least two channels having a substantially equivalent cross-sectional area. Conductors in separate channels may have different cross-sectional areas. A spacer dielectric on a side of a channel may be included. The method of manufacture includes establishing a signal conductor layer including a first channel and a second channel having a substantially equivalent cross-sectional area, introducing a spacer dielectric on a side of the second channel, introducing a first conductor in the first channel having a first cross-sectional area, and introducing a second conductor in the second channel having a second cross-sectional area where the second cross-sectional area is smaller than the first cross-sectional area. | 09-18-2014 |
20140264890 | NOVEL PILLAR STRUCTURE FOR USE IN PACKAGING INTEGRATED CIRCUIT PRODUCTS AND METHODS OF MAKING SUCH A PILLAR STRUCTURE - One illustrative pillar disclosed herein includes a bond pad conductively coupled to an integrated circuit and a pillar comprising a base that is conductively coupled to the bond pad, wherein the base has a first lateral dimension, and an upper portion that is conductively coupled to the base, wherein the upper portion has a second lateral dimension that is less than the first lateral dimension. A method disclosed herein of forming a pillar includes forming a base such that it is conductively coupled to a bond pad on an integrated circuit product and, after forming the base, forming an upper portion such that it is conductively coupled to the base. | 09-18-2014 |
20140264891 | FORMING FENCE CONDUCTORS IN AN INTEGRATED CIRCUIT - A spacer etching process produces ultra-narrow conductive lines in a plurality of semiconductor dice. Sub-lithographic patterning of the conductive lines are compatible with existing aluminum and copper backend processing. A first dielectric is deposited onto the semiconductor dice and trenches are formed therein. A conductive film is deposited onto the first dielectric and the trench surfaces. All planar conductive film is removed from the faces of the semiconductor dice and bottoms of the trenches, leaving only conductive films on the trench walls, whereby “fence conductors” are created therefrom. Thereafter the gap between the conductive films on the trench walls are filled in with insulating material. A top portion of the insulated gap fill is thereafter removed to expose the tops of the fence conductors. Portions of the fence conductors and surrounding insulating materials are removed at appropriate locations to produce desired conductor patterns comprising isolated fence conductors. | 09-18-2014 |
20140264892 | SEMICONDUCTOR DEVICE WITH DUMMY LINES - A semiconductor device includes a first main strap, a second main strap, a plurality of first sub straps, a plurality of second sub straps, and a plurality of dummy lines. The first main strap is extended in a first direction. The second main strap is extended in the first direction. A plurality of first sub straps is branched from the first main strap. The plurality of second sub straps is branched from the second main strap. The plurality of dummy lines is positioned between the first main strap and the second main strap. Each of the plurality of dummy lines is positioned between each of the plurality of first sub straps and each of the plurality of second sub straps. Each of the dummy lines is spaced apart from the first main strap, the second main strap, each of the first sub straps and each of the second sub straps. | 09-18-2014 |
20140264893 | PITCH-HALVING INTEGRATED CIRCUIT PROCESS AND INTEGRATED CIRCUIT STRUCTURE MADE THEREBY - A pitch-halving IC process is described. Parallel base line patterns are formed over a substrate, each being connected with a hammerhead pattern at a first or second side of the base line patterns, wherein the hammerhead patterns are arranged at the first side and the second side alternately, and the hammerhead patterns at the first or second side are arranged in a staggered manner. The above patterns are trimmed. A spacer is formed on the sidewalls of each base line pattern and the corresponding hammerhead pattern, including a pair of derivative line patterns, a loop pattern around the hammerhead pattern, and a turning pattern at the other end of the base line pattern. The base line patterns and the hammerhead patterns are removed. A portion of each loop pattern and at least a portion of each turning pattern are removed to disconnect each pair of derivative line patterns. | 09-18-2014 |
20140264894 | SYSTEM AND METHOD FOR ARBITRARY METAL SPACING FOR SELF-ALIGNED DOUBLE PATTERNING - An integrated circuit includes a first conductive structure of a device configured to have a first voltage potential, a second conductive structure of the device configured to have a second voltage potential that is different than the first voltage potential, and a peacekeeper structure disposed between and separating the first conductive structure and the second conductive structure. The peacekeeper structure is separated from at least one of the first conductive structure and the second conductive structure by a fixed spacing distance for conductive lines for a self-aligned double patterning (“SADP”) process from the integrated circuit was formed. | 09-18-2014 |
20140264895 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming an etch stop layer over a workpiece. The etch stop layer has an etch selectivity to a material layer of the workpiece of greater than about 4 to about 30. The method includes forming an insulating material layer over the etch stop layer, and patterning the insulating material layer using the etch stop layer as an etch stop. | 09-18-2014 |
20140264896 | Structure and Method for a Low-K Dielectric with Pillar-Type Air-Gaps - A circuit device having an interlayer dielectric with pillar-type air gaps and a method of forming the circuit device are disclosed. In an exemplary embodiment, the method comprises receiving a substrate and depositing a first layer over the substrate. A copolymer layer that includes a first constituent polymer and a second constituent polymer is formed over the first layer. The first constituent polymer is selectively removed from the copolymer layer. A first region of the first layer corresponding to the selectively removed first constituent polymer is etched. The etching leaves a second region of the first layer underlying the second constituent polymer unetched. A metallization process is performed on the etched substrate, and the first layer is removed from the second region to form an air gap. The method may further comprise depositing a dielectric material within the etched first region. | 09-18-2014 |
20140264897 | DAMASCENE CONDUCTOR FOR A 3D DEVICE - A method of forming a conductor structure can result in vertical sidewalls. The method deposits a lining over a plurality of spaced-apart stacks of active layers. An isolation material is formed over the lining, over and in between the spaced-apart stacks. A plurality of trenches in the isolation material is arranged to cross over the plurality of spaced-apart stacks of active strips, leaving at least a residue of the lining on a bottom of the trenches between the stacks of active strips and over a sidewall of the spaced-apart stacks of active strips. The residue of the lining on the bottom of the trenches and the sidewalls of the spaced-apart stacks of active layers is selectively removed. Then the plurality of trenches is filled with conductive or semiconductor material to form the damascene structure. | 09-18-2014 |
20140264898 | 3-D IC Device with Enhanced Contact Area - A device includes a substrate with a recess, having a bottom and sides, extending into the substrate from the substrate's upper surface. The sides include first and second sides oriented transversely to one another. A stack of alternating active and insulating layers overlie the substrate's surface and the recess. At least some of the active layers have an upper and lower portions extending along upper and lower planes over and generally parallel to the upper surface and to the bottom, respectively. The active layers have first and second upward extensions positioned along the first and second sides to extend from the lower portions of their respective active layers. Conductive strips adjoin the second upward extensions of the said active layers. The conductive strips can comprise sidewall spacers on the sides of the second upward extensions, the conductive strips connected to overlying conductors by interlayer conductors. | 09-18-2014 |
20140264899 | Pattern Modification with a Preferred Position Function - A method for pattern modification for making an integrated circuit layout is disclosed. The method includes determining a feature within a pattern of the integrated circuit layout that can be rearranged; determining a range in which the feature can be repositioned; for the feature, determining a preferred position function that exhibits extreme values at preferable positions; and rearranging the position of the feature within the range to match an extreme value of the function. | 09-18-2014 |
20140264900 | ANISOTROPIC CONDUCTOR AND METHOD OF FABRICATION THEREOF - An anisotropic conductor and a method of fabrication thereof. The anisotropic conductor includes an insulating matrix and a plurality of nanoparticles disposed therein. A first portion of the plurality of nanoparticles provides a conductor when subjected to a voltage and/or current pulse. A second portion of the plurality of the nanoparticles does not form a conductor when the voltage and or current pulse is applied to the first portion. The anisotropic conductor forms a conductive path between conductors of electronic devices, components, and systems, including microelectromechanical systems (MEMS) devices, components, and systems. | 09-18-2014 |
20140264901 | SEMICONDUCTOR DEVICE AND LAYOUT DESIGN SYSTEM - In a semiconductor device including a seal ring area containing multiple seal rings are coupled to each other at equal intervals via bridge patterns, improper local relocation of bridge patterns may reduce the reliability of the semiconductor device. A semiconductor device has a first group containing a predetermined number of the bridge patterns spaced at a first interval and a second group containing a predetermined number of the bridge patterns spaced at the first interval, the second group being located at a second interval from the first group. The second interval is larger than the first interval. | 09-18-2014 |
20140284803 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is disclosed, which includes: a substrate having a plurality of switching pads, a plurality of first conductive pads and a plurality of circuits formed between the switching pads and the first conductive pads; an insulating layer covering the circuits; a conductive layer formed on the insulating layer and extending to the switching pads and the first conductive pads; and a semiconductor element disposed on the substrate and electrically connected to the switching pads through a plurality of bonding wires. By electrically connecting the switching pads and the first conductive pads through the conductive layer, the invention dispenses with the conventional short bonding wires so as to prevent the conventional problem of short circuits caused by contact of the short bonding wires with other bonding wires. | 09-25-2014 |
20140284804 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first electrode formed on a substrate, the first electrode being a first electrical potential; and a second electrode formed on the first electrode, the second electrode including a signal wiring that transmits a signal and a planar electrode part with a prescribed area. A shape of the first electrode corresponding to the planar electrode part is made into a slit shape such that a longitudinal direction of a slit is parallel to a direction in which the signal proceeds in the planar electrode part. | 09-25-2014 |
20140284805 | MULTIPLE HELIX SUBSTRATE AND THREE-DIMENSIONAL PACKAGE WITH SAME - A three dimensional package includes a substrate having a columnar part including a sidewall, and stairs or steps arranged along the sidewall of the columnar part in the form of multiple helixes twisted around the columnar part. Semiconductor integrated circuits (IC dies) are attached on one or both of the supporting surfaces of the stairs. The columnar part, the stairs and the IC dies can be encapsulated with a mold compound. | 09-25-2014 |
20140284806 | SEMICONDUCTOR DEVICE DIE ATTACHMENT - A semiconductor device has first and semiconductor dies having active faces presenting electrical contact elements and back faces attached to first and second bonding areas side by side on an electrically conductive die support. A layer of electrically insulating material is applied to the first bonding area of the die support. A layer of electrically insulating adhesive bonding material attaches the back face of the first semiconductor die to the first bonding area of the die support through the layer of electrically insulating material. A layer of electrically conductive adhesive bonding material attaches the back face of the second semiconductor die to the second bonding area of the die support. | 09-25-2014 |
20140284807 | ENCAPSULATION PROCESS AND ASSOCIATED DEVICE - The invention relates to an encapsulation process for an electronic component ( | 09-25-2014 |
20140284808 | STACKED SEMICONDUCTOR DEVICE, AND METHOD AND APPARATUS OF MANUFACTURING THE SAME - Provided is a method of manufacturing a stacked semiconductor device, which includes forming a stacked film on a semiconductor substrate, the stacked film including a plurality of silicon oxide films and a plurality of silicon nitride films, which are alternately arranged on top of each other, and the stacked film being obtained by repeatedly performing a series of operations of forming the silicon oxide film on the semiconductor substrate using one of triethoxysilane, octamethylcyclotetrasiloxane, hexamethyldisilazane and diethylsilane gases, and forming the silicon nitride film on the formed silicon oxide film; etching the silicon nitride films in the stacked film; removing carbons contained in the silicon oxide films, which are not removed in the etching, to reduce a concentration of the carbons; and forming electrodes in regions where the silicon nitride films are etched in the etching. | 09-25-2014 |
20140284809 | POWER CONVERTER - A power converter includes a bus bar, a semiconductor device, a lead, and solder. The bus bar has a vertical wall. The semiconductor device includes an electrode. The lead has one end connected to the bus bar and another end connected to the semiconductor device to supply power from the bus bar to the electrode of the semiconductor device via the lead. The one end of the lead includes a bending part which is spaced away from the bus bar by a predetermined distance and which is inclined in a vertical downward direction. The vertical wall of the bus bar and the bending part are bonded to each other via the solder. The vertical wall extends in a substantially vertical direction to face the bending part. | 09-25-2014 |
20140284810 | SEMICONDUCTOR DEVICE - In a semiconductor device, a first contact-diffusion-layer is in a first well to be connected to the first well and extends in a channel width direction of a first transistor in a first well. A second contact-diffusion-layer is in the first well so as to be electrically connected to the first well and extends in a channel-length direction of the first transistor. A first contact on the first contact-diffusion-layer has a shape with a diameter in the channel-width direction larger than that in the channel-length direction when viewed from above the substrate. A second contact on the second contact-diffusion-layer has a shape with a diameter in the channel-width direction smaller than that of the first contact and a diameter in the channel-length direction almost equal to that of the first contact when viewed from above the substrate. A wiring is electrically connected to the first transistor through the second contact. | 09-25-2014 |
20140284811 | Methods for Multi-Wire Routing and Apparatus Implementing Same - A rectangular interlevel connector array (RICA) is defined in a semiconductor chip. To define the RICA, a virtual grid for interlevel connector placement is defined to include a first set of parallel virtual lines that extend across the layout in a first direction, and a second set of parallel virtual lines that extend across the layout in a second direction perpendicular to the first direction. A first plurality of interlevel connector structures are placed at respective gridpoints in the virtual grid to form a first RICA. The first plurality of interlevel connector structures of the first RICA are placed to collaboratively connect a first conductor channel in a first chip level with a second conductor channel in a second chip level. A second RICA can be interleaved with the first RICA to collaboratively connect third and fourth conductor channels that are respectively interleaved with the first and second conductor channels. | 09-25-2014 |
20140284812 | FORMING ARRAY CONTACTS IN SEMICONDUCTOR MEMORIES - Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts. | 09-25-2014 |
20140291849 | Multi-Level Semiconductor Package - A semiconductor package includes a semiconductor die having a first electrode at a first side and a second electrode at a second side opposing the first side, a first lead under the semiconductor die and connected to the first electrode at a first level of the package, and a second lead having a height greater than the first lead and terminating at a second level in the package above the first level, the second level corresponding to a height of the semiconductor die. A connector of a single continuous planar construction over the semiconductor die and the second lead is connected to both the second electrode and the second lead at the same second level of the package. | 10-02-2014 |
20140291850 | METHOD FOR MANUFACTURING ELECTRONIC DEVICES - An embodiment for manufacturing electronic devices is proposed. The embodiment includes the following phases: a) forming a plurality of chips in a semiconductor material wafer including a main surface; each chip includes respective integrated electronic components and respective contact pads facing the main surface; said contact pads are electrically coupled to the integrated electronic components; b) attaching at least one conductive ribbon to at least one contact pad of each chip; c) covering the main surface of the semiconductor material wafer and the at least one conductive ribbon with a layer of plastic material; d) lapping an exposed surface of the layer of plastic material to remove a portion of the plastic material layer at least to uncover portions of the at least one conductive ribbon, and e) sectioning the semiconductor material wafer to separate the chips. | 10-02-2014 |
20140291851 | LEAD PIN FOR PACKAGE SUBSTRATE - A lead pin for a package substrate includes: a connection pin being inserted into a hole formed in an external substrate; a head part formed on one end of the connection pin; and a barrier part formed on one surface of the head part in order to block the path of a solder paste so that the solder paste is prevented from flowing so as to cover the upper portion of the head part when the head part is mounted on the package substrate. | 10-02-2014 |
20140291852 | INTERCONNECT FOR AN OPTOELECTRONIC DEVICE - Interconnects for optoelectronic devices are described. For example, an interconnect for an optoelectronic device includes an interconnect body having an inner surface, an outer surface, a first end, and a second end. A plurality of bond pads is coupled to the inner surface of the interconnect body, between the first and second ends. A stress relief feature is disposed in the interconnect body. The stress relief feature includes a slot disposed entirely within the interconnect body without extending through to the inner surface, without extending through to the outer surface, without extending through to the first end, and without extending through to the second end of the interconnect body. | 10-02-2014 |
20140299997 | SPACER PROCESS FOR ON PITCH CONTACTS AND RELATED STRUCTURES - Methods are disclosed, including for increasing the density of isolated features in an integrated circuit. Also disclosed are associated structures. In some embodiments, contacts are formed on pitch with other structures, such as conductive interconnects that may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. Features in the selectively definable material are trimmed, and spacer material is blanket deposited over the features and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed, leaving a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts. In some embodiments, the on pitch contacts may be used to electrically contact conductive interconnects in the substrate. | 10-09-2014 |
20140299998 | METHOD FOR MAKING CONTACT WITH A SEMICONDUCTOR AND CONTACT ARRANGEMENT FOR A SEMICONDUCTOR - The invention relates to a method for making contact with a semiconductor ( | 10-09-2014 |
20140306347 | Semiconductor Device with an Insulation Layer Having a Varying Thickness - A layer with a laterally varying thickness, a substrate with a first surface and an insulation layer formed on the first surface of the substrate is provided. A plurality of at least one of recesses and openings is formed in the insulation layer, wherein the plurality is arranged at a pitch. Each of the at least one of recesses and openings has a lateral width, wherein at least one of the pitch and the lateral width varies in a lateral direction. The plurality of the at least one of recesses and openings defines a given region in the insulation layer. The insulation layer having the plurality of the at least one of the recesses and openings is tempered at elevated temperatures so that the insulation layer at least partially diffluences to provide the insulation layer with a laterally varying thickness at least in the given region. | 10-16-2014 |
20140306348 | CHIP ON FILM AND DISPLAY DEVICE HAVING THE SAME - A flexible chip on film includes a base insulating layer, a metal layer disposed on an upper surface of the base insulating layer and including a circuit pattern, an integrated circuit chip disposed on an upper surface of the metal layer and electrically connected to the metal layer, a solder resist layer disposed on the metal layer and insulated from the integrated circuit chip, and a reinforcing layer disposed on an upper surface of the solder resist layer. When the chip on film COF is bent, a neutral surface, in which a vector sum of a tensile force and a compressive force becomes substantially zero, is placed in the metal layer. | 10-16-2014 |
20140312500 | COMBINING CUT MASK LITHOGRAPHY AND CONVENTIONAL LITHOGRAPHY TO ACHIEVE SUB-THRESHOLD PATTERN FEATURES - Features are fabricated on a semiconductor chip. The features are smaller than the threshold of the lithography used to create the chip. A method includes patterning a first portion of a feature (such as a local interconnect) and a second portion of the feature to be separated by a predetermined distance, such as a line tip to tip space or a line space. The method further includes patterning the first portion with a cut mask to form a first sub-portion (e.g., a contact) and a second sub-portion. A dimension of the first sub-portion is less than a dimension of a second predetermined distance, which may be a line length resolution of a lithographic process having a specified width resolution. A feature of a semiconductor device includes a first portion and a second portion having a dimension less than a lithographic resolution of the first portion. | 10-23-2014 |
20140312501 | NON-RANDOM ARRAY ANISOTROPIC CONDUCTIVE FILM (ACF) AND MANUFACTURING PROCESSES - Structures and manufacturing processes of an ACF array using a non-random array of microcavities of predetermined configuration, shape and dimension. The manufacturing process includes fluidic filling of conductive particles onto a substrate or carrier web comprising a predetermined array of microcavities, of selective metallization of the array followed by filling the array with a filler material and a second selective metallization on the filled microcavity array. The thus prepared filled conductive microcavity array is then over-coated or laminated with an adhesive film. Cavities in the array, and particles filling the cavities, can have a unimodal, bimodal, or multimodal distribution. | 10-23-2014 |
20140319690 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a storage node contact on a substrate, and a lower electrode on the storage node contact, a lower sidewall of the lower electrode being covered by a contact residue of a same material as the storage node contact. | 10-30-2014 |
20140319691 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip having a multilayer interconnect, a first spiral inductor formed in the multilayer interconnect, and a second spiral inductor formed in the multilayer interconnect. The first spiral inductor and the second spiral inductor collectively include a line, the line being spirally wound in a first direction in the first spiral inductor toward outside of the first spiral inductor, and being spirally wound in a second direction in the second spiral inductor toward inside of the second spiral inductor. The first direction and the second direction are opposite directions. | 10-30-2014 |
20140319692 | Semiconductor Device and Method of Forming High Routing Density Interconnect Sites on Substrate - A semiconductor device has a semiconductor die with a plurality of bumps formed over contact pads on a surface of the semiconductor die. The bumps can have a fusible portion and non-fusible portion. A plurality of conductive traces is formed over a substrate with interconnect sites having a width greater than 20% and less than 80% of a width of a contact interface between the bumps and contact pads. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate. The conductive traces have a pitch as determined by minimum spacing between adjacent conductive traces that can be placed on the substrate and the width of the interconnect site provides a routing density equal to the pitch of the conductive traces. | 10-30-2014 |
20140332966 | EPOXY-AMINE UNDERFILL MATERIALS FOR SEMICONDUCTOR PACKAGES - Epoxy-amine underfill materials for semiconductor packages and semiconductor packages having an epoxy-amine underfill material are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon. A semiconductor package substrate has a surface with a plurality of contact pads thereon. A plurality of conductive contacts couples the surface of the semiconductor die to the surface of the semiconductor package substrate. An epoxy-amine underfill material is disposed between the surface of the semiconductor die and the surface of the semiconductor package substrate and surrounds the plurality of conductive contacts. The epoxy-amine underfill has high adhesion and is based on a low volatility multi-functional amine species. | 11-13-2014 |
20140332967 | BIT CELL WITH DOUBLE PATTERENED METAL LAYER STRUCTURES - An approach for providing SRAM bit cells with double patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process, a word line structure, a ground line structure, a power line structure, or a combination thereof; and providing, via a second patterning process, a bit line structure proximate the word line structure, the ground line structure, the power line structure, or a combination thereof Embodiments include: providing a first landing pad as the word line structure, and a second landing pad as the ground line structure; and providing the first landing pad to have a first tip edge and a first side edge, and the second landing pad to have a second tip edge and a second side edge, wherein the first side edge faces the second side edge. | 11-13-2014 |
20140332968 | CHIP PACKAGE - A chip package is provided. The chip package includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a sensing region or device region and a signal pad region adjacent to the upper surface. A shallow recess structure is located outside of the signal pad region and extends from the upper surface toward the lower surface along the sidewall. The shallow recess structure has at least a first recess and a second recess under the first recess. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A first end of a wire is located in the shallow recess structure and is electrically connected to the redistribution layer. A second end of the wire is used for external electrical connection. A method for forming the chip package is also provided. | 11-13-2014 |
20140332969 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A chip package including a chip having an upper surface, a lower surface and a sidewall is provided. The chip includes a signal pad region adjacent to the upper surface. A first recess extends from the upper surface toward the lower surface along the sidewall. At least one second recess extends from a first bottom of the first recess toward the lower surface. The first and second recesses further laterally extend along a side of the upper surface, and a length of the first recess extending along the side is greater than that of the second recess extending along the side. A redistribution layer is electrically connected to the signal pad region and extends into the second recess. A method for forming the chip package is also provided. | 11-13-2014 |
20140332970 | SEMICONDUCTOR DEVICE AND METHOD FORMING PATTERNS WITH SPACED PADS IN TRIM REGION - In a semiconductor device, parallel first and second conductive lines having a unit width extend from a memory cell region into a connection region. A trim region in the connection region includes pads respectively connected to the first and second conductive lines but are separated by a width much greater than the unit width. | 11-13-2014 |
20140332971 | METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT - An integrated circuit layout includes a P-type active region and an N-type active region, and a plurality of trunks. The integrated circuit layout further includes a first metal connection connected to the P-type active region; and a second metal connection connected to the N-type active region. Each trunk of the plurality of trunks is electrically connected with the first metal connection and the second metal connection. Each trunk of the plurality of trunks is substantially perpendicular to the first metal connection and the second metal connection. A first trunk of the plurality of trunks has a width wider than a width of other trunks of the plurality of trunks. | 11-13-2014 |
20140332972 | COMPOSITE RECONSTITUTED WAFER STRUCTURES - A reconstituted electronic device comprising at least one die and at least one passive component. A functional material is incorporated in the substrate of the device to modify the electrical behaviour of the passive component. The passive component may be formed in redistribution layers of the device. Composite functional materials may be used in the substrate to forms part of or all of the passive component. A metal carrier may form part of the substrate and part of the at least one passive component. | 11-13-2014 |
20140339704 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate; and first and second semiconductor chips sequentially disposed on the substrate so that active surfaces of the first and second semiconductor chips face each other, wherein the first and second semiconductor chips are center pad-type semiconductor chips each having I/O pads arranged in two columns to be adjacent to a central line thereof, and I/O pads of the second semiconductor chip are electrically connected directly to the substrate without intersecting the central line of the second semiconductor chip. | 11-20-2014 |
20140346676 | SEMICONDUCTOR DEVICE - Semiconductor chips are disposed on an insulating substrate with conductive patterns, and a printed circuit board with metal pins is disposed above the insulating substrate with conductive patterns, with the semiconductor chips therebetween. A plurality of external lead terminals is fixed to the insulating substrate with conductive patterns, with the plurality of external lead terminals disposed adjacent to each other in parallel. Furthermore, metal foil pieces, formed on front and rear surfaces of the printed circuit board with metal pins respectively so as to face each other, are disposed above the semiconductor chips. | 11-27-2014 |
20140353835 | METHODS OF SELF-FORMING BARRIER INTEGRATION WITH PORE STUFFED ULK MATERIAL - A process is provided for methods of reducing contamination of the self-forming barrier of an ultra-low k layer during semiconductor fabrication. In one aspect, a method includes: providing a cured ultra-low k film which contains at least one trench, and the pores of the film are filled with a pore-stuffing material; removing exposed pore-stuffing material at the surface of the trench to form exposed pores; and forming a self-forming barrier layer on the surface of the trench. | 12-04-2014 |
20140353836 | CHIP ARRANGEMENTS AND A METHOD FOR MANUFACTURING A CHIP ARRANGEMENT - A chip arrangement may include: a semiconductor chip; an encapsulating structure at least partially encapsulating the semiconductor chip, the encapsulating structure having a first side and a second side opposite the first side, the encapsulating structure including a recess over the first side of the encapsulating structure, the recess having a bottom surface located at a first level; and at least one electrical connector disposed at the first side of the encapsulating structure outside the recess, wherein a surface of the at least one electrical connector facing the encapsulating structure may be disposed at a second level different from the first level. | 12-04-2014 |
20140353837 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device according to the present embodiment includes an insulating film provided above a semiconductor substrate. A plurality of upper-layer wirings are provided on the insulating film. A plurality of lower-layer wirings are provided in the insulating film. The lower-layer wirings are respectively located between the upper-layer wirings adjacent to each other when viewed from above the semiconductor substrate. Side surfaces of the lower-layer wirings substantially match surfaces of the upper-layer wirings present on both sides of the lower-layer wirings, respectively when viewed from above the semiconductor substrate. | 12-04-2014 |
20140353838 | 3D Packages and Methods for Forming the Same - Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including bonding a die to a top surface of a first substrate, the die being electrically coupled to the first substrate, and forming a support structure on the top surface of the first substrate, the support structure being physically separated from the die with a top surface of the support structure being coplanar with a top surface of the die. The method further includes performing a sawing process on the first substrate, the sawing process sawing through the support structure. | 12-04-2014 |
20140361437 | PACKAGE SUBSTRATES AND METHODS OF FABRICATING THE SAME - Package substrates are provided. The package substrate includes a core layer having a first surface defining trench portions and ridge portions between the trench portions, at least one first trace on a bottom surface of each of the trench portions, and second traces on respective ones of top surfaces of the ridge portions. Related methods are also provided. | 12-11-2014 |
20140374913 | CIRCUIT ARRANGEMENT AND METHOD FOR MANUFACTURING THE SAME - Various embodiments may provide a circuit arrangement. The circuit arrangement may include a carrier having at least one electrically conductive line; a plurality of discrete encapsulated integrated circuits arranged on the carrier; wherein a first integrated circuit of the plurality of integrated circuits is in electrical contact with a second integrated circuit of the plurality of integrated circuits to form a first current path bypassing the carrier; and wherein the first integrated circuit of the plurality of integrated circuits is in electrical contact with the second integrated circuit of the plurality of integrated circuits to form a second current path via the at least one electrically conductive line. | 12-25-2014 |
20140374914 | STRESS COMPENSATION PATTERNING - An apparatus includes a device that includes at least one layer. The at least one layer includes an inter-device stress compensation pattern configured to reduce an amount of inter-device warpage prior to the device being detached from another device. | 12-25-2014 |
20150008584 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a plurality of wires arranged in parallel at a predetermined pitch, a plurality of first contacts that are each connected to an odd-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to a wiring direction of the wires, and a plurality of second contacts that are each connected to an even-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to the wiring direction of the wires in such a way as to be offset from the first contacts in the wiring direction of the wires, in which the first contacts are offset from the second contacts by a pitch of the wires in an orthogonal direction with respect to the wiring direction of the wires. | 01-08-2015 |
20150014855 | MICROELECTRONIC PACKAGES AND METHODS FOR THE FABRICATION THEREOF - Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method comprises encapsulating a first semiconductor die having one or more core redistribution layers formed thereover in an outer molded body. The outer molded body has a portion, which circumscribes the core redistribution layer. One or more topside redistribution layers are produced over the core redistribution layer. A contact array is formed over the topside redistribution layer and electrically coupled to the first semiconductor die encapsulated in the outer molded body through the topside redistribution layers and the core redistribution layers. | 01-15-2015 |
20150014856 | MICROELECTRONIC ASSEMBLIES HAVING REINFORCING COLLARS ON CONNECTORS EXTENDING THROUGH ENCAPSULATION - A microelectronic assembly or package can include first and second support elements and a microelectronic element between inwardly facing surfaces of the support elements. First connectors and second connectors such as solder balls, metal posts, stud bumps, or the like face inwardly from the respective support elements and are aligned with and electrically coupled with one another in columns. Dielectric reinforcing collars are provided on outer surfaces of the first connectors, second connectors or both, and an encapsulation separates pairs of coupled connectors from one another and may fill spaces between support elements. | 01-15-2015 |
20150014857 | Low-Resistance Electrode Design - A solution for designing a semiconductor device, in which two or more attributes of a pair of electrodes are determined to, for example, minimize resistance between the electrodes, is provided. Each electrode can include a current feeding contact from which multiple fingers extend, which are interdigitated with the fingers of the other electrode in an alternating pattern. The attributes can include a target depth of each finger, a target effective width of each pair of adjacent fingers, and/or one or more target attributes of the current feeding contacts. Subsequently, the device and/or a circuit including the device can be fabricated. | 01-15-2015 |
20150021779 | HARD MASK FOR BACK-END-OF-LINE (BEOL) INTERCONNECT STRUCTURE - A method of fabricating an interconnect structure on a wafer and an interconnect structure are provided. A dielectric layer is provided on the wafer. An interconnect is formed by etching a recess into the dielectric layer, where the etching utilizes a hard mask that includes a first layer deposited over the dielectric layer. The interconnect is planarized using a chemical mechanical polishing (CMP) process, where the first layer remains on the dielectric layer at a completion of the CMP process. The first layer or a portion of the first layer is transformed into a nitride layer or an oxide layer after the CMP process. | 01-22-2015 |
20150021780 | THIN POWER DEVICE AND PREPARATION METHOD THEREOF - A thin power device comprises a substrate having a first set of first contact pads at a front surface of the substrate electrically connecting to a second set of second contact pads at a back surface of the substrate, a through opening opened from the front surface and through the substrate exposing a third contact pad at the back surface of the substrate, a semiconductor chip embedded into the through opening with a back metal layer at a back surface of the semiconductor chip attached on the third contact pad, and a plurality of conductive structures electrically connecting electrodes at a front surface of the semiconductor chip with the corresponding first contact pads in the first sets of first contact pads. | 01-22-2015 |
20150021781 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device has a plurality of first opening portions formed in an interlayer insulating film. The surface is covered with a metal film with a surface having concavities and convexities which scatter reflected light. Size of the first opening portion is of the same level as a contact hole of a component and cannot be recognized by an image recognition apparatus. The metal film can be recognized by the image recognition apparatus. By forming a TiN film serving as a reflection prevention film on an end of the metal film, portions that can easily scatter light and a portion that cannot easily reflect light are adjacent in an alignment marker. A passivation film is formed on the interlayer insulating film and the TiN film. Recessed portions disposed in the metal film are exposed to a second opening portion formed in the passivation film and the TiN film. | 01-22-2015 |
20150021782 | DESIGN METHOD OF WIRING LAYOUT, SEMICONDUCTOR DEVICE, PROGRAM FOR SUPPORTING DESIGN OF WIRING LAYOUT, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a design method of layout formed by a sidewall method is provided. The method includes: preparing a base pattern on which a plurality of first patterns extending in a first direction and arranged at a first space in a second direction intersecting the first direction and a plurality of second patterns extending in the first direction and arranged at a center between the first patterns, respectively, are provided; and drawing a connecting portion which extends in the second direction and connects two neighboring first patterns sandwiching one of the second patterns, and separating the one of the second patterns into two patterns not contacting the connecting portion. | 01-22-2015 |
20150021783 | SEMICONDUCTOR MEMORY SYSTEM - According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed. | 01-22-2015 |
20150028485 | SUBSTRATE STRUCTURE AND SEMICONDUCTOR PACKAGE HAVING THE SAME - A substrate structure is provided. The substrate structure includes a substrate body; a metal layer formed on a surface of the substrate body; an insulating layer formed on the surface of the substrate body and having at least an opening for exposing the metal layer; and at least a die attach area defined on the surface of the substrate body corresponding in position to the opening for a semiconductor chip to be disposed thereon. The die attach area covers the entire opening or the metal layer is formed within the die attach area, thereby effectively preventing package delamination and improving the product yield. | 01-29-2015 |
20150028486 | INTERCONNECT STRUCTURES FOR EMBEDDED BRIDGE - Embodiments of the present disclosure are directed towards interconnect structures for embedded bridge in integrated circuit (IC) package assemblies. In one embodiment, a method includes depositing an electrically insulative layer on a bridge interconnect structure, the bridge interconnect structure including a die contact that is configured to route electrical signals between a first die and a second die, depositing a sacrificial layer on the electrically insulative layer, forming an opening through the sacrificial layer and the electrically insulative layer to expose the die contact and forming a die interconnect of the first die or the second die by depositing an electrically conductive material into the opening. Other embodiments may be described and/or claimed. | 01-29-2015 |
20150028487 | Chip Package with Passives - A chip package device includes an electrically conducting chip carrier, at least one semiconductor chip attached to the electrically conducting chip carrier, and an insulating laminate structure embedding the chip carrier, the at least one semiconductor chip and a passive electronic device. The passive electronic device includes a first structured electrically conducting layer, the first structured electrically conducting layer extending over a surface of the laminate structure. | 01-29-2015 |
20150028488 | METHOD FOR MANUFACTURING A CONDUCTING CONTACT ON A CONDUCTING ELEMENT - The invention relates to a method for producing an interconnection pad on a conducting element comprising an upper face and a side wall; the method being executed from a substrate at least the upper face of which is insulating; the conducting element going through at least an insulating portion of the substrate, the method being characterized in that it comprises the sequence of the following steps: a step of embossing the conducting element, a step of forming, above the upper insulating face of the substrate, a stack of layers comprising at least one electrically conducting layer and one electrically resistive layer, a step of partially removing the electrically resistive layer, a step of electrolytic growth on the portion of the electrically conducting layer so as to form at least one interconnection pad on said conducting element. | 01-29-2015 |
20150028489 | METHOD FOR OFF-GRID ROUTING STRUCTURES UTILIZING SELF ALIGNED DOUBLE PATTERNING (SADP) TECHNOLOGY - A method for efficient off-track routing and the resulting device are disclosed. Embodiments include: providing a hardmask on a substrate; providing a plurality of first mandrels on the hardmask; providing a first spacer on each side of each of the first mandrels; providing a plurality of first non-mandrel regions of the substrate being separated from the first mandrels and between two of the first spacers, each of the first mandrels, first non-mandrel regions, and first spacers having a width equal to a distance; and providing a second mandrel having a width of at least twice the distance and being separated from one of the first non-mandrel regions by a second spacer. | 01-29-2015 |
20150035160 | PAD CONFIGURATIONS FOR AN ELECTRONIC PACKAGE ASSEMBLY - Embodiments of the present disclosure provide an electronic package assembly comprising a solder mask layer, the solder mask layer having at least one opening, and a plurality of pads coupled to the solder mask layer, wherein at least one pad of the plurality of pads includes (i) a first side, (ii) a second side, the first side being disposed opposite to the second side, (iii) a terminal portion and (iv) an extended portion, wherein the first side at the terminal portion is configured to receive a package interconnect structure through the at least one opening in the solder mask layer, the package interconnect structure to route electrical signals between a die and another electronic device that is external to the electronic package assembly, and wherein the second side at the extended portion is configured to receive one or more electrical connections from the die. | 02-05-2015 |
20150041984 | Electronic Component and Method - An electronic component includes a high-voltage depletion-mode transistor, a low-voltage enhancement-mode transistor arranged adjacent and spaced apart from the high-voltage depletion-mode transistor, and an electrically conductive member electrically coupling a first current electrode of the high-voltage depletion-mode transistor to a first current electrode of the low-voltage enhancement-mode transistor. The electrically conductive member has a sheet-like form. | 02-12-2015 |
20150041985 | Semiconductor Device and Method of Making Wafer Level Chip Scale Package - A semiconductor device has a semiconductor wafer and a first conductive layer formed over the semiconductor wafer as contact pads. A first insulating layer formed over the first conductive layer. A second conductive layer including an interconnect site is formed over the first conductive layer and first insulating layer. The second conductive layer is formed as a redistribution layer. A second insulating layer is formed over the second conductive layer. An opening is formed in the second insulating layer over the interconnect site. The opening extends to the first insulating layer in an area adjacent to the interconnect site. Alternatively, the opening extends partially through the second insulating layer in an area adjacent to the interconnect site. An interconnect structure is formed within the opening over the interconnect site and over a side surface of the second conductive layer. The semiconductor wafer is singulated into individual semiconductor die. | 02-12-2015 |
20150041986 | MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE AND METHOD FOR CREATING A LAYOUT THEREOF - A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity. | 02-12-2015 |
20150048512 | SEMICONDUCTOR DEVICES INCLUDING MULTIPLE INTERCONNECTION STRUCTURES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device is manufactured by forming a lower structure on a substrate including first and second regions, simultaneously forming a first interconnection on the lower structure of the first region and a first portion of a second interconnection on the lower structure of the second region, forming a first interlayer insulating layer on the first interconnection and on the first portion of the second interconnection, forming a trench exposing a top surface of the first portion of the second interconnection in the first interlayer insulating layer, and forming a second portion of the second interconnection in the trench. Related structures are also disclosed. | 02-19-2015 |
20150048513 | METHOD FOR OBTAINING THREE-DIMENSIONAL ACTIN STRUCTURES AND USES THEREOF - The present invention relates to a method for preparing three-dimensional actin structures having a well-defined shape and displaying improved mechanical rigidity. This method comprises the steps of (a) providing a polymerization solution comprising actin monomers, a branching agent and a capping agent, (b) providing at least one surface having thereon a pattern which is coated with a nucleating agent, and (c) contacting the at least one surface of step (b) with the polymerization solution of step (a) so as to induce the polymerization of actin and obtain the said desired three-dimensional actin structure. Applications of the present invention in various technological fields such as microelectronics are also provided. | 02-19-2015 |
20150054164 | Semiconductor Constructions - Some embodiments include semiconductor constructions having first and second electrically conductive lines that intersect with one another at an intersection. The first line has primarily a first width, and has narrowed regions directly against the second line and on opposing sides of the second line from one another. Electrically conductive contacts are along the first line and directly electrically coupled to the first line, and one of the electrically conductive contacts is directly against the intersection. Some embodiments include methods of forming intersecting lines of material. First and second trenches are formed, and intersect with one another at an intersection. The first trench has primarily a first width, and has narrowed regions directly against the second trench and on opposing sides of the second trench from one another. Material is deposited within the first and second trenches to substantially entirely fill the first and second trenches. | 02-26-2015 |
20150054165 | THIN FILM TRANSISTOR SUBSTRATE AND LIQUID CRYSTAL DISPLAY INCLUDING THE SAME - A thin film transistor substrate includes: first and second driving chips; a plurality of signal lines respectively connected to the first and second driving chips; a plurality of first and second branch repair lines extended across the plurality of signal lines connected to the first driving chip; a plurality of third and fourth branch repair lines extended across the plurality of signal lines connected to the second driving chip; an insulating layer between the plurality of first and second branch repair lines and the plurality of signal lines connected to the first driving chip, and between the plurality of third and fourth branch repair lines and the plurality of signal lines connected to the second driving chip; a first repair line connecting the first and second branch repair lines to each other; and a second repair line connecting the third and fourth branch repair lines to each other. | 02-26-2015 |
20150054166 | Semiconductor Arrangement, Method for Producing a Number of Chip Assemblies and Method for Producing a Semiconductor Arrangement - A semiconductor arrangement includes a plurality of chip assemblies, each of which includes a semiconductor chip having a semiconductor body with a top side and an underside, a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, an electrically conductive top compensation lamina arranged on a side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode, an electrically conductive bottom compensation lamina arranged on a side of the bottom main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the bottom main electrode, and a dielectric embedding compound enclosing the semiconductor chip laterally circumferentially in a ring-shaped fashion such that the side of the compensation laminae facing away from the semiconductor body are at least not completely covered by the embedding compound. | 02-26-2015 |
20150054167 | Semiconductor Device and Method of Forming Pad Layout for Flipchip Semiconductor Die - A semiconductor device has a semiconductor die with a die pad layout. Signal pads in the die pad layout are located primarily near a perimeter of the semiconductor die, and power pads and ground pads are located primarily inboard from the signal pads. The signal pads are arranged in a peripheral row or in a peripheral array generally parallel to an edge of the semiconductor die. Bumps are formed over the signal pads, power pads, and ground pads. The bumps can have a fusible portion and non-fusible portion. Conductive traces with interconnect sites are formed over a substrate. The bumps are wider than the interconnect sites. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surfaces of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate. | 02-26-2015 |
20150054168 | Single Spacer Process for Multiplying Pitch by a Factor Greater Than Two and Related Intermediate IC Structures - Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n≧2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n−1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n−1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate. | 02-26-2015 |
20150054169 | STACK PACKAGES HAVING TOKEN RING LOOPS - Stack packages are provided. The stack package includes a substrate having first and second bond fingers and a plurality of semiconductor chips stacked on the substrate. Each of the plurality of semiconductor chips has an input bonding pad and an output bonding pad. A first interconnection electrically connects the first bond finger to the input bonding pad of a lowermost semiconductor chip of the plurality of semiconductor chips. A second interconnection electrically connects the output bonding pad of a lower semiconductor chip of the plurality of semiconductor chips to the input bonding pad of an upper semiconductor chip stacked on the lower semiconductor chip. A third interconnection electrically connects the output bonding pad of an uppermost semiconductor chip of the plurality of semiconductor chips to the second bond finger. | 02-26-2015 |
20150061139 | MICROELECTRONIC PACKAGES CONTAINING OPPOSING DEVICES AND METHODS FOR THE FABRICATION THEREOF - Microelectronic packages and methods for fabricating microelectronic packages are provided. The fabrication method may be carried-out utilizing a preformed panel having a frontside cavity and a backside cavity in which first and second microelectronic devices are positioned, respectively. One or more frontside RDL layers are produced over the frontside of the preformed panel in ohmic contact with or otherwise electrically coupled to the first microelectronic device. Similarly, one or more backside RDL layers are formed over the backside of the preformed panel in ohmic contact with or otherwise electrically coupled to the second microelectronic device. A frontside contact array is produced over the frontside of the preformed panel and electrically coupled to at least the first microelectronic device through the frontside RDL layers. Lastly, the preformed panel is singulated to yield a microelectronic package including a package body in which the first and second microelectronic devices are embedded. | 03-05-2015 |
20150061140 | Molded Semiconductor Package with Pluggable Lead - A semiconductor package includes a semiconductor die having a plurality of terminals, a molding compound encapsulating the semiconductor die, and a pluggable lead dimensioned for insertion into an external receptacle. The pluggable lead protrudes from the molding compound and provides a separate electrical pathway for more than one terminal of the semiconductor die. The separate electrical pathways of the pluggable lead can be provided by electrical conductors isolated from one another by electrical insulator such as molding compound or other insulation material/medium. | 03-05-2015 |
20150061141 | INTERCONNECT STRUCTURES AND METHODS OF FORMING SAME - A semiconductor device, an interconnect structure, and methods of forming the same are disclosed. An embodiment is a method of forming a semiconductor device, the method including forming a first dielectric layer over a substrate, forming a first conductive layer in the first dielectric layer, and removing a first portion of the first conductive layer to form at least two conductive lines in the first dielectric layer, the at least two conductive lines being separated by a first spacing. The method further includes forming a capping layer on the at least two conductive lines, and forming an etch stop layer on the capping layer and the first dielectric layer. | 03-05-2015 |
20150061142 | ULTRA FINE PITCH PoP CORELESS PACKAGE - A bottom package for a PoP (package-on-package) may be formed with a reinforcement layer supporting a thin or coreless substrate. The reinforcement layer may provide stiffness and rigidity to the substrate to increase the stiffness and rigidity of the bottom package and provide better handling of the substrate. The reinforcement layer may be formed using core material, a laminate layer, and a metal layer. The substrate may be formed on the reinforcement layer. The reinforcement layer may include an opening sized to accommodate a die. The die may be coupled to an exposed surface of the substrate in the opening. Metal filled vias through the reinforcement layer may be used to couple the substrate to a top package. | 03-05-2015 |
20150061143 | ULTRA FINE PITCH AND SPACING INTERCONNECTS FOR SUBSTRATE - Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a second interconnect. The first dielectric layer includes first and second surfaces. The first interconnect is embedded in the first dielectric layer. The first interconnect includes a first side and a second side. The first side is surrounded by the first dielectric layer, where at least a part of the second side is free of contact with the first dielectric layer. The first cavity traverses the first surface of the first dielectric layer to the second side of the first interconnect, where the first cavity overlaps the first interconnect. The second interconnect includes a third side and a fourth side, where the third side is coupled to the first surface of the first dielectric layer. | 03-05-2015 |
20150061144 | Semiconductor Arrangement, Method for Producing a Semiconductor Module, Method for Producing a Semiconductor Arrangement and Method for Operating a Semiconductor Arrangement - A semiconductor arrangement includes upper and lower contact plates and basic chip assemblies. Each chip assembly has a semiconductor chip having a semiconductor body with upper and lower spaced apart sides. An individual upper main electrode and an individual control electrode are arranged on the upper side. The chip assemblies have either respectively a separate lower main electrode arranged on the lower side of the semiconductor chip of the corresponding basic chip assembly, or a common lower main electrode, which for each of the chip assemblies is arranged on the lower side of the semiconductor body of that chip assembly. An electrical current between the individual upper main electrode and the individual or common lower main electrode is controllable by its control electrode. The chip assemblies are connected to one another with a material bonded connection by a dielectric embedding compound, forming a solid assembly. | 03-05-2015 |
20150061145 | SEMICONDUCTOR DEVICE - The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer. | 03-05-2015 |
20150061146 | ESD PROTECTION DEVICE - An ESD protection device includes a semiconductor substrate including input/output electrodes and a rewiring layer located on the top surface of the semiconductor substrate. An ESD protection circuit is provided in the top layer of the semiconductor substrate, and the input/output electrodes are connected to the ESD protection circuit. The rewiring layer includes interlayer wiring lines, in-plane wiring lines, and post-shaped electrodes. First ends of the interlayer wiring lines provided in the thickness direction are connected to the input/output electrodes provided on the top surface of the semiconductor substrate and the second ends are connected to first ends of the in-plane wiring lines extending in the plane direction. The distance between the centers of the first and second post-shaped electrodes is larger than the distance between the centers of the first and second input/output electrodes. | 03-05-2015 |
20150069615 | SEMICONDUCTOR DEVICE - In one embodiment, a semiconductor device includes first and second semiconductor layers of a first conductivity type above a substrate via a first film, a first electrode above the second semiconductor layer, and a second electrode disposed on a side of the first electrode or an opposite side of the first electrode with respect to the second semiconductor layer. The device further includes a first pad layer connected to the first electrode, a second pad layer connected to the second electrode and including a first upper portion contacting the second electrode, a second upper portion disposed at a level between upper and lower portions of the substrate, and a third upper portion opposed to the lower portion of the substrate, and a third semiconductor layer of a second conductivity type between the second upper portion of the second pad layer and a lower portion of the first film. | 03-12-2015 |
20150069616 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate on which a plurality of contact regions are defined, a plurality of transistors formed in the plurality of contact regions, a support body formed over the plurality of transistors and including a top surface, portions of which have different heights in the plurality of contact regions, a plurality of stacked structures including a plurality of conductive layers stacked over the support body, slits located between the plurality of stacked structures, first lines coupled to first junctions of the plurality of transistors through the slits, and second lines coupled to second junctions of the plurality of transistors through the slits. | 03-12-2015 |
20150069617 | EXTREMELY STRETCHABLE ELECTRONICS - In embodiments, the present invention may attach at least two isolated electronic components to an elastomeric substrate, and arrange an electrical interconnection between the components in a boustrophedonic pattern interconnecting the two isolated electronic components with the electrical interconnection. The elastomeric substrate may then be stretched such that the components separate relative to one another, where the electrical interconnection maintains substantially identical electrical performance characteristics during stretching, and where the stretching may extend the separation distance between the electrical components to many times that of the un-stretched distance. | 03-12-2015 |
20150076700 | SYSTEM-IN-PACKAGES CONTAINING EMBEDDED SURFACE MOUNT DEVICES AND METHODS FOR THE FABRICATION THEREOF - Embodiments of a method for fabricating System-in-Packages (SiPs) are provided, as are embodiments of a SiP. In one embodiment, the method includes producing one or more frontside redistribution layers over a molded panel having a backside and an opposing frontside through which a semiconductor die and a first Surface Mount Device (SMD) are exposed. Material is removed from the backside of the molded panel to expose the first SMD therethrough. A contact array is formed over the frontside of the molded panel and electrically coupled to the semiconductor die and to the first SMD through the frontside redistribution layers. The molded panel is singulated to produce a SiP having a molded body in which the semiconductor die and the first SMD are embedded and through which the first SMD extends. | 03-19-2015 |
20150076701 | SEMICONDUCTOR DEVICE - Certain embodiments provide a semiconductor device including a semiconductor substrate, a side wall portion, a cap substrate, a plurality of external connection terminals, and a ground conductor. The semiconductor substrate includes a semiconductor element on its front surface. The side wall portion has conductivity and is provided on the front surface of the semiconductor substrate so as to surround the semiconductor element. The cap substrate is provided on the side wall portion so as to be electrically connected to the side wall portion. Each of the plurality of external connection terminals is provided on a back surface of the semiconductor substrate so as to be electrically connected to the semiconductor element. The ground conductor is provided to be electrically connected to the side wall portion on the entire back surface of the semiconductor substrate except an area in which the plurality of external connection terminals is provided. | 03-19-2015 |
20150076702 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including a semiconductor substrate having a hook-up region; wirings extending in a first direction above the semiconductor substrate and being aligned with a first spacing between one another, every two wirings forming pairs of wirings, each pair having a first portion being bent in a second direction different from the first direction in the hook-up region, the wirings of each pair being spaced from one another by a first spacing, the pairs being spaced from one another by a second spacing greater than the first spacing; and fringe patterns each being formed on a first side of each of the wirings of each of the pairs, the first side facing the second spacing. | 03-19-2015 |
20150076703 | SEMICONDUCTOR MEMORY DEVICE HAVING PADS - A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power. | 03-19-2015 |
20150084200 | IMPRINTED MULTI-LEVEL MICRO-WIRE CIRCUIT STRUCTURE METHOD - A method of making a multi-level micro-wire structure includes imprinting first micro-channels in a curable first layer over a substrate with a first stamp, curing the first layer, and locating and curing a curable conductive ink in the first micro-channels to form first micro-wires. Second micro-channels are imprinted in a curable second layer in contact with the first layer with a second stamp, the second layer is cured, and a curable conductive ink is located and cured in the second micro-channels to form second micro-wires. At least one of the second micro-channels contacts at least one first micro-wire and a second micro-wire in at least one of the second micro-channels is in electrical contact with at least one first micro-wire. | 03-26-2015 |
20150084201 | IMPRINTED MICRO-WIRE CIRCUIT MULTI-LEVEL STAMP METHOD - A method of making a multi-level micro-wire structure includes imprinting first micro-channels in a curable first layer over a substrate, curing the first layer, and locating and curing a curable conductive ink in the first micro-channels to form first micro-wires. Multi-level second micro-channels are imprinted in a curable second layer in contact with the first layer with a multi-level stamp, the second layer is cured, and a curable conductive ink is located and cured in the multi-level second micro-channels to form multi-level second micro-wires. At least one of the multi-level second micro-channels contacts at least one first micro-wire. A multi-level second micro-wire in at least one of the multi-level second micro-channels is in electrical contact with at least one first micro-wire. | 03-26-2015 |
20150084202 | DIE EDGE SIDE CONNECTION - An apparatus comprises a first integrated circuit (IC) die that includes a top layer, a bottom surface, a sidewall surface extending from a top surface of the top layer to the bottom surface, and at least one multi-surface contact pad, a second IC die including a top layer, a bottom surface, a sidewall surface extending from a top surface of the top layer to the bottom surface, and at least one multi-surface contact pad, wherein the second IC die is arranged adjacent to the first IC die, and includes an electrically conductive bond in contact with at least one of the top surface or the side surface of the multi-surface contact pad of the first IC die and the top surface of the multi-surface contact pad of the second IC die. | 03-26-2015 |
20150084203 | CONTACT STRUCTURE AND FORMING METHOD - A method for forming a contact structure includes forming a stack of alternating active layers and insulating layers. The stack includes first and second sub stacks each with active layers separated by insulating layers. The active layers of each sub stack include an upper boundary active layer. A sub stack insulating layer is formed between the first and second sub stacks with an etching time different from the etching times of the insulating layers for a given etching process. The upper boundary active layers are accessed, after which the remainder of the active layers are accessed to create a stairstep structure of landing areas on the active layers. Interlayer conductors are formed to extend to the landing areas, the interlayer conductors separated from one another by insulating material. | 03-26-2015 |
20150084204 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the same. The device may include a substrate including a cell array region and a peripheral circuit region, stacks on the cell array region of the substrate, the stacks having a first height and extending along a direction, a common source structure disposed between adjacent ones of the stacks, a peripheral logic structure disposed on the peripheral circuit region of the substrate and having a second height smaller than the first height, a plurality of upper interconnection lines disposed on the peripheral logic structure and extending parallel to each other, and a interconnection structure disposed between the peripheral logic structure and the upper interconnection lines, when viewed in vertical section, and electrically connected to at least two of the upper interconnection lines. | 03-26-2015 |
20150091175 | INTERCONNECTS WITH FULLY CLAD LINES - A metallization layer including a fully clad interconnect and a method of forming a fully clad interconnect. An opening is formed in a dielectric layer, wherein the dielectric layer has a surface and the opening includes walls and a bottom. A diffusion barrier layer and an adhesion layer are deposited on the dielectric layer. An interconnect material is deposited on the dielectric layer and reflowed into the opening forming an interconnect. An adhesion capping layer and diffusion barrier capping layer are deposited over the interconnect. The interconnect is surrounded by the adhesion layer and the adhesion capping layer and the adhesion layer and the adhesion capping layer are surrounded by the diffusion barrier layer and the diffusion capping layer. | 04-02-2015 |
20150091176 | Electronic Component, Arrangement and Method - An electronic component includes at least one semiconductor device and a redistribution board comprising at least two nonconductive layers and a conductive redistribution structure. The semiconductor device is embedded in the redistribution board and electrically coupled to the redistribution structure and the redistribution board has a side face with a step. An outer contact pad of the redistribution structure is arranged on the step. | 04-02-2015 |
20150091177 | EXTERNAL CONNECTION TERMINAL, SEMICONDUCTOR PACKAGE HAVING EXTERNAL CONNECTION TERMINAL, AND METHODS FOR MANUFACTURING THE SAME - Disclosed herein are an external connection terminal part, a semiconductor package having the external connection terminal part, and a method for manufacturing the same. According to a preferred embodiment of the present invention, the external connection terminal part includes an insulating material and metal plating pattern formed on both surfaces of the insulating material. | 04-02-2015 |
20150097293 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE THEREOF - Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming an insulating material layer over a workpiece, patterning an upper portion of the insulating material layer with a conductive line pattern, and forming a stop layer comprising a metal oxide or a metal nitride over the patterned insulating material layer. A masking material is formed over the stop layer, and the masking material is patterned with a via pattern. The via pattern of the masking material is transferred to a lower portion of the insulating material layer. | 04-09-2015 |
20150097294 | METHOD FOR PROCESSING A WAFER AND WAFER STRUCTURE - A method for processing a wafer in accordance with various embodiments may include: removing wafer material from an inner portion of the wafer to form a structure at an edge region of the wafer to at least partially surround the inner portion of the wafer, and printing material into the inner portion of the wafer using the structure as a printing mask. A method for processing a wafer in accordance with various embodiments may include: providing a carrier and a wafer, the wafer having a first side and a second side opposite the first side, the first side of the wafer being attached to the carrier, the second side having a structure at an edge region of the wafer, the structure at least partially surrounding an inner portion of the wafer; and printing material onto at least a portion of the second side of the wafer. | 04-09-2015 |
20150097295 | Semiconductor Device and Method of Forming Conductive Layer Over Substrate with Vents to Channel Bump Material and Reduce Interconnect Voids - A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A first conductive layer having first and second segments is formed over a surface of the substrate with a first vent separating an end of the first segment and the second segment and a second vent separating an end of the second segment and the first segment. A second conductive layer is formed over the surface of the substrate to electrically connect the first segment and second segment. The thickness of the second conductive layer can be less than a thickness of the first conductive layer to form the first vent and second vent. The semiconductor die is mounted to the substrate with the bumps aligned to the first segment and second segment. Bump material from reflow of the bumps is channeled into the first vent and second vent. | 04-09-2015 |
20150102493 | Die and Chip - A die according to an embodiment includes a contact pad configured to provide an electrical contact to a circuit element included in the die, a lateral edge closest to the contact pad and a cover layer including a protective structure, the protective structure including at least one elongated structure, wherein the cover layer includes an opening providing access to the contact pad to couple the contact pad electrically to an external contact, wherein the protective structure is arranged between the lateral edge and the contact pad. Using an embodiment may reduce a danger of contamination of a top side of a die during fabrication and packaging a chip. | 04-16-2015 |
20150102494 | METHOD FOR FORMING VOIDS AND STRUCTURE WITH VOIDS FORMED USING THE SAME - A method for forming voids corresponding to pads of SMT components is provided. The method comprises following steps: One or more condition parameters are inputted into a searching unit. The searching unit searches all of the pads with reference to the condition parameters to obtain a pre-selected group of pads. A judgment unit is provided to determine whether each pad of the pre-selected group of pads meets a pre-determined processing requirement to generate a to-be-processed group of pads. An execution unit executes a void formation step with reference to corner coordinates of each of the to-be-processed group of pads, so as to form at least a void at the portion of a contact surface corresponding to a corner of the pad. In an embodiment, four voids which are related to respective corners of each pad of the to-be-processed group are formed at the contact surface accordingly. | 04-16-2015 |
20150108652 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD - A semiconductor device and its fabrication method are provided. A first dielectric layer is provided to cover a substrate. The first dielectric layer contains a plurality of first conductive layers. A portion of each first conductive layer is removed to form a plurality of first openings in the first dielectric layer. A second dielectric layer is formed in each first opening. A third dielectric layer having second-openings are formed on the first dielectric layer and on the second dielectric layers. Each second-opening exposes at least two adjacent second dielectric layers. Second dielectric layers exposed by a first second-opening are removed to form third openings to expose corresponding first conductive layers. Second conductive layers are formed in the third opening and the second-openings including the first second-opening. Stable electrical interconnections with high quality electrical isolations can be provided. | 04-23-2015 |
20150115454 | MICROELECTRONIC PACKAGES HAVING LAYERED INTERCONNECT STRUCTURES AND METHODS FOR THE MANUFACTURE THEREOF - Microelectronic packages having layered interconnect structures are provided, as are methods for the fabrication thereof. In one embodiment, the method includes forming a first plurality of interconnect lines in ohmic contact with a first bond pad row provided on a semiconductor. A dielectric layer is deposited over the first plurality of interconnect lines, the first bond pad row, and a second bond pad row adjacent the first bond pad row. A trench via is then formed in the dielectric layer to expose at least the second bond pad row therethrough. A second plurality of interconnect lines is formed in ohmic contact with the second bond pad row within the trench via. The second plurality of interconnect lines extends over the first bond pad row and is electrically isolated therefrom by the dielectric layer to produce at least a portion of the layered interconnect structure. | 04-30-2015 |
20150115455 | STACKED 3D MEMORY - A memory can include a plurality of memory blocks, including a first block and a second block disposed over the first block. An isolation layer is disposed in this structure, between the first and second blocks to isolate the vertical conductors in the memory kernels of the first and second blocks. Access conductors are provided outside the kernels, such as adjacent the memory blocks or through regions of the blocks that only include decoding element. The access conductors are coupled to the decoding elements in the first and second blocks, and provide for connection of the memory cells to peripheral circuits. | 04-30-2015 |
20150115456 | DIE UP FULLY MOLDED FAN-OUT WAFER LEVEL PACKAGING - A method of manufacturing a semiconductor chip comprising placing a plurality of die units each having an active front surface and a back surface facing front surface up on an encapsulant layer, encapsulating the plurality of die units on the active surface of the encapsulant layer with an encapsulant covering a front surface and four side surfaces of each of the plurality of die units, and exposing, through the encapsulation on the front surface, conductive interconnects electrically connecting a die bond pad to a redistribution layer. | 04-30-2015 |
20150115457 | SEMICONDUCTOR DEVICE - A semiconductor device, including a substrate having an active region defined therein, a plurality of bit lines extending on the substrate in a first direction, a plurality of interconnection lines extending on the substrate in a second direction, a pad electrically connected to the plurality of interconnection lines and configured to apply an external voltage, a plurality of metal contacts electrically connecting the interconnection lines and the plurality of bit lines, and a plurality of bit line contacts that are in contact with the active region and electrically connect the plurality of bit lines and the active region, wherein a size of at least some of the bit line contacts and/or at least some of the metal contacts vary based on a distance of the respective bit line contact or the metal contact from the pad. | 04-30-2015 |
20150123281 | SEMICONDUCTOR PACKAGE SUBSTRATE, PACKAGE SYSTEM USING THE SAME AND METHOD FOR MANUFACTURING THEREOF - A semiconductor package substrate includes an insulating substrate; a circuit pattern on the insulating substrate; a protective layer on the insulating substrate, the protective layer covering the circuit pattern on the insulating substrate; a pad on the protective layer; and an adhesive member on the protective layer, wherein the pad includes a first pad buried in the protective layer, and a second pad on the first pad, the second pad protruding over the protective layer. | 05-07-2015 |
20150123282 | SEMICONDUCTOR DEVICE - A semiconductor device includes an interlayer dielectric on a semiconductor substrate, a contact plug penetrating the interlayer dielectric, a pillar pattern disposed on the interlayer dielectric and having a central axis laterally offset from a central axis of the contact plug, a pad extending on the contact plug and along a sidewall of the pillar pattern, the pad being electrically connected to the contact plug, and a data storage portion on the pillar pattern and electrically connected to the pad. | 05-07-2015 |
20150130066 | INTEGRATED CIRCUIT DEVICE WITH A CONNECTOR ACCESS REGION AND METHOD FOR MAKING THEREOF - An integrated circuit device and a method for making it are provided. The integrated circuit device comprises plural conductive layers, plural dielectric layers and plural first stopping layers. The conductive layers are extending in a first direction. The dielectric layers are paralleled to the conductive layers, and the conductive layers and the dielectric layers are disposed in an alternative arrangement. The first stopping layers are disposed over the conductive layers and the dielectric layers. The first stopping layers make no contact with the conductive layers. | 05-14-2015 |
20150130067 | OHMIC CONTACT STRUCTURE AND SEMICONDUCTOR DEVICE HAVING THE SAME - This invention provides an ohmic contact structure including: a semiconductor substrate having a top surface which includes a plurality of micro-structures; and a conductive layer, which is formed on the micro-structures. An ohmic contact is formed by the conductive layer and the semiconductor substrate. The present invention also provides a semiconductor device having the ohmic contact structure. | 05-14-2015 |
20150130068 | APPARATUS AND METHOD OF THREE DIMENSIONAL CONDUCTIVE LINES - An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column. | 05-14-2015 |
20150130069 | Self-Aligned Capillarity-Assisted Microfabrication - A manufacturing process, which we term Self-Aligned Capillarity-Assisted Lithography for manufacturing devices having nano-scale or micro-scale features, such as flexible electronic circuits, is described. | 05-14-2015 |
20150137378 | Semiconductor Device having Voids and Method of Forming Same - A method embodiment includes forming a hard mask over a dielectric layer and forming a first metal line and a second metal line extending through the hard mask into the dielectric layer. The method further includes removing the hard mask, wherein removing the hard mask defines an opening between the first metal line and the second metal line. A liner is then formed over the first metal line, the second metal line, and the dielectric layer, wherein the liner covers sidewalls and a bottom surface of the opening. | 05-21-2015 |
20150137379 | Fan Out Package Structure and Methods of Forming - An embodiment is a structure comprising a die having a pad on a surface and an encapsulant at least laterally encapsulating the die. The pad is exposed through the encapsulant. The structure further includes a first dielectric layer over the encapsulant and the die, a first conductive pattern over the first dielectric layer, and a second dielectric layer over the first conductive pattern and the first dielectric layer. The first dielectric layer and the second dielectric layer have a first opening to the pad of the die. The structure further includes a second conductive pattern over the second dielectric layer and in the first opening. The second conductive pattern adjoins a sidewall of the first dielectric layer in the first opening and a sidewall of the second dielectric layer in the first opening. | 05-21-2015 |
20150137380 | ELECTRONIC DEVICE INCORPORATING A RANDOMIZED INTERCONNECTION LAYER - An electronic device incorporating a randomized interconnection layer. In one example, the device includes a randomized interconnection layer having a randomized conductive pattern formed by etching of a heterogeneous layer; and a sensing circuit, electrically coupled to the randomized interconnection layer to detect the randomized conductive pattern. In another example, a method of fabricating the device includes forming a set of electrodes proximate to a silicon substrate; depositing a heterogeneous layer of elements onto the substrate; etching the heterogeneous layer to form a randomized conductive pattern; and electrically coupling the electrodes to a sensing circuit and the randomized conductive pattern. | 05-21-2015 |
20150137381 | OPTICALLY-MASKED MICROELECTRONIC PACKAGES AND METHODS FOR THE FABRICATION THEREOF - Microelectronic packages and methods for fabricating microelectronic packages having optical mask layers are provided. In one embodiment, the method includes building redistribution layers over the frontside of a semiconductor die. The redistribution layers includes a body of dielectric material in which a plurality of interconnect lines are formed. An optical mask layer is formed over the frontside of the semiconductor die and at least a portion of the redistribution layers. The optical mask layer has an opacity greater than the opacity of the body of dielectric material and blocks or obscures visual observation of an interior portion of the microelectronic package through the redistribution layers. | 05-21-2015 |
20150145137 | METHOD TO PROVIDE THE THINNEST AND VARIABLE SUBSTRATE THICKNESS FOR RELIABLE PLASTIC AND FLEXIBLE ELECTRONIC DEVICE - An electronic device is formed by depositing polyimide on a glass substrate. A conductive material is deposited on the polyimide and patterned to form electrodes and signal traces. Remaining portions of the electronic device are formed on the polyimide. A second polyimide layer is then formed on the first polyimide layer. The glass substrate is then removed, exposing the electrodes and the top surface of the electronic device. | 05-28-2015 |
20150145138 | EMBEDDED SEMICONDUCTIVE CHIPS IN RECONSTITUTED WAFERS, AND SYSTEMS CONTAINING SAME - A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer. | 05-28-2015 |
20150294947 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device with improved reliability is provided. The semiconductor device is characterized by its embodiments in that sloped portions are formed on connection parts between a pad and a lead-out wiring portion, respectively. This feature suppresses crack formation in a coating area where a part of the pad is covered with a surface protective film. | 10-15-2015 |
20150294957 | CHIP PACKAGING STRUCTURE - A chip packaging structure includes an encapsulating material, plurality of first leads, plurality of second leads, a first chip, a second chip and an adhesion layer. The encapsulating material has a top package surface and a corresponding bottom package surface. Each first lead has a first inner lead portion and a first outer lead portion. The first chip is located on the first inner lead portion and electrically coupled to the first leads. Each second lead has a second inner lead portion and a second outer lead portion. The second chip is located on the second inner lead portion and electrically coupled to the second leads. The adhesion layer is located between the first leads and second leads so that the first leads and second leads are connected to each other. | 10-15-2015 |
20150294986 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - The present invention provides an array substrate and a manufacturing method thereof, and a display device. The array substrate of the present invention comprises: common electrodes, pixel electrodes, common electrode lines and at least one auxiliary common electrode line, and the at least one auxiliary common electrode line is arranged to intersect with and be electrically connected to the common electrode lines. The manufacturing method of an array substrate of the present invention comprises a step of forming common electrode lines and a step of forming auxiliary common electrode lines, wherein the auxiliary common electrode lines are arranged to intersect with and be electrically connected to the common electrode lines. The display device of the present invention comprises the above array substrate. | 10-15-2015 |
20150301416 | ARRAY SUBSTRATE AND DISPLAY DEVICE - Embodiments of the invention provide an array substrate and a display device. The array substrate comprises a common electrode and a pixel electrode that are formed on a base substrate. The common electrode comprises a first common electrode and a second common electrode, the first common electrode is provided below the pixel electrode and separated from the pixel electrode by an insulating layer, the second common electrode is provided in the same layer as the pixel electrode. The pixel electrode comprises a plurality of strip electrodes, the second common electrode also comprises a plurality of strip electrodes, and the strip electrodes of the pixel electrode and the strip electrodes of the second common electrode are alternately arranged. | 10-22-2015 |
20150301419 | ARRAY PLATE AND LIQUID CRYSTAL DISPLAY PANEL HAVING THE SAME - An LCD panel is disclosed. The LCD panel has an array plate and a CF plate. The array plate has a plurality of array common electrode lines, a pixel array, a plurality of gate lines, and a plurality of transparent conduct pads. The pixel array has a plurality of pixel units. The pixel units are arranged in rows and columns Each pixel unit has a pixel common electrode, and the pixel common electrodes of each row of pixel units are connected to the same array common electrode line. The gate lines are disposed between rows of pixel units. Each transparent conduct pad is disposed astride one of the gate lines and disposed between the adjacent pixel units of the same column of pixel units. The adjacent pixel units of the same column of pixel units are electrically connected with each other by one of the transparent conduct pads. | 10-22-2015 |
20150311112 | Patterning Method For Low-K Inter-Metal Dielectrics And Associated Semiconductor Device - Semiconductor fabrication techniques and associated semiconductor devices are provided in which conductive lines are separated by a low dielectric constant (low-k) material such as low-k film portions or air. An insulation layer such as SiO2 is etched to form raised structures. The structures are slimmed and a low-k material or sacrificial material is deposited. A further etching removes the material except for portions on sidewalls of the slimmed structures. A metal barrier layer and seed layer are then deposited, followed by a metal filler such as copper. Chemical mechanical polishing (CMP) removes portions of the metal above the raised structures, leaving only portions of the metal between the raised structures as spaced apart conductive lines. The sacrificial material can be removed by a thermal process, leaving air gaps. The raised structures provide strength while the air gap or other low-k material reduces capacitance. | 10-29-2015 |
20150311113 | TRENCH STRUCTURE FOR HIGH PERFORMANCE INTERCONNECTION LINES OF DIFFERENT RESISTIVITY AND METHOD OF MAKING SAME - An integrated circuit includes a substrate with an interlevel dielectric layer positioned above the substrate. First trenches having a first depth are formed in the interlevel dielectric layer and a metal material fills the first trenches to form first interconnection lines. Second trenches having a second depth are also formed in the interlevel dielectric layer and filled with a metal material to form second interconnection lines. The first and second interconnection lines have a substantially equal pitch, which in a preferred implementation is a sub-lithographic pitch, and different resistivities due to the difference in trench depth. The first and second trenches are formed with an etching process through a hard mask having corresponding first and second openings of different depths. A sidewall image transfer process is used to define sub-lithographic structures for forming the first and second openings in the hard mask. | 10-29-2015 |
20150311114 | SEMICONDUCTOR STRUCTURE AND METHOD OF MAKING THE SAME - The present disclosure provides a method for forming a semiconductor structure. In accordance with some embodiments, the method includes providing a substrate and a conductive feature formed over the substrate; forming a low-k dielectric layer over the conductive feature; forming a contact trench aligned with the conductive feature; and selectively growing a sealing layer which is a monolayer formed on sidewalls of the contact trench. | 10-29-2015 |
20150311134 | UNDERFILL MATERIAL INCLUDING BLOCK COPOLYMER TO TUNE COEFFICIENT OF THERMAL EXPANSION AND TENSILE MODULUS - Embodiments of the present disclosure are directed toward underfill material including block copolymer. In one embodiment, an underfill material includes epoxy material and a copolymer including an epoxy-philic block and an epoxy-phobic block, wherein the epoxy-philic block is miscible in the epoxy material, the epoxy-phobic block is covalently bonded with the epoxy-philic block, the epoxy-phobic block is separated in a microphase domain within the epoxy material and the epoxy-philic block is configured to restrict thermal expansion or contraction of the epoxy material. | 10-29-2015 |
20150311151 | Interconnect Structure Having Air Gap and Method of Forming the Same - A method for forming a semiconductor device includes forming a first dielectric layer overlying a substrate, forming at least a first opening in the first dielectric layer, forming a conformal dense layer lining the at least first opening in the first dielectric layer, forming a barrier layer overlying the conformal dense layer, forming a conductive feature in the at least first opening, removing a portion of the first dielectric layer between any two adjacent conductive features to form a second opening, wherein the second opening exposes the conformal dense layer between the two adjacent conductive features, and depositing between the two adjacent conductive features a second dielectric layer having an air gap formed therein. | 10-29-2015 |
20150311157 | NANOTUBE STRUCTURE BASED METAL DAMASCENE PROCESS - In various embodiments a method for manufacturing a metallization layer on a substrate is provided, wherein the method may include forming a plurality of groups of nanotubes over a substrate, wherein the groups of nanotubes may be arranged such that a portion of the substrate is exposed and forming metal over the exposed portion of the substrate between the plurality of groups of nanotubes. | 10-29-2015 |
20150318236 | INTEGRATED CIRCUIT PACKAGE SUBSTRATE - Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first lamination layer on a first side of a package substrate and a first surface finish on one or more electrical contacts disposed on a second side of the package substrate; removing the first lamination layer from the first side of the package substrate; depositing a second lamination layer on the second side of the package substrate and a second surface finish on the one or more electrical contacts disposed on the first side of the package substrate; and removing the second lamination layer from the second side of the package substrate. Other embodiments may be described and/or claimed. | 11-05-2015 |
20150318241 | STRUCTURES, DEVICES AND METHODS FOR MEMORY DEVICES - Structures, devices and methods are provided for fabricating memory devices. A structure includes: a first conductive line disposed in a first conductive layer; a first landing pad disposed in the first conductive layer and associated with a second conductive line disposed in a second conductive layer; and a second landing pad disposed in the first conductive layer and associated with a third conductive line disposed in a third conductive layer. The second conductive layer and the third conductive layer are different from the first conductive layer. | 11-05-2015 |
20150318250 | Bonding Structures and Methods of Forming the Same - A package includes a package component and a second package component. A first elongated bond pad is at a surface of the first package component, wherein the first elongated bond pad has a first length in a first longitudinal direction, and a first width smaller than the first length. A second elongated bond pad is at a surface of the second package component. The second elongated bond pad is bonded to the first elongated bond pad. The second elongated bond pad has a second length in a second longitudinal direction, and a second width smaller than the second width. The second longitudinal direction is un-parallel to the first longitudinal direction. | 11-05-2015 |
20150318304 | ARRAY SUBSTRATE, METHOD OF MANUFACTURING THE SAME, AND DISPLAY DEVICE - The present disclosure relates to an array substrate, a method of manufacturing the same and a display device. The array substrate comprises a gate line PAD region and a data line PAD region. In the gate line PAD region of the array substrate, gate-line wirings, which are parallel to the gate lines and are electrically insulated from the gate lines, are provided between adjacent gate lines. In the data line PAD region of the array substrate, data-line wirings, which are parallel to the data lines and are electrically insulated from the data lines, are provided between adjacent data lines. Both of the gate-line wirings and the data-line wirings are conductive wiring segments. By forming the gate-line wirings and the data-line wirings in the PAD region, the ability of resisting scratch of the product can be improved while not deteriorating performance of display of the product. | 11-05-2015 |
20150318305 | AN ARRAY SUBSTRATE AND A METHOD FOR MANUFACTURING THE SAME - An array substrate is disclosed. The array substrate comprises a base substrate ( | 11-05-2015 |
20150325470 | Sublithographic Kelvin Structure Patterned With DSA - In one aspect, a DSA-based method for forming a Kelvin-testable structure includes the following steps. A guide pattern is formed on a substrate which defines i) multiple pad regions of the Kelvin-testable structure and ii) a region interconnecting two of the pad regions on the substrate. A self-assembly material is deposited onto the substrate and is annealed at a temperature/duration sufficient to cause it to undergo self-assembly to form a self-assembled pattern on the substrate, wherein the self-assembly is directed by the guide pattern such that the self-assembled material in the region interconnecting the two pad regions forms multiple straight lines. A pattern of the self-assembled material is transferred to the substrate forming multiple lines in the substrate, wherein the pattern of the self-assembled material is configured such that only a given one of the lines is a continuous line between the two pad regions on the substrate. | 11-12-2015 |
20150325478 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE FABRICATED BY THE METHOD - A method of fabricating a semiconductor device includes stacking an etch target layer, a first mask layer, and a second mask layer on a first surface of a substrate. A plurality of first spacer lines are formed parallel to each other and a first spacer pad line on the second mask layer is formed. A third mask pad in contact with at least the first spacer pad line on the second mask layer is formed. The second mask layer and the first mask layer are etched to form one or more first mask lines, a first mask preliminary pad, and second mask patterns. Second spacer lines are respectively formed covering sidewalls of the first mask preliminary pad and the first mask lines. First mask pads are formed. The etch target layer is etched to form conductive lines and conductive pads connected to the conductive lines. | 11-12-2015 |
20150325525 | FORMING INTERCONNECT STRUCTURE WITH POLYMERIC LAYER AND RESULTING DEVICE - Methods for forming an interconnect structure using a carbon-rich polymeric layer and the resulting devices are disclosed. Embodiments may include forming a carbon-rich polymeric layer above a semiconductor element, forming a silicon oxide material layer above the carbon-rich polymeric layer, and forming an interconnect through the silicon oxide material layer and the carbon-rich polymeric layer. | 11-12-2015 |
20150325533 | Methods and Apparatus of Guard Rings for Wafer-Level-Packaging - A method of forming a semiconductor device includes forming a passivation layer on top of a guard ring and an active area of a circuit device, forming a passivation contact within the passivation layer, the passivation contact being over and electrically connected to the guard ring, forming a post-passivation interconnect (PPI) guard ring over the passivation layer and electrically connected to the passivation contact, and forming a first polymer layer over the PPI guard ring, the first polymer layer extending along a sidewall of the PPI guard ring. | 11-12-2015 |
20150325586 | MEMORY DEVICE - Provided is a memory device including first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction, multiple sets of first to third vertical pillars, each set coupled with a corresponding one of the first to third selection lines and sequentially arranged in the second direction, a first sub-interconnection connecting the third vertical pillar coupled with the first selection line to the first vertical pillar coupled with the second selection line, a second sub-interconnection connecting the third vertical pillar coupled with the second selection line to the first vertical pillar coupled with the third selection line, and bit lines extending in the second direction and connected to corresponding ones of the first and second sub-interconnections. | 11-12-2015 |
20150332954 | SEMICONDUCTOR DEVICE HAVING AIR GAP STRUCTURES AND METHOD OF FABRICATING THEREOF - One method includes forming a conductive feature in a dielectric layer on a substrate for a semiconductor device. A hard mask layer and an underlying etch stop layer are formed on the substrate. The hard mask layer and the underlying etch stop layer are then patterned. The patterned etch stop layer is disposed over the conductive feature. At least one of the patterned hard mask layer and the patterned etch stop layer are used as a masking element during etching of a trench in the dielectric layer adjacent the conductive feature. A cap is then formed over the etched trench. The cap is disposed on the patterned etch stop layer disposed on the conductive feature. | 11-19-2015 |
20150332983 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR - A manufacturing method for a semiconductor device in which connection portions of a semiconductor chip are electrically connected to connection portions of a wiring circuit substrate or a semiconductor device in which connection portions of a plurality of semiconductor chips are electrically connected to each other, the method comprising a step of sealing at least part of the connection portions with an adhesive for a semiconductor comprising a compound having a group represented by the following formula (1): | 11-19-2015 |
20150332984 | UNDERFILL COMPOSITION AND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To provide a solid preapplication underfill material that has excellent workability, has a high degree of freedom for solder bonding processes, and enables the formation of a solder bond with high reliability. (Resolution Means) The underfill composition of the present disclosure contains a hardened epoxy resin and has a viscosity of 1000 Pa·s or more at 30° C. The hardening epoxy resin includes a crystalline epoxy resin at not less than 50 wt % relative to an entire resin composition. | 11-19-2015 |
20150332998 | PACKAGING SUBSTRATE AND PACKAGE STRUCTURE - A packaging substrate and a package structure are provided. The packaging substrate includes a plurality of dielectric layers, two of which have a difference in thickness; and a plurality of circuit layers alternately stacked with the dielectric layers. Therefore, the package warpage encountered in the prior art is avoided. | 11-19-2015 |
20150332999 | SEMICONDUCTOR INTERCONNECT STRUCTURE AND MANUFACTURING METHOD THEREOF - The present disclosure provides an interconnect structure, including a low k dielectric layer with an air gap region and a non-air gap region. A first conductive line is positioned in the air gap region, and a second conductive line is positioned in the non-air gap region of the low k dielectric layer. A height of the first conductive line is different from a height of the second conductive line. The present disclosure also provides a method for manufacturing a semiconductor interconnect structure, including forming a photoresist layer over a hard mask layer with openings exposing a low k dielectric layer; treating the low k dielectric layer to be more hydrophilic through the openings of the hard mask layer; and removing the treated low k dielectric region to form an air gap in the air gap region. | 11-19-2015 |
20150333000 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND DEVICE MANUFACTURED USING THE SAME - A method for manufacturing a semiconductor device and a device manufactured using the same are provided. According to the embodiment, substrate with a dielectric layer formed thereon is provided. Plural trenches are defined in the dielectric layer, and the trenches are isolated by the dielectric layer. A first barrier layer is formed in the trenches as barrier liners of the trenches, followed by filling the trenches with a conductor. Then, the conductor in the trenches is partially removed to form a plurality of recesses, wherein remained conductor has a flat surface. Next, a second barrier layer is formed in the recesses as barrier caps of the trenches. | 11-19-2015 |
20150333039 | BONDING PAD ARRANGMENT DESIGN FOR MULTI-DIE SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package structure includes a base. A first die is mounted on the base. The first die comprises a plurality of first pads with a first pad area arranged in a first tier. A plurality of second pads with a second pad area is arranged in a second tier. A second die is mounted on the base. The second die includes a plurality of third pads arranged in a third tier. A first bonding wire has two terminals respectively coupled to one of the first pads and one of the third pads. A second bonding wire has two terminals respectively coupled to one of the third pads and one of the second pads. | 11-19-2015 |
20150333046 | INTEGRATED DEVICE - An integrated device with high insulation tolerance is provided. A groove having an inclined side surface is provided between adjacent devices. When a side where an electronic circuit or MEMS device is mounted is a front surface, the groove becomes narrower from the front surface to a back surface because of the inclined surface. A mold material (insulating material) is disposed inside the groove, so that the plurality of devices are mechanically joined together, being electrically insulated from one another. A line member that establishes an electrical conduction between the adjacent devices is formed to lie along the side surface and the bottom surface of the groove. To lead the line out to the backside, the bottom surface of the groove has a hole, so that the line member is exposed to the backside from the hole. | 11-19-2015 |
20150333056 | METHODS FOR CONSTRUCTING THREE DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs) AND RELATED SYSTEMS - Methods for constructing three dimensional integrated circuits and related systems are disclosed. In one aspect, a first tier is constructed by creating active elements such as transistors on a holding substrate. An interconnection metal layer is created above the active elements. Metal bonding pads are created within the interconnection metal layer. A second tier is also created, either concurrently or sequentially. The second tier is created in much the same manner as the first tier and is then placed on the first tier, such that the respective metal bonding pads align and are bonded one tier to the other. The holding substrate of the second tier is then released. A back side of the second tier is then thinned, such that the back surfaces of the active elements (for example, a back of a gate in a transistor) are exposed. Additional tiers may be added if desired essentially repeating this process. | 11-19-2015 |
20150340234 | METHOD FOR PROCESSING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for processing a semiconductor device in accordance with various embodiments may include: depositing a first metallization material over a semiconductor body; performing a heating process so as to form at least one region in the semiconductor body including a eutectic of the first metallization material and material of the semiconductor body; and depositing a second metallization material over the semiconductor body so as to contact the semiconductor body via the at least one region in the semiconductor body. | 11-26-2015 |
20150340311 | SEMICONDUCTOR DEVICE INCLUDING PLURAL SEMICONDUCTOR CHIPS STACKED ON SUBSTRATE - A semiconductor chip at least includes a row of first electrode pad group, which includes at least one first independent electrode pad and multiple first common electrode pads. The interval between the first independent electrode pad and an electrode pad adjacent thereto is defined as “first pitch”, and the interval between adjacent electrode pads making up the multiple first common electrode pads is defined as “second pitch”. The first pitch is determined to be larger than the second pitch. | 11-26-2015 |
20150340313 | Semiconductor Devices Having Nonlinear Bitline Structures - Semiconductor devices are provided including a plurality of nonlinear bit lines formed on a substrate including a plurality of active areas; a plurality of word lines that pass through the plurality of active areas; an integral spacer that covers two sidewalls of the plurality of nonlinear bit lines and defines a plurality of spaces that expose two adjacent ones of the plurality of active areas; two conductive patterns that respectively abut on the two adjacent active areas in one of the plurality of spaces that is selected; and a contact separating insulation layer that is formed between the two conductive patterns in the one selected space. | 11-26-2015 |
20150340329 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - In some embodiments in accordance with the present disclosure, a semiconductor device having a semiconductor substrate is provided. A metal structure is disposed over the semiconductor substrate, and a post-passivation interconnect (PPI) is disposed over the metal structure. In addition, the upper surface of the PPI is configured to receive a bump thereon. In certain embodiments, the upper surface of the PPI for receiving the bump is substantially flat. A positioning member is formed over the PPI and configured to accommodate the bump. In some embodiments, the positioning member is configured to limit bump movement after the bump is disposed over the PPI so as to retain the bump at a predetermined position. | 11-26-2015 |
20150340341 | PACKAGE SYSTEMS - A package system includes a first substrate; and a second substrate electrically coupled with the first substrate. The package system further includes a semiconductor material between the first substrate and the second substrate. The semiconductor material includes a pad, and at least one guard ring surrounding the pad and spaced from the pad. The package system further includes a metallic material bonded to the semiconductor material, wherein the metallic material at least partially fills at least one opening in at least one of the first substrate or the second substrate. | 11-26-2015 |
20150348896 | CHIP ON FILM AND DISPLAY APPARATUS - The present disclosure of the present invention provides a chip on film and a display apparatus. The chip on film comprises a substrate having an input end lead and an output end lead, a region where the input end lead is located and a region where the output end lead is located are defined as a binding region, wherein the maximum thickness of the binding region is larger than the maximum thickness of other parts of the substrate than the binding region. | 12-03-2015 |
20150348898 | APPARATUS AND METHOD FOR PLACING STRESSORS WITHIN AN INTEGRATED CIRCUIT DEVICE TO MANAGE ELECTROMIGRATION FAILURES - A method for selecting locations within an integrated circuit device for placing stressors to manage electromigration failures includes calculating an electric current for an interconnect within the integrated circuit device and determining an electromigration stress profile for the interconnect based on the electric current. The method further includes determining an area on the interconnect for placing a stressor to alter the electromigration stress profile for the interconnect. | 12-03-2015 |
20150348938 | Apparatus and Methods for High-Density Chip Connectivity - An electronic circuit and method may include a first chip including first electronics and a first connector including multiple self-alignment features and conductive pads. A second chip may include second electronics and a second connector including multiple self-alignment features and conductive pads. The first chip and second chip may be indirectly horizontally aligned with one another and in electrical communication with one another via the first and second connectors. | 12-03-2015 |
20150348942 | FLEXIBLE STACK PACKAGES HAVING WING PORTIONS - A flexible stack package includes a first package and a second package. Each of the first and second packages includes a flexible layer, a chip embedded in the flexible layer, and a contact portion disposed on the chip to penetrate the flexible layer and exposed at a surface of the flexible layer. Each of the first and second packages includes a fixing portion and a wing portion. A first adhesion part is disposed between the fixing portion of the first package and the fixing portion of the second package to combine the first package with the second package. A first stretchable interconnector electrically connects or couples the contact portion of the first package to the contact portion of the second package. | 12-03-2015 |
20150348946 | SEMICONDUCTOR DEVICE - Provided is a small and thin semiconductor device while preventing contamination of a wire bonding terminal caused by creeping-up of a die bond. The semiconductor device includes: a first semiconductor chip having a main surface formed with electrodes; an extension part extended outward from a side end surface of the first semiconductor chip; a rewiring layer formed from the main surface of the first semiconductor chip to a first surface of the extension part; a connection terminal provided on the rewiring layer of the extension part; a die bond that fixes the first semiconductor chip and the extension part to a substrate; and in the extension part, a step outside the connection terminal. | 12-03-2015 |
20150348994 | ARRAY SUBSTRATE WIRING AND THE MANUFACTURING AND REPAIRING METHOD THEREOF - This disclosure relates to an array substrate wiring and manufacturing and repairing method thereof. The array substrate wiring comprises a first wiring formed on the substrate for transmitting electric signals; an insulating layer formed on the first wiring; a second wiring formed on the insulating layer, being opposite to the first wiring, the second wiring being in a hanging state and not transmitting electric signals. By means of such a double layer wiring structure, the holes produced in the insulating layer are blocked using the second wiring in the upper layer, such that the outside moisture cannot reach the first wiring via the holes in the insulating layer, thereby protecting the first wiring for transmitting electric signals from corrosion and scratch. | 12-03-2015 |
20150349242 | CONDUCTIVE PAD STRUCTURE AND METHOD OF FABRICATING THE SAME - A structure of a conductive pad is provided. The structure includes a first conductive layer. A first dielectric layer covers the first conductive layer. A first contact hole is disposed within the first dielectric layer. A second conductive layer fills in the first conductive hole and extends from the first conductive hole to a top surface of the first dielectric layer so that the second conductive layer forms a step profile. A second dielectric layer covers the first dielectric layer and the second conductive layer. A third conductive layer contacts and covers the step profile. | 12-03-2015 |
20150357280 | MEMORY CARD AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a memory card is disclosed. The memory card includes a substrate, a memory provided on the substrate, a controller provided on the substrate, and a first interconnect provided on the substrate. A distance between an edge of the substrate and the first interconnect is greater than or equal to 0.4 mm. The memory card further includes a resin covering the memory, the controller and the interconnect. The resin includes a first region and a second region, the amount of carbide in the first region is larger than the amount of carbide in the second region. | 12-10-2015 |
20150357281 | MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE AND METHOD FOR CREATING A LAYOUT THEREOF - A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity. | 12-10-2015 |
20150357298 | SEMICONDUCTOR CHIP, SEMICONDUCTOR PACKAGE HAVING THE SAME AND METHOD OF MANUFACTURING THE SAME - A semiconductor chip includes a semiconductor chip die having a first surface and a second surface facing the first surface, a connection pad on the first surface of the semiconductor chip die, and a redistribution pad arranged on the first surface of the semiconductor chip die and electrically connected to the connection pad and including an end portion having a concave-convex structure and extended to a lateral surface of the semiconductor chip die. | 12-10-2015 |
20150357302 | STRUCTURE AND METHOD FOR PACKAGE WARPAGE CONTROL - Presented herein is a package comprising a molding compound layer and an active device in the molding compound layer. A conductive via passes through the molding compound layer and is adjacent to the active device. A passivation layer is disposed on the molding compound layer. An active PPI is disposed on the passivation layer and is electrically connected to the conductive via. A dummy PPI is disposed on the passivation layer and is electrically isolated from the conductive via and the active device. | 12-10-2015 |
20150364406 | STACKABLE MOLDED MICROELECTRONIC PACKAGES - A microelectronic package has a microelectronic element overlying or mounted to a first surface of a substrate and substantially rigid conductive posts projecting above the first surface or projecting above a second surface of the substrate remote therefrom. Conductive elements exposed at a surface of the substrate opposite the surface above which the conductive posts project are electrically interconnected with the microelectronic element. An encapsulant overlies at least a portion of the microelectronic element and the surface of the substrate above which the conductive posts project, the encapsulant having a recess or a plurality of openings each permitting at least one electrical connection to be made to at least one conductive post. At least some conductive posts are electrically insulated from one another and adapted to simultaneously carry different electric potentials. In particular embodiments, the openings in the encapsulant at least partially expose conductive masses joined to posts, fully expose top surfaces of posts and partially expose edge surfaces of posts, or may only partially expose top surfaces of posts. | 12-17-2015 |
20150364422 | FAN OUT WAFER LEVEL PACKAGE USING SILICON BRIDGE - A semiconductor device package includes a logic die coupled to a memory die in a side-by-side configuration on a redistribution layer (e.g., the logic die and the memory die are substantially adjacent). A silicon bridge may be used to interconnect the logic die and the memory die. The silicon bridge may be positioned between the die and the redistribution layer. The silicon bridge and the redistribution layer may be coupled to the lower (active) surfaces of the logic die and the memory die. The package may be formed using a wafer level process that forms a plurality of packages simultaneously. | 12-17-2015 |
20150364430 | Semiconductor Device and Method of Forming a Dampening Structure to Improve Board Level Reliability - A semiconductor device has a semiconductor die. An encapsulant is deposited over the semiconductor die. A first insulating layer is formed over the semiconductor die and encapsulant. A plurality of first grooves is formed in the first insulating layer. A first conductive layer is formed over the first insulating layer and in the first grooves. A second insulating layer is formed over the first conductive layer. A plurality of second grooves is formed in the second insulating layer. A second conductive layer is formed in the second grooves. An interconnect structure is disposed over the second conductive layer and the first and second grooves. The first conductive layer disposed in the first grooves and the second conductive layer disposed in the second grooves form a dampening structure under the interconnect structure. The dampening structure improves the TCoB and BLR of the semiconductor device. | 12-17-2015 |
20150364434 | HYBRID BONDING WITH AIR-GAP STRUCTURE - A package component includes a surface dielectric layer having a first planar surface, and a metal pad in the surface dielectric layer. The metal pad includes a diffusion barrier layer that includes sidewall portions, and a metallic material encircled by the sidewall portions of the diffusion barrier layer. The metallic material has a second planar surface level with the first planar surface. An air gap extends from the second planar surface of the metallic material into the metallic material. An edge of the air gap is aligned to an edge of the metallic material. | 12-17-2015 |
20150364443 | Two Terminal Packaging - A solution for packaging a two terminal device, such as a light emitting diode, is provided. In one embodiment, a method of packaging a two terminal device includes: patterning a metal sheet to include a plurality of openings; bonding at least one two terminal device to the metal sheet, wherein a first opening corresponds to a distance between a first contact and a second contact of the at least one two terminal device; and cutting the metal sheet around each of the least one two terminal device, wherein the metal sheet forms a first electrode to the first contact and a second electrode to the second contact. | 12-17-2015 |
20150364493 | ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE - An array substrate comprises: a plurality of flexible cushions; and a plurality of signal lines, wherein the signal lines have ends respectively located on the flexible cushions. | 12-17-2015 |
20150371950 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE DESIGN METHOD, SEMICONDUCTOR DEVICE DESIGN APPARATUS, AND PROGRAM - A semiconductor device includes a multilayer interconnect layer formed over a substrate, an outer peripheral cell column disposed along an edge of the substrate in a plan view, the outer peripheral cell column including a first I/O cell, first and second inner peripheral cell columns formed at an inner peripheral side of the outer peripheral cell column, the first and second inner peripheral cell columns including a second I/O cell, and signal interconnects for forming an internal circuit of the semiconductor device, arranged between the first inner peripheral cell column and the second inner peripheral cell column. | 12-24-2015 |
20150371954 | ENHANCING BARRIER IN AIR GAP TECHNOLOGY - A semiconductor structure including a first metal line and a second metal line in a dielectric layer, the first metal line and the second metal line are adjacent and within the same dielectric level; an air gap structure in the dielectric layer and between the first metal line and the second metal line, wherein the air gap structure includes an air gap oxide layer and an air gap; and a barrier layer between the air gap structure and the first metal line, wherein the barrier layer is an oxidized metal layer. | 12-24-2015 |
20150371993 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a stacked structure including conductive layers and insulating layers stacked alternately with each other, first semiconductor patterns passing through the stacked structure and arranged in a first direction, second semiconductor patterns passing through the stacked structure and arranged in the first direction, wherein the second semiconductor patterns are adjacent to the first semiconductor patterns in a second direction crossing the first direction, air gaps located between the first semiconductor patterns and the second semiconductor patterns and extending in the first direction, and at least one blocking pattern passing through the stacked structure and filling portions of the air gaps. | 12-24-2015 |
20150372001 | MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and a method for manufacturing the same are disclosed. The semiconductor structure includes a first electrode layer, a second electrode layer and a dielectric layer between the first electrode layer and the second electrode layer. A width of the second electrode layer becomes larger in a direction away from the dielectric layer. | 12-24-2015 |
20150372010 | Thin Film Transistor Array Substrate and Method for Manufacturing the Same - The present invention proposes a TFT array substrate includes: a substrate; scan lines on the substrate; data lines intercrossing with the scan lines; a first insulating layer between the scan lines and the data lines; a second insulating layer on the first insulating layer and covering the data lines; a common electrode layer on the second insulating layer, comprising first holes located above the data lines. The first holes uncover the second insulating layer. The present invention decreases parasitic capacitance between the common electrode layer and data lines and between the common electrode layer and scan lines by decreasing overlaping sections between a common electrode layer and the data lines and between the common electrode layer and the scan lines. Therefore load of the data lines and the scan lines decreases, charge efficiency of the pixels increases, and display effect of an LCD panel is therefore improved. | 12-24-2015 |
20150379181 | Routing Standard Cell-Based Integrated Circuits - This disclosure describes a multi-height routing cell and utilization of the multi-height routing in an integrated circuit to reduce routing congestion in a standard cell design floorplan. The multi-height routing cell includes a bypass connection, or “tunnel,” that routes a signal through a non-routing layer and under an impeding power rail. The multi-height routing cell includes bypass connectors on both sides of the bypass connection that provide connection points for which to connect standard cells on opposite sides of the impeding power rail. As such, the multi-height routing cell provides a route underneath the impeding power rail and, in turn, reducing routing congestion in the standard cell design floorplan. | 12-31-2015 |
20150380341 | Three-Dimensional Semiconductor Device - A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips is disclosed. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device. | 12-31-2015 |
20150380355 | SELF-SIMILAR AND FRACTAL DESIGN FOR STRETCHABLE ELECTRONICS - The present invention provides electronic circuits, devices and device components including one or more stretchable components, such as stretchable electrical interconnects, electrodes and/or semiconductor components. Stretchability of some of the present systems is achieved via a materials level integration of stretchable metallic or semiconducting structures with soft, elastomeric materials in a configuration allowing for elastic deformations to occur in a repeatable and well-defined way. The stretchable device geometries and hard-soft materials integration approaches of the invention provide a combination of advance electronic function and compliant mechanics supporting a broad range of device applications including sensing, actuation, power storage and communications. | 12-31-2015 |
20150380359 | SEMICONDUCTOR PACKAGE INCLUDING MARKING LAYER - A semiconductor package includes at least one semiconductor chip, an encapsulation layer encapsulating the at least one semiconductor chip, a marking layer formed on the encapsulation layer, and a product information mark formed in the marking layer. | 12-31-2015 |
20150380377 | Multiple bond via arrays of different wire heights on a same substrate - Apparatuses relating generally to a substrate are disclosed. In such an apparatus, first wire bond wires (“first wires”) extend from a surface of the substrate. Second wire bond wires (“second wires”) extend from the surface of the substrate. The first wires and the second wires are external to the substrate. The first wires are disposed at least partially within the second wires. The first wires are of a first height. The second wires are of a second height greater than the first height for coupling of at least one electronic component to the first wires at least partially disposed within the second wires. | 12-31-2015 |
20150380386 | MICROELECTRONIC PACKAGES HAVING EMBEDDED SIDEWALL SUBSTRATES AND METHODS FOR THE PRODUCING THEREOF - Methods for fabricating microelectronic packages and microelectronic packages are provided. In one embodiment, the microelectronic package fabrication method includes producing a molded panel containing a sidewall substrate. The molded panel is singulated to produce a Fan-Out Wafer Level Package core including a molded body having a fan-out region in which the sidewall substrate is embedded. A side connect trace is printed or otherwise formed on a sidewall of the Fan-Out Wafer Level Package core and extends at least partially across the embedded sidewall substrate. | 12-31-2015 |
20150382443 | SUBSTRATE AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE - A substrate for a semiconductor package and a method for manufacturing a semiconductor package are disclosed. The substrate comprises a surface, and package unit regions arranged on the surface in a row direction to form a plurality of rows. The package unit regions of an n+1-th row are arranged offset in a row direction from the package unit regions of an n-th row. The method includes molding semiconductor chips and spaces between the substrate and the semiconductor chips on the package unit regions of the last row at substantially the same time. | 12-31-2015 |
20160004134 | ARRAY SUBSTRATE, METHOD FOR FABRICATING THE SAME AND DISPLAY DEVICE - An array substrate, a method for fabricating the same and a display device comprising the array substrate are disclosed. The array substrate includes: a base substrate; a plurality of gate lines (s | 01-07-2016 |
20160013050 | INTEGRATED CIRCUITS WITH AN INSULTATING LAYER AND METHODS FOR PRODUCING SUCH INTEGRATED CIRCUITS | 01-14-2016 |
20160013132 | SEMICONDUCTOR WIRING PATTERNS | 01-14-2016 |
20160013148 | Semiconductor Device and Method of Forming Wafer-Level Interconnect Structures with Advanced Dielectric Characteristics | 01-14-2016 |
20160013152 | Methods of Packaging Semiconductor Devices and Packaged Semiconductor Devices | 01-14-2016 |
20160014895 | SUBSTRATE STRUCTURE | 01-14-2016 |
20160020143 | Semiconductor Devices and Fabrication Methods With Reduced Topology And Reduced Word Line Stringer Residual Material - Provided are improved semiconductor memory devices and methods for manufacturing such semiconductor memory devices. A method may incorporate the formation of a first dielectric layer over buried oxide regions and the removal of such dielectric layer to prepare a substantially planar substrate for subsequent formation of word lines. The method may allow for the production of semiconductor memory devices of reduced size with reduced word line stringer residual material. | 01-21-2016 |
20160020166 | TRACE STRUCTURE OF FINE-PITCH PATTERN - A trace structure of fine-pitch pattern includes a connection portion, a first conductive wire portion and a second conductive wire portion, the first conductive wire portion comprises a first section and a second section connected to the first section, the first section connects to the connection portion, the second conductive wire portion comprises a third section and a fourth section connected to the third section, the third section connects to the connection portion, wherein an etching space closed on three sides is formed by the connection portion, the third section and the first section, a first spacing is defined between the third section and the first section, a second spacing is defined between the fourth section and the second section, wherein the first spacing is larger than the second spacing so as to make an metal layer within the etching space completely removed to avoid metal layer residues. | 01-21-2016 |
20160020167 | SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided. The semiconductor structure includes a conductive strip, a conductive layer, a first dielectric layer, and a second dielectric layer. The first dielectric layer is between the conductive strip and the conductive layer arranged in a crisscross manner. The second dielectric layer is different from the first dielectric layer. The second dielectric layer and the first dielectric layer are adjoined with the conductive strip in different positions on the same sidewall of the conductive strip. | 01-21-2016 |
20160020199 | SEMICONDUCTOR STRUCTURE WITH SPARE CELL REGION - A semiconductor structure includes a first spare cell region, a first conductive line and a second conductive line. The first spare cell region has a plurality of spare cells. The first conductive line is coupled between a first reference voltage and the plurality of spare cells, and is arranged for providing the first reference voltage to the plurality of spare cells of the first spare cell region. The second conductive line is coupled to a plurality of spare cells, and is arranged for providing a second reference voltage to the plurality of spare cells of the first spare cell region. | 01-21-2016 |
20160027749 | TEST CIRCUIT UNDER PAD - Aspects of the present invention relate to the arrangement of points of interconnection of integrated circuit die to the package in which they are enclosed. More specifically, aspects of the present invention pertain to an arrangement of bond pads over the active circuitry of an integrated circuit die, in order to permit a reduction in size of the die. An embodiment of the present invention may place a first bond pad over the active area of an integrated circuit, wherein the first bond pad is electrically coupled to a second bond pad outside of the active area of the integrated circuit. Production and delivery of the integrated circuit may proceed using the second bond pad during packaging, in parallel with the testing of packaging using the first bond pad. When processes related to the use of the first bond pad have been proven successful and sustainable, the second bond pad may be eliminated, resulting in a reduction of the size of the integrated circuit device. This approach may be employed to save die area, increasing the number of devices that may be produced on a silicon wafer, resulting in a reduction in device cost. The approach of the present invention works well whether the chip is pad or core limited. Although reference has been made to the used of this technique on a silicon wafer, an embodiment of the present invention may be employed in the fabrication of integrated circuit device using other materials as well, without departing from the spirit and scope of the present invention. | 01-28-2016 |
20160027770 | Methods for Linewidth Modification and Apparatus Implementing the Same - A linear-shaped core structure of a first material is formed on an underlying material. A layer of a second material is conformally deposited over the linear-shaped core structure and exposed portions of the underlying material. The layer of the second material is etched so as to leave a filament of the second material on each sidewall of the linear-shaped core structure, and so as to remove the second material from the underlying material. The linear-shaped core structure of the first material is removed so as to leave each filament of the second material on the underlying material. Each filament of the second material provides a mask for etching the underlying material. Each filament of the second material can be selectively etched further to adjust its size, and to correspondingly adjust a size of a feature to be formed in the underlying material. | 01-28-2016 |
20160027797 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - The present disclosure discloses an array substrate, manufacturing method thereof, and display device. The present disclosure belongs to the technical field of display technology, solves the technical problem of high impedance of the jumper joints of the array substrate in the prior art. The array substrate comprises: a first wiring and a second wiring located in a first metal layer; a first insulating layer covering the first metal layer, wherein the first insulating layer is provided with via holes corresponding to the first wiring and the second wiring respectively; and a jumper located in a second metal layer provided on the first insulating layer, wherein the jumper is connected with the first wiring and the second wiring through the via holes, thereby the first wiring and the second wiring being electrically conducted with each other through the jumper. The array substrate of the present disclosure can be used in liquid crystal television, liquid crystal display, mobile phone, tablet personal computer and other display devices. | 01-28-2016 |
20160035396 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes a plurality of wiring patterns of wiring lines disposed in parallel in a line-and-space pattern in a predetermined pitch and extend in a first direction in a first region, first bending patterns that extend pairs of the wiring lines in a second in a second region adjacent to the first region, second bending patterns extend the pairs of wiring lines in opposite directions along the orientation of the first direction in the second region, and dummy patterns separated from the two second bending patterns at a predetermined distance. | 02-04-2016 |
20160035665 | CIRCUIT ARRANGEMENT AND METHOD FOR MANUFACTURING THE SAME - A circuit arrangement is provided, which may include: an embedding package chip carrier; a first chip and a second chip arranged over the embedding package chip carrier, each of the first chip and the second chip comprising: a control terminal, a first controlled terminal, and a second controlled terminal, wherein the control terminal and the first controlled terminal are arranged on a first side of the chip, and wherein the second controlled terminal is arranged on a second side of the chip, wherein the second side is opposite the first side; wherein the first chip is arranged on the embedding package chip carrier such that its first side is facing towards the embedding package chip carrier; and wherein the second chip is arranged on the embedding package chip carrier such that its first side is facing away from the embedding package chip carrier. | 02-04-2016 |
20160035668 | AUTOMATED SHORT LENGHT WIRE SHAPE STRAPPING AND METHODS OF FABRICATING THE SAME - An automatic short length wire shape generation and strapping and method of fabricating such wires is provided. The method of manufacturing includes breaking of a wiring into adjacent short length wires which are below a maximum short length effect length. The adjacent short length wires are formed in a same wiring level of an integrated circuit. The method further includes forming a conductive strap in a single deposition process which overlaps and is in contact with the adjacent short length wires. | 02-04-2016 |
20160035699 | Power Semiconductor Package Having Vertically Stacked Driver IC - In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier. | 02-04-2016 |
20160035714 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of bit lines that intersect an active region on a substrate and extend in a first direction, a contact pad formed on the active region between adjacent bit lines, and a plurality of spacers disposed on sidewalls of the plurality of bit lines. An upper portion of the contact pad is interposed between adjacent spacers, and a lower portion of the contact pad has a width greater than a distance between adjacent spacers. | 02-04-2016 |
20160041316 | DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY APPARATUS - The present invention provides a display substrate and a manufacturing method thereof, and a display apparatus. The display substrate comprises a base substrate and a black matrix provided above the base substrate, the black matrix comprises a first black matrix and a second black matrix, the first black matrix and the second black matrix are intersected with each other, a photo spacer is provided over the first black matrix, wherein, the first black matrix comprises a non-spacer part not provided correspondingly to the photo spacer and a spacer part provided correspondingly to the photo spacer, and the non-spacer part has a line width smaller than width of the spacer part. In the present invention, the line width of the non-spacer part is reduced, the first black matrix will have a reduced area, that is, shading area of the first black matrix is reduced, and transmittance of the manufactured product is improved. | 02-11-2016 |
20160041444 | ACTIVE MATRIX SUBSTRATE AND DISPLAY DEVICE - An active matrix substrate includes: a first inorganic insulating film (first insulating layer) provided on a gate insulating film (insulating film); an organic insulating film (second insulating layer) provided on the first inorganic insulating film and having a thermal expansion coefficient different from that of the first inorganic insulating film; and a second inorganic insulating film (third insulating layer) provided in such a manner as to cover the organic insulating film and partially contacting the first inorganic insulating film. A notch is provided above the gate insulating film and in a portion of the second inorganic insulating film where the organic insulating film is not present. | 02-11-2016 |
20160042978 | DEVICE AND METHOD FOR LOCALIZED UNDERFILL - A device and method for localizing underfill includes a substrate, a plurality of dies, and underfill material. The substrate includes a plurality of contacts and a plurality of cavities separated by a plurality of mesas. The plurality of dies is mounted to the substrate using the plurality of contacts. The underfill material is located between the substrate and the dies. The underfill material is localized into a plurality of regions using the mesas. Each of the contacts is located in a respective one of the cavities. In some embodiments, the substrate further includes a plurality of channels interconnecting the cavities. In some embodiments, the substrate further includes a plurality of intra-cavity mesas for further localizing the underfill material. In some embodiments, outer edges of a first one of the dies rest on first mesas located on edges of a first one of the cavities. | 02-11-2016 |
20160043031 | SEMICONDUCTOR DEVICE - One semiconductor device includes first to fourth wirings disposed within a prescribed interval in a first direction, extending in a second direction, and arranged at a first pitch in the first direction, first to third lead-out wirings disposed within the prescribed interval in the first direction, extending in the second direction, and arranged at a second pitch in the first direction, a bridge part disposed between the first lead-out wiring, and the second lead-out wiring, and connected to the first lead-out wiring, and the second lead-out wiring, a first contact part in contact with at least one part of the bridge part, and a second contact part in contact with the third lead-out wiring. One of either the first lead-out wiring, or the second lead-out wiring is connected to the second wiring, and the third lead-out wiring is connected to the fourth wiring. | 02-11-2016 |
20160043047 | Semiconductor Device and Method of Forming Double-Sided Fan-Out Wafer Level Package - A semiconductor device comprises a first semiconductor package including a conductive layer. A substrate including an interconnect structure is disposed over the conductive layer. The interconnect structure of the substrate with the conductive layer of the first semiconductor package are self-aligned. A plurality of openings is formed in the substrate. An adhesive is disposed between the substrate and the first semiconductor package and in the openings of the substrate. A redistribution layer (RDL) is formed over the first semiconductor package opposite the substrate. A pitch of the substrate is different from a pitch of the RDL. The adhesive extends to the interconnect structure of the substrate. A second semiconductor package is disposed over the substrate and the first semiconductor package. | 02-11-2016 |
20160043104 | DISPLAY PANEL - A display panel including first and second pixel structures and a light shielding pattern layer is provided. The first pixel structure includes a first pixel electrode including first pixel electrode bars, wherein a first maximum spacing is formed between any two adjacent first pixel electrode bars of the first pixel structure. The second pixel structure includes a second pixel electrode including second pixel electrode bars, wherein a second maximum spacing which is larger than the first maximum spacing is formed between two adjacent second pixel electrode bars of the second pixel structure. The light shielding pattern layer has first and second light shielding portions. The area of the second light shielding portion is larger than the area of the first light shielding portion. The first pixel electrode is close to the second light shielding portion and the second pixel electrode is away from the second light shielding portion. | 02-11-2016 |
20160043129 | Stress Release Layout and Associated Methods and Devices - An embodiment semiconductor device includes a substrate such as a silicon or silicon-containing film, a pixel array supported by the substrate, and a metal stress release feature arranged around a periphery of the pixel array. The metal stress release feature may be formed from metal strips or discrete metal elements. The metal stress release feature may be arranged in a stress release pattern that uses a single line or a plurality of lines. The metal stress release pattern may also use metal corner elements at ends of the lines. | 02-11-2016 |
20160049372 | Ceramic substrate, package substrate, semiconductor chip package component and manufacturing method thereof - A method for manufacturing a ceramic substrate is characterized in using a preformed trench, a patterned protective layer and a sand blasting process to manufacture a cavity in a ceramic substrate and control the cavity size and shape of the ceramic substrate. The ceramic substrate is collocated with a base substrate to form a package substrate for packaging a semiconductor chip. The manufacturing method set forth above can lower the manufacturing cost and raise the accuracy of the size and shape of the cavity of the ceramic substrate. The abovementioned method can reduce the fabrication cost and increase the precision of the shape and size of a ceramic substrate. | 02-18-2016 |
20160056206 | 3-D PLANES MEMORY DEVICE - The present invention is a means and a method for manufacturing large three dimensional memory arrays. The present invention is a means and a method for addressing the WL and BL resistance by creating arrays having not only large plane conductors for each of the memory layers (WLs) but also for the opposite polarity common layer (BL). The present invention is also a means and a method to form via interconnections between the substrate logic and the respective layers of a multidimensional array. The present invention is also a way to operate an array in which the select device is unipolar but the array is above to be operated in a bipolar way. This facilitates a bipolar operation for memory cell technologies such as Resistive RAM (e.g., RRAM, ReRAM and Memresistors). | 02-25-2016 |
20160062201 | DISPLAY APPARATUS - A display apparatus includes gate lines configured to receive gate signals, data lines arranged to cross the gate lines and configured to receive data voltages, and pixels grouped into first pixel groups and second pixel groups and connected to the gate lines and the data lines. The gate signals are configured to be applied to the gate lines in a predetermined order while skipping at least one gate line without being sequentially and consecutively applied to two gate lines adjacent to each other among the gate lines. | 03-03-2016 |
20160064309 | SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME - According to an exemplary embodiment, a semiconductor package is provided. The semiconductor package includes: a chip having a plurality of joint pads; a component having a plurality of metal caps on one side and having a grinded surface on the other side, wherein the metal caps are in contact with the joint pads of the chip. | 03-03-2016 |
20160064316 | PACKAGE SUBSTRATE WITH IMPROVED RELIABILITY - A packaged semiconductor device having a package substrate that includes a plurality of electrical contacts on a first major surface and a die positioned on a second major surface. Each of the plurality of electrical contacts includes a perimeter portion. A first subset of the electrical contacts have more than fifty percent of the perimeter portion bounded by a solder mask. A second subset of the electrical contacts have less than fifty percent of the perimeter portion bounded by a solder mask. The die is positioned over only the first subset of the electrical contacts. | 03-03-2016 |
20160064320 | COUPLING OF AN INTERPOSER TO A PACKAGE SUBSTRATE - An integrated circuit chip stack and a method for forming the same in which bond pads of an interposer are directly bonded to bond pads of a package substrate using only pre-solder. The interposer can have a bond pad pitch of less than 150 micrometers. The interposer can be an organic interposer. The pro-solder can be melted to make contact with the bond pads of the package substrate and the interposer. After solidifying, the pre-solder can form an electrical connection between a bond pad of the interposer and a bond pad of the package substrate. | 03-03-2016 |
20160064340 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device structure includes a first substrate having a first surface and a second surface opposite to the first surface, a conductive pad at the first surface of the first substrate, and a connector overlying the conductive pad, wherein the connector is configured for electrically connecting with a conductive land of a second substrate, wherein a geometric center of the connector is deviated from a geometric center of the conductive pad and a geometric center of the conductive land. | 03-03-2016 |
20160064345 | Word Line Hook Up with Protected Air Gap - A method of forming a semiconductor device includes forming a plurality of word lines separated by air gaps with contact pad structures connected to the word lines, and forming a dummy structure directly opposite an air gap between neighboring word lines. Subsequently, the contact pad structures are cut into individual contact pads by a contact pad cut that intersects the dummy structure. | 03-03-2016 |
20160064366 | SEMICONDUCTOR MEMORY DEVICE INCLUDING OUTPUT BUFFER - A semiconductor module includes a module substrate, a line pattern provided to the module substrate, first and second semiconductor chips on the module substrate and coupled to the line pattern, and a termination resister on the module substrate and coupled to the line pattern, the termination resistor being located between the first and second semiconductor chips. | 03-03-2016 |
20160071790 | WIRING STRUCTURES - Wiring structures with dummy metal features and methods of manufacture are disclosed. A structure includes a metal wiring structure, and dummy metal features in electrical and direct physical contact with the metal wiring structure in a same plane as the metal wiring structure. The dummy metal features do not change a resistance of the metal wiring structure and are remote from other structures. | 03-10-2016 |
20160071792 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device according to the present embodiment includes a plurality of wires. A plurality of wire drawing pads are provided correspondingly to the wires and electrically connecting a plurality of contacts to the wires, respectively. First space portions widen toward a first direction from the wires to the wire drawing pads and are located between adjacent ones of the wire drawing pads in a connection region between the wires and the wire drawing pads. Second space portions are provided at edge portions of the wire drawing pads. Air gaps or insulating layers are provided in the first space portions and the second space portions. | 03-10-2016 |
20160071821 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a substrate having an insulating resin and a metal pattern provided on the insulating resin; a mounted component mounted on the metal pattern; and an epoxy resin encapsulating the metal pattern and the mounted component, wherein a slit is provided in the metal pattern around the mounted component, and the insulating resin exposed from the metal pattern and the epoxy resin are brought into intimate contact with each other in the slit. | 03-10-2016 |
20160071829 | Packages and Methods of Forming Packages - Various packages and methods of forming packages are discussed. According to an embodiment, a package includes a processor die at least laterally encapsulated by an encapsulant, a memory die at least laterally encapsulated by the encapsulant, and a redistribution structure on the encapsulant. The processor die is communicatively coupled to the memory die through the redistribution structure. According to further embodiments, the memory die can include memory that is a cache of the processor die, and the memory die can comprise dynamic random access memory (DRAM). | 03-10-2016 |
20160079087 | METHOD OF PROCESSING A SEMICONDUCTOR DEVICE AND CHIP PACKAGE - In various embodiments, a method of processing a semiconductor device may include providing a semiconductor device comprising a contact pad and a polymer layer; and subjecting at least a part of the contact pad and the polymer layer to a plasma comprising ammonia. | 03-17-2016 |
20160079110 | SEMICONDUCTOR PACKAGE, CARRIER STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor package is provided, which includes: a carrier; a frame having a plurality of openings, wherein the frame is bonded to the carrier and made of a material different from that of the carrier; a plurality of electronic elements disposed in the openings of the frame, respectively; an encapsulant formed in the openings of the frame for encapsulating the electronic elements; and a circuit layer formed on and electrically connected to the electronic elements. By accurately controlling the size of the openings of the frame, the present invention increases the accuracy of positioning of the electronic elements so as to improve the product yield in subsequent processes. | 03-17-2016 |
20160079157 | SEMICONDUCTOR PACKAGE STRUCTURE - The present disclosure relates to a semiconductor package structure, including a die and a package substrate. The die includes a semiconductor substrate, multiple interconnect metal layers, and at least one inter-level dielectric disposed between ones of the interconnect metal layers. Each inter-level dielectric is formed of a low k material. An outermost interconnect metal layer has multiple first conductive segments exposed from a surface of the inter-level dielectric. The package substrate includes a substrate body and multiple second conductive segments exposed from a surface of the substrate body. The second conductive segments are electrically connected to the first conductive segments. | 03-17-2016 |
20160079159 | Enforcement of Semiconductor Structure Regularity for Localized Transistors and Interconnect - A global placement grating (GPG) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the GPG is positioned to intersect each contact that interfaces with the chip level. A number of subgratings are defined. Each subgrating is a set of equally spaced virtual lines of the GPG that supports a common layout shape run length thereon. The layout for the chip level is partitioned into subgrating regions. Each subgrating region has any one of the defined subgratings allocated thereto. Layout shapes placed within a given subgrating region in the chip level are placed in accordance with the subgrating allocated to the given subgrating region. Non-standard layout shape spacings at subgrating region boundaries can be mitigated by layout shape stretching, layout shape insertion, and/or subresolution shape insertion, or can be allowed to exist in the final layout. | 03-17-2016 |
20160079178 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package including a marking film and a method of fabricating the same are provided wherein a marking film including a thermoreactive layer may be applied to a molding layer to protect a semiconductor chip under the molding layer and to efficiently perform a marking process. The thickness of the molding layer may thereby be reduced so the entire thickness of the semiconductor package may be reduced. Also, it is possible to prevent warpage of the semiconductor package through the marking film, provide the surface of the semiconductor package with gloss and freely adjust the color of the surface of the semiconductor package. | 03-17-2016 |
20160079191 | PACKAGE WITH UBM AND METHODS OF FORMING - Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, a dummy pattern, a second dielectric layer, and an external connector on the connector support metallization. The redistribution structure comprises a first dielectric layer having a first surface disposed distally from the encapsulant and the integrated circuit die. The dummy pattern is on the first surface of the first dielectric layer and around the connector support metallization. The second dielectric layer is on the first surface of the first dielectric layer and on at least a portion of the dummy pattern. The second dielectric layer does not contact the connector support metallization. | 03-17-2016 |
20160079210 | SEMICONDUCTOR PACKAGES INCLUDING THROUGH ELECTRODES AND METHODS OF MANUFACTURING THE SAME - A semiconductor package includes a substrate and a plurality of semiconductor chips stacked on the substrate. Each of the semiconductor chips has a front surface, a rear surface opposite to the front surface, a sidewall surface connecting the front surface to the rear surface, a vertical through electrode extending from the front surface toward the rear surface with a predetermined depth, and a horizontal through electrode laterally extending from the sidewall surface to be connected to the vertical through electrode. At least one connection member is disposed on the sidewall surfaces of the semiconductor chips to connect the horizontal through electrodes of the semiconductor chips to each other. Related methods are also provided. | 03-17-2016 |
20160079280 | DISPLAY APPARATUS - A display apparatus including a display area on a substrate, the display area including at least a display device; and a non-display area adjacent to the display area, wherein the non-display area includes a pull-in area, the pull-in area includes a wiring unit that includes a plurality of wires electrically connected to the display device of the display area, and a conductive pattern unit that is electrically connected to the display device and that includes at least one area separated from and overlapping the wiring unit, and the plurality of wires of the wiring unit are not arranged in parallel such that respective angles between an edge of the display area and at least two of the plurality of wires are different. | 03-17-2016 |
20160086848 | Conductive Line Structure with Openings - Wide and narrow mandrels that are used to form sidewall spacers for patterning are formed in a sacrificial layer with openings in wide mandrels near sides of the wide mandrels. Sidewall spacers are formed on the sides of mandrels and the sacrificial layer is removed. The sidewall spacers are then used for patterning of underlying layers. | 03-24-2016 |
20160086882 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a device isolation in a trench that defines first to third active patterns that are spaced apart from each other and having a long axis parallel to a first direction, first and second word lines extending in a second direction perpendicular to the first direction, a bit line, and a source line. The first and second active patterns are arranged in the second direction to constitute a column. The third active pattern is at a side of the column. The first word line intersects the first and second active patterns. The second word line intersects the third active pattern. When viewed from a plan view, the bit line extends in the first direction between the first and third active patterns, and the source line extends in the first direction between the second and third active patterns. | 03-24-2016 |
20160086884 | MITIGATING ELECTROMIGRATION EFFECTS USING PARALLEL PILLARS - Systems, methods, and other embodiments associated with an integrated circuit that includes a plurality of parallel pillar structures is described. In one embodiment, an integrated circuit includes a series of layers. The series of layers include a plurality of pillar metals in each of the series of layers. Pillars within each of the series of layers are oriented to be parallel. Pillars in adjacent layers are aligned to be perpendicular. Each of the plurality of pillar metals is a rectangular segment of metal. The plurality of pillar metals form a reconvergent mesh grid. The series of layers includes a plurality of vias connecting the plurality of parallel pillar metals between the series of layers. Vias of the plurality of vias are located at intersections in the reconvergent mesh grid. | 03-24-2016 |
20160086909 | METHODS AND APPARATUSES FOR SHAPING AND LOOPING BONDING WIRES THAT SERVE AS STRETCHABLE AND BENDABLE INTERCONNECTS - A capillary tool for use in feeding, bending, and attaching a bonding wire between a pair of bond pads includes a body and a heating element. The body has an internal tube that extends from a first surface of the capillary tool to a second surface of the capillary tool. In some implementations, the internal tube has a portion with a generally helical shape that includes at least a portion of one complete revolution about a central axis of the body. The heating element is coupled to the body to provide a heat affected zone along a portion of the internal tube that heats the bonding wire as the bonding wire is fed through the internal tube. | 03-24-2016 |
20160086930 | FAN-OUT WAFER LEVEL PACKAGE CONTAINING BACK-TO-BACK EMBEDDED MICROELECTRONIC COMPONENTS AND ASSEMBLY METHOD THEREFOR - Fan-Out Wafer Level Packages (FO-WLPs) include double-sided molded package bodies in which first and second layers of components are embedded in a back-to-back relationship. In one embodiment, the FO-WLP fabrication method includes positioning a first microelectronic component carried by a first temporary substrate in a back-to-back relationship with a second microelectronic component carried by a second temporary substrate. The first and second components are overmolded while positioned in the back-to-back relationship to produce a double-sided molded package body. The first temporary substrate is then removed to expose a first principal surface of the package body at which the first component is exposed, and the second temporary substrate is likewise removed to expose a second, opposing principal surface of the package body at which the second component is exposed. | 03-24-2016 |
20160086977 | DISPLAY DEVICE - A display device includes a first substrate having an active area, a circuit area extending outwardly from the active area, and a cell seal area extending outwardly from the circuit area, a second substrate covering the first substrate, a sealing part between the first substrate and the second substrate, the sealing part covering at least a portion of the circuit area, a wiring part in the circuit area of the first substrate and electrically connected to elements in the active area of the first substrate, the wiring part including at least one level-difference compensation part, and a stepped part between the sealing part and at least a portion of the wiring part, the at least one level-difference compensation part of the wiring part being adjacent to the stepped part. | 03-24-2016 |
20160093533 | SUBSTRATE FOR ALTERNATIVE SEMICONDUCTOR DIE CONFIGURATIONS - A method of assembling semiconductor devices with semiconductor dies of alternative different configurations uses the same substrate panel. The dies of the selected configuration are placed in an array, mounted, and connected to internal electrical contact pads on a first face of the panel using main fiducial markings and an array of subsidiary fiducial markings corresponding universally to arrays of semiconductor dies of the different alternative configurations. The pitch of the subsidiary fiducial markings is equal to the spacing between adjacent rows of the internal electrical contact pads on the panel and is a sub-multiple of the pitch of the array of dies. | 03-31-2016 |
20160099172 | LOW-K INTERCONNECT STRUCTURE AND FORMING METHOD THEREOF - A method of forming low-k interconnect structure is disclosed, which comprises: providing at least one protruding structure on a substrate traversing between a first connection region to a second connection region defined thereon; performing anodic oxidation on the substrate having the protruding structure; forming one or more nanowire interconnect in the protruding structure traversing between the first connection region and the second connection region; the nanowire interconnect being surrounded by a dielectric layer formed during the anodic oxidation. | 04-07-2016 |
20160099203 | SEMICONDUCTOR STACK PACKAGES - A semiconductor stack package includes a printed circuit board (PCB), a first semiconductor chip, and a second semiconductor chip. The first and second semiconductor chips are disposed side-by-side on a first surface of the PCB to be spaced apart from each other. Each of the first and second semiconductor chips includes a command/address (CA) chip pad and a data input/output (DQ) chip pad. The CA chip pad of the first semiconductor chip is electrically coupled to the CA chip pad of the second semiconductor chip through a CA bonding wire. | 04-07-2016 |
20160099204 | PACKAGE SUBSTRATE, PACKAGE STRUCTURE, AND METHODS OF FABRICATING THE SAME - A package structure is provided, including: a board having a plurality of conductive traces; a plurality of conductive pads formed on the board and each having a height greater than a height of each of the conductive traces; and an electronic component disposed on and electrically connected to the conductive pads via a plurality of conductive elements, wherein at least one of the conductive traces is positioned in proximity of at least one of the conductive pads. Therefore, the conductive elements are prevented from being in contact with the conductive traces, and the problem that the conductive pads and the conductive traces are shorted is solved. The present invention further provides a method for fabricating the packaging substrate. | 04-07-2016 |
20160099221 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a semiconductive substrate, a post passivation interconnect (PPI) and a polymer layer. The PPI is disposed above the semiconductive substrate and includes a landing area for receiving a conductor. The polymer layer is on the PPI, wherein the conductor is necking a turning point so as to include an oval portion being substantially surrounded by the polymer layer, and the oval portion of the conductor is disposed on the landing area of the PPI. | 04-07-2016 |
20160099226 | CIRCUIT SUBSTRATE INTERCONNECT - A packaged integrated circuit (IC) includes a substrate including a first substrate pad disposed on a first side of the substrate, an IC die disposed on the first side of the substrate, and a first insulating layer molded over the IC die and the substrate. The IC die includes a first die pad on a side of the die opposite from a side of the die adjacent to the first side of the substrate. The first insulating layer includes a first channel extending through the first insulating layer to the first substrate pad, a second channel extending through the first insulating layer to the first die pad, conductive paste filling the first channel and in contact with the first substrate pad, and conductive paste filling the second channel and in contact with the die pad. | 04-07-2016 |
20160104652 | PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME - A method for fabricating a package structure is provided, which includes the steps of: forming a wiring layer on a carrier by electroplating; disposing at least one electronic component on the wiring layer; forming on the carrier an insulating layer that encapsulates the wiring layer and the electronic component; and removing the carrier. With the single wiring layer having one surface electrically connected the at least one electronic component and the other surface electrically connected to a plurality of conductive elements, the package structure has a signal transmission path that is shortened. | 04-14-2016 |
20160104653 | ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING SAME - In a substrate, at least one lateral surface between one surface and another surface is a cut surface that is cut together with mold resin. The mold resin, which is cut together with the substrate, is provided with a surface that is flush with the cut surface. A portion of the mold resin constituting the surface flush with the cut surface has a surface that is joined to the surface flush with the cut surface and parallel to the one surface of the substrate; this portion is thinner than a portion that seals electronic parts. Consequently, the mold resin is cut with a dicing blade brought into contact with a surface parallel to the one surface of the substrate. | 04-14-2016 |
20160104684 | SEMICONDUCTOR MEMORY DEVICE HAVING PADS - A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power. | 04-14-2016 |
20160104692 | DISPLAY DEVICE - A display device includes a panel substrate including a pad region, and a COF (Chip On Film) including a wire region, the wire region including a plurality of wires connected to the pad region of the panel substrate, wherein the plurality of wires in the wire region is arranged into a plurality of sections, intervals between wires within each section being different from intervals between wires within an adjacent section, and at least one of the plurality of sections including a plurality of wires at a fixed interval. | 04-14-2016 |
20160111366 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME - A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate having a trench, a stacked strip structure formed in the trench, and at least a conductive structure. The stacked strip structure includes a plurality of interlaced conductive strips and insulating strips. Each of the conductive strips has a horizontal conductive segment and two vertical conductive segments connected to the corresponding horizontal conductive segment. Each of the insulating strips has a horizontal insulating segment and two vertical insulating segments. The conductive structure is electrically connected to at least one of the conductive strips. The stacked strip structure has a horizontal stacked portion corresponding to the horizontal conductive segments and two vertical stacked portions corresponding to the vertical conductive segments, wherein a width of the vertical stacked portions is larger than a thickness of the horizontal stacked portion. | 04-21-2016 |
20160111367 | POWER SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING THE SAME - A power semiconductor module may include a first device and a second device spaced apart from the first device at a predetermined interval. A first assembling terminal is fixedly disposed between the first device and the second device to be a first connection terminal. A second assembling terminal is fixedly assembled to contact outer surfaces of the first device and the second device to be a second connection terminal. | 04-21-2016 |
20160111378 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD OF THE SAME - The present disclosure provides a method for manufacturing a semiconductor package. The method includes (1) determining a die warpage value under a predetermined temperature range; (2) determining a difference between a density of a top metal and a density of a bottom metal of a substrate according to the die warpage value; and (3) joining the die and the substrate under the predetermined temperature range. The top metal includes all metal layers overlying a middle layer, and the bottom metal includes all metal layers underlying the middle layer. The middle layer includes a core or a metal layer. | 04-21-2016 |
20160111406 | TOP-SIDE INTERCONNECTION SUBSTRATE FOR DIE-TO-DIE INTERCONNECTION - At least one method, apparatus and system disclosed involves a multi-die integrated circuit device. A first substrate portion having a first height is formed. A first device over the first substrate portion is formed. A second substrate portion having a second height is formed. A second device is formed over the second substrate portion. An interconnect substrate feature is formed above the first and second devices. The interconnect substrate is configured to accommodate a plurality of interconnect lines electrically coupling the first and second devices. | 04-21-2016 |
20160118292 | INTEGRATED CIRCUITS WITH AN AIR GAP AND METHODS OF PRODUCING THE SAME - Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming an interconnect trench in a dielectric layer, and forming a conformal barrier layer overlying the dielectric layer and within the interconnect trench. A barrier spacer is formed by removing the conformal barrier layer from an interconnect trench bottom, and an interconnect is formed within the interconnect trench after forming the barrier spacer. An air gap trench is formed in the dielectric layer adjacent to the barrier spacer, and a top cap is formed overlying the interconnect and the air gap trench, where the top cap bridges the air gap trench to produce an air gap in the air gap trench. | 04-28-2016 |
20160118313 | FAN-OUT WAFER LEVEL PACKAGES CONTAINING EMBEDDED GROUND PLANE INTERCONNECT STRUCTURES AND METHODS FOR THE FABRICATION THEREOF - Fan-Out Wafer Level Packages (FO-WLPs) and methods for fabricating FO-WLPs containing Embedded Ground Planes (EGPs) and backside EGP interconnect structures are provided. In one embodiment, the method includes electrically coupling an EGP to a backside terminal of a first microelectronic device through a backside EGP interconnect structure. A molded package body is formed around the first microelectronic device, the EGP, and the EGP interconnect structure. The molded package body has a frontside at which the EGP is exposed. One or more Redistribution Layers are formed over the frontside of the molded packaged body and contain at least one interconnect line electrically coupled to the backside contact through the EGP and the backside EGP interconnect structure. | 04-28-2016 |
20160118332 | Semiconductor Device and Method of Fabricating 3D Package With Short Cycle Time and High Yield - A method of making a semiconductor device comprises the steps of providing a first manufacturing line, providing a second manufacturing line, and forming a first redistribution interconnect structure using the first manufacturing line while simultaneously forming a second redistribution interconnect structure using the second manufacturing line. The method further includes the steps of testing a first unit of the first redistribution interconnect structure to determine a first known good unit (KGU), disposing a known good semiconductor die (KGD) over the first KGU of the first redistribution interconnect structure, testing a unit of the second redistribution interconnect structure to determine a second known good unit (KGU, and disposing the second KGU of the second redistribution interconnect structure over the first KGU of the first redistribution interconnect structure and the KGD. A resolution of the second manufacturing line is greater than a resolution of the first manufacturing line. | 04-28-2016 |
20160118333 | Semiconductor Device and Method of Fabricating 3D Package with Short Cycle Time and High Yield - A method of making a semiconductor device comprising the steps of providing a first manufacturing line, providing a second manufacturing line, and forming a first redistribution interconnect structure using the first manufacturing line while forming a second redistribution interconnect structure using the second manufacturing line. The method further includes the steps of testing a first unit of the first redistribution interconnect structure to determine a first known good unit (KGU), disposing a known good semiconductor die (KGD) over the first KGU of the first redistribution interconnect structure, and dicing the first KGU and KGD from the first redistribution interconnect structure. The method further includes the steps of testing a unit of the second redistribution interconnect structure to determine a second KGU of the second redistribution interconnect structure and disposing first KGU of the first redistribution interconnect structure and the KGD over the second KGU of the second redistribution interconnect structure. | 04-28-2016 |
20160118334 | Interconnect Structure and Method of Forming The Same - An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a low-k (LK) dielectric layer over a substrate; a first conductive feature and a second conductive feature in the LK dielectric layer; a first spacer along a first sidewall of the first conductive feature; a second spacer along a second sidewall of the second conductive feature, wherein the second sidewall of the second conductive feature faces the first sidewall of the first conductive feature; an air gap between the first spacer and the second spacer; and a third conductive feature over the first conductive feature, wherein the third conductive feature is connected to the first conductive feature. | 04-28-2016 |
20160118355 | PLANAR PASSIVATION FOR PADS - Devices and methods for forming a device are presented. The method includes providing a substrate having circuit component and a dielectric layer over the substrate. The dielectric layer includes a plurality of inter level dielectric (ILD) layers and the uppermost dielectric layer includes at least one interconnect. A pad dielectric layer is provided over the uppermost ILD layer. A pad interconnect for receiving a wire bond is formed in the pad dielectric layer. The pad interconnect is coupled to the at least one interconnect of the uppermost ILD layer. A top surface of the pad dielectric layer is substantially coplanar with a top surface of the pad interconnect. A passivation layer is formed over the pad dielectric layer. | 04-28-2016 |
20160118357 | PACKAGED SEMICONDUCTOR DEVICE WITH INTERIOR POLYGONAL PADS - Embodiments of a packaged semiconductor device with interior polygon pads are disclosed. One embodiment includes a semiconductor chip and a package structure defining a rectangular boundary and having a bottom surface that includes interior polygonal pads exposed at the bottom surface of the package structure and located on a centerline of the bottom surface of the package structure and edge polygonal pads exposed at the bottom surface of the package structure, located at an edge of the rectangular boundary, and including one edge polygonal pad in the vicinity of each corner of the rectangular boundary. The interior polygonal pads are configured such that a line running between at least one vertex of each of the interior polygonal pads is parallel to an edge of the rectangular boundary of the package structure. | 04-28-2016 |
20160118366 | Semiconductor Packages Including Heat Dissipation Parts - A semiconductor package includes a lower package with a lower substrate and a lower semiconductor chip. A heat dissipation part is provided adjacent to a side of the lower package and covers a portion of the lower semiconductor chip, and an upper package is on the lower package and is laterally spaced apart from the heat dissipation part. | 04-28-2016 |
20160118371 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a package substrate, a first semiconductor chip having a plurality of first connection terminals disposed on a bottom surface thereof, and a second semiconductor chip having a plurality of second connection terminals disposed on a top surface thereof. The first semiconductor chip is stacked on the package substrate so that a first group of connection terminals among the plurality of first connection terminals are combined with the package substrate. The second semiconductor chip is disposed so that the plurality of second connection terminals are combined with a second group of connection terminals among the plurality of first connection terminals. | 04-28-2016 |
20160126136 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes a low-adhesion film, a pair of substrates, and a metal electrode. The low-adhesion film has lower adhesion to metal than a semiconductor oxide film. The pair of substrates is provided with the low-adhesion film interposed therebetween. The metal electrode passes through the low-adhesion film and connects the pair of substrates, and includes, between the pair of substrates, a part thinner than parts embedded in the pair of substrates. A portion of the metal electrode embedded in one substrate is provided with a gap interposed between the portion and the low-adhesion film on the other substrate. | 05-05-2016 |
20160126174 | SUBSTRATES AND METHODS OF MANUFACTURE - An interposer ( | 05-05-2016 |
20160126182 | DUMMY PATTERNS - A semiconductor layout pattern includes a device layout pattern, a plurality of rectangular first dummy patterns having a first size, a plurality of rectangular second dummy patterns having second sizes, and a plurality of bar-like third dummy patterns having varied third sizes. The pattern densities are smartly equalized by positioning the second dummy patterns. | 05-05-2016 |
20160126201 | DUAL LAYER STACK FOR CONTACT FORMATION - A semiconductor structures includes a contact fabricated utilizing a multi material trench-layer. The multi material trench layer is utilized to form a contact trench and the contact trench is utilized to form the contact therein. The trench-layer includes a lower barrier trench layer and an upper photoprocessing layer. The photoprocessing layer is utilized pattern and form contact trench. The barrier layer protects an electroplating conductive layer utilized in forming the contact from corrosion that may occur during the removal of the photoprocessing layer. | 05-05-2016 |
20160126226 | Integrated Fan-Out Structure and Method - A semiconductor package comprises a top package and a bottom package with fan-out interconnect structures. A plurality of inter-package connectors electrically connect the top package and the bottom package, and are located near a perimeter of the semiconductor package. A first material is located in a space delimited by a lower surface of the top package, an upper surface of the bottom package, and the inner-most inter-package connectors of the semiconductor package, wherein the first material partially fills the space. A second material different from the first material encapsulates the inter-package connectors. | 05-05-2016 |
20160126227 | Method for Attaching a Semiconductor Die to a Carrier - A method for fabricating an electronic device includes providing a first semiconductor chip and a second semiconductor chip. The first semiconductor chip has a first semiconductor die and a first solder interconnect layer applied to a main face of the first semiconductor die. The second semiconductor chip has a second semiconductor die, an insulating layer applied to a main face of the second semiconductor die, and a second solder interconnect layer applied to the insulating layer. The method further includes attaching the first semiconductor chip with the first solder interconnect layer to a first carrier and attaching the second semiconductor chip with the second solder interconnect layer to a second carrier. | 05-05-2016 |
20160126259 | ARRAY SUBSTRATE AND METHOD OF PRODUCING THE SAME, DISPLAY PANEL AND DISPLAY DEVICE - Embodiments of the present invention provide an array substrate and a method of producing the same, a display panel and a display device, solving problems of detaching of film formed by CVD in the array substrate in prior art. The array substrate includes a plurality of data lines and a plurality of gate lines that are disposed in cross orientation. The array substrate further includes: a conductive repairing structure located at a damaged region of the data line and/or a damaged region of the gate line; and an insulating protective film configured to cover a region where at least one conductive repairing structure is located. As the region where the at least one conductive repairing structure is located is covered by the insulating protective film, the conductive repairing structure covered by the insulating protective film is not prone to be detached off. | 05-05-2016 |
20160133300 | CONNECTIONS FOR MEMORY ELECTRODE LINES - Subject matter disclosed herein may relate to word line electrodes and/or digit line electrodes in a cross-point array memory device. One or more word line electrodes may be configured to form a socket area to provide connection points to drivers and/or other circuitry that may be located within a footprint of an array of memory cells. | 05-12-2016 |
20160133534 | SILICON PACKAGE FOR EMBEDDED SEMICONDUCTOR CHIP AND POWER CONVERTER - A packaged transistor device ( | 05-12-2016 |
20160133539 | MOLD PACKAGE AND MANUFACTURING METHOD THEREOF - A mold package includes a substrate having a first surface and a second surface disposed opposite to the first surface, a wiring part disposed on the first surface in protruded manner, a molding resin, and a resin film. The molding resin partially seals the first surface of the substrate and the wiring part and intersects with the wiring part. The resin film is disposed between the first surface of the substrate and the end of the molding resin, and seals the wiring part and the first surface of the substrate adjacent to the wiring part. The resin film includes a first portion disposed inside the molding resin and a second portion disposed outside the molding resin. An upper surface of the second portion is lower than an upper surface of the first portion and has less uneven portions than the upper surface of the first portion. | 05-12-2016 |
20160133541 | Semiconductor Device - A semiconductor device includes a wiring substrate, a semiconductor element mounted on the wiring substrate, a heat dissipation plate arranged on an upper surface of the semiconductor element with an adhesive arranged in between, and an encapsulation resin filling a gap between the heat dissipation plate and the wiring substrate. The heat dissipation plate includes a body and a projection. The body is overlapped with the semiconductor element in a plan view and has a larger planar shape than the semiconductor element. The projection is formed integrally with the body. The projection projects outward from an end of the body and is located below the body. The encapsulation resin covers upper and lower surfaces of the projection. The body includes an upper surface exposed from the encapsulation resin. | 05-12-2016 |
20160133586 | SEMICONDUCTOR DEVICE - A semiconductor device includes a main pad part and a sub pad part formed in a peripheral area of at least one side of the main pad part. The sub pad part is spaced apart from the main pad part. The sub pad part operates in a first state in which the sub pad part is short-circuited with the main pad part or in a second state in which the sub pad part is open from the main pad part. | 05-12-2016 |
20160133587 | SUBSTRATES AND INTEGRATED CIRCUIT CHIP WITH IMPROVED PATTERN - The present invention relates to a substrate and integrated circuit chip with improved patterns, and more particularly to technology that is efficient in terms of thermal control and that can reduce the causes of occurrence of defects during the operation of a terminal to which a high voltage is applied. The present invention is characterized in that a first clearance distance between a first terminal, to which a voltage higher than voltages to be applied to the remaining terminals is applied, or first terminal pattern corresponding to the first terminal and a body pattern present between an integrated circuit chip and a substrate is larger than a second clearance distance between a second terminal, including at least some of the remaining terminals other than the first terminal, or second terminal pattern corresponding to the second terminal and the body pattern. | 05-12-2016 |
20160133608 | DEVICES AND STACKED MICROELECTRONIC PACKAGES WITH PACKAGE SURFACE CONDUCTORS AND METHODS OF THEIR FABRICATION - Embodiments of methods for forming a device include performing an oxidation inhibiting treatment to exposed ends of first and second device-to-edge conductors, and forming a package surface conductor to electrically couple the exposed ends of the first and second device-to-edge conductors. Performing the oxidation inhibiting treatment may include applying an organic solderability protectant coating to the exposed ends, or plating the exposed ends with a conductive plating material. The method may further include applying a conformal protective coating over the package surface conductor. An embodiment of a device formed using such a method includes a package body, the first and second device-to-edge conductors, the package surface conductor on a surface of the package body and extending between the first and second device-to-edge conductors, and the conformal protective coating over the package surface conductor. | 05-12-2016 |
20160133614 | SEMICONDUCTOR PACKAGE WITH INCORPORATED INDUCTANCE ELEMENT - The present disclosure provides semiconductor packages and methods for fabricating semiconductor packages. The semiconductor package may comprise a semiconductor device mounted to a first substrate, a voltage regulator mounted to the first substrate and coupled to the semiconductor device, and an inductive element located on a perimeter of the semiconductor device and coupled to the voltage regulator, wherein the inductive element is formed by a plurality of interconnected conductive elements extending vertically from the first substrate. | 05-12-2016 |
20160137485 | Epi-Poly Etch Stop for Out of Plane Spacer Defined Electrode - In one embodiment, a method of forming an out-of-plane electrode includes forming an oxide layer above an upper surface of a device layer, etching an etch stop perimeter defining trench extending through the oxide layer, forming a first cap layer portion on an upper surface of the oxide layer and within the etch stop perimeter defining trench, etching a first electrode perimeter defining trench extending through the first cap layer portion and stopping at the oxide layer, depositing a first material portion within the first electrode perimeter defining trench, depositing a second cap layer portion above the deposited first material portion, and vapor releasing a portion of the oxide layer with the etch stop portion providing a lateral etch stop. | 05-19-2016 |
20160141217 | ELECTRONIC PACKAGE AND FABRICATION METHOD THEREOF - A method for fabricating an electronic package, including the steps of: providing a substrate having a plurality of electronic elements and a plurality of separation portions formed between the electronic elements, wherein each of the electronic elements has an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; forming at least an opening in each of the separation portions from a side corresponding to the inactive surfaces of the electronic elements, wherein the at least an opening does not penetrate the separation portion; forming an encapsulant in the opening; and singulating the electronic elements along the opening from a side corresponding to the active surfaces of the electronic elements. As such, each of the electronic elements has a side surface adjacent to and connecting the active and inactive surfaces of the electronic element and the side surface is partially covered by the encapsulant for protection. | 05-19-2016 |
20160141269 | MULTI-CHIP SEMICONDUCTOR DEVICE - A multi-chip semiconductor device includes a plate-shaped first semiconductor chip having a first connection portion in which a first semiconductor chip electrode is formed on a first main surface of the first semiconductor chip or on a first side surface vertical to the first main surface, and a plate-shaped second semiconductor chip having a second connection portion in which a second semiconductor chip electrode is formed on a second side surface vertical to a second main surface of the second semiconductor chip. Each of the first and second connection portions includes at least an inclined surface that is inclined with respect to each of the first and second main surfaces. The first connection portion and the second connection portion are connected to each other such that the first main surface of the first semiconductor chip and the second main surface of the second semiconductor chip are vertical to each other. | 05-19-2016 |
20160141353 | DISPLAY PANEL - A display panel is disclosed. The display panel includes a substrate, a plurality of first unit pixel and a plurality of second unit pixel. The substrate includes a first region and a second region extending in a first direction. The plurality of first unit pixels is disposed in the first region of the substrate. The first unit pixel has a first area. The plurality of second unit pixel is disposed in the second region of the substrate. The second unit pixel has a second area which is smaller than the first area. | 05-19-2016 |
20160148865 | Electronic Circuit Board, Semiconductor Device Using the Same and Manufacturing Method for the Same - The present invention aims to provide an electronic circuit board with insulation reliability improved by increasing volume resistivity of a ceramics substrate fabricated by an aerosol deposition method, a semiconductor device using it and a manufacturing method therefor. The present invention provides the electronic circuit board which includes a metal material, and an insulating film formed on a front surface of the metal material and including an inorganic material containing a crystal of a grain diameter of 10 to 20 nm and in which the insulating layer is less than 0.08 g/cm | 05-26-2016 |
20160148871 | ELECTRONIC COMPONENT AND METHOD FOR PRODUCING THE SAME - An aspect of the invention is an electronic component including a semiconductor substrate | 05-26-2016 |
20160148880 | ELECTRONIC DEVICE WITH STACKED CHIPS - An electronic device includes a first and a second integrated-circuit chip that are stacked at a distance from one another, and a plurality of electrical connection pillars and at least one protective barrier interposed between the chips. The protective barrier delimits a free space between mutually opposing local regions of the chips, and an encapsulation block extends around the chip that has the smaller mounting face and over the periphery of the mounting face of the other chip. The electrical connection pillars and the protective barrier are made of at least one identical metallic material with a view to simultaneous fabrication. | 05-26-2016 |
20160148887 | Device Package with Reduced Thickness and Method for Forming Same - A device package includes a die and a molding compound around the die. The molding compound has a non-planar surface recessed from a top surface of the die. The device package also includes an interconnect structure over the die. The interconnect structure includes a redistribution layer extending onto the molding compound and conformal to the non-planar surface of the molding compound. The device package further includes a first connector disposed over the die and bonded to the interconnect structure. | 05-26-2016 |
20160155675 | VOID MONITORING DEVICE FOR MEASUREMENT OF WAFER TEMPERATURE VARIATIONS | 06-02-2016 |
20160155691 | MULTI-LAYERED CIRCUIT DEVICE | 06-02-2016 |
20160163581 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor device includes a first insulator, and conductors and second insulators alternately provided on the first insulator. Each second insulator of the second insulators has a first side face adjacent to one of the conductors via a first air gap, a second side face adjacent to one of the conductors via a second air gap, first lower faces in contact with the first insulator, and second lower faces provided above the first insulator via third air gaps. | 06-09-2016 |
20160163650 | INTEGRATED CIRCUIT ASSEMBLIES WITH RIGID LAYERS USED FOR PROTECTION AGAINST MECHANICAL THINNING AND FOR OTHER PURPOSES, AND METHODS OF FABRICATING SUCH ASSEMBLIES | 06-09-2016 |
20160163666 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - To improve an integration degree of a semiconductor device. | 06-09-2016 |
20160163667 | SEMICONDUCTOR DEVICE - Even when a thermal stress is applied to an electrode pad, the electrode pad is prevented from being moved. A substrate of a semiconductor chip has a rectangular planar shape. The semiconductor chip has a plurality of electrode pads. The center of a first electrode pad is positioned closer to the end of a first side in the direction along the first side of the substrate as compared to the center of a first opening. Thus, in a part of the first electrode pad covered with an insulating film, a width of the part closer to the end of the first side in the direction along the first side is larger than another width of the part opposite to the above-mentioned width. | 06-09-2016 |
20160163713 | STATIC RANDOM ACCESS MEMORY (SRAM) BIT CELLS WITH WORDLINES ON SEPARATE METAL LAYERS FOR INCREASED PERFORMANCE, AND RELATED METHODS - Static random access memory (SRAM) bit cells with wordlines on separate metal layers for increased performance are disclosed. In one aspect, an SRAM bit cell is disclosed employing a write wordline in a second metal layer, a first read wordline in a third metal layer, and a second read wordline in a fourth metal layer. Employing wordlines in separate metal layers allows wordlines to have increased widths, which decrease wordline resistance, decrease access time, and increase performance of the SRAM bit cell. To employ wordlines in separate metal layers, multiple tracks in a first metal layer are employed. To couple read wordlines to the tracks to communicate with SRAM bit cell transistors, landing pads are disposed on corresponding tracks disposed in the first metal layer. Landing pads corresponding to the write wordline are placed on corresponding tracks disposed in the first metal layer. | 06-09-2016 |
20160163714 | STATIC RANDOM ACCESS MEMORY (SRAM) BIT CELLS WITH WORDLINE LANDING PADS SPLIT ACROSS BOUNDARY EDGES OF THE SRAM BIT CELLS - Static random access memory (SRAM) bit cells with wordline landing pads split across boundary edges of the SRAM bit cells are disclosed. In one aspect, an SRAM bit cell is disclosed employing write wordline in second metal layer, first read wordline in third metal layer, and second read wordline in fourth metal layer. Employing wordlines in separate metal layers allows wordlines to have wider widths, which decrease wordline resistance, decrease access time, and increase performance of SRAM bit cell. To employ wordlines in separate metal layers, multiple tracks in first metal layer are employed. To couple read wordlines to the tracks to communicate with SRAM bit cell transistors, landing pads are disposed on corresponding tracks inside and outside of a boundary edge of the SRAM bit cell. Landing pads corresponding to the write wordline are placed on corresponding tracks within the boundary edge of the SRAM bit cell. | 06-09-2016 |
20160170116 | POLARIZING PLATE, TFT SUBSTRATE INCLUDING THE POLARIZING PLATE, AND METHOD OF MANUFACTURING THE POLARIZING PLATE | 06-16-2016 |
20160172237 | NON-LITHOGRAPHICALLY PATTERNED DIRECTED SELF ASSEMBLY ALIGNMENT PROMOTION LAYERS | 06-16-2016 |
20160172296 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME | 06-16-2016 |
20160172331 | SEMICONDUCTOR PACKAGE INCLUDING A PLURALITY OF STACKED CHIPS | 06-16-2016 |
20160172377 | DISPLAY DEVICE | 06-16-2016 |
20160181138 | Method of manufacturing a semiconductor component and semiconductor component | 06-23-2016 |
20160181148 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | 06-23-2016 |
20160181173 | INTEGRATED CIRCUIT BARRIERLESS MICROFLUIDIC CHANNEL | 06-23-2016 |
20160190039 | SUBSTRATE STRUCTURE - A substrate structure includes: a substrate body defined with a layout area, a sealing member and a cutting area, the sealing member being adjacent to the layout area, and the cutting area being adjacent to the sealing member; a wiring layer formed on the layout area; an insulating layer formed on the layout area and the wiring layer; and a metal layer formed on the insulating layer and the layout area. The insulating layer is prevented from being delaminated due to the formation of the metal layer. | 06-30-2016 |
20160190043 | Electronic Devices and Methods of Manufacturing Electronic Devices - Disclosed are a foldable and spreadable electronic device and a method of manufacturing the electronic device. The electronic device may include a flexible chip, a protection film and a flexible substrate. The flexible chip may include a first wiring on a first face thereof. The flexible chip may have a foldable and spreadable structure by reducing a thickness from a second face thereof. The protection film may be disposed on the second face of the flexible chip for protecting the flexible chip. The flexible substrate may include a second wiring on one face thereof. The protection film on disposed on the second face of the flexible chip may make contact with the flexible substrate. The first wiring of the flexible chip may be electrically connected to the second wiring of the flexible substrate using a wire. | 06-30-2016 |
20160190080 | SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME - The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved. | 06-30-2016 |
20160190100 | STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS IN ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE - A microelectronic assembly can include a circuit panel having first and second panel contacts at respective first and second surfaces thereof, and first and second microelectronic packages each having terminals mounted to the respective panel contacts. Each package can include a microelectronic element having a face and contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. The terminals can include first terminals at positions within first and second parallel grids. The first terminals can be configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. Signal assignments of the first terminals in the first grid can be a mirror image of signal assignments of the first terminals in the second grid. | 06-30-2016 |
20160190158 | ARRAY SUBSTRATE AND DISPLAY PANEL - The disclosure provides an array substrate and a display panel. The array substrate comprises a display region and a non-display region surrounding the display region comprising a first non-display sub region at one side of the display region. An. integrated circuit chip is arranged in the first non-display sub region. The display region comprises data lines arranged along a first direction, first conductive lines comprising gate lines or common lines and arranged along a second direction, and second conductive lines. A first insulating layer having through holes is arranged between the first conductive lines and the second conductive lines. Each of the first conductive lines electrically connects to one end of the second conductive lines through corresponding through holes, and the other end of the second conductive lines and the data lines electrically connect to the integrated circuit chip. The array substrate has a narrower bezel. | 06-30-2016 |
20160197022 | Semiconductor Device and Method of Forming Sacrificial Adhesive Over Contact Pads of Semiconductor Die | 07-07-2016 |
20160197040 | POWER LINE STRUCTURE FOR SEMICONDUCTOR APPARATUS | 07-07-2016 |
20160197043 | SUPPORT STRUCTURE FOR BARRIER LAYER OF SEMICONDUCTOR DEVICE | 07-07-2016 |
20160204002 | Self-Aligned Via and Plug Patterning for Back End of Line (BEOL) Interconnects | 07-14-2016 |
20160204094 | DISPLAY PANEL | 07-14-2016 |
20160254218 | PACKAGING MODULE OF POWER CONVERTING CIRCUIT AND METHOD FOR MANUFACTURING THE SAME | 09-01-2016 |
20160254223 | Coarse Grid Design Methods and Structures | 09-01-2016 |
20160254250 | SEMICONDUCTOR MODULE | 09-01-2016 |
20160379946 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a pad electrode | 12-29-2016 |
20160379948 | CORROSION RESISTANT ALUMINUM BOND PAD STRUCTURE - A method of manufacturing a bond pad structure may include depositing an aluminum-copper (Al—Cu) layer over a dielectric layer; and depositing an aluminum-chromium (Al—Cr) layer directly over the Al—Cu layer. | 12-29-2016 |
20160379959 | CAVITY BRIDGE CONNECTION FOR DIE SPLIT ARCHITECTURE - An integrated circuit (IC) package structure may include a substrate. The substrate may include a semiconductor bridge having a first surface directly on a surface of the substrate that faces a first semiconductor die and a second semiconductor die. The semiconductor bridge may be disposed within a cavity extending through a photo-sensitive layer on the surface of the substrate. The semiconductor bridge may have an exposed, second surface substantially flush with the photo-sensitive layer. The first semiconductor die and the second semiconductor die are supported by the substrate and coupled together through the semiconductor bridge. | 12-29-2016 |
20170233620 | RESIN COMPOSITION AND ELECTRONIC COMPONENT | 08-17-2017 |
20170236764 | ELECTRONIC DEVICE PACKAGE AND MANUFACTURING METHOD THEREOF | 08-17-2017 |
20180025911 | Monolithic Integration of Semiconductor Materials | 01-25-2018 |
20180025972 | POWER LINE LAYOUT STRUCTURE FOR SEMICONDUCTOR DEVICE | 01-25-2018 |
20180025990 | PREVENTION OF PREMATURE BREAKDOWN OF INTERLINE POROUS DIELECTRICS IN AN INTEGRATED CIRCUIT | 01-25-2018 |
20180026001 | Integrated Fan-Out Structure and Method of Forming | 01-25-2018 |
20180026109 | SEMICONDUCTOR DEVICE | 01-25-2018 |
20190148250 | METALLIZATION PATTERNS IN SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME | 05-16-2019 |
20190148266 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SAME | 05-16-2019 |
20190148304 | Embedding Known-Good Component in Known-Good Cavity of Known-Good Component Carrier Material With Pre-formed Electric Connection Structure | 05-16-2019 |
20190148319 | CHIP, FLEXIBLE DISPLAY PANEL AND DISPLAY DEVICE | 05-16-2019 |
20190148322 | SEMICONDUCTOR DEVICE WITH POST PASSIVATION STRUCTURE | 05-16-2019 |
20190148324 | 3D-Interconnect | 05-16-2019 |
20190148538 | SEMICONDUCTOR DEVICES | 05-16-2019 |
20220139825 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a semiconductor device, an interconnect structure, a capacitor, and a plurality of pads. The semiconductor device is disposed at the substrate. The interconnect structure is disposed on the substrate and electrically connected to the semiconductor device. The capacitor is disposed on the interconnect structure and electrically connected to the interconnect structure. The capacitor includes a first electrode, a second electrode covering a top surface and a sidewall of the first electrode, and an insulating layer disposed between the first electrode and the second electrode. The plurality of pads are disposed on the interconnect structure and electrically connected to the interconnect structure, wherein at least one of the plurality of pads is electrically connected to the capacitor. | 05-05-2022 |