Class / Patent application number | Description | Number of patent applications / Date published |
257772000 | Solder composition | 60 |
20080303163 | THROUGH SILICON VIA DIES AND PACKAGES - A method for preparing a die for packaging is disclosed. A die having first and second major surfaces is provided. Vias and a mask layer are formed on the first major surface of the die. The mask includes mask openings that expose the vias. The mask openings are filled with a conductive material. The method includes reflowing to at least partially fill the vias and contact openings to form via contacts in the vias and surface contacts in the mask openings. | 12-11-2008 |
20080315427 | SUBSTRATE BONDING METHOD AND SEMICONDUCTOR DEVICE - (a) A first Sn absorption layer ( | 12-25-2008 |
20090065943 | Microelectronic Assembly Having Second Level Interconnects Including Solder Joints Reinforced with Crack Arrester Elements and Method of Forming Same - A microelectronic assembly and a method of forming the assembly. The microelectronic assembly includes a package having a package substrate having a die side and a carrier side, and substrate lands on the carrier side thereof; a microelectronic die mounted on the package substrate at the die side thereof; and an array of first level interconnects electrically coupling the die to the package substrate. The assembly further includes a carrier having a substrate side, the package being mounted on the carrier at the substrate side thereof; and an array of second level interconnects electrically coupling the package to the carrier, each of the second level interconnects including a solder joint connecting the substrate lands to the carrier lands, and a crack arrester element at least partially encompassed within the solder joint. | 03-12-2009 |
20090085216 | Semiconductor device - The present invention provides a semiconductor device excellent in the reliability of connection between the semiconductor device and a mounting board. The semiconductor device has external connecting terminals. Each of the external connecting terminals includes a Cu electrode, intermetallic compounds containing Cu, each formed over the Cu electrode, stopper portions which cover surfaces of the intermetallic compounds at intervals, and a solder alloy comprising Bi and an impurity containing Sn formed over the stopper portions and the intermetallic compounds. | 04-02-2009 |
20090166876 | SEMICONDUCTOR DEVICE AND DIE BONDING MATERIAL - In a semiconductor device bonded to a motherboard with a bonding material having a melting point of 200° C. to 230° C., a bonding material | 07-02-2009 |
20090294974 | BONDING METHOD FOR THROUGH-SILICON-VIA BASED 3D WAFER STACKING - There is described a bonding method for through-silicon-via bonding of a wafer stack in which the wafers are formed with through-silicon-vias and lateral microchannels that are filled with solder. To fill the vias and channels the wafer stack is placed in a soldering chamber and molten solder is drawn through the vias and channels by vacuum. The wafers are held together by layers of adhesive during the assembly of the wafer stack. Means are provided for local reheating of the solder after it has cooled to soften the solder to enable it to be removed from the soldering chamber. | 12-03-2009 |
20100276808 | SURFACE MOUNTING ELECTRONIC COMPONENT AND MANUFACTURING METHOD THEREOF - The electric component includes at least a set of electrode terminals | 11-04-2010 |
20100289148 | SEMICONDUCTOR POWER MODULE - Use of Pb-free solder has become essential due to the environmental problem. A power module is formed by soldering substrates with large areas. It is known that in Sn-3Ag-0.5Cu which hardly creeps and deforms with respect to large deformation followed by warpage of the substrate, life is significantly shortened with respect to the temperature cycle test, and the conventional module structure is in the situation having difficulty in securing high reliability. Thus, the present invention has an object to select compositions from which increase in life can be expected at a low strain rate. In Sn solder, by doping In by 3 to 7% and Ag by 2 to 4.5%, the effect of delaying crack development at a low strain rate is found out, and as a representative composition stable at a high temperature, Sn-3Ag-0.5Cu-5In is selected. Further, for enhancement of reliability, a method for partially coating a solder end portion with a resin is shown. | 11-18-2010 |
20100308465 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - There is provided a semiconductor device including: a circuit board formed by bonding a first and a second metal plates to both surfaces of an insulating substrate respectively, at least one semiconductor element to be bonded to an external surface of the first metal plate through a first solder, and a radiating base plate to be bonded to an external surface of the second metal plate through a second solder, wherein the first and the second solders are constituted by solder materials of the same type, and a ratio of a sum of thicknesses of the first and the second metal plates to a thickness of the insulating substrate is set in a predetermined range to ensure an endurance to a temperature stress of each of the first and the second solders. | 12-09-2010 |
20110012263 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - In order to achieve the highly reliable and highly functional semiconductor device capable of the high-speed transmission by stacking thin chips and substrates, a connecting process and a connecting structure capable of making a solid connection at a low temperature with a low load and maintaining the shape of a connecting portion even if the connecting portion is heated in the stacking process and the subsequent mounting process are provided. In a semiconductor device in which semiconductor chips or wiring boards on which semiconductor chips are mounted are stacked, a connecting structure between electrodes of the stacked semiconductor chips or wiring boards includes a pair of electrodes mainly made of Cu and a solder layer made of Sn—In based alloy sandwiched between the electrodes, and Sn—Cu—Ni intermetallic compounds are dispersed in the solder layer. | 01-20-2011 |
20110042817 | SOLDER JOINT STRUCTURE, AND JOINING METHOD OF THE SAME | 02-24-2011 |
20110079911 | Method for the Connection of Two Wafers, and a Wafer Arrangement - A method for the connection of two wafers in which a contact area is formed between the two wafers by placing the two wafers one on top of the other. The contact area is heated locally and for a limited time. A wafer arrangement comprises two wafers which have been placed one on top of the other and between whose opposite surfaces a contact area is located. The wafers are connected to one another at selected areas of the contact area. | 04-07-2011 |
20110089567 | Production Method and Production Apparatus of Tin or Solder Alloy for Electronic Components, and Solder Alloy - The invention provides a technique and a device that dramatically improve joint reliability of miniature joints of fine electronic components. According to the invention, when producing a tin or a solder alloy used for electronic components, an ingot of a tin or a solder alloy is heated, melted and delivered to a reactor. Also, a solution containing organic acid having a carboxyl group (—COOH) is delivered to the reactor. After stirring and mixing the two liquids intensively, the mixed liquid is separated into a molten tin or a molten solder alloy liquid and an organic acid solution according to the difference in specific gravity. Then, the respective liquids are circulated to the reactor, and the metal oxides and the impurities existing in the molten tin or the molten solder alloy are removed, and the molten tin or the molten alloy is purified to have oxygen concentration of 5 ppm or less. | 04-21-2011 |
20110089568 | POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A power semiconductor device includes a substrate, an element circuit pattern formed on the substrate and made of Cu covered with an electroless Ni—P plating layer, and a power semiconductor element bonded to the element circuit pattern by a solder, wherein the solder is an alloy of Sn, Sb, and Cu, and the weight percent of Cu is in the range of 0.5 to 1%, inclusive. | 04-21-2011 |
20110180929 | GOLD-TIN-INDIUM SOLDER FOR PROCESSING COMPATIBILITY WITH LEAD-FREE TIN-BASED SOLDER - Disclosed in this specification is a lead-free soldering alloy made of gold, tin and indium. The tin is present in a concentration of 17.5% to 20.5%, the indium is present in a concentration of 2.0% to 6.0% and the balance is gold and the alloy has a melting point between 290° C. and 340° C. and preferably between 300° C. and 340° C. The soldering alloy is particularly useful for hermetically sealing semiconductor devices since the melting temperature is sufficiently high to permit post-seal heating and sufficiently low to allow sealing of the semiconductor without causing damage. | 07-28-2011 |
20110227228 | FILLING COMPOSITION, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE - Provided is a filling composition. The filling composition includes: a first particle including Cu and/or Ag; a second particle electrically connecting the first particles; and a resin containing a high molecular compound, a hardener, and a reducer, in which the first and second particles are dispersed, wherein the hardener includes amine and/or anhydride, and the reducer includes carboxyl. | 09-22-2011 |
20110291282 | JUNCTION BODY, SEMICONDUCTOR MODULE, AND MANUFACTURING METHOD FOR JUNCTION BODY - A junction body has a first member and a second member each of which is provided with a joining surface whose main component is copper. A solder member containing, in a tin-base solder material, a three-dimensional web structure whose main component is copper is provided between the first member and the second member. A copper-tin alloy whose average thickness is 2 μm or more but 20 μm or less is provided between the joining surfaces and the three-dimensional web structure. | 12-01-2011 |
20110304051 | THERMAL INTERFACE MATERIAL WITH SUPPORT STRUCTURE - Various semiconductor chip thermal interface material methods and apparatus are disclosed. In one aspect, a method of establishing thermal contact between a first semiconductor chip and a heat spreader is provided. The method includes placing a thermal interface material layer containing a support structure on the first semiconductor chip. The heat spreader is positioned proximate the thermal interface material layer. The thermal interface material layer is reflowed to establish thermal contact with both the first semiconductor chip and the heat spreader. | 12-15-2011 |
20120007247 | Resin-Encapsulated Semiconductor Device - A resin-sealed semiconductor device includes a semiconductor chip including a silicon substrate; a die pad on which the semiconductor chip is secured via a solder layer; a sealing resin layer sealing the semiconductor chip; and lead terminals connected electrically with the semiconductor chip. One end portion of the lead terminals is covered by the sealing resin layer. The die pad and the lead terminals are formed of copper and a copper alloy, and the die pad is formed with a thickness larger than a thickness of the lead terminals, which is a thickness of 0.25 mm or more. | 01-12-2012 |
20120032335 | ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING THE SAME - An electronic component including a wiring board having a power-source pattern and a signal pattern, a semiconductor element mounted on the wiring board and having a power-source electrode pad and a signal electrode pad, a first connection portion being made of a conductive material and connecting the signal pattern of the wiring board and the signal electrode pad of the semiconductor element, and a second connection portion being made of a conductive material and connecting the power-source pattern of the wiring board and the power-source electrode pad of the semiconductor element. The conductive material of the first connection portion and the conductive material of the second connection portion are selected such that the conductive material of the second connection portion has an electrical resistance which is lower than an electrical resistance of the conductive material of the first connection portion. | 02-09-2012 |
20120080799 | Semiconductor Module Comprising an Insert and Method for Producing a Semiconductor Module Comprising an Insert - A power semiconductor module is fabricated by providing a base with a metal surface and an insulating substrate comprising an insulation carrier having a bottom side provided with a bottom metallization layer. An insert exhibiting a wavy structure is provided. The insert is positioned between the insulation carrier and metal surface, after which the metal surface is soldered to the bottom side metallization layer and insert by means of a solder packing all interstices between the metal surface and bottom side metallization layer with the solder. | 04-05-2012 |
20120104618 | LOW TEMPERATURE BONDING MATERIAL AND BONDING METHOD - A bonding material comprising metal particles coated with an organic substance having carbon atoms of 2 to 8, wherein the metal particles comprises first portion of 100 nm or less, and a second portion larger than 100 nm but not larger than 100 μm, each of the portions having at least peak of a particle distribution, based on a volumetric base. The disclosure is further concerned with a bonding method using the bonding material. | 05-03-2012 |
20120112351 | SEMICONDUCTOR DEVICE PACKAGING METHOD AND SEMICONDUCTOR DEVICE PACKAGE - Disclosed is a method of manufacturing a discrete semiconductor device package ( | 05-10-2012 |
20120126411 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device of the present invention has a purpose to form a structure of preventing outflow of solder at low costs. A semiconductor element is bonded to a substrate through a solder layer. An outflow-preventing part is provided to surround the solder layer to prevent solder outflow during soldering. The outflow-preventing part is formed by a cold spray method and has a surface in an oxidized state. | 05-24-2012 |
20120146228 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME AND A MOUNTING STRUCTURE OF A SEMICONDUCTOR DEVICE - The semiconductor device includes a tab including a chip supporting surface, and a back surface opposite to the chip supporting surface; a plurality of suspension leads supporting the tab; a plurality of leads arranged between the suspension leads; a semiconductor chip mounted on the chip supporting surface of the tab, the semiconductor chip including a main surface, a plurality of pads formed on the main surface, and a rear surface opposite to the main surface; a seal portion sealing the semiconductor chip such that a part of each of the leads is exposed from the seal portion; and a Pb-free solder formed on the part of each of the leads. A part of the rear surface of the semiconductor chip is contacted with the seal portion. | 06-14-2012 |
20120153488 | SIMULTANEOUS WAFER BONDING AND INTERCONNECT JOINING - Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip. | 06-21-2012 |
20120161326 | COMPOSITION FOR FILLING THROUGH SILICON VIA (TSV), TSV FILLING METHOD AND SUBSTRATE INCLUDING TSV PLUG FORMED OF THE COMPOSITION - Provided is a composition for filling a Through Silicon Via (TSV) including: a metal powder; a solder powder; a curable resin; a reducing agent; and a curing agent. A TSV filling method using the composition and a substrate including a TSV plug formed of the composition are also provided. | 06-28-2012 |
20120193800 | SOLDER, SOLDERING METHOD, AND SEMICONDUCTOR DEVICE - A solder includes Sn (tin), Bi (bismuth) and Zn (zinc), wherein the solder has a Zn content of 0.01% by weight to 0.1% by weight. | 08-02-2012 |
20120193801 | RFID TRANSPONDER AND METHOD FOR CONNECTING A SEMICONDUCTOR DIE TO AN ANTENNA - An RFID transponder having a semiconductor die with a solderable contact area and an antenna made from a winding wire, wherein the winding wire is soldered to the contact area, and the solderable contact area is made from a nickel based alloy. | 08-02-2012 |
20120223433 | SEMICONDUCTOR PACKAGE INCLUDING CONNECTING MEMBER HAVING CONTROLLED CONTENT RATIO OF GOLD - A semiconductor package including connecting members having a controlled content ratio of gold capable of increasing durability and reliability by preventing an intermetallic compound having high brittleness from being formed. The semiconductor package includes a base substrate; a first semiconductor chip disposed on the base substrate; and a first connecting member for electrically connecting the base substrate and the first semiconductor chip, and comprising a first bonding portion that includes gold and has a first content ratio of gold that is controlled to prevent an intermetallic compound of AuSn | 09-06-2012 |
20120223434 | CO-AXIAL RESTRAINT FOR CONNECTORS WITHIN FLIP-CHIP PACKAGES - An assembly can include a microelectronic element such as, for example, a semiconductor element having circuits and semiconductor devices fabricated therein, and a plurality of electrical connectors, e.g., solder balls attached to contacts of the microelectronic element. The connectors can be surrounded by first, inner regions | 09-06-2012 |
20120248616 | ELECTRONIC COMPONENT, ELECTRONIC EQUIPMENT, AND SOLDERING PASTE - To provide an electronic component, containing: a wiring board containing electrode pads; a component including a plurality of electrodes, the component being mounted on the wiring board; a sealing resin covering the component; and a plurality of terminals configured to connect a wiring provided within the wiring board to an external substrate, wherein the plurality of electrodes and the electrode pads are connected with solder, and wherein a first resin layer and a second resin layer are provided between the solder and the sealing resin in this order from the side of the solder, where the first resin layer has a first Young's modulus and the second resin layer has a second Young's modulus larger than the first Young's modulus. | 10-04-2012 |
20120306087 | SEMICONDUCTOR DEVICE INCLUDING EXCESS SOLDER - A semiconductor device includes a substrate including a first metal layer, a first semiconductor chip having sidewalls, and a first solder layer contacting the first semiconductor chip and the first metal layer. The first metal layer includes a groove extending around sidewalls of the first semiconductor chip. The groove is at least partly filled with excess solder from the first solder layer. | 12-06-2012 |
20130015582 | CIRCUIT BOARD, SEMICONDUCTOR DEVICE, PROCESS FOR MANUFACTURING CIRCUIT BOARD AND PROCESS FOR MANUFACTURING SEMICONDUCTOR DEVICEAANM Kondo; MasayoshiAACI TokyoAACO JPAAGP Kondo; Masayoshi Tokyo JPAANM Makino; NatsukiAACI TokyoAACO JPAAGP Makino; Natsuki Tokyo JPAANM Fujiwara; DaisukeAACI TokyoAACO JPAAGP Fujiwara; Daisuke Tokyo JPAANM Ito; YukaAACI TokyoAACO JPAAGP Ito; Yuka Tokyo JP - A circuit board ( | 01-17-2013 |
20130026638 | Wafer-Level Chip Scale Package - A chip scale package implements solder bars to form a connection between a chip and a trace, formed in a substrate, such as another chip or PCB. Solder bars are formed by depositing one or more solder layers into the socket, or optionally, depositing a base metal layer into the socket and applying the solder layer to the base metal layer. The geometry of a solder bars may be rectangular, square, or other regular or irregular geometry. Solder bars provide a greater utilization of the connectivity footprint and increase the electrical and thermal flow capacity. Solder bars also provide a robust connection. | 01-31-2013 |
20130037957 | FLUX COMPOSITION, PROCESS FOR PRODUCING ELECTRICALLY CONNECTED STRUCTURES, ELECTRICALLY CONNECTED STRUCTURE, AND SEMICONDUCTOR DEVICE - A flux composition includes an alditol (A) and a polymer (B) which has a repeating structural unit represented by Formula (1): | 02-14-2013 |
20130099383 | Semiconductor Device and Method - An electrical device includes a semiconductor chip. The semiconductor chip includes a routing line. An insulating layer is arranged over the semiconductor chip. A solder deposit is arranged over the insulating layer. A via extends through an opening of the insulating layer to electrically connect the routing line to the solder deposit. A front edge line portion of the via facing the routing line is substantially straight, has a concave curvature or has a convex curvature of a diameter greater than a maximum lateral dimension of the via. | 04-25-2013 |
20130099384 | Stacked IC Devices Comprising a Workpiece Solder Connected to the TSV - A stacked integrated circuit (IC) device with at least one IC die having a top semiconductor surface and a bottom surface and at least one through substrate via (TSV) including a tip protruding beyond the bottom surface to a tip length is provided. The tip has an outer dielectric tip liner, and an electrically conductive portion within the outer dielectric tip liner. A compliant layer is applied to the bottom surface of the IC die. The dielectric tip liner is removed from a distal portion of the tip to expose an electrically conductive tip portion. A solder material is deposited on the exposed distal portion of the tip. The solder material is reflowed and coalesced to form a solder bump on the distal portion of the tip. | 04-25-2013 |
20130105980 | SINTERABLE BONDING MATERIAL USING COPPER NANOPARTICLES, PROCESS FOR PRODUCING SAME, AND METHOD OF BONDING ELECTRONIC COMPONENT | 05-02-2013 |
20130113108 | SYSTEM IN PACKAGE PROCESS FLOW - A method comprises connecting a substrate having a plurality of integrated circuit (IC) dies to a package substrate, so that the package substrate extends beyond at least two edges of the substrate, leaving first and second edge portions of the package substrate having exposed contacts. The first and second edge portions meet at a first corner of the package substrate. At least a first upper die package is placed over the substrate, so that first and second edge portions of the first upper die package extend beyond the at least two edges of the substrate. Pads on the first and second edge portions of the first upper die package are connected to the contacts of the first and second edge portions of the package substrate. | 05-09-2013 |
20130119549 | Mold Chase Design for Package-on-Package Applications - A method includes placing a mold chase over a bottom package, wherein the bottom package has a connector at a top surface of the bottom package. The mold chase includes a cover, and a pin under and connected to the cover. The pin occupies a space extending from a top surface of the connector to the cover. A polymer is filled into a space between the cover of the mold chase and the bottom package. The polymer is then cured. After the step of curing the polymer, the mold chase is removed, and the connector is exposed through an opening in the polymer, wherein the opening is left by the pin of the mold chase. | 05-16-2013 |
20130134593 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR ELEMENT - A method for manufacturing a semiconductor device includes preparing a semiconductor element including electrode pads laid out along the periphery of the semiconductor element in a tetragonal frame-shaped array to form a line of electrode pads along each side of the semiconductor element, preparing a wiring substrate including connection pads corresponding to the electrode pads, applying solder including a bulging central portion on an upper surface of each connection pad, forming pillar-shaped electrode terminals on the electrode pads so that each electrode terminal has an axis separated from a peak of the bulging central portion of the solder on the corresponding connection pad in a longitudinal direction of the corresponding connection pad, and electrically connecting the electrode terminals with the solder to the connection pad. | 05-30-2013 |
20130134594 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR ELEMENT, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element on which electrode pads are laid out. A wiring substrate includes connecting pads respectively arranged in correspondence with the electrode pads. Pillar-shaped electrode terminals are respectively formed on the electrode pads of the semiconductor element. A solder joint electrically connects a distal portion of each electrode terminal and the corresponding connecting pad on the wiring substrate. Each electrode terminal includes a basal portion, which is connected to the corresponding electrode pad, and a guide, which is formed in the distal portion. The guide has a smaller cross-sectional area than the basal portion as viewed from above. The guide has a circumference and the basal portion has a circumference that is partially flush with the circumference of the guide. The guide is formed to guide solder toward the circumference of the guide. | 05-30-2013 |
20130249100 | POWER SEMICONDUCTOR DEVICE MODULE - A power semiconductor device module includes: a base plate; an insulating substrate mounted on the base plate; and a diode chip mounted on the insulating substrate, wherein the insulating substrate has an upper surface electrode layer disposed on an upper main surface and a lower surface electrode layer disposed on a lower main surface, the diode chip is joined onto the upper surface electrode layer, the lower surface electrode layer is joined onto the upper main surface of the base plate, and a thermal resistance reducing section that reduces thermal resistance is provided in lower surface electrode layer or the base plate of a portion corresponding to a place immediately below the diode chip. | 09-26-2013 |
20130277847 | CHIP PACKAGE AND METHOD FOR ASSEMBLING CHIP PACKAGE - A chip package includes a PCB, a connecting pad fixed on a surface of the PCB and a chip fixed on the connecting pad. The connecting pad includes a first metal film on its surface facing away from the PCB. The chip includes a second metal film formed on its surface opposite to the PCB. The first and the second metal are connected to each other via a eutectic manner. | 10-24-2013 |
20130313711 | Semiconductor Device And A Method Of Manufacturing Same - In a semiconductor device where a metal circuit layer is disposed over a main planar surface of an insulating substrate, a semiconductor chip is connected by way of a solder over the metal circuit layer, and a metal wiring is connected over the metal circuit layer, in which a solder flow prevention area comprising a linear oxide material is formed between the semiconductor chip and the ultrasonic metal bonding region over the metal circuit layer. | 11-28-2013 |
20130320548 | INTEGRATED CIRCUIT DIE ASSEMBLY WITH HEAT SPREADER - A packaged semiconductor device comprises a package substrate comprising a first package substrate contact and a second package substrate contact, and a semiconductor die over the package substrate. The semiconductor device further includes electrical connections between signal contact pads of the die and the package substrate, and a heat spreader that comprises a first heat spreader portion which is electrically connected to a first signal contact pad and the first package substrate contact and provides an electrical conduction path and a thermal conduction path. A second heat spreader portion provides an electrical conduction path between a second signal contact pad and the second package substrate contact and a thermal conduction path between the die and package substrate. An insulating layer is positioned between the first and second heat spreader portions. | 12-05-2013 |
20140008805 | Component and Method of Manufacturing a Component Using an Ultrathin Carrier - A system and method for manufacturing a packaged component are disclosed. An embodiment comprises forming a plurality of components on a carrier, the plurality of components being separated from each other by kerf regions on a front side of the carrier and forming a metal pattern on a backside of the carrier, wherein the metal pattern covers the backside of the carrier except over regions corresponding to the kerf regions. The method further comprises generating the component by separating the carrier. | 01-09-2014 |
20140035150 | METAL CORED SOLDER DECAL STRUCTURE AND PROCESS - A method and system of producing metal cored solder structures on a substrate which includes: providing a decal having a plurality of apertures, the apertures being tapered from a top surface to a bottom surface; positioning a carrier beneath the bottom of the decal, the carrier having cavities located in alignment with the apertures of the decal; positioning the decal on the carrier having the decal bottom surface in contact with the carrier top surface to form feature cavities defined by the decal apertures and the carrier cavities; positioning a plurality of metal elements in the feature cavities; filling the feature cavities with molten solder and cooling the solder; separating the decal from the carrier to partially expose metal core solder contacts; positioning the metal core solder contacts on receiving elements of a substrate; and exposing the metal core solder contacts on the substrate. | 02-06-2014 |
20140124937 | Contoured Package-on-Package Joint - A contoured package on package joint and a method for making the same are disclosed herein. A method for forming a device comprises providing a substrate having a package land and forming a mounting stud on the package land. A molded underfill is applied to the substrate and in contact with the mounting stud. A contoured stud surface is formed on the mounting stud is contoured and connecting member attached to the contoured stud surface with a second package attached to the connecting member. The connecting member may be solder and have a spherical shape. The contoured stud surface may be etched or mechanically formed to have a hemispherical shape conforming to the connecting member shape. | 05-08-2014 |
20140183746 | Zero Stand-Off Bonding System and Method - A system and method for a zero stand-off configuration are provided. An embodiment comprises forming a seal layer over a conductive region that is part of a first substrate and breaching the seal with a conductive member of a second substrate in order to bond the first substrate to the second substrate. | 07-03-2014 |
20140197541 | MICROELECTRONIC ASSEMBLY HAVING A HEAT SPREADER FOR A PLURALITY OF DIE - A microelectronic assembly ( | 07-17-2014 |
20140217595 | MOUNTING STRUCTURE AND MANUFACTURING METHOD FOR SAME - In a provided mounting structure, an electronic component such as a semiconductor chip having a fragile film is mounted on a substrate such as a circuit board with higher connection reliability. A junction that connects an electrode terminal ( | 08-07-2014 |
20140232005 | STACKED PACKAGE, METHOD OF FABRICATING STACKED PACKAGE, AND METHOD OF MOUNTING STACKED PACKAGE FABRICATED BY THE METHOD - Provided are a stacked package, a method of fabricating a stacked package, and a method of mounting the stacked package fabricated by the same. The method of fabricating a stacked package includes providing an upper semiconductor package including an upper package substrate, upper semiconductor chips formed on a top surface of the upper package substrate, and first solders formed on a bottom surface of the upper package substrate and having a first melting temperature, providing a lower semiconductor package including a lower package substrate, lower semiconductor chips formed on a top surface of the lower package substrate, and solder paste nodes formed on the top surface of the lower package substrate and having a second melting temperature lower than the first melting temperature, and forming inter-package bonding units by attaching respective first solders and solder paste nodes to each other by performing annealing at a temperature higher than the second melting temperature and lower than the first melting temperature. | 08-21-2014 |
20140353834 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first electrode, a second electrode, and an endothermic layer. The first electrode, the second electrode and the endothermic layer are formed on a semiconductor substrate. The first electrode is electrically conductive with an element formed inside of the semiconductor substrate. The endothermic layer is in contact with the first electrode and has electric conductivity. The second electrode is in contact with at least one of the first electrode and the endothermic layer and soldered to a metal electric conductor. Herein, at least one of a work function and contact resistivity of the first electrode is smaller than that of the endothermic layer. A heat of melting of the endothermic layer is larger than that of the first electrode. Solder joinability of the second electrode is higher than that of the endothermic layer. | 12-04-2014 |
20150303156 | SINGLE INLINE NO-LEAD SEMICONDUCTOR PACKAGE - Embodiments of a packaged semiconductor device with no leads are disclosed. One embodiment includes a semiconductor chip and a no leads package structure defining a boundary and having a bottom surface and includes three or more pads exposed at the bottom surface of the package structure. Each of the pads is located in a single inline row. | 10-22-2015 |
20150311171 | ELECTRONIC COMPONENT AND ELECTRONIC DEVICE - A surface of a connection terminal of an electronic component is covered with a protection layer made of a AgSn alloy. The electronic component is soldered to a connection terminal of a circuit board. | 10-29-2015 |
20160035691 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME - A semiconductor device includes, an alloy layer sandwiched between a first Ag layer formed on a mounting board or circuit board and a second Ag layer formed on a semiconductor element, wherein the alloy layer contains an intermetallic compound of Ag | 02-04-2016 |
20160181169 | ORGANIC-INORGANIC HYBRID STRUCTURE FOR INTEGRATED CIRCUIT PACKAGES | 06-23-2016 |
20190148233 | Component and Method of Manufacturing a Component Using an Ultrathin Carrier | 05-16-2019 |