Class / Patent application number | Description | Number of patent applications / Date published |
257753000 | With adhesion promoting means (e.g., layer of material) to promote adhesion of contact to an insulating layer | 56 |
20080217778 | METHOD TO CREATE FLEXIBLE CONNECTIONS FOR INTEGRATED CIRCUITS - A method of producing flexible interconnections for integrated circuits, and, in particular, the forming of flexible or compliant interconnections preferably by a laser-assisted chemical vapor deposition process in semiconductor or glass substrate-based carriers which are employed for mounting and packaging multiple integrated circuit chips and selectively, other devices in the technology. | 09-11-2008 |
20080230909 | Method for forming anti-stiction bumps on a micro-electro mechanical structure - A technique for forming anti-stiction bumps on a bottom surface of a micro-electro mechanical (MEM) structure includes a number of process steps. The MEM structure is fabricated from an assembly that includes a support substrate bonded to a single-crystal semiconductor layer, via an insulator layer. A plurality of holes are formed through the single-crystal semiconductor layer to the insulator layer on an interior portion of a defined movable structure. A portion of the insulator layer underneath the holes is removed. The holes are then filled with a conformal film that extends below a lower surface of the defined movable structure to provide a plurality of anti-stiction bumps. A trench is then formed through the single-crystal semiconductor layer to the insulator layer to form the defined movable structure. Finally, a remainder of the insulator layer underneath the defined movable structure is removed to free the defined movable structure. | 09-25-2008 |
20080230910 | INTEGRATED CIRCUIT AND METHOD FOR PRODUCING THE SAME - An integrated circuit provides a carrier substrate, a wiring level above a carrier substrate, wherein the wiring level comprises a first conductor track composed of a first conductive material and a second conductor track composed of the first conductive material, an insulating layer above the wiring level, wherein the insulating layer comprises a first opening in a region of the first conductor track of the wiring level and a second opening in a region of the second conductor track of the wiring level and a contact bridge composed of a second conductive material, wherein the contact bridge is connected to the first conductor track in a region of the first opening and is connected to the second conductor track in a region of the second opening. | 09-25-2008 |
20080237865 | SEMICONDUCTOR DEVICE INCLUDING AN AMORPHOUS NITRIDED SILICON ADHESION LAYER AND METHOD OF MANUFACTURE THEREFOR - Provided is a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, without limitation, includes forming a first semiconductor layer over a substrate, and forming a second semiconductor layer over the first semiconductor layer, wherein an amorphous nitrided silicon adhesion layer is located between and adheres the first and second semiconductor layers. | 10-02-2008 |
20080237866 | SEMICONDUCTOR DEVICE WITH STRENGTHENED PADS - A semiconductor device is provided having an increased hardness against contact of a probe needle. The semiconductor device includes: a semiconductor substrate; a semiconductor element formed in the semiconductor substrate; an insulating film formed above the semiconductor substrate and covering the semiconductor element; a multilayer wiring structure formed in the insulating film; and a pad electrode structure connected to the multilayer wiring structure and formed on the insulating film, the pad electrode structure including a conductive adhesion film, a conductive pad electrode formed above the conductive adhesion film, and a conductive hydrogen barrier film formed above the conductive pad electrode. | 10-02-2008 |
20080265419 | SEMICONDUCTOR STRUCTURE COMPRISING AN ELECTRICALLY CONDUCTIVE FEATURE AND METHOD OF FORMING THE SAME - A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a layer of a dielectric material. A recess is provided in the layer of dielectric material. A first glue layer and a second glue layer are formed over the recess. The first glue layer comprises titanium and the second glue layer comprises tungsten nitride. The recess is filled with a material comprising tungsten. | 10-30-2008 |
20090026619 | Method for Backside Metallization for Semiconductor Substrate - A wafer circuit, such as a wafer-level package, that includes a semiconductor substrate on which is fabricated one or more integrated circuits. A backside metal layer is deposited on the semiconductor substrate, and is electrically coupled to the integrated circuit by metallized vias extending through the substrate wafer. The backside metal layer is cut to provide electrically isolated backside metal layers for RF, DC and/or ground signals. An adhesion layer is deposited on the backside of the substrate before the metal layer is deposited so that the metal layer is firmly secured to the substrate, and resists peeling. The adhesion layer can be sputtered silicon, sputtered silicon nitride, silicon nitride deposited by chemical vapor deposition, nickel deposited by evaporation and nickel chromium deposited by evaporation. | 01-29-2009 |
20090051034 | Semiconductor device and method for the same - A method for forming a semiconductor device is provided. The method includes the following steps. A substrate having a first contact is provided. A layered structure is formed on the substrate. A recess is formed into the layered structure to expose at least a portion of the first contact. A glue layer is formed on the layered structure and the at least a portion of the first contact. The glue layer is removed from the at least a portion of the first contact. A second contact is formed contacting the first contact and the glue layer. | 02-26-2009 |
20090072404 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A highly reliable semiconductor device in which connection reliability is assured at very small vias comprises: a semiconductor substrate; a first wiring structure placed on the semiconductor substrate and having one or more first wiring layers, one or more insulating layers and a first via; a second wiring structure placed on the first wiring structure and having one or more second wiring layers, one or more second insulating layers, a second via and a third via; and an external terminal provided on the second wiring structure. The second via, which is connected to the second wiring layer of the second wiring structure and to the external terminal, has a connection interface disposed at an end of the via that is on the side of the external terminal. | 03-19-2009 |
20090085212 | CLADDED SILVER AND SILVER ALLOY METALLIZATION FOR IMPROVED ADHESION ELECTROMIGRATION RESISTANCE - In semiconductor integrated circuit and device fabrication interconnect metallization is accomplished by a clad Ag deposited on a SiO2 level on a Si surface. The clad Ag has a layer of an alloy of Ag and Al (5 atomic %) contacting the SiO2, a layer of substantially pure Ag and an outer layer of the Ag and Al alloy. The alloy improves adhesion to the SiO2, avoids agglomeration of the Ag, reduces or eliminates diffusion at the SiO2 surface, reduces electromigration and presents a passive exterior surface. | 04-02-2009 |
20090152727 | BONDING PAD FOR ANTI-PEELING PROPERTY AND METHOD FOR FABRICATING THE SAME - A bonding pad includes a conductive layer formed over an insulation layer, and a dummy pattern penetrating the insulation layer and stuck in the conductive layer, wherein a bonding process is performed. | 06-18-2009 |
20090243107 | NOVEL APPROACH TO HIGH TEMPERATURE WAFER PROCESSING - At temperatures near, and above, 385° C., gold can diffuse into silicon and into some contact materials. Gold, however, is an excellent material because it is corrosion resistant, electrically conductive, and highly reliable. Using an adhesion layer and removing gold from the contact area above and around a contact allows a Micro-Electro-Mechanical Systems device or semiconductor to be subjected to temperatures above 385° C. without risking gold diffusion. Removing the risk of gold diffusion allows further elevated temperature processing. Bonding a device substrate to a carrier substrate can be an elevated temperature process. | 10-01-2009 |
20100038789 | CONFORMAL ADHESION PROMOTER LINER FOR METAL INTERCONNECTS - A dielectric layer is patterned with at least one line trough and/or at least one via cavity. A metallic nitride liner is formed on the surfaces of the patterned dielectric layer. A metal liner is formed on the surface of the metallic nitride liner. A conformal copper nitride layer is formed directly on the metal liner by atomic layer deposition (ALD) or chemical vapor deposition (CVD). A Cu seed layer is formed directly on the conformal copper nitride layer. The at least one line trough and/or the at least one via cavity are filled with an electroplated material. The direct contact between the conformal copper nitride layer and the Cu seed layer provides enhanced adhesion strength. The conformal copper nitride layer may be annealed to covert an exposed outer portion into a contiguous Cu layer, which may be employed to reduce the thickness of the Cu seed layer. | 02-18-2010 |
20100059891 | ALTERNATIVE TO DESMEAR FOR BUILD-UP ROUGHENING AND COPPER ADHESION PROMOTION - In some embodiments, an alternative to desmear for build-up roughening and copper adhesion promotion is presented. In this regard, a substrate in introduced having a dielectric layer, a plurality of polyelectrolyte multilayers on the dielectric layer, and a copper plating layer on the polyelectrolyte multilayers. Other embodiments are also disclosed and claimed. | 03-11-2010 |
20100117236 | TOP LAYERS OF METAL FOR HIGH PERFORMANCE IC'S - The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads for flip chip applications. Photoresist define electroplating, sputter/etch, or dual and triple damascene techniques are used for forming the metal lines and via fill. | 05-13-2010 |
20100308463 | INTERFACIAL CAPPING LAYERS FOR INTERCONNECTS - Adhesive layers residing at an interface between metal lines and dielectric diffusion barrier (or etch stop) layers are used to improve electromigration performance of interconnects. Adhesion layers are formed by depositing a precursor layer of metal-containing material (e.g., material containing Al, Ti, Ca, Mg, etc.) over an exposed copper line, and converting the precursor layer to a passivated layer (e.g., nitridized layer). For example, a substrate containing exposed copper line having exposed Cu—O bonds is contacted with trimethylaluminum to form a precursor layer having Al—O bonds and Al—C bonds on copper surface. The precursor layer is then treated to remove residual organic substituents and to form Al—N, Al—H bonds or both. The treatment can include direct plasma treatment, remote plasma treatment, UV-treatment, and thermal treatment with a gas such as NH | 12-09-2010 |
20110031624 | MEMS and a Protection Structure Thereof - A protection structure of a pad is provided. The pad is disposed in a dielectric layer on a semiconductor substrate and the pad includes a connection region and a peripheral region which encompasses the connection region. The protection structure includes at least a barrier, an insulation layer and a mask layer. The barrier is disposed in the dielectric layer in the peripheral region. The insulation layer is disposed on the dielectric layer. The mask layer is disposed on the dielectric layer and covers the insulation layer and the mask layer includes an opening to expose the connection region of the pad. | 02-10-2011 |
20110031625 | Method of Processing a Contact Pad, Method of Manufacturing a Contact Pad, and Integrated Circuit Element - An integrated circuit includes a substrate. A surface region of the substrate includes a contact pad region. A passivation layer stack includes at least one passivation layer. The passivation layer stack is formed over the surface region and adjacent to the contact pad region. An upper portion of the passivation layer stack is removed in, in a portion of the passivation layer stack proximate the contact pad region. | 02-10-2011 |
20110233782 | ELECTRONIC DEVICE PACKAGE AND FABRICATION METHOD THEREOF - An electronic device package is disclosed. The package includes at least one semiconductor chip having a first surface and a second surface opposite thereto, in which at least one redistribution layer is disposed on the first surface of the semiconductor chip and is electrically connected to at least one conductive pad structure. At least one abut portion is disposed on the redistribution layer and electrically contacting thereto. A passivation layer covers the first surface of the semiconductor chip and surrounds the abut portion. A substrate is attached onto the second surface of the semiconductor chip. A fabrication method of the electronic device package is also disclosed. | 09-29-2011 |
20110285022 | INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME - A method for fabricating an integrated circuit (IC) chip includes forming a metal trace having a thickness of between 5 μm and 27 μm over a semiconductor substrate, and forming a passivation layer on the metal trace, wherein the passivation layer includes a layer of silicon nitride on the metal trace and a layer of silicon oxide on the layer of silicon nitride, or includes a layer of silicon oxynitride on the metal trace and a layer of silicon oxide on the layer of silicon oxynitride. | 11-24-2011 |
20120013010 | BONDING PAD FOR ANTI-PEELING PROPERTY AND METHOD FOR FABRICATING THE SAME - A bonding pad includes a conductive layer formed over an insulation layer, and a dummy pattern penetrating the insulation layer and stuck in the conductive layer, wherein a bonding process is performed. | 01-19-2012 |
20120098133 | STRUCTURE AND METALLIZATION PROCESS FOR ADVANCED TECHNOLOGY NODES - The problem of poor adherence of a dielectric coating on a patterned metal structure can be solved by forming an adhesion layer on exposed surfaces of such metal structure prior to deposition of such dielectric. According to an embodiment, the invention provides a method to form a self-aligned adhesion layer on the surface of metal interconnect structure within an integrated circuit by exposing the metal structure to a controlled atmosphere and a flow of nitrogen-containing gas. | 04-26-2012 |
20120112348 | DEVICES, METHODS, AND SYSTEMS FOR WAFER BONDING - Devices, methods, and systems for wafer bonding are described herein. One or more embodiments include forming a bond between a first wafer and a second wafer using a first material adjacent the first wafer and a second material adjacent the second wafer. The first material includes a layer of gold (Au) and a layer of indium (In), and the second material includes a layer of Au. Forming the bond between the first wafer and the second wafer includes combining the layer of Au in the first material, the layer of In in the first material, and a portion of the layer of Au in the second material, wherein an additional portion of the layer of Au in the second material is not combined with the layer of Au in the first material and the layer of In in the first material. | 05-10-2012 |
20120161323 | SUBSTRATE FOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein are a substrate for a package and a method for manufacturing the same. The substrate for the package according to the present invention includes: a base substrate; a photosensitive insulating layer formed on one surface of the base substrate and having a roughness formed on a surface thereof; and a seed layer formed on one surface of the photosensitive insulating layer. | 06-28-2012 |
20120175777 | DEVICE HAVING CONDUCTIVE SUBSTRATE VIA WITH CATCH-PAD ETCH-STOP - An electronic device ( | 07-12-2012 |
20120193795 | SEMICONDUCTOR DEVICE HAVING AN AIRBRIDGE AND METHOD OF FABRICATING THE SAME - A method of forming a device having an airbridge on a substrate includes forming a plated conductive layer of the airbridge over at least a photoresist layer on a portion of the substrate, the plated conductive layer defining a corresponding opening for exposing a portion of the photoresist layer. The method further includes undercutting the photoresist layer to form a gap in the photoresist layer beneath the plated conductive layer at the opening, and forming an adhesion layer on the plated conductive layer and the exposed portion of the photoresist layer, the adhesion layer having a break at the gap beneath the plated conductive layer. The photoresist layer and a portion of the adhesion layer formed on the exposed portion of the photoresist layer is removed, which includes etching the photoresist layer through the break in the adhesion layer. An insulating layer is formed on at least the adhesion layer, enhancing adhesion of the insulating layer to the plated conductive layer. | 08-02-2012 |
20120205808 | MEMS and Protection Structure Thereof - A protection structure of a pad is provided. The pad is disposed in a dielectric layer on a semiconductor substrate and the pad includes a connection region and a peripheral region which encompasses the connection region. The protection structure includes at least a barrier, an insulation layer and a mask layer. The barrier is disposed in the dielectric layer in the peripheral region. The insulation layer is disposed on the dielectric layer. The mask layer is disposed on the dielectric layer and covers the insulation layer and the mask layer includes an opening to expose the connection region of the pad. | 08-16-2012 |
20120292770 | METHOD AND DEVICE FOR PREVENTING CORROSION ON SENSORS - A device for preventing corrosion on sensors and a method of fabricating the same is disclosed, wherein the device comprises an insulation layer and an adhesion layer covering a metallization layer of a silicon sensor with a corrosion resistant layer located over the adhesion layer. | 11-22-2012 |
20120292771 | FABRICATING A CONTACT RHODIUM STRUCTURE BY ELECTROPLATING AND ELECTROPLATING COMPOSITION - A contact rhodium structure is fabricated by a process that comprises obtaining a substrate having a dielectric layer thereon, wherein the dielectric layer has cavities therein into which the contact rhodium is to be deposited; depositing a seed layer in the cavities and on the dielectric layer; and depositing the rhodium by electroplating from a bath comprising a rhodium salt; an acid and a stress reducer; and then optionally annealing the structure. | 11-22-2012 |
20130026632 | SEMICONDUCTOR ELEMENT-EMBEDDED WIRING SUBSTRATE - A wiring substrate in which a semiconductor element is built includes a semiconductor element; a peripheral insulating layer covering at least an outer circumferential side surface of this semiconductor element; and an upper surface-side wiring line provided on the upper surface side of the wiring substrate. The semiconductor element includes an internal terminal electrically connected to the upper surface-side wiring line on the upper surface side of the semiconductor element. This internal terminal includes a first conductive part exposed out of an insulating surface layer of the semiconductor element; an adhesion layer on this first conductive part; and a second conductive part on this adhesion layer. The adhesion layer covers an exposed surface of the first conductive part, and is formed on a portion of the insulating surface layer around the exposed surface of the first conductive part, and the adhesion layer extends around the outer side of an outer edge of this second conductive part so as to surround the second conductive part. | 01-31-2013 |
20130075912 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a method for manufacturing a semiconductor device includes: forming a silicon oxide film on a semiconductor substrate; forming a via in the silicon oxide film; forming a contact layer inside the via; forming a silicon layer on the contact layer; and forming a tungsten film embedded in the via by making a tungsten-containing gas react with the silicon layer. | 03-28-2013 |
20130113106 | THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT WITH ENHANCED COPPER-TO-COPPER BONDING - At least one metal adhesion layer is formed on at least a Cu surface of a first device wafer. A second device wafer having another Cu surface is positioned atop the Cu surface of the first device wafer and on the at least one metal adhesion layer. The first and second device wafers are then bonded together. The bonding includes heating the devices wafers to a temperature of less than 400° C., with or without, application of an external applied pressure. During the heating, the two Cu surfaces are bonded together and the at least one metal adhesion layer gets oxygen atoms from the two Cu surfaces and forms at least one metal oxide bonding layer between the Cu surfaces. | 05-09-2013 |
20130168864 | METHOD FOR PRODUCING ULTRA-THIN TUNGSTEN LAYERS WITH IMPROVED STEP COVERAGE - A tungsten nucleation film is formed on a surface of a semiconductor substrate by alternatively providing to that surface, reducing gases and tungsten-containing gases. Each cycle of the method provides for one or more monolayers of the tungsten film. The film is conformal and has improved step coverage, even for a high aspect ratio contact hole. | 07-04-2013 |
20130193579 | STRUCTURE FOR NANO-SCALE METALLIZATION AND METHOD FOR FABRICATING SAME - A method for forming structure aligned with features underlying an opaque layer is provided for an interconnect structure, such as an integrated circuit. In one embodiment, the method includes forming an opaque layer over a first layer, the first layer having a surface topography that maps to at least one feature therein, wherein the opaque layer is formed such that the surface topography is visible over the opaque layer. A second feature is positioned and formed in the opaque layer by reference to such surface topography. | 08-01-2013 |
20130200520 | THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT WITH ENHANCED COPPER-TO-COPPER BONDING - At least one metal adhesion layer is formed on at least a Cu surface of a first device wafer. A second device wafer having another Cu surface is positioned atop the Cu surface of the first device wafer and on the at least one metal adhesion layer. The first and second device wafers are then bonded together. The bonding includes heating the devices wafers to a temperature of less than 400° C., with or without, application of an external applied pressure. During the heating, the two Cu surfaces are bonded together and the at least one metal adhesion layer gets oxygen atoms from the two Cu surfaces and forms at least one metal oxide bonding layer between the Cu surfaces. | 08-08-2013 |
20140001636 | ELECTRONIC COMPONENT AND METHOD OF MANUFACTURING ELECTRONIC COMPONENT | 01-02-2014 |
20140061921 | GOLD BONDING IN SEMICONDUCTOR DEVICES USING POROUS GOLD - A method of manufacturing comprising providing a semiconductor layer having metal adhesion layer on a planar surface of the semiconductor layer and an alloy layer on the metal adhesion layer, the alloy layer comprising an alloy of gold and a non-gold metal. The method comprises removing a portion of the non-gold metal from the alloy layer to form a porous gold layer. The method comprises applying pressure between the porous gold layer and a metal layer to form a bond between the semiconductor layer and the metal layer. | 03-06-2014 |
20140097540 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a silicon substrate, a titanium layer, a nickel layer, a silver layer and a metallic adhesion layer, wherein the silicon substrate comprises a back surface, and the titanium layer comprises an upper surface. The titanium layer is formed on the back surface, the nickel layer is formed on the upper surface, the silver layer is formed on the nickel layer, and the metallic adhesion layer is formed between the nickel layer and the silver layer. | 04-10-2014 |
20140203437 | Method Of Semiconductor Integrated Circuit Fabrication - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A patterned adhesion layer is formed on the substrate. A metal layer is deposited on the patterned adhesion layer. An elevated temperature thermal process is applied to agglomerate the metal layer to form a self-forming-metal-feature (SFMF) and a dielectric layer is deposited between SFMFs. | 07-24-2014 |
20140246776 | DOPING OF COPPER WIRING STRUCTURES IN BACK END OF LINE PROCESSING - A method of forming a metal interconnect structure includes forming a copper line within an interlevel dielectric (ILD) layer; directly doping a top surface of the copper line with a copper alloy material; and forming a dielectric layer over the ILD layer and the copper alloy material; wherein the copper alloy material serves an adhesion interface layer between the copper line and the dielectric layer. | 09-04-2014 |
20150041982 | STACKED REDISTRIBUTION LAYERS ON DIE - Some implementations provide a semiconductor device (e.g., die) that includes a substrate, several metal layers and dielectric layers coupled to the substrate, a pad coupled to one of the plurality of metal layers, a first metal redistribution layer coupled to the pad, and a second metal redistribution layer coupled to the first metal redistribution layer. The second metal redistribution layer includes a cobalt tungsten phosphorous material. In some implementations, the first metal redistribution layer is a copper layer. In some implementations, the semiconductor device further includes a first underbump metallization (UBM) layer and a second underbump metallization (UBM) layer. | 02-12-2015 |
20150041983 | SEMICONDUCTOR-DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - Provided are a semiconductor device and semiconductor-device manufacturing method that make it possible to improve the contact between an insulating film and a wiring member and the reliability thereof. This method for manufacturing a semiconductor device ( | 02-12-2015 |
20150076698 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad. | 03-19-2015 |
20150325484 | METAL-SEMICONDUCTOR CONTACT STRUCTURE WITH DOPED INTERLAYER - Disclosed herein is a method of forming a metal-to-semiconductor contact with a doped metal oxide interlayer. An insulating layer is formed on a top surface of a semiconductor substrate with target region at the top surface of the semiconductor substrate. An opening is etched through the insulating layer with the opening exposing a top surface of a portion of the target region. A doped metal oxide interlayer is formed in the opening and contacts the top surface of the target region. The remainder of the opening is filled with a metal plug, the doped metal oxide interlayer disposed between the metal plug and the substrate. The doped metal oxide interlayer is formed from one of tin oxide, titanium oxide or zinc oxide and is doped with fluorine. | 11-12-2015 |
20150333010 | BOND PAD HAVING RUTHENIUM DIRECTLY ON PASSIVATION SIDEWALL - A method of forming bond pads includes providing a substrate including an integrated circuit (IC) device formed thereon having an oxidizable uppermost metal interconnect layer which provides a plurality of bond pads that are coupled to circuit nodes on the IC device. The plurality of bond pads include a metal bond pad area. At least one passivation layer provides a trench including dielectric sidewalls above the metal bond pad area. A ruthenium (Ru) layer is deposited directly on the dielectric sidewalls and directly on the metal bond pad area, which removes the need for a barrier layer lining the dielectric sidewalls of the trench. The Ru layer is patterned to provide a bond pad surface for the plurality of bond pads. | 11-19-2015 |
20160005647 | Contacts for Semiconductor Devices and Methods of Forming Thereof - A method for a method of forming a semiconductor device includes providing a semiconductor substrate having a bottom surface opposite a top surface with circuitry disposed at the top surface. The method further includes forming a first metal layer having a first metal over the bottom surface of the semiconductor substrate. The first metal layer is formed by depositing an adhesion promoter followed by depositing the first metal. | 01-07-2016 |
20160035620 | METHOD FOR FORMING SEED LAYER ON HIGH-ASPECT RATIO VIA AND SEMICONDUCTOR DEVICE HAVING HIGH-ASPECT RATIO VIA FORMED THEREBY - Disclosed are a method of forming a seed layer on a high-aspect ratio via and a semiconductor device having a high-aspect ratio via formed thereby. Thus, efficient Cu filling-plating is possible, and plating adhesion of the seed layer to filling-plated Cu can be simply and profitably enhanced, thus imparting high durability upon forming metal wiring for electronic components. Moreover, stress of the seed layer can be lowered, thereby enhancing plating adhesion. | 02-04-2016 |
20160043050 | Metallization stack and chip arrangement - A metallization stack for a chip arrangement is provided, wherein the metallization stack comprises a first metallic layer; a plating layer comprising an alloy comprising nickel and zinc arranged over the first metallic structure; and a second metallic layer arranged over the plating layer. | 02-11-2016 |
20160056121 | Metallized electric component - Various embodiments provide a metallized electric component for an electronic module, wherein the metallized electric component comprises a conductive electric element; and a metallization structure arranged over the conductive electric element and comprising at least a surface metallization layer, wherein the surface metallization layer comprises gold and silver and has a thickness between 2 nm and 100 nm. | 02-25-2016 |
20160079176 | SEMICONDUCTOR DEVICE - According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming a first film having a first melting point, forming a pattern of a second film on an upper surface of the first film, the second film having a second melting point lower than the first melting point, and forming a graphene film on the upper surface of the first film, the graphene film being formed from a side surface of the pattern of the second film. | 03-17-2016 |
20160104669 | SEMICONDUCTOR STRUCTURE WITH IMPROVED METALLIZATION ADHESION AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure is disclosed. The semiconductor structure may include a substrate, a first layer formed on a first side of the substrate and second layer formed over the first layer. The second layer may include a plurality of substantially pointed structures which interpenetrate through the first layer and extend into the substrate. A method for manufacturing a semiconductor structure is likewise disclosed. | 04-14-2016 |
20160108254 | ZINC IMMERSION COATING SOLUTIONS, DOUBLE-ZINCATE METHOD, METHOD OF FORMING A METAL PLATING FILM, AND SEMICONDUCTOR DEVICE - Invention provides a zinc immersion coating solution used in the double-zincate method for applying first and second zinc immersion coating treatments to aluminum or aluminum alloy. Zinc immersion coating solution used for first zinc immersion coating treatment at least contains a zinc compound, alkali hydroxide, iron salt, chelating agent for complexation of iron ions, and zinc immersion coating inhibitor that is at least one out of the group consisting of a polymer of a secondary amine, polymer of a tertiary amine, and polymer of a quaternary amine, or copolymer containing the same, and zinc immersion coating solution used for second zinc immersion coating treatment at least contains a zinc compound, alkali hydroxide, iron salt, chelating agent for complexation of iron ions, and zinc immersion coating inhibitor that is at least one out of the group consisting of a primary and secondary amines, and a tertiary amine. | 04-21-2016 |
20160118337 | EMBEDDED PACKAGES, METHODS OF FABRICATING THE SAME, ELECTRONIC SYSTEMS INCLUDING THE SAME, AND MEMORY CARDS INCLUDING THE SAME - An embedded package includes a chip having a top surface on which a connection member is disposed, a first insulation layer surrounding a portion of the chip, a second insulation layer disposed on the first insulation layer to cover the chip, circuit patterns disposed on a bottom surface of the first insulation layer, a third insulation layer disposed on the bottom surface of the first insulation layer to cover the circuit patterns, an external connection terminal penetrating the third insulation layer to contact any one of the circuit patterns, a metal layer disposed on a top surface of the second insulation layer, a first via penetrating the first insulation layer to electrically couple the connection member to any one of the circuit patterns, and a second via penetrating the first and second insulation layers to electrically couple the metal layer to any one of the circuit patterns. | 04-28-2016 |
20160133575 | AIR GAP STRUCTURE WITH BILAYER SELECTIVE CAP - A semiconductor substrate including one or more conductors is provided. A first layer and a second layer are deposited on the top surface of the conductors. A dielectric cap layer is formed over the semiconductor substrate and air gaps are etched into the dielectric layer. The result is a bilayer cap air gap structure with effective electrical performance. | 05-12-2016 |
20160163567 | SUBSTRATE SURFACE METALLIZATION METHOD AND SUBSTRATE HAVING METALLIZED SURFACE MANUFACTURED BY THE SAME - A coating device for coating a coating liquid onto a substrate includes: a coating head having a coating-liquid outlet, adapted to move with respect to the substrate along a first axial direction and capable of coating the substrate with coating liquid through the coating-liquid outlet; and adjustment unit connected to the coating head and including a movable pad disposed proximal to the coating-liquid outlet and adapted to move along a second axial direction for adjusting the size of the opening of the coating-liquid outlet; and a drive assembly connected to the adjustment unit for controlling the adjustment unit to move along the second axial direction. Additionally a coating method is provided. | 06-09-2016 |
20180026157 | Ultraviolet Reflective Rough Adhesive Contact | 01-25-2018 |