Entries |
Document | Title | Date |
20080197496 | Semiconductor device having at least two layers of wirings stacked therein and method of manufacturing the same - A semiconductor device according to the present invention is a semiconductor device having a first wiring formed in a first insulating layer and a second wiring formed in a second insulating layer formed on the first insulating layer and the first wiring. Here, at least one of the first wiring and the second wiring is a CuAl wiring. The second wiring is electrically connected to the first wiring at its via-plug portion, with a plurality of barrier layers interposed between the second wiring and the first wiring. In the barrier layers, a CuAl-contact barrier layer which is in contact with the CuAl wiring has a nitrogen atom content of less than 10 atomic %. Therefore, the present semiconductor device has high reliability and small variations in initial via resistance value. | 08-21-2008 |
20080197497 | BARRIER FOR USE IN 3-D INTEGRATION OF CIRCUITS - A method for forming a semiconductor device includes providing a first integrated circuit having a landing pad and attaching a second integrated circuit to the first integrated circuit using at least one bonding layer. The second integrated circuit has an inter-circuit trace, the inter-circuit trace has an inter-circuit trace opening. The method further includes forming an opening through the second integrated circuit, the opening extending through the inter-circuit trace opening, forming a selective barrier on exposed portions of the inter-circuit trace in the opening, extending the opening through the at least one bonding layer to the landing pad, and filling the opening with a conductive fill material. The selective barrier layer comprises at least one of cobalt or nickel, and the conductive fill material electrically connects the inter-circuit trace and the landing pad. | 08-21-2008 |
20080203570 | STRUCTURE INCLUDING VIA HAVING REFRACTORY METAL COLLAR AT COPPER WIRE AND DIELECTRIC LAYER LINER-LESS INTERFACE AND RELATED METHOD - Structures including a refractory metal collar at a copper wire and dielectric layer liner-less interface, and a related method, are disclosed. In one embodiment, a structure includes a copper wire having a liner-less interface with a dielectric layer thereabove; a via extending upwardly from the copper wire through the dielectric layer; and a refractory metal collar extending from a side of the via and partially along the liner-less interface. Refractory metal collar prevents electromigration induced slit voiding by improving the interface around the via, and prevents void nucleation from occurring near the via. Also, the refractory metal collar provides electrical redundancy in the presence of voids around the via and dielectric layer liner-less interface. | 08-28-2008 |
20080203571 | BACKSIDE METALLIZATION FOR INTEGRATED CIRCUIT DEVICES - A method of forming backside metallization on a substrate that includes a plurality of integrated circuit die formed on a front side of the substrate is disclosed. The method includes forming an adhesion layer of aluminum or an aluminum alloy on a backside surface of the substrate, forming a barrier metal layer on the adhesion layer and forming a metal layer on the barrier metal layer. An integrated circuit device is also disclosed which includes a substrate having an integrated circuit die formed on a front side of the substrate, an adhesion layer on a backside surface of the substrate, wherein the adhesion layer is aluminum or an aluminum alloy, a barrier metal layer on the adhesion layer and a metal layer on the barrier metal layer. | 08-28-2008 |
20080203572 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - The present invention provides a semiconductor device having interconnects, reduced in leakage current between the interconnects and improved in the TDDB characteristic, which comprises an insulating interlayer | 08-28-2008 |
20080211096 | Switching Element and Reconfigurable Logic Integrated Circuit - A switching element is of a configuration that includes: an ion conduction layer ( | 09-04-2008 |
20080211097 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes an insulating interlayer formed above a silicon substrate and provided with a concave portion in a certain location, a barrier metal film covering an inner wall of the insulating interlayer, a lower layer copper interconnect provided so as to be in contact with the barrier metal film and buried in the interior of the concave portion, and a protective film provided so as to be in contact with the lower layer copper interconnect and also provided on substantially the entire top surface of the lower layer copper interconnect. An upper surface of the lower layer copper interconnect is provided so as to be retracted to be closer to the substrate than an upper surface of barrier metal film on the side wall of the concave portion. The protective film contains Co or Ni as constituent element, and Co concentration or Ni concentration in the protective film in vicinity of the side wall of the barrier metal film is higher than Co concentration or Ni concentration in the barrier metal film in the central region of the concave portion. | 09-04-2008 |
20080211098 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device in which the resistance of a copper wiring to electromigration is increased. The copper wiring is formed so that copper grains will be comparatively large in a central portion of the copper wiring and so that copper grains will be comparatively small in an upper portion and a lower portion of the metal wiring. The copper wiring having this structure is formed by a damascene method. This structure can be formed by controlling electric current density at electroplating time. With the copper wiring having this structure, it is easier for an electric current to run through the central portion than to run through the upper portion. As a result, the diffusion of copper atoms in the upper portion is suppressed and therefore the diffusion of copper atoms from an interface between the copper wiring and a cap film is suppressed. | 09-04-2008 |
20080211099 | SEMICONDUCTOR DEVICE - A semiconductor device ( | 09-04-2008 |
20080211100 | METHOD AND STRUCTURE FOR REDUCING CONTACT RESISTANCE BETWEEN SILICIDE CONTACT AND OVERLYING METALLIZATION - A semiconductor structure in which the contact resistance in the contact opening is reduced as well as a method of forming the same are provided. This is achieved in the present invention by replacing conventional contact metallurgy, such as tungsten, or a metal silicide, such as Ni silicide or Cu silicide, with a metal germanide-containing contact material. The term “metal germanide-containing” is used in the present application to denote a pure metal germanide (i.e., MGe alloy) or a metal germanide that includes Si (i.e., MSiGe alloy). | 09-04-2008 |
20080217775 | Method of forming contact plugs for eliminating tungsten seam issue - A method of forming a contact plug of an eDRAM device includes the following steps: forming a tungsten layer with tungsten seam on a dielectric layer to fill a contact hole; removing the tungsten layer from the top surface of the dielectric layer, recessing the tungsten layer in the contact hole to form a recess of about 600˜900 Angstroms in depth below the top surface of the dielectric layer, depositing a conductive layer on the dielectric layer and the recessed tungsten plug to fill the recess; and removing the conductive layer from the top surface of the dielectric layer to form a conductive plug on the recessed tungsten plug in the contact hole. | 09-11-2008 |
20080217776 | Process for manufacturing integrated circuits formed on a semiconductor substrate and comprising tungsten layers - An embodiment is described for manufacturing integrated circuits formed on a semiconductor substrate, which embodiment comprises forming a cobalt suicide layer on said semiconductor substrate, forming a layer comprising tungsten on said silicide layer, said cobalt suicide layer forming a barrier against the migration of the silicon atoms of said semiconductor substrate during the formation step of said layer comprising tungsten. An embodiment is also described for manufacturing contacts comprising tungsten of an integrated circuit formed on a semiconductor substrate. | 09-11-2008 |
20080217777 | EMBEDDED BARRIER FOR DIELECTRIC ENCAPSULATION - A semiconductor interconnect structure and method providing an embedded barrier layer to prevent damage to the dielectric material during or after Chemical Mechanical Polishing. The method employs a combination of an embedded film, etchback, using either selective CoWP or a conformal cap such as a SiCNH film, to protect the dielectric material from the CMP process as well as subsequent etch, clean and deposition steps of the next interconnect level. | 09-11-2008 |
20080224316 | Electronic device and method for producing electronic devices - An explanation is given of, inter alia, an electronic device ( | 09-18-2008 |
20080230904 | Gallium Nitride-Based III-V Group Compound Semiconductor Device and Method of Manufacturing the Same - The present invention relates to a gallium nitride-based compound semiconductor device and a method of manufacturing the same. According to the present invention, there is provided a gallium nitride-based III-V group compound semiconductor device comprising a gallium nitride-based semiconductor layer and an ohmic electrode layer formed on the gallium nitride-based semiconductor layer. The ohmic electrode layer comprises a contact metal layer, a reflective metal layer, and a diffusion barrier layer. | 09-25-2008 |
20080230905 | Power Semiconductor Module, Method for Producing a Power Semiconductor Module, and Semiconductor Chip - In a power semiconductor module, a copper-containing first soldering partner, a connection layer, and a copper-containing second soldering partner are arranged successively and fixedly connected with one another. The connection layer has a portion of intermetallic copper-tin phases of at least 90% by weight. For producing such a power semiconductor module the soldering partners and the solder arranged there between are pressed against one another with a predefined pressure and the solder is melted. After termination of a predefined period of time the diffused copper and the tin from the liquid solder form a connection layer comprising intermetallic copper-tin phases, the portion of which is at least 90% by weight of the connection layer created from the solder layer. | 09-25-2008 |
20080230906 | CONTACT STRUCTURE HAVING DIELECTRIC SPACER AND METHOD - A contact structure and method of forming same are disclosed. The contact structure may include a metal body surrounded by a dielectric spacer, the metal body and the dielectric spacer positioned within an interlevel dielectric layer, wherein the metal body is electrically coupled to a silicide region below a lowermost portion of the metal body. | 09-25-2008 |
20080230907 | INTEGRATED CIRCUIT SYSTEM WITH CARBON ENHANCEMENT - An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; forming a via opening through the low-K dielectric layer to the interconnect layer; and forming a carbon implant region around the via opening, a trench opening, or a combination thereof, for protecting the low-K dielectric layer. | 09-25-2008 |
20080230908 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a pad that is formed on a semiconductor layer, contains Al, and has an interconnection portion that is formed outside a bonding area; an interconnection layer that contains Au and is electrically connected to the interconnection portion of the pad, an edge of the interconnection layer being formed outside of the bonding area; and a barrier layer that is provided between the interconnection portion and the interconnection layer. | 09-25-2008 |
20080237859 | DIFFUSION BARRIER FOR INTEGRATED CIRCUITS FORMED FROM A LAYER OF REACTIVE METAL AND METHOD OF FABRICATION - An interconnect structure for an integrated circuit and method of forming the interconnect structure. The method includes depositing a metallic layer containing a reactive metal in an interconnect opening formed within a dielectric material containing a dielectric reactant element, thermally reacting at least a portion of the metallic layer with at least a portion of the dielectric material to form a diffusion barrier primarily containing a compound of the reactive metal from the metallic layer and the dielectric reactant element from the dielectric material, and filling the interconnect opening with Cu metal, where the diffusion barrier surrounds the Cu metal within the opening. The reactive metal can be Co, Ru, Mo, W, or Ir, or a combination thereof. The interconnect opening can be a trench, a via, or a dual damascene opening. | 10-02-2008 |
20080237860 | INTERCONNECT STRUCTURES CONTAINING A RUTHENIUM BARRIER FILM AND METHOD OF FORMING - Embodiments of the invention provide a method for integrating a Ru barrier film with good barrier properties into Cu metallization. The method includes exposing a substrate to a Ta-, Ti-, or W-containing precursor at a substrate temperature below the thermal decomposition temperature of the Ta-, Ti-, or W-containing precursor on the substrate to form a chemisorbed seed layer of partially decomposed Ta-, Ti-, or W-containing precursor on the substrate. The method further includes depositing a Ru barrier film on the chemisorbed seed layer, and forming bulk Cu metal on the Ru barrier film. According to additional embodiments, an interconnect structure and method of forming are provided. | 10-02-2008 |
20080237861 | Novel Fluorine-Free Precursors and Methods for the Deposition of Conformal Conductive Films for Nanointerconnect Seed and Fill - A method including introducing a fluorine-free organometallic precursor in the presence of a substrate; and forming a conductive layer including a moiety of the organometallic precursor on the substrate according to an atomic layer or chemical vapor deposition process. A method including forming an opening through a dielectric layer to a contact point; introducing a fluorine-free copper film precursor and a co-reactant; and forming a copper-containing seed layer in the opening. A system including a computer including a microprocessor electrically coupled to a printed circuit board, the microprocessor including conductive interconnect structures formed from fluorine-free organometallic precursor. | 10-02-2008 |
20080237862 | Implementation of diffusion barrier in 3D memory - One or more diffusion barriers are formed around one or more conductors in a three dimensional or 3D memory cell. The diffusion barriers allow the conductors to comprise very low resistivity materials, such as copper, that may otherwise out diffuse into surrounding areas, particularly at elevated processing temperatures. Utilizing lower resistivity materials allows device dimension to be reduced by mitigating increases in resistance that occur when the size of the conductors is reduced. As such, more cells can be produced over a given area, thus increasing the density and storage capacity of a resulting memory array. | 10-02-2008 |
20080237863 | Semiconductor device and manufacturing method of semiconductor device - A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided. | 10-02-2008 |
20080237864 | METAL INTERCONNECTION STRUCTURE OF A SEMICONDUCTOR DEVICE HAVING LOW RESISTANCE AND METHOD OF FABRICATING THE SAME - Provided is a metal interconnection structure of a semiconductor device, including a first metal film pattern disposed on an upper part of an insulation film of a semiconductor substrate; an intermetallic dielectric film having a metal contact plug in which a barrier layer, a metal film for contact plug and a second metal film are sequentially disposed, on the first metal film pattern; and a second metal film pattern disposed on the metal contact plug and intermetallic dielectric film and connected to the metal contact plug. | 10-02-2008 |
20080246149 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING DEVICE ISOLATION FILM OF SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device comprises growing a carbon nano tube (CNT) in a contact hole to form a contact plug, thereby preventing diffusion of a tungsten layer. The method does not require forming a titanium nitride (TiN) film deposited to improve an adhesive strength. The CNT has an excellent electric conductivity and a high mechanical strength to improve characteristics of the device. | 10-09-2008 |
20080246150 | FORMATION OF A MASKING LAYER ON A DIELECTRIC REGION TO FACILITATE FORMATION OF A CAPPING LAYER ON ELECTRICALLY CONDUCTIVE REGIONS SEPARATED BY THE DIELECTRIC REGION - Devices are presented including: a substrate including a dielectric region and a conductive region; a molecular self-assembled layer selectively formed on the dielectric region; and a capping layer formed on the conductive region, where the capping layer is an electrically conductive material such as: an alloy of cobalt and boron material, an alloy of cobalt, tungsten, and phosphorous material, an alloy of nickel, molybdenum, and phosphorous. In some embodiments, devices are presented where the molecular self-assembled layer includes one or more of a polyelectrolyte, a dendrimer, a hyper-branched polymer, a polymer brush, a block co-polymer, and a silane-based material where the silane-based material includes one or more hydrolysable substituents of a general formula R | 10-09-2008 |
20080246151 | INTERCONNECT STRUCTURE AND METHOD OF FABRICATION OF SAME - A damascene wire and method of forming the wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing the sidewalls of the trench under the mask layer; forming a conformal conductive liner on all exposed surface of the trench and the mask layer; filling the trench with a core electrical conductor; removing portions of the conductive liner extending above the top surface of the dielectric layer and removing the mask layer; and forming a conductive cap on a top surface of the core conductor. The structure includes a core conductor clad in a conductive liner and a conductive capping layer in contact with the top surface of the core conductor that is not covered by the conductive liner. | 10-09-2008 |
20080251919 | Ultra-low resistance interconnect - A method for fabricating a semiconductor interconnect device. A preferred embodiment comprises forming a low-k or very low-k dielectric layer on a wafer substrate and forming a recess in the dielectric layer that exposes a region on the substrate to which electrical contact is desired. A barrier layer is formed by first forming an organic layer on the walls of the substrate, then forming a catalyst metal layer on the organic layer, and finally forming a barrier metal layer over the catalyst layer. The remainder of the recess formed in the dielectric layer is then filled with a conductive material such as copper that will function as the main electrical connector to the contact region on the substrate. | 10-16-2008 |
20080251920 | Dielectric film forming method - In a film forming sequence for a HDP-CVD oxide film, Ar gas is introduced into a reactive chamber and then source power (or RF power) is applied to excite plasma. After that, a carrier gas (He) is introduced into the reactive chamber. After a semiconductor substrate is heated by plasma of the Ar and He gasses, introduction of the Ar gas is stopped. Subsequently, SiH | 10-16-2008 |
20080251921 | Structure for a Semiconductor Device and a Method of Manufacturing the Same - There is described a method of manufacturing a damascene interconnect ( | 10-16-2008 |
20080258302 | Methods of forming a denuded zone in a semiconductor wafer using rapid laser annealing - Methods for forming a denuded zone in an oxygen-containing semiconductor wafer using rapid laser annealing (RLA) are disclosed. The method includes scanning an intense beam of laser radiation over the surface of the wafer to raise the temperature of each point on the wafer surface to be at or near the wafer's melting temperature for a time period on the order of a millisecond or so. This rapid heating and cooling causes oxygen in the wafer near the wafer surface to diffuse out from the wafer surface. Oxygen in the body of the wafer remains unheated and thus does not diffuse toward the wafer surface. The result is an oxygen-depleted zone—called a “denuded zone”—formed immediately adjacent the wafer surface. The methods further include forming a semiconductor device feature in the denuded zone such as by implanting the wafer with dopants. | 10-23-2008 |
20080258303 | Novel structure for reducing low-k dielectric damage and improving copper EM performance - A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a dielectric layer; a chemical mechanical polish (CMP) stop layer on the dielectric layer; a conductive wiring in the dielectric layer; and a metal cap over the conductive wiring. | 10-23-2008 |
20080258304 | Semiconductor device having multiple wiring layers - A semiconductor device includes: a substrate; and wiring layers on the substrate. Each wiring layer includes: an interlayer insulation film having a wiring groove with a via hole; a copper wiring in the groove and the hole; an barrier metal layer between an inner wall of the groove with the hole and the copper wiring; and an upper barrier metal layer on the interlayer insulation film and covering an upper surface of the copper wiring. The barrier metal layer prevents a copper component in the copper wiring from diffusing into the interlayer insulation film. The copper wiring of an upper layer is electrically coupled with the copper wiring of a lower layer. The upper barrier metal layer of the lower layer prevents a copper component in the copper wiring of the lower layer from diffusing into the interlayer insulation film of the upper layer. | 10-23-2008 |
20080265416 | Metal line formation using advaced CMP slurry - An integrated circuit and methods for forming the same are provided. The method includes providing a semiconductor substrate; forming a low-k dielectric layer over the semiconductor substrate; forming an opening extending from a top surface of the low-k dielectric layer into the low-k dielectric layer; forming a diffusion barrier layer in the opening, wherein the diffusion barrier layer has a top edge substantially level with a top surface of the low-k dielectric layer; filling a metal line in the opening; recessing a top surface of the metal line below a top edge of the diffusion barrier layer to form a recess; and forming a metal cap on the metal line, wherein the metal cap is substantially within the recess. | 10-30-2008 |
20080265417 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device, includes the steps of forming an insulating film on a semiconductor substrate having a silicide layer, forming a hole in the insulating film on the silicide layer, cleaning an inside of the hole and a surface of the silicide layer, forming a titanium layer on a bottom surface and an inner peripheral surface of the hole by a CVD method, forming a copper diffusion preventing barrier metal layer on the titanium layer in the hole, and burying a copper layer in the hole. | 10-30-2008 |
20080265418 | Method of Manufacturing Semiconductor Device, and Semiconductor Device - A semiconductor device including a substrate, a metal wiring on the substrate, an insulation film on the substrate covering the metal wiring, a connection hole in the insulation film which extends to a portion of the metal wiring, a via in the connection hole, and an alloy layer. The metal wiring includes a first metallic material, the alloy layer comprises a portion of the metal wiring and a second metallic material which is different than the first metallic material, and the via extends to the alloy layer. | 10-30-2008 |
20080272490 | Semiconductor device including ruthenium electrode and method for fabricating the same - A semiconductor device includes a semiconductor substrate, an insulation pattern on the semiconductor substrate, and an etch stop layer on the insulating pattern, the insulation pattern and the etch stop layer defining a contact hole that exposes the substrate, a first plug filled in a portion of the contact hole, a diffusion barrier layer formed above the first plug and in a bottom portion and on sidewalls of a remaining portion of the contact hole, a second plug formed on the diffusion barrier layer and filled in the contact hole, and a storage node coupled to and formed on the second plug. | 11-06-2008 |
20080272491 | MANUFACTURING OF A SEMICONDUCTOR DEVICE AND THE MANUFACTURING METHOD - A technology that improves the reliability of a semiconductor device and realizes a high performance by a laminated structure that has enough barrier properties against copper, reduces the wire delay time by lowering the capacitance between wirings and improves the adhesion between wirings is provided. There is a semiconductor device having: a first copper wiring layer, a first barrier layer on the first copper wiring layer, a silicon oxide series porous insulating layer on the first barrier layer, a second barrier layer on the silicon oxide series porous insulating layer, and a second copper wiring layer on the second barrier layer, wherein at least one of the first barrier layer and the second barrier layer consists of an amorphous carbon film, wherein a silicon oxide series insulating layer is directly connected between the amorphous carbon film and any of the first copper wiring layer or the second copper wiring layer. | 11-06-2008 |
20080277788 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE, AND SAID SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device has forming a first metal wire in a groove formed in an insulating film on a semiconductor substrate, forming an interlayer dielectric on the insulating film and the first metal wire, forming a via hole by etching the interlayer dielectric, forming a first barrier metal on sidewalls of the via hole, forming an organic film in the via hole having the first barrier metal formed therein, etching the first barrier metal exposed by performing an etchback on the organic film to a predetermined position, forming a trench integrally with an upper portion of the via hole by etching the interlayer dielectric to a predetermined position, forming a second barrier metal on the first barrier metal and sidewalls of the trench in the via hole, after the organic film remaining in the via hole is removed, and forming a second metal wire in the via hole and the trench having the second barrier metal formed therein. | 11-13-2008 |
20080277789 | DAMASCENE STRUCTURE AND OPENING THEREOF - A method for fabricating a single-damascene opening is described. The method includes providing a substrate having a conductive line formed therein. A barrier layer, a dielectric layer, a metal hard mask layer, a silicon oxynitride layer, a bottom antireflection layer and a patterned photoresist layer are sequentially formed on the substrate. The bottom antireflection layer, the silicon oxynitride layer and the metal hard mask layer that are not covered by the patterned photoresist layer are removed in a single process step, until a part of the surface of the dielectric layer is exposed. Thereafter, the patterned photoresist layer and the bottom antireflection layer are removed. Further using the silicon oxynitride layer and the metal hard mask layer as a mask, a portion of the dielectric layer and a portion of the barrier layer are removed to form a damascene opening that exposes the surface of the conductive line. | 11-13-2008 |
20080277790 | Semiconductor Device - A semiconductor device having a semiconductor substrate, an interlayer insulating layer formed on the substrate and having a contact hole partially exposing the substrate, and a diffusion barrier formed on the interlayer insulating layer and in the contact hole. The diffusion barrier comprises a plurality of TaSiN thin films. The present invention advantageously provides a semiconductor device with enhanced step coverage and reduced resistivity of a TaSiN layer. | 11-13-2008 |
20080277791 | Semiconductor Devices and Methods for Manufacturing the Same - Semiconductor devices having a copper line layer and methods for manufacturing the same are disclosed. An illustrated semiconductor device comprises a damascene insulating layer having a contact hole, a barrier metal layer including a first ruthenium layer, a ruthenium oxide layer and a second ruthenium layer, a seed copper layer formed on the barrier metal layer, and a copper line layer made of a Cu—Ag—Au solid solution. A disclosed example method of manufacturing a semiconductor device reduces and/or prevents contact characteristic degradation of the barrier metal layer with the silicon substrate or the damascene insulating layer. In addition, by forming the copper line layer made of the Cu—Ag—Au solid solution, long term device reliability may be improved. | 11-13-2008 |
20080284020 | SEMICONDUCTOR CONTACT STRUCTURE CONTAINING AN OXIDATION-RESISTANT DIFFUSION BARRIER AND METHOD OF FORMING - The method includes providing a patterned structure in a process chamber, where the patterned structure contains a micro-feature formed in a dielectric material and a contact layer at the bottom of the micro-feature, and depositing a metal carbonitride or metal carbide film on the patterned structure, including in the micro-feature and on the contact layer. The method further includes forming an oxidation-resistant diffusion barrier by increasing the nitrogen-content of the deposited metal carbide or metal carbide film, depositing a Ru film on the oxidation-resistant diffusion barrier, and forming bulk Cu metal in the micro-feature. A semiconductor contact structure is described. | 11-20-2008 |
20080284021 | Method for FEOL and BEOL Wiring - A method for forming a conductive structure of sub-lithographic dimension suitable for FEOL and BEOL semiconductor fabrication applications. The method includes forming a topographic feature of silicon-containing material on a substrate; forming a dielectric cap on the topographic feature; applying a mask structure to expose a pattern on a sidewall of the topographic feature, the exposed pattern corresponding to a conductive structure to be formed; depositing a metal at the exposed portions of the sidewall and forming one or more metal silicide conductive structures at the exposed sidewall portions; removing the dielectric cap layer; and removing the silicon-containing topographic feature. The result is the formation of one or more metal silicide conductor structures formed for a single lithographically defined feature. In example embodiments, the formed metal silicide conductive structures have a high aspect ratio, e.g., ranging from 1:1 to 20:1 (height to width dimension). | 11-20-2008 |
20080284022 | Semiconductor device and method for manufacturing the same - A semiconductor device ( | 11-20-2008 |
20080284023 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING BOAC/COA - A BOAC/COA of a semiconductor device is manufactured by forming a conductive pad over a semiconductor device, forming a passivation oxide film over the semiconductor device including the conductive pad, forming an oxide film over the entire surface of the conductive pad and the passivation oxide film, forming an oxide film pattern defining a bond pad region on the conductive pad, sequentially forming a barrier film and a metal seed layer over the oxide film pattern, the passivation oxide film and the conductive pad, forming a metal layer over the metal seed layer, planarizing the metal layer exposing the oxide film pattern and portions of the barrier film and the metal seed layer, and removing the oxide film pattern by an etching process. | 11-20-2008 |
20080284024 | Semiconductor Device and Method of Manufacturing the Same - A metal interconnection of semiconductor device and method for fabricating the same is provided. The semiconductor device can include a semiconductor substrate formed with device structures such as transistors. An interlayer dielectric layer can be formed on the semiconductor substrate with a metal interconnection formed therethrough. A spacer can be formed on at least a portion of a sidewall of the metal interconnection. A diffusion barrier can be formed on an upper surface of the metal interconnection. | 11-20-2008 |
20080290515 | PROPERTIES OF METALLIC COPPER DIFFUSION BARRIERS THROUGH SILICON SURFACE TREATMENTS - In accordance with the invention, there are diffusion barriers, integrated circuits, and semiconductor devices and methods of fabricating them. The method of fabricating a diffusion barrier can include providing a dielectric layer, forming a first silicon enriched layer over the dielectric layer by exposing the dielectric layer to a silicon-containing ambient, and forming a barrier layer over the first silicon enriched layer. | 11-27-2008 |
20080290516 | SEMICONDUCTOR DEVICE WITH BONDING PAD SUPPORT STRUCTURE - A semiconductor device having bonding pads on a semiconductor substrate includes: an upper copper layer that is formed on the lower surface of the bonding pads with a barrier metal interposed and that has a copper area ratio that is greater than layers in which circuit interconnects are formed; and a lower copper layer that is electrically insulated from the upper copper layer and that is formed closer to the semiconductor substrate than the upper copper layer. | 11-27-2008 |
20080290517 | Semiconductor device - A semiconductor device of the present invention includes an insulating film made of a low dielectric constant material having a smaller specific dielectric constant than SiO | 11-27-2008 |
20080290518 | DIELECTRIC INTERCONNECT STRUCTURES AND METHODS FOR FORMING THE SAME - Dielectric interconnect structures and methods for forming the same are provided. Specifically, the present invention provides a dielectric interconnect structure having a noble metal layer (e.g., Ru, Ir, Rh, Pt, RuTa, and alloys of Ru, Ir, Rh, Pt, and RuTa) that is formed directly on a modified dielectric surface. In a typical embodiment, the modified dielectric surface is created by treating an exposed dielectric layer of the interconnect structure with a gaseous ion plasma (e.g., Ar, He, Ne, Xe, N | 11-27-2008 |
20080290519 | DUAL LINER CAPPING LAYER INTERCONNECT STRUCTURE - A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer is plasma treated prior to depositing each succeeding dielectric layer such that the dielectric cap has an internal tensile stress. | 11-27-2008 |
20080296768 | Copper nucleation in interconnects having ruthenium layers - A method for fabrication a metal interconnect that includes a ruthenium layer and minimizes void formation comprises forming a barrier layer on a substrate having a trench, depositing a ruthenium layer on the barrier layer, depositing an alloy-seed layer on the ruthenium layer, using an electroless plating process to deposit a copper seed layer on the alloy-seed layer, and using an electroplating process to deposit a bulk metal layer on the copper seed layer. The alloy-seed layer inhibits void formation issues at the ruthenium-copper interface and improves electromigration issues. The electroless copper seed layer inhibits the alloy-seed layer from dissolving into the electroplating bath and reduces electrical resistance across the substrate during the electroplating process. | 12-04-2008 |
20080296769 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment of the present invention includes a line layer containing Cu (copper), an inter layer dielectric formed on the line layer, a via hole formed in the inter layer dielectric on the line layer, a first barrier layer formed on the line layer in the via hole, a second barrier layer formed on the first barrier layer and on a sidewall of the via hole, and a conductive layer formed on the second barrier layer and containing Al (aluminum). | 12-04-2008 |
20080296770 | Semiconductor device - A semiconductor device of the present invention includes a semiconductor substrate; a diffusion layer formed about a surface of the semiconductor substrate; a first conductive layer formed on the semiconductor substrate, and an insulating layer formed on the semiconductor substrate after the first conductive layer and the diffusion layer are formed, and a second conductive layer formed on the insulating layer, and a first contact formed in the insulating layer, connecting the first conductive layer to the second conductive layer, and a second contact formed in the insulating layer, connecting the first conductive layer to the diffusion layer. In addition, a part of the diffusion layer extends to a lower portion of the first contact. | 12-04-2008 |
20080303154 | Through-silicon via interconnection formed with a cap layer - An integrated circuit structure and methods for forming the same are provided. The method includes providing a substrate; forming a through-silicon via (TSV) opening extending into the substrate; forming an under-bump metallurgy (UBM) in the TSV opening, wherein the UBM extends out of the TSV opening; filling the TSV opening with a metallic material; forming a patterned cap layer on the metallic material; and etching a portion of the UBM outside the TSV opening, wherein the patterned cap layer is used as a mask. | 12-11-2008 |
20080303155 | DIELECTRIC BARRIER FILMS FOR USE AS COPPER BARRIER LAYERS IN SEMICONDUCTOR TRENCH AND VIA STRUCTURES - The present invention is directed to improved dielectric copper barrier layer and related interconnect structures. One structure includes a semiconductor substrate having a copper line. An insulating layer formed of at least one of silicon and carbon is formed on the underlying copper line. An opening is formed in the insulating layer to expose a portion of the copper line. The inner surface of the opening in the insulating layer has a dielectric barrier layer formed thereon to prevent the diffusion of copper into the insulating layer. A copper plug is formed to fill the opening and make electrical contact with the underlying copper interconnect structure. Aspects of the invention also include methods for forming the dielectric copper barrier layers and associate copper interconnects to the underlying copper lines. | 12-11-2008 |
20080308937 | COPPER-FREE SEMICONDUCTOR DEVICE INTERFACE AND METHODS OF FABRICATION AND USE THEREOF - Embodiments of copper-free semiconductor device interfaces and methods for forming and/or utilizing the same are provided herein. In some embodiments, a semiconductor structure may include a substrate having an exposed copper-containing feature; and a copper-free interface disposed over the substrate and providing a conductive interconnect between the copper-containing feature and an upper surface of the copper-free interface to facilitate electrical coupling of the substrate to a semiconductor device while physically isolating the semiconductor device from the copper-containing feature. | 12-18-2008 |
20080308938 | Under bump metallurgy structure and wafer structure using the same and method of manufacturing wafer structure - An under bump metallurgy structure and wafer structure using the same and method of manufacturing wafer structure are provided. The under bump metallurgy structure includes an adhesion layer, a barrier layer and a wetting layer. The adhesion layer is disposed on a bonding pad of a wafer. The barrier layer is disposed on the adhesion layer. The wetting layer is disposed on the barrier layer. The adhesion layer, the barrier layer and the wetting layer are respectively made of nickel with boron, cobalt and gold. | 12-18-2008 |
20080315418 | Methods of post-contact back end of line through-hole via integration - Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. In one embodiment, the method comprises forming metal plug contacts through a hard mask and a premetal dielectric to transistors in the semiconductor. The method also includes etching a hole for a through-hole via through the hard mask to the semiconductor using a patterned photoresist process, removing the patterned photoresist and using a hard mask process to etch the hole to an amount into the semiconductor. The method further includes depositing a dielectric liner to isolate the hole from the semiconductor, depositing a gapfill metal to fill the hole, and planarizing the surface of the substrate to the hard mask. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention. | 12-25-2008 |
20080315419 | CHROMIUM/TITANIUM/ALUMINUM-BASED SEMICONDUCTOR DEVICE CONTACT - A contact to a semiconductor including sequential layers of Cr, Ti, and Al is provided, which can result in a contact with one or more advantages over Ti/Al-based and Cr/Al-based contacts. For example, the contact can: reduce a contact resistance; provide an improved surface morphology; provide a better contact linearity; and/or require a lower annealing temperature, as compared to the prior art Ti/Al-based contacts. | 12-25-2008 |
20090001577 | METAL LINE OF SEMICONDUCTOR DEVICE WITH A TRIPLE LAYER DIFFUSION BARRIER AND METHOD FOR FORMING THE SAME - A metal line in a semiconductor device includes an insulation layer formed on a semiconductor substrate. A metal line forming region is formed in the insulation layer. A diffusion barrier is formed on a surface of the metal line forming region and a metal line is formed to fill the metal line forming region of the insulation layer. The diffusion barrier is formed between the metal line and the insulation layer. The diffusion barrier has a structure in which a TaSi | 01-01-2009 |
20090001578 | METAL LINE OF SEMICONDUCTOR DEVICE HAVING A DIFFUSION BARRIER WITH AN AMORPHOUS TaBN LAYER AND METHOD FOR FORMING THE SAME - A metal line in a semiconductor device includes an insulation layer formed on a semiconductor substrate. A metal line forming region is formed in the insulation layer. A metal line is formed to fill the metal line forming region of the insulation layer. And a diffusion barrier that includes an amorphous TaBN layer is formed between the metal line and the insulation layer. The amorphous TaBN layer prevents a copper component from diffusing into the semiconductor substrate, thereby improving upon the characteristics and the reliability of a device. | 01-01-2009 |
20090001579 | MULTI-LAYERED METAL LINE HAVING AN IMPROVED DIFFUSION BARRIER OF A SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A multi-layered metal line of a semiconductor device and a process of forming the same are described. The multi-layered metal line includes a lower metal line formed on a semiconductor substrate. An insulation layer is subsequently formed on the semiconductor substrate including the lower metal line and has an upper metal line forming region that exposes a portion of the lower metal line. A diffusion barrier formed on a surface of the upper metal line forming region of the insulation layer. The diffusion barrier includes a W—B—N ternary layer. An upper metal line is finally formed on the diffusion barrier to fill the upper metal line forming region of the insulation layer. | 01-01-2009 |
20090001580 | METAL LINE OF SEMICONDUCTOR DEVICE HAVING A DIFFUSION BARRIER INCLUDING CRxBy AND METHOD FOR FORMING THE SAME - A metal line of a semiconductor device having a diffusion barrier including Cr | 01-01-2009 |
20090001581 | METAL LINE OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A metal line of a semiconductor device includes an insulating layer in which damascene patterns have been formed, a first metal layer formed on sidewalls and bottom surfaces of the damascene patterns, a second metal layer formed on the first metal layer within the damascene patterns and having a lower resistance than the first metal layer, and a third metal layer formed on the second metal layer. | 01-01-2009 |
20090001582 | SEMICONDUCTOR DEVICE WITH METAL GATE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate, a gate dielectric layer over the substrate, a silicon electrode over the gate dielectric layer, wherein the silicon electrode comprises a damascene pattern, a diffusion barrier layer on a bottom and a sidewall of the damascene pattern, and a metal electrode over the diffusion barrier layer, wherein the metal electrode fills the damascene pattern. | 01-01-2009 |
20090001583 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The present invention relates to a semiconductor device and a method of fabricating the same. In an embodiment of the present invention, an insulating layer in which contact holes are formed is formed over a semiconductor substrate in which lower metal lines are formed. A barrier metal layer, having a stack structure of a first tungsten (W) layer and a tungsten nitride (WN) layer, is formed within the contact holes. Contact plugs are formed within the contact holes. | 01-01-2009 |
20090001584 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method of fabricating a semiconductor device that may include at least one of the following steps: Forming a lower metal wiring on and/or over a semiconductor substrate. Forming an interlayer insulating film having a damascene hole on and/or over the semiconductor substrate and the lower metal wiring. Forming an anti-diffusion film on and/or over the exposed lower metal wiring below the damascene hole and/or on side surfaces of the damascene hole. Selectively removing the anti-diffusion film formed on and/or over the exposed lower metal wiring at the bottom of the damascene hole using a plasma process that uses an inert gas. | 01-01-2009 |
20090001585 | METHOD OF MANUFACTURING FLASH MEMORY DEVICE - A method of manufacturing a flash memory that can include forming a titanium nitride (TiN) layer on the pre-metal dielectric having the via hole and then forming a TiSiN layer by injecting silane (SiH | 01-01-2009 |
20090001586 | INTEGRATED CIRCUIT AND SEED LAYERS - Structures are provided that include a conducting layer disposed on a layered arrangement of a diffusion barrier layer and a seed layer in an integrated circuit. Apparatus and systems having such structures and methods of forming these structures for apparatus and systems are disclosed. | 01-01-2009 |
20090001587 | Ta-TaN SELECTIVE REMOVAL PROCESS FOR INTEGRATED DEVICE FABRICATION - Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor. | 01-01-2009 |
20090008779 | Composite Carbon Nanotube-Based Structures and Methods for Removing Heat from Solid-State Devices - One embodiment involves an article of manufacture that includes: a copper substrate plug with a front surface and a back surface; a catalyst on top of a single surface of the copper substrate plug; and a thermal interface material on top of the single surface of the copper substrate plug. The thermal interface material comprises: a layer of carbon nanotubes that contacts the catalyst, and a filler material located between the carbon nanotubes. The carbon nanotubes are oriented substantially perpendicular to the single surface of the copper substrate plug. The copper substrate plug is configured to be incorporated in a peripheral structure of a heat spreader or a heat sink. In another embodiment, the thermal interface material is on top of both the top and bottom surfaces of the copper substrate plug. | 01-08-2009 |
20090008780 | METHODS FOR FORMING INTERCONNECTS IN MICROELECTRONIC WORKPIECES AND MICROELECTRONIC WORKPIECES FORMED USING SUCH METHODS - Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces having such interconnects are disclosed herein. One aspect of the invention is directed toward a method for manufacturing a microelectronic workpiece having a plurality of microelectronic dies. The individual dies include an integrated circuit and a terminal electrically coupled to the integrated circuit. In one embodiment, the method includes forming an opening in the workpiece in alignment with the terminal. The opening can be a through-hole extending through the workpiece or a blind hole that extends only partially through the substrate. The method continues by constructing an electrically conductive interconnect in the workpiece by depositing a solder material into at least a portion of the opening and in electrical contact with the terminal. In embodiments that include forming a blind hole, the workpiece can be thinned either before or after forming the hole. | 01-08-2009 |
20090014877 | Selective Formation of Boron-Containing Metal Cap Pre-layer - An interconnect structure with improved reliability is provided. The interconnect structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a metallic wiring in the dielectric layer; a pre-layer over the metallic wiring, wherein the pre-layer contains boron; and a metal cap over the pre-layer, wherein the metal cap contains tungsten, and wherein the pre-layer and the metal cap are formed of different materials. | 01-15-2009 |
20090014878 | STRUCTURE AND METHOD OF FORMING ELECTRODEPOSITED CONTACTS - A contact metallurgy structure comprising a patterned dielectric layer having cavities on a substrate; a silicide or germanide layer such as of cobalt and/or nickel located at the bottom of cavities; a contact layer comprising Ti or Ti/TiN located on top of the dielectric layer and inside the cavities and making contact to the silicide or germanide layer on the bottom; a diffusion barrier layer located on top of the contact layer and inside the cavities; optionally a seed layer for plating located on top of the barrier layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer is electrodeposited with at least one member selected from the group consisting of copper, rhodium, ruthenium, iridium, molybdenum, gold, silver, nickel, cobalt, silver, gold, cadmium and zinc and alloys thereof. When the metal fill layer is rhodium, ruthenium, or iridium, an effective diffusion barrier layer is not required between the fill metal and the dielectric. When the barrier layer is platable, such as ruthenium, rhodium, platinum, or iridium, the seed layer is not required. | 01-15-2009 |
20090014879 | Semiconductor device and method of manufacturing the same - In a method of forming a wiring structure for a semiconductor device, an insulation layer is formed on a semiconductor substrate on which a plurality of conductive structures is positioned. An upper surface of the insulation layer is planarized and spaces between the conductive structures are filled with the insulation layer. The insulation layer is partially removed from the substrate to form at least one opening through which the substrate is partially exposed. A residual metal layer is formed on a bottom and a lower portion of the sidewall of the at least one opening and a metal nitride layer is formed on the residual metal layer and an upper sidewall of the opening with a metal material. Accordingly, an upper portion of the barrier layer can be prevented from being removed in a planarization process for forming the metal plug. | 01-15-2009 |
20090014880 | DUAL DAMASCENE PROCESS FLOW ENABLING MINIMAL ULK FILM MODIFICATION AND ENHANCED STACK INTEGRITY - Interconnect structures possessing an organosilicate glass interlayer dielectric material with minimal stoichiometeric modification and optionally an intact organic adhesion promoter for use in semiconductor devices are provided herein. The interconnect structure is capable of delivering improved device performance, functionality and reliability owing to the reduced effective dielectric constant of the stack compared with that of those conventionally employed because of the use of a sacrificial polymeric material deposited onto the dielectric and optional organic adhesion promoter during the barrier open step done prior to ashing the patterning material. This sacrificial film protects the dielectric and optional organic adhesion promoter from modification/consumption during the subsequent ashing step during which the polymeric film is removed. | 01-15-2009 |
20090026616 | INTEGRATED CIRCUIT HAVING A SEMICONDUCTOR SUBSTRATE WITH A BARRIER LAYER - An integrated circuit having a semiconductor substrate with a barrier layer is disclosed. The arrangement includes a semiconductor substrate and a metallic element. A carbon-based barrier layer is disposed between the semiconductor substrate and the metallic element. | 01-29-2009 |
20090026617 | SEMICONDUCTOR DEVICE HAVING A COPPER METAL LINE AND METHOD OF FORMING THE SAME - A semiconductor device having a copper line and a method of forming the same so as to prevent a bridge phenomenon between neighboring upper lines are described. The method may include the steps of forming a capping layer and an intermetal dielectric layer in a stacked configuration over a substrate in which lower lines are formed, forming trenches defining an upper metal line region on the intermetal dielectric layer, and forming a spacer on inner sidewalls of the trenches. A via may then be formed under the exposed first trench using a photolithography process and the spacer for alignment. After removing the spacer, a barrier metal film may be formed on inner walls of the trenches and the via, a copper metal line film may be gap-filled within the trenches and the via, and a surface of the semiconductor device may be polished. | 01-29-2009 |
20090026618 | Semiconductor device including interlayer interconnecting structures and methods of forming the same - In a method of forming a semiconductor device, and a semiconductor device formed according to the method, an insulating layer is provided on an underlying contact region of the semiconductor device. An opening is formed in the insulating layer to expose the underlying contact region. A seed layer is provided on sidewalls and a bottom of the opening, the seed layer comprising cobalt. A barrier layer of conductive material is provided in a lower portion of the opening, the seed layer being exposed on sidewalls of an upper portion of the opening. A metal layer is provided on the barrier layer in the opening to form an interlayer contact, the metal layer contacting the seed layer at the sidewalls of the upper portion of the opening. | 01-29-2009 |
20090032950 | FILM FORMING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE, PROGRAM AND RECORDING MEDIUM - An adhesion between a Cu diffusion barrier film and a Cu wiring in a semiconductor device is improved and reliability of the semiconductor device is improved. A film forming method for forming a Cu film on a substrate to be processed is provided with a first process of forming an adhesion film on the Cu diffusion barrier film formed on the substrate to be processed, and a second process of forming a Cu film on the adhesion film. The adhesion film includes Pd. | 02-05-2009 |
20090032951 | Small Area, Robust Silicon Via Structure and Process - A semiconductor structure includes: at least one silicon surface wherein the surface can be a substrate, wafer or other device. The structure further includes at least one electronic circuit formed on each side of the at least one surface; and at least one conductive high aspect ratio through silicon via running through the at least one surface. Each through silicon via is fabricated from at least one etch step and includes: at least one thermal oxide dielectric for coating at least some of a sidewall of the through silicon via for a later etch stop in fabrication of the through silicon via. | 02-05-2009 |
20090032952 | TANTALUM AMIDO-COMPLEXES WITH CHELATE LIGANDS USEFUL FOR CVD AND ALD OF TaN AND Ta205 THIN FILMS - Tantalum compounds of Formula I hereof are disclosed, having utility as precursors for forming tantalum-containing films such as barrier layers. The tantalum compounds of Formula I may be deposited by CVD or ALD for forming semiconductor device structures including a dielectric layer, a barrier layer on the dielectric layer, and a copper metallization on the barrier layer, wherein the barrier layer includes a Ta-containing layer and sufficient carbon so that the Ta-containing layer is amorphous. According to one embodiment, the semiconductor device structure is fabricated by depositing the Ta-containing barrier layer, via CVD or ALD, from a precursor including the tantalum compound of Formula I hereof at a temperature below about 400° C. in a reducing or inert atmosphere, e.g., a gas or plasma optionally containing a reducing agent. | 02-05-2009 |
20090032953 | Semiconductor device and method of manufacturing the same - A semiconductor device is described includes a wiring layer, an insulating layer stacked on the wiring layer, a trench formed by digging down the insulating layer from the surface thereof, a film-shaped lower electrode formed along the inner surface of the trench, a capacitor film formed along the surface of the lower electrode, and an upper electrode opposed to the lower electrode with the capacitor film sandwiched therebetween. | 02-05-2009 |
20090039512 | ELECTROMIGRATION RESISTANT INTERCONNECT STRUCTURE - A line trench is formed in a dielectric layer that may contain an interlayer dielectric material. A metal liner is formed on the sidewalls and the bottom surface of the line trench. A conductive metal is deposited within a remaining portion of the line trench at least up to a top surface of the dielectric layer and planarized to form a metal line in the line trench. The metal line is recessed by a recess etch below the top surface of the dielectric layer. A dielectric line cap or a metallic line cap is formed by deposition of a dielectric cap layer or a metallic cap layer, followed by planarization of the dielectric or metallic cap layer. The dielectric line cap or the metallic line cap applies a highly compressive stress on the underlying metal line, which increases electromigration resistance of the metal line. | 02-12-2009 |
20090039513 | Contacting Method for Semiconductor Material and Semiconductor Device - A contact-making method for a semiconductor material contains the method steps of forming a diffusion barrier which promotes electrical contact and adhesion on at least one portion of a surface of a semiconductor and forming a metallization on the diffusion barrier. The diffusion barrier being formed by applying a metalliforous paste to at least one portion of the semiconductor surface or to at least one portion of a layer covering the semiconductor surface, and a semiconductor component with a diffusion barrier which is arranged in the surface of the semiconductor and which promotes electrical contact between the semiconductor material and a metallization. The metallization is applied to the diffusion barrier. The diffusion barrier is formed by a sintered metalliforous paste applied to at least one portion of the semiconductor surface. | 02-12-2009 |
20090045514 | SEMICONDUCTOR DEVICE CONTAINING AN ALUMINUM TANTALUM CARBONITRIDE BARRIER FILM AND METHOD OF FORMING - The method includes providing a substrate containing a dielectric layer having a recessed feature and forming a aluminum tantalum carbonitride barrier film over a surface of the recessed feature. The aluminum tantalum carbonitride barrier film is formed by depositing a plurality of tantalum carbonitride films, and depositing aluminum between each of the plurality of tantalum carbonitride films. One embodiment further comprises depositing a Ru film on the aluminum tantalum carbonitride barrier film, depositing a Cu seed layer on the Ru film, and filling the recessed feature with bulk Cu. A semiconductor device containing an aluminum tantalum carbonitride barrier film is described. | 02-19-2009 |
20090045515 | MONITORING THE MAGNETIC PROPERTIES OF A METAL LAYER DURING THE MANUFACTURE OF SEMICONDUCTOR DEVICES - A method for manufacturing a semiconductor device that comprises forming an interconnect structure in an insulating layer located on a semiconductor substrate. The method also comprises depositing a metal cap layer on the interconnect structure and measuring a magnetic property of the metal cap layer. The magnetic property is compared to a target magnetic property. If the measured magnetic property differs from the target magnetic property by a predefined amount, then one or both of an interconnect structure formation process or a metal cap layer deposition process are altered. | 02-19-2009 |
20090051033 | RELIABILITY IMPROVEMENT OF METAL-INTERCONNECT STRUCTURE BY CAPPING SPACERS - The present invention relates to a metal-interconnect structure for electrically connecting integrated-circuit elements in an integrated-circuit device. It solves several problems of operational reliability in damascene interconnect structures, due to corner effects and structural defects present at top edges of interconnect lines fabricated according to prior-art processing technologies. In alternative configurations of the metal interconnect structure, capping spacers ( | 02-26-2009 |
20090057904 | COPPER METAL LINE IN SEMICONDCUTOR DEVICE AND METHOD OF FORMING SAME - A Cu line in a semiconductor device and method of forming same are disclosed. The method may include forming an insulating interlayer on a semiconductor substrate, forming a contact hole and a trench in the insulating interlayer in sequence, forming a short-circuit preventing layer on the insulating interlayer including the contact hole and the trench, forming a spacer on a sidewall of the trench by etching the short-circuit preventing layer, forming a Cu line layer over the semiconductor substrate including the contact hole and the trench, planarizing the Cu line layer by CMP, and forming a Cu-diffusion preventing capping layer over the semiconductor substrate including the Cu line layer. | 03-05-2009 |
20090057905 | Semiconductor Device and Method of Manufacturing the Same - A metal interconnection layout for a semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device can maintain a minimum design rule and secure a distance between via holes to inhibit a metal bridge phenomenon from being generated. The semiconductor device comprises a substrate, an interlayer dielectric, a first metal interconnection, and a second metal interconnection parallel to the first metal interconnection. The interlayer dielectric can be disposed on the substrate. The first metal interconnection is connected to the substrate or lower interconnect through at least one first via hole in the interlayer dielectric. The second metal interconnection is adjacent to the first metal interconnection and can be connected to the substrate or another lower interconnect through at least one second via hole in the interlayer dielectric. The first via hole and the second via hole are staggered from each other along the first metal interconnection and the second metal interconnection, respectively. | 03-05-2009 |
20090065939 | METHOD FOR INTEGRATING SELECTIVE RUTHENIUM DEPOSITION INTO MANUFACTURING OF A SEMICONDUCTIOR DEVICE - A method for integrating selective Ru metal deposition into manufacturing of semiconductor devices to improve electromigration and stress migration in bulk Cu. The method includes selectively depositing a Ru metal film on a metallization layer or on bulk Cu using a process gas containing Ru | 03-12-2009 |
20090072400 | CONTACT FORMING IN TWO PORTIONS AND CONTACT SO FORMED - Methods of forming a contact in two or more portions and a contact so formed are disclosed. One method includes providing a device including a silicide region; and forming a contact to the silicide region by: first forming a lower contact portion to the silicide region through a first dielectric layer, and second forming an upper contact portion to the lower contact portion through a second dielectric layer over the first dielectric layer. A contact may include a first contact portion contacting a silicide region, the first contact portion having a width less than 100 nm; and a second contact portion coupled to the first contact portion from above, the second contact portion having a width greater than the width of the first contact portion. | 03-19-2009 |
20090072401 | METHODS TO MITIGATE PLASMA DAMAGE IN ORGANOSILICATE DIELECTRICS USING A PROTECTIVE SIDEWALL SPACER - Plasma damage in ultra low k dielectric materials during formation of a dual damascene metal interconnect structure is reduced by providing a protective spacer on sidewalls of a line trench. A densified trench bottom region may be additionally formed directly beneath an exposed horizontal surface of the line trench. The protective spacer and/or the densified trench bottom region protects an ultra low k intermetal dielectric layer from plasma damage during a plasma strip process that is used to remove a disposable via fill plug employed in the dual damascene metal interconnect structure. | 03-19-2009 |
20090072402 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device comprising forming a metal layer on a semiconductor substrate, patterning the metal layer to form a plurality of metal wires having side surfaces, forming spacers on both side surfaces of each of the metal wires, and forming an insulating layer between the spacers of the adjacent metal wires, the insulating layer having voids formed therein and being formed with material having a dielectric constant which differs from that of the spacers, and a semiconductor device made by this method. | 03-19-2009 |
20090072403 | Wiring Structure, Semiconductor Device and Manufacturing Method Thereof - A semiconductor device with a high-strength porous modified layer having a pore size of 1 nm or less, which is formed, in a multilayer wiring forming process, by forming a via hole and a wiring trench in a via interlayer insulating film and a wiring interlayer insulting film and then irradiating an electron beam or an ultraviolet ray onto the opening side walls. | 03-19-2009 |
20090079077 | INTERCONNECT STRUCTURE WITH A VIA GOUGING FEATURE ABSENT PROFILE DAMAGE TO THE INTERCONNECT DIELECTRIC AND METHOD OF FABRICATING SAME - An interconnect structure including a gouging feature at the bottom of the via openings and a method of forming the same, which does not introduce either damages caused by Ar sputtering into the dielectric material that includes the via and line openings, nor plating voids into the structure are provided. The method includes the uses of at least one infusion process that forms an infused surface region within a conductive material of a lower interconnect level. The infused surface region has a different etch rate as compared with the conductive material and thus in a subsequent etching process, the infused surface region can be selectively removed forming a gouging feature within the structure. | 03-26-2009 |
20090079078 | Minimization of Interfacial Resitance Across Thermoelectric Devices by Surface Modification of the Thermoelectric Material - A coating architecture ( | 03-26-2009 |
20090085209 | SEMICONDUCTOR DEVICE WITH COPPER WIREBOND SITES AND METHODS OF MAKING SAME - Semiconductor devices with external wirebond sites that include copper and methods for fabricating such semiconductor devices are disclosed. One embodiment of a method for fabricating a semiconductor device comprises forming a dielectric layer on an active side of a semiconductor substrate. The dielectric layer has openings aligned with corresponding wirebond sites at the active side of the substrate. The method further includes forming a plurality of wirebond sites located at the openings in the dielectric layer. The wirebond sites are electrically coupled to an integrated circuit in the semiconductor substrate and electrically isolated from each other. Individual wirebond sites are formed by electrolessly depositing nickel into the openings and forming a wirebond film on the nickel without forming a seam between the nickel and the dielectric layer. | 04-02-2009 |
20090085210 | STRUCTURES AND METHODS FOR REDUCTION OF PARASITIC CAPACITANCES IN SEMICONDUCTOR INTEGRATED CIRCUITS - A semiconductor structure and a method for forming the same. The structure includes (a) a substrate which includes semiconductor devices and (b) a first ILD (inter-level dielectric) layer on top of the substrate. The structure further includes N first actual metal lines in the first ILD layer, N being a positive integer. The N first actual metal lines are electrically connected to the semiconductor devices. The structure further includes first trenches in the first ILD layer. The first trenches are not completely filled with solid materials. If the first trenches are completely filled with first dummy metal lines, then (i) the first dummy metal lines are not electrically connected to any semiconductor device and (ii) the N first actual metal lines and the first dummy metal lines provide an essentially uniform pattern density of metal lines across the first ILD layer. | 04-02-2009 |
20090085211 | ELECTRICAL CONTACTS FOR INTEGRATED CIRCUITS AND METHODS OF FORMING USING GAS CLUSTER ION BEAM PROCESSING - Embodiments of the invention describe electrical contacts for integrated circuits and methods of forming using gas cluster ion beam (GCIB) processing. The electrical contacts contain a fused metal-containing layer formed by exposing a patterned structure to a gas cluster ion beam containing a transition metal precursor or a rare earth metal precursor. | 04-02-2009 |
20090096102 | CONDUCTOR STRUCTURE INCLUDING MANGANESE OXIDE CAPPING LAYER - A microelectronic structure includes a dielectric layer located over a substrate. The dielectric layer is separated from a copper containing conductor layer by an oxidation barrier layer. The microelectronic structure also includes a manganese oxide layer located aligned upon a portion of the copper containing conductor layer not adjoining the oxidation barrier layer. A method for fabricating the microelectronic structure includes sequentially forming and sequentially planarizing within an aperture within a dielectric layer an oxidation barrier layer, a manganese containing layer (or alternatively a mobile and oxidizable material layer) and finally, a planarized copper containing conductor layer (or alternatively a base material layer comprising a material less mobile and oxidizable than the mobile and oxidizable material layer) to completely fill the aperture. The manganese layer and the planarized copper containing conductor layer are then thermally oxidized to form a manganese oxide layer self aligned to a portion of the copper containing conductor layer not adjoining the oxidation barrier layer. | 04-16-2009 |
20090096103 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING BARRIER METAL LAYER THEREOF - A method for forming a barrier metal layer includes forming a metal compound film composed of a first metal and a second metal on sidewalls of a contact hole, and then selectively etching the metal compound film and then simultaneously forming a barrier metal layer and a first metal seed layer on sidewalls of the contact hole by performing a thermal treatment process on the metal compound film. Accordingly, the process time can be shortened because the sputtering process can be reduced by forming a barrier metal layer and a copper seed layer by reaction between the second metal material and an underlying insulating film by performing the thermal treatment process. | 04-16-2009 |
20090102051 | METHOD TO CREATE SUPER SECONDARY GRAIN GROWTH IN NARROW TRENCHES - The present invention relates to a method for obtaining enlarged Cu grains in small trenches. More specifically it related to a method for creating enlarged copper grains or inducing super secondary grain growth in electrochemically deposited copper in narrow trenches and/or vias to be used in semiconductor devices. | 04-23-2009 |
20090102052 | Semiconductor Device and Fabricating Method Thereof - A semiconductor device and fabricating method thereof are disclosed. The method includes forming a first metal line over a substrate, forming a barrier layer over the substrate and the first metal line, forming an insulating layer on the barrier layer, forming a capping layer on the insulating layer, forming a photoresist pattern on the capping layer, implanting halogen ions into the insulating layer using the photoresist pattern as a mask, forming a via-hole exposing the first metal line by dry-etching the insulating layer using the photoresist pattern as an etch mask, and forming a second metal line in the via-hole in contact with the first metal line. | 04-23-2009 |
20090102053 | METAL LINE STACKING STRUCTURE IN SEMICONDUCTOR DEVICE AND FORMATION METHOD THEREOF - The method for forming a metal line stacking structure according to a preferred embodiment of the present invention comprises: sequentially forming a first barrier metal and a first metal layer on a lower dielectric layer that is disposed over a semiconductor substrate, and performing a plasma treatment; forming a second barrier metal on the plasma-treated first metal layer; selectively etching the second barrier metal, the first metal layer, and the first barrier metal to form a metal line layer including the second barrier metal, the first metal layer, and the first barrier metal, which respectively have a predetermined width; and sintering the metal line layer to raise a reaction between the first metal layer and the second barrier metal, thereby generating a metal compound layer. | 04-23-2009 |
20090108450 | INTERCONNECT STRUCTURE AND METHOD OF MAKING SAME - An interconnect structure and method of fabricating the same is provided. The interconnect structure is a highly reliable copper interconnect structure. The interconnect structure includes a planarized lower dielectric layer and a lower cap layer on the planarized lower dielectric layer. A copper material is formed in a trench of the planarized lower dielectric layer, below the lower cap layer. A lower liner extends into a pattern of the lower cap layer and contacts the copper layer. An upper dielectric layer is on the lower cap layer and a copper layer contacts the lower liner and is formed in a via of at least the lower cap layer. An upper liner is formed over the copper layer, sandwiching the copper layer between the lower liner and the upper liner. An upper copper layer is formed over the upper liner. | 04-30-2009 |
20090108451 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a pattern layer formed on and/or over a semiconductor substrate, a fluorine-diffusion barrier layer containing a silicon-doped silicon oxide formed on and/or over the pattern layer, and an interlayer dielectric layer containing fluorine formed on and/or over the fluorine-diffusion barrier layer. | 04-30-2009 |
20090108452 | Semiconductor device and method for manufacturing the same - A method of manufacturing a semiconductor device including a sputtering process for forming a barrier film mainly having tantalum or tantalum nitride on an interlayer insulator formed by sputtering using a xenon gas. The sputtering process may include a step of forming one barrier film mainly composed of tantalum nitride on a substrate by sputtering using a xenon gas by applying a RF bias, and a step for forming another barrier film mainly composed of tantalum on the first barrier film by sputtering using a xenon gas without applying the RF bias. The barrier film may be formed by changing the RF bias continuously, and forming the interlayer insulator side by applying the RF bias, and forming the wiring side without applying the RF bias. | 04-30-2009 |
20090115061 | Solving Via-Misalignment Issues in Interconnect Structures Having Air-Gaps - An integrated circuit structure is provided. The integrated circuit structure includes a semiconductor substrate; and a metallization layer over the semiconductor substrate. The metallization layer includes a conductive line; a low-k dielectric region adjacent and horizontally spaced apart from the conductive line by a space; and a filler dielectric material filling at least a portion of the space, wherein the filler dielectric material and the low-k dielectric region are formed of different materials. The integrated circuit structure further includes a capping layer over and adjoining the filler dielectric material and the low-k dielectric region. The filler dielectric material has a dielectric constant (k value) less than a k value of the capping layer. | 05-07-2009 |
20090121353 | DUAL DAMASCENE BEOL INTEGRATION WITHOUT DUMMY FILL STRUCTURES TO REDUCE PARASITIC CAPACITANCE - In accordance with the invention, there are methods of making semiconductor devices. The method can include forming a hard mask layer over a dielectric layer, forming a via through the hard mask layer and the dielectric layer, and depositing an anti-reflective coating in the via and over the hard mask layer. The method can also include etching a trench through the hard mask layer, etching a dummy fill pattern in the hard mask layer to a desired thickness, and etching the trench through the dielectric layer and the dummy fill through the hard mask layer and in the dielectric layer. The method can further include depositing copper in the via and in the trench and removing excess copper using chemical mechanical polishing, wherein the dummy fill in the dielectric layer is of desired reduced depth. | 05-14-2009 |
20090121354 | Semiconductor Device and Method of Fabricating the Same - In a method of fabricating a semiconductor device a plurality of metal lines is formed over a semiconductor substrate. A reaction-prevention layer is formed on the metal line of a region in which a via hole will be formed. An interlayer insulating layer is formed over the semiconductor substrate including the reaction-prevention layer. The via hole is formed by etching the interlayer insulating layer over the reaction-prevention layer. A via plug is formed within the via hole. | 05-14-2009 |
20090121355 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, an oxygen-containing insulating film disposed above the above-described semiconductor substrate, a concave portion disposed in the above-described insulating film, a copper-containing first film disposed on an inner wall of the above-described concave portion, a copper-containing second film disposed above the above-described first film and filled in the above-described concave portion, and a manganese-containing oxide layer disposed between the above-described first film and the above-described second film. Furthermore, a copper interconnection is formed on the above-described structure by an electroplating method and, subsequently, a short-time heat treatment is conducted at a temperature of 80° C. to 120° C. | 05-14-2009 |
20090121356 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The semiconductor device according to the present invention includes a first interlayer dielectric film, a plurality of copper damascene wires embedded in the first interlayer dielectric film at an interval from each other, and a diffusion preventing film stacked on the first interlayer dielectric film for preventing diffusion of copper contained in the copper damascene wires, while an air gap closed with the diffusion preventing film is formed between the copper damascene wires adjacent to each other by partially removing the first interlayer dielectric film from the space between these copper damascene wires. | 05-14-2009 |
20090134517 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A first insulating film is formed on a semiconductor substrate. A first interconnection is formed in a trench formed in the first insulating film. A first barrier film is formed between the first interconnection and first insulating film. A second insulating film is formed on the upper surface of the first interconnection, and in a first hollow portion between the side surface of the first barrier film and the first insulating film. The second insulating film is formed from the upper surface of the first interconnection to a depth higher than the bottom surface of the first interconnection. The first hollow portion is formed below the bottom surface of the second insulating film. | 05-28-2009 |
20090134518 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device of the present invention is provided with a substrate; an insulating film made of a fluorine-containing carbon film and formed on the substrate; a copper wiring buried in the insulating film; and a barrier film formed between the insulating film and the copper wiring. The barrier film includes a first film made of titanium for suppressing a diffusion of fluorine, and a second film made of tantalum for suppressing a diffusion of copper and formed between the first film and the copper wiring. | 05-28-2009 |
20090134519 | SEMICONDUCTOR DEVICE - Embodiments relate to a semiconductor device. In embodiments, the semiconductor device may include a semiconductor substrate having a first metal line; a pre-metal dielectric (PMD) layer over the first metal line on the semiconductor substrate; a first metal layer formed in a first contact hole in the PMD layer; a second metal layer formed in a second contact hole in the PMD layer; and a second metal line electrically connected to the first and second metal layers, respectively, over the PMD layer, wherein the first and second metal layers are located at prescribed positions and configured to be electrically connected to the first metal line. | 05-28-2009 |
20090134520 | PROCESS INTEGRATION SCHEME TO LOWER OVERALL DIELECTRIC CONSTANT IN BEOL INTERCONNECT STRUCTURES - Back-End of Line (BEoL) interconnect structures, and methods for their manufacture, are provided. The structures are characterized by narrower conductive lines and reduced overall dielectric constant values. Conformal diffusion barrier layers, and selectively formed capping layers, are used to isolate the conductive lines and vias from surrounding dielectric layers in the interconnect structures. The methods of the invention employ techniques to narrow the openings in photoresist masks in order to define narrower vias. More narrow vias increase the amount of misalignment that can be tolerated between the vias and the conductive lines. | 05-28-2009 |
20090140428 | AIR GAP STRUCTURE HAVING PROTECTIVE METAL SILICIDE PADS ON A METAL FEATURE - A hard mask is formed on an interconnect structure comprising a low-k material layer and a metal feature embedded therein. A block polymer is applied to the hard mask layer, self-assembled, and patterned to form a polymeric matrix of a polymeric block component and containing cylindrical holes. The hard mask and the low-k material layer therebelow are etched to form cavities. A conductive material is plated on exposed metallic surfaces including portions of top surfaces of the metal feature to form metal pads. Metal silicide pads are formed by exposure of the metal pads to a silicon containing gas. An etch is performed to enlarge and merge the cavities in the low-k material layer. The metal feature is protected from the etch by the metal silicide pads. An interconnect structure having an air gap and free of defects to surfaces of the metal feature is formed. | 06-04-2009 |
20090140429 | Metal interconnection of a semiconductor device and method of manufacturing the same - A method of manufacturing a metal interconnection of a semiconductor device includes forming a base layer with at least one groove, the at least one groove having an open upper portion, forming a first metal layer in the at least one groove, forming a seed metal layer on the first metal layer in the at least one groove, the seed metal layer being only on a bottom surface of the at least one groove, and forming a metal pattern grown from the seed metal layer to fill the at least one grove. | 06-04-2009 |
20090140430 | Copper Alloy Sputtering Target and Semiconductor Element Wiring - A first copper alloy sputtering target comprising 0.5 to 4.0 wt % of Al and 0.5 wtppm or less of Si and a second copper alloy sputtering target comprising 0.5 to 4.0 wt % of Sn and 0.5 wtppm or less of Mn are disclosed. The first and/or the second alloy sputtering target can further comprise one or more elements selected from among Sb, Zr, Ti, Cr, Ag, Au, Cd, In and As in a total amount of 1.0 wtppm or less. A semiconductor element wiring formed by the use of the above targets is also disclosed. The above copper alloy sputtering target allows the formation of a wiring material for a semiconductor element, in particular, a seed layer being stable, uniform and free from the occurrence of coagulation during electrolytic copper plating and exhibits excellent sputtering film formation characteristics. | 06-04-2009 |
20090146305 | POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS - A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide post-passivation interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick passivation interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate. | 06-11-2009 |
20090152723 | INTERCONNECT STRUCTURE AND METHOD OF MAKING SAME - An interconnect structure and method of fabricating the same is provided. More specifically, the interconnect structure is a defect free capped interconnect structure. The structure includes a conductive material formed in a trench of a planarized dielectric layer which is devoid of cap material. The structure further includes the cap material formed on the conductive material to prevent migration. The method of forming a structure includes selectively depositing a sacrificial material over a dielectric material and providing a metal capping layer over a conductive layer within a trench of the dielectric material. The method further includes removing the sacrificial material with any unwanted deposited or nucleated metal capping layer thereon. | 06-18-2009 |
20090152724 | IC INTERCONNECT FOR HIGH CURRENT - IC interconnect for high current device, design structure thereof and method are disclosed. One embodiment of the IC interconnect includes a first via positioned in a dielectric and coupled to a high current device at one end; a buffer metal segment positioned in a dielectric and coupled to the first via at the other end thereof; and a plurality of second vias positioned in a dielectric and coupled to the buffer metal segment at one end and to a metal power line at the other end thereof, wherein the buffer metal segment is substantially shorter in length than the metal power line. | 06-18-2009 |
20090152725 | Thick metal interconnect with metal pad caps at selective sites and process for making the same - The present invention relates to a high power IC (Integrated Circuit) semiconductor device and process for making same. More particularly, the invention encompasses a high conductivity or low resistance metal stack to reduce the device R-on which is stable at high temperatures while in contact with a thick aluminum wire-bond that is required for high current carrying capability and is mechanically stable against vibration during use, and process thereof. The invention further discloses a thick metal interconnect with metal pad caps at selective sites, and process for making the same. | 06-18-2009 |
20090152726 | METAL LINE OF SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A metal line includes a lower metal line pattern having a first width formed over the dielectric pattern and an upper metal line pattern formed over and contacting the lower metal line pattern such that the upper metal line pattern has a second width less than the first width. | 06-18-2009 |
20090160055 | IC solder reflow method and materials - Embodiments of IC manufacture resulting in improved electromigration and gap-fill performance of interconnect conductors are described in this application. Reflow agent materials such as Sn, Al, Mn, Mg, Ag, Au, Zn, Zr, and In may be deposited on an IC substrate, allowing PVD depositing of a Cu layer for gap-fill of interconnect channels in the IC substrate. The Cu layer, along with reflow agent layer, may then be reflowed into the interconnect channels, forming a Cu alloy with improved gap-fill and electromigration performance. Other embodiments are also described. | 06-25-2009 |
20090160056 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same. The method can include forming a plurality of vias in a first interlayer insulation layer formed on a semiconductor substrate; and then forming a photoresist pattern over the first interlayer insulation layer to expose a portion of the first interlayer insulation layer and expose each via; and then forming a trench around an upper portion of each via by etching the exposed first interlayer insulation layer using the photoresist pattern as an etching mask; and then forming a metal layer over the first interlayer insulation layer including each trench; and then forming a plurality of metal lines over the vias and each trench by patterning the metal layer; and then forming a second interlayer insulation layer over the metal lines. Therefore, void generation between the metal lines during the highly integrated aluminum wiring process can be prevented. | 06-25-2009 |
20090160057 | Semiconductor device and method of manufacturing the same - A semiconductor device is provided in which penetration of a metal into a high impurity-doped active region from a side wall portion of a contact hole is prevented by reducing an aspect ratio to improve coverage of a titanium nitride film for the side wall portion of the contact hole, and in which increase in current consumption is eliminated. In a semiconductor device including an interlayer insulating film formed on a silicon substrate, and a interconnection formed of a barrier metal film and an aluminum alloy film and connected to the silicon substrate through a contact hole of the interlayer insulating film, a low-concentration impurity layer is epitaxially grown on a bottom surface of the contact hole, whereby the aspect ratio is reduced to improve coverage of the titanium nitride film for the side wall portion of the contact hole, and penetration of the metal into the high impurity-doped active region from the side wall portion of the contact hole is prevented. | 06-25-2009 |
20090166864 | METHOD TO PREVENT COPPER MIGRATION IN A SEMICONDUCTOR PACKAGE - A semiconductor package comprises a semiconductor die, a substrate that is coupled to the die, a trace formed in the substrate that comprises a first conductive material, e.g., copper, doped with a second conductive material, e.g., aluminum, the first conductive material has a first diffusivity that is lower than a second diffusivity of the second conductive material to prevent migration of the first conductive material. | 07-02-2009 |
20090166865 | MANUFACTURABLE RELIABLE DIFFUSION-BARRIER - Devices and methods are presented to fabricate diffusion barrier layers on a substrate. Presently, barrier layers comprising a nitride layer and a pure metal layer are formed using a physical vapor deposition (PVD) process that requires multiple ignition steps, and results in nitride-layer thicknesses of no less than 2 nm. This invention discloses devices and process to produce nitride-layers of less than <1 nm, while allowing for formation of a pure metal layer on the nitride-layer without re-igniting the plasma. To achieve this, the flow of nitrogen gas is cut off either before the plasma is ignited, or before the formation of a continuous-flow plasma. This ensures that a limited number of nitrogen atoms is deposited in conjunction with metal atoms on the substrate, thereby allowing for controlled thickness of the nitride layer. | 07-02-2009 |
20090166866 | CONTACT METALLIZATION FOR SEMICONDUCTOR DEVICES - Methods for forming metal contacts to silicon substrates in semiconductor devices for contact diameters less than 60 nm and the devices formed from such processes are described. The methods includes the steps of pre-cleaning the silicon surface where the metal contact will be formed, depositing a silicide material and a sacrificial liner, forming the silicide material, removing or stripping the non-reacted portions of the silicide material non-reacted portions of the sacrificial liner, optionally performing an additional oxide clean, and depositing the liner and the metal for the contact. Such a process allows the formation of W contacts with dimension of 60 nm and below without a significant amount of defects. | 07-02-2009 |
20090166867 | METAL INTERCONNECT STRUCTURES FOR SEMICONDUCTOR DEVICES - Cu interconnect structures using a bottomless liner to reduce the copper interfacial electron scattering and lower the electrical resistance are described in this application. The interconnect structures comprise a nucleation layer and a liner layer that may be formed by an oxide or nitride. The bottom portion of the liner layer is removed to expose the nucleation layer. Since the liner is bottomless, the nucleation layer is exposed during Cu deposition and serves to catalyze copper nucleation and enable selective growth of copper near the bottom (where the nucleation layer is exposed), rather than near the liner sidewalls. Thus, copper may be selectively grown with a bottom-up fill behavior than can reduce or eliminate formation of voids. Other embodiments are described. | 07-02-2009 |
20090166868 | Semiconductor devices including metal interconnections and methods of fabricating the same - A semiconductor device includes a first interlayer dielectric including a trench on a semiconductor layer, a mask pattern on the first interlayer dielectric, a first conductive pattern in the trench, and a second interlayer dielectric on the mask pattern. The second interlayer dielectric includes an opening over the first conductive pattern. A second conductive pattern is in the opening and is electrically connected to the first conductive pattern. The first conductive pattern has an upper surface lower than an upper surface of the mask pattern. | 07-02-2009 |
20090166869 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING METAL INTERCONNECTION LAYER THEREOF - Technologies related to forming metal lines of a semiconductor device are disclosed. A method of forming metal lines of a semiconductor device may include forming at least one interlayer insulating layer on a semiconductor substrate, forming via holes and trenches in the at least one interlayer insulating layer, forming an anti-diffusion film on the via holes and the trenches, depositing a seed Cu layer on the anti-diffusion film, after the seed Cu layer is deposited, depositing rhodium (Rh), and forming Cu line on the deposited Rh. The Rh improves an adhesive force between Cu layers and prevents oxide materials or a corrosion phenomenon from occurring on the seed Cu layer. Accordingly, occurrence of delamination in subsequent processes (for example, annealing and CMP) can be prevented or reduced. | 07-02-2009 |
20090166870 | METAL LINE OF SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A metal line of a semiconductor device includes an insulation layer formed on a semiconductor substrate and having a metal line forming region. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer. The diffusion barrier has a multi-layered structure of a V layer, a V | 07-02-2009 |
20090166871 | METAL LINE OF SEMICONDUCTOR DEVICE WITHOUT PRODUCTION OF HIGH RESISTANCE COMPOUND DUE TO METAL DIFFUSION AND METHOD FOR FORMING THE SAME - A metal line includes a lower metal line formed on a semiconductor substrate. An insulation layer is formed on the semiconductor substrate having the lower metal line, and a metal line forming region exposing at least a portion of the lower metal line is defined in the insulation layer. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer and includes a WN | 07-02-2009 |
20090174075 | SIMULTANEOUS GRAIN MODULATION FOR BEOL APPLICATIONS - The invention is directed to an improved semiconductor structure, such that within the same insulating layer, Cu interconnects embedded within the same insulating level layer have a different Cu grain size than other Cu interconnects embedded within the same insulating level layer. | 07-09-2009 |
20090174076 | SEMICONDUCTOR DEVICE AND THE METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate; a metal electrode wiring laminate on the semiconductor substrate, the metal electrode wiring laminate being patterned with a predetermined wiring pattern; the metal electrode wiring laminate including an undercoating barrier metal laminate and aluminum or aluminum alloy film on the undercoating barrier metal laminate; and organic passivation film covering the metal electrode wiring laminate, wherein the barrier metal laminate is a three-layered laminate including titanium films sandwiching a titanium nitride film. The semiconductor device according to the invention facilitates improving the moisture resistance of the portion of the barrier metal laminate exposed temporarily in the manufacturing process, facilitates employing only one passivation film, facilitates preventing the failures caused by cracks from occurring and the failures caused by Si nodules remaining in the aluminum alloy from increasing. | 07-09-2009 |
20090184422 | METHOD FOR FORMING METAL LINE OF SEMICONDUCTOR DEVICE WITHOUT PRODUCTION OF SIDEWALL OXIDE IN METAL LINE FORMING REGION - A method for forming a metal line of a semiconductor device includes forming an insulation layer having a contact hole over a semiconductor substrate. Any one of a TiN layer and a TaN layer is formed on the insulation layer, including a surface of the contact hole, and an anti-reflection layer is formed on any one of the TiN layer and the TaN layer. A trench is defined at an upper end of the contact hole by etching the anti-reflection layer, any one of the TiN layer and the TaN layer, and the insulation layer. Subsequently, the anti-reflection layer is removed and a metal layer is formed to fill the trench and the contact hole. | 07-23-2009 |
20090184423 | LOW RESISTANCE AND INDUCTANCE BACKSIDE THROUGH VIAS AND METHODS OF FABRICATING SAME - A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench aligned over and within a perimeter of the dielectric isolation and extending to the dielectric isolation; extending the trench formed in the first dielectric layer through the dielectric isolation and into the substrate to a depth less than a thickness of the substrate; filling the trench and co-planarizing a top surface of the trench with a top surface of the first dielectric layer to form an electrically conductive through via; and thinning the substrate from a backside of the substrate to expose the through via. | 07-23-2009 |
20090189282 | Semiconductor device - A semiconductor device according to the present invention includes: a low dielectric layer made of a low dielectric material; a high dielectric layer formed on the low dielectric layer and made of a high dielectric material having a higher dielectric constant than the low dielectric material; a protective layer formed on the high dielectric layer and made of an insulating material differing from the low dielectric material and the high dielectric material; a groove formed by digging in from an upper surface of the protective layer to the low dielectric layer; a barrier film coated onto a bottom surface and side surfaces of the groove and made of a material having a barrier property with respect to diffusion of Cu; and a wiring formed on the barrier film, made of a metal material having Cu as a main component, and completely filling the groove. | 07-30-2009 |
20090189283 | ALUMINUM METAL LINE OF A SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of forming an aluminum line of a semiconductor device where first A metal thin layer, a first aluminum layer, and a first B metal thin layer are sequentially applied on an interlayer insulating layer. A photolithography process is performed to form a metal line pattern, and etching is performed thereon. An intermetallic dielectric layer is applied on the metal line pattern. The first B metal thin layer is removed by a chemical mechanical planarization process to form a first stage metal line. A second aluminum layer and a second metal thin layer are sequentially applied. Photoresist is applied, a photolithography process is performed to form a metal line pattern, and etching is performed to form a second stage metal line. An intermetallic dielectric layer is applied on the second stage metal line. A chemical mechanical planarization process is performed on the second intermetallic dielectric layer. | 07-30-2009 |
20090189284 | SEMICONDUCTOR DEVICE HAVING A REDUCTANT LAYER AND MANUFACTURING METHOD THEREOF - A semiconductor device includes an inter-metal dielectric (IMD) formed on a substrate and having at least one via hole, a via hole formed by filling the via hole with a first metal, a reductant layer formed on the via plug and the inter-metal dielectric to a predetermined thickness, and a metal line layer formed by depositing a second metal on the reductant layer. | 07-30-2009 |
20090194875 | HIGH PURITY Cu STRUCTURE FOR INTERCONNECT APPLICATIONS - A structure and method of forming a high purity copper structure for interconnect applications is described. The structure includes a patterned dielectric material and at least one Cu-containing conductive material having an upper surface embedded within the dielectric material; and a diffusion barrier and a noble metal liner separating the patterned dielectric material from the at least one Cu-containing conductive material; where the Cu-containing conductive material having high purity, C<10 ppm, Cl<10 ppm, S<10 ppm, and uniform impurity. A method of fabricating the interconnect structure is also described. The method includes providing an initial interconnect structure that includes a dielectric having at least one opening; forming a diffusion barrier layer on all exposed surfaces; forming a noble metal layer on the diffusion barrier layer; forming a Cu containing layer on the noble metal layer; and completely filling the at least one opening with the Cu containing layer. | 08-06-2009 |
20090194876 | INTERCONNECT STRUCTURE AND METHOD FOR Cu/ULTRA LOW k INTEGRATION - A semiconductor structure is provided that includes a lower interconnect level including a first dielectric material having at least one conductive feature embedded therein; a dielectric capping layer located on the first dielectric material and some, but not all, portions of the at least one conductive feature; and an upper interconnect level including a second dielectric material having at least one conductively filled via and an overlying conductively filled line disposed therein, wherein the conductively filled via is in contact with an exposed surface of the at least one conductive feature of the first interconnect level by an anchoring area. Moreover, the conductively filled via and conductively filled line of the inventive structure are separated from the second dielectric material by a single continuous diffusion barrier layer. As such, the second dielectric material includes no damaged regions in areas adjacent to the conductively filled line. A method of forming such an interconnect structure is also provided. | 08-06-2009 |
20090200668 | INTERCONNECT STRUCTURE WITH HIGH LEAKAGE RESISTANCE - An interconnect structure is provided in which the conductive feature (i.e., conductive material) is not coplanar with the upper surface of the dielectric material, but instead the conductive material is recessed below an upper surface of the dielectric material. In addition to being recessed below the upper surface of the dielectric material, the conductive material of the interconnect structure is surrounded on all sides (i.e., sidewall surfaces, upper surface and bottom surface) by a diffusion barrier material. Unlike prior art interconnect structures, the barrier material located on the upper surface of the recessed conductive material is located with an opening including the recessed conductive material. | 08-13-2009 |
20090200669 | ENHANCED INTERCONNECT STRUCTURE - The present invention provides a semiconductor interconnect structure with improved mechanical strength at the capping layer/dielectric layer/diffusion barrier interface. The interconnect structure has Cu diffusion barrier material embedded in the Cu capping material. The barrier can be either partially embedded in the cap layer or completely embedded in the capping layer. | 08-13-2009 |
20090200670 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first conductor disposed on a semiconductor substrate; an oxygen-containing insulation film disposed on the semiconductor substrate and on the first conductor, the insulation film having a contact hole which extends to the first conductor and a trench which is connected to an upper portion of the contact hole; a zirconium oxide film disposed on a side surface of the contact hole and a side surface and a bottom surface of the trench; a zirconium film disposed on the zirconium oxide film inside the contact hole and inside the trench; and a second conductor composed of Cu embedded into the contact hole and into the trench. | 08-13-2009 |
20090200671 | SIP SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A System In Package (SIP) semiconductor device and a method for manufacturing a SIP device. A TiSiN film may be used as a diffusion barrier film for metal wiring in a SIP semiconductor device. A TiSiN film may provide relatively good step coverage in a relatively easy formation process, which may maximize reliability of a semiconductor device. | 08-13-2009 |
20090200672 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Disclosed is a method for manufacturing a semiconductor device. This method includes the step of forming a diffusion barrier film, which is interposed between a silicon film and a metal film and functions to prevent diffusion between the silicon and metal films. The diffusion barrier film is formed of a WSixNy film or a WSix film by using an ALD process. | 08-13-2009 |
20090200673 | VIA BOTTOM CONTACT AND METHOD OF MANUFACTURING SAME - A method of fabricating a device includes depositing a electromigration (EM) resistive material in an etched trench formed in a substrate and a wiring layer. The EM resistive material is formed in electrical contact with an underlying diffusion barrier layer and wiring layer. The method further includes forming a via structure in electrical contact with the EM resistive material and the wiring layer. The method results in a structure which prevents an open circuit. | 08-13-2009 |
20090206484 | MICROSTRUCTURE MODIFICATION IN COPPER INTERCONNECT STRUCTURE - Cobalt is added to a copper seed layer, a copper plating layer, or a copper capping layer in order to modify the microstructure of copper lines and vias. The cobalt can be in the form of a copper-cobalt alloy or as a very thin cobalt layer. The grain boundaries configured in bamboo microstructure in the inventive metal interconnect structure shut down copper grain boundary diffusion. The composition of the metal interconnect structure after grain growth contains from about 1 ppm to about 10% of cobalt in atomic concentration. Grain boundaries extend from a top surface of a copper-cobalt alloy line to a bottom surface of the copper-cobalt alloy line, and are separated from any other grain boundary by a distance greater than a width of the copper-cobalt alloy line. | 08-20-2009 |
20090206485 | NOVEL STRUCTURE AND METHOD FOR METAL INTEGRATION - An interconnect structure including a gouging feature at the bottom of one of the via openings and a method of forming the same are provided. In accordance with the present invention, the method of forming the interconnect structure does not disrupt the coverage of the deposited diffusion barrier in the overlying line opening, nor does it introduce damages caused by Ar sputtering into the dielectric material including the via and line openings. In accordance with the present invention, such an interconnect structure contains a diffusion barrier layer only within the via opening, but not in the overlying line opening. This feature enhances both mechanical strength and diffusion property around the via opening areas without decreasing volume fraction of conductor inside the line openings. In accordance with the present invention, such an interconnect structure is achieved by providing the gouging feature in the bottom of the via opening prior to formation of the line opening and deposition of the diffusion barrier in said line opening. | 08-20-2009 |
20090212432 | SEMICONDUCTOR DEVICE, ITS MANUFACTURING METHOD, AND SPUTTERING TARGET MATERIAL FOR USE IN THE METHOD - A semiconductor device enables a barrier layer to fully acquire a barriering property against the diffusion of Cu from a wiring main body and the diffusion of Si from an insulating film, enhances the adhesiveness of the barrier layer and the insulating film and excels in reliability of operation over a long period of time. In this invention, a semiconductor device | 08-27-2009 |
20090212433 | STRUCTURE AND PROCESS FOR METALLIZATION IN HIGH ASPECT RATIO FEATURES - A high aspect ratio metallization structure is provided in which a noble metal-containing material is present at least within a lower portion of a contact opening located in a dielectric material and is in direct contact with a metal semiconductor alloy located on an upper surface of a material stack of at least one semiconductor device. In one embodiment, the noble metal-containing material is plug located within the lower region of the contact opening and an upper region of the contact opening includes a conductive metal-containing material. The conductive metal-containing material is separated from plug of noble metal-containing material by a bottom walled portion of a U-shaped diffusion barrier. In another embodiment, the noble metal-containing material is present throughout the entire contact opening. | 08-27-2009 |
20090212434 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES AND A SEMICONDUCTOR STRUCTURE - Processes for improving adhesion of films to semiconductor wafers and a semiconductor structure are provided. By implementing the processes of the invention, it is possible to significantly suppress defect creation, e.g., decrease particle generation, during wafer fabrication processes. More specifically, the processes described significantly reduce flaking of a TaN film from edges or extreme edges (bevel) of the wafer by effectively increasing the adhesion properties of the TaN film on the wafer. The method increasing a mol percent of nitride with respect to a total tantalum plus nitride to 25% or greater during a barrier layer fabrication process. | 08-27-2009 |
20090218691 | BILAYER METAL CAPPING LAYER FOR INTERCONNECT APPLICATIONS - The invention provides semiconductor interconnect structures that have improved reliability and technology extendibility. In the present invention, a second metallic capping layer is located on a surface of a first metallic cap layer which is, in turn, located on a surface of the conductive feature embedded within a first dielectric material. Both the first and second metallic capping layers are located beneath an opening, e.g., a via opening, the is present within an overlying second dielectric material. The second metallic capping layer protects the first dielectric capping layer from being removed (either completely or partially) during subsequent processing steps. Interconnect structures including via gouging features as well as non-via gouging features are disclosed. The present invention provides methods of fabricating such semiconductor interconnect structures. | 09-03-2009 |
20090218692 | Barrier for Copper Integration in the FEOL - Copper integration in the FEOL stage is disclosed for a preliminary semiconductor device by forming a recess in a substrate of the device, the recess having a bottom surface and sidewall surfaces, depositing a barrier layer having about a 100% step coverage on the sidewall surfaces and the bottom surface, and depositing copper into the recess over the barrier layer to form a contact providing electrical connection to the preliminary semiconductor device. | 09-03-2009 |
20090218693 | LOW RESISTANCE HIGH RELIABILITY CONTACT VIA AND METAL LINE STRUCTURE FOR SEMICONDUCTOR DEVICE - A semiconductor contact structure includes a copper plug formed within a dual damascene, single damascene or other opening formed in a dielectric material and includes a composite barrier layer between the copper plug and the sidewalls and bottom of the opening. The composite barrier layer preferably includes an ALD TaN layer disposed on the bottom and along the sides of the opening although other suitable ALD layers may be used. A barrier material is disposed between the copper plug and the ALD layer. The barrier layer may be a Mn-based barrier layer, a Cr-based barrier layer, a V-based barrier layer, a Nb-based barrier layer, a Ti-based barrier layer, or other suitable barrier layers. | 09-03-2009 |
20090218694 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, SEMICONDUCTOR MANUFACTURING AND INSPECTING APPARATUS, AND INSPECTING APPARATUS - A semiconductor device having Cu wiring including a basic crystal structure which can reduce surface voids, and an inspecting technique for the semiconductor device. In the semiconductor device, surface voids can be reduced down to 1/10 or less of a current practical level by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 27 or less to all crystal grain boundaries of a Cu wiring to 60% or higher. Alternatively, a similar effect of surface void reduction can be obtained by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 3 to all crystal grain boundaries of a Cu wiring to 40% or higher. | 09-03-2009 |
20090230555 | TUNGSTEN LINER FOR ALUMINUM-BASED ELECTROMIGRATION RESISTANT INTERCONNECT STRUCTURE - An underlying interconnect level containing underlying W vias embedded in a dielectric material layer are formed on a semiconductor substrate. A metallic layer stack comprising, from bottom to top, a low-oxygen-reactivity metal layer, a bottom transition metal layer, a bottom transition metal nitride layer, an aluminum-copper layer, an optional top transition metal layer, and a top transition metal nitride layer. The metallic layer stack is lithographically patterned to form at least one aluminum-based metal line, which constitutes a metal interconnect structure. The low-oxygen-reactivity metal layer enhances electromigration resistance of the at least one aluminum-based metal line since formation of compound between the bottom transition metal layer and the dielectric material layer is prevented by the low-oxygen-reactivity metal layer, which does not interact with the dielectric material layer. | 09-17-2009 |
20090236744 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - A semiconductor device having a copper interconnection with high electromigration resistance is provided. A semiconductor device of the present invention includes an interconnection layer formed by forming a groove or a hole in an insulating film formed on a substrate, forming a barrier layer on the resulting substrate, forming a copper seed layer on the barrier layer, forming a copper-plated layer by an electrolytic plating method by use of this copper seed layer, and removing the copper-plated layer and the copper seed layer on the surface, wherein the copper seed layer comprises a plurality of layers including a small grain layer and a large grain layer, having different crystal grain sizes from each other, and the small grain layer is in contact with the barrier layer. | 09-24-2009 |
20090236745 | Adhesion to Copper and Copper Electromigration Resistance - The present invention relates to the improved adhesion between a patterned conductive metal layer, usually a copper layer, and a patterned barrier dielectric layer. The structure with the improved adhesion comprises an adhesion layer between a patterned barrier dielectric layer and a patterned conductive metal layer. The adhesion layer improves adhesion between the metal layer and the barrier layer without increasing the copper bulk electrical resistance. The method of making the structure with the improved adhesion comprises steps of thermal expositing the patterned conductive metal layer to an organometallic precursor to deposit an adhesion layer at least on the top of the patterned conductive metal layer. | 09-24-2009 |
20090236746 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device includes a contact plug electrically connected to a semiconductor substrate; a first barrier metal film with a columnar crystal structure arranged in contact with the semiconductor substrate at least on a bottom surface side of the contact plug; an amorphous film made of a material of the first barrier metal film arranged in contact with the first barrier metal film at least on the bottom surface side of the contact plug; a second barrier metal film made of a material identical to that of the first barrier metal film and having a columnar crystal structure, at least a portion of which is arranged in contact with the amorphous film on the bottom surface side and a side surface side of the contact plug; and a dielectric film arranged on the side surface side of the contact plug. | 09-24-2009 |
20090243104 | FORMING THICK METAL INTERCONNECT STRUCTURES FOR INTEGRATED CIRCUITS - Embodiments of an apparatus and methods for forming thick metal interconnect structures for integrated structures are generally described herein. Other embodiments may be described and claimed. | 10-01-2009 |
20090243105 | WIRE BONDING ON REACTIVE METAL SURFACES OF A METALLIZATION OF A SEMICONDUCTOR DEVICE BY PROVIDING A PROTECTIVE LAYER - In semiconductor devices having a copper-based metallization system, bond pads for wire bonding may be formed directly on copper surfaces, which may be covered by an appropriately designed protection layer to avoid unpredictable copper corrosion during the wire bond process. A thickness of the protection layer may be selected such that bonding through the layer may be accomplished, while also ensuring a desired high degree of integrity of the copper surface. | 10-01-2009 |
20090243106 | STRUCTURES AND METHODS TO ENHANCE COPPER METALLIZATION - Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary structure includes an inhibiting layer between an insulator and a metallization layer. The insulator includes a polymer or an insulating oxide compound. And, the inhibiting layer has a compound formed from a reaction between the polymer or insulating oxide compound and a transition metal, a representative metal, or a metalloid. | 10-01-2009 |
20090250816 | ULTRA-THIN DIFFUSION-BARRIER LAYER FOR CU METALLIZATION - Diffusion barrier layer is required during copper metallization in IC processing to prevent Cu from diffusion into the contacting silicon material and reacting to form copper silicide, which consumes Cu and deteriorates electrical conduction. With decreasing feature sizes of IC devices, such as those smaller than 90 nano-meter (nm), the thickness of diffusion barrier layer must be thinner than 10 nm. For example, a thickness of 2 nm will be called for at the feature size 27 nm. Disclosed in the present invention is ultra-thin barrier materials and structures based on tantalum silicon carbide, and its composite with another metallic layer Ru film. The retarding temperature, by which no evidence of copper diffusion can be identified, is 600˜850° C. depending on thickness, composition and film structure, at a thickness 1.6˜5 nm. | 10-08-2009 |
20090250817 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device according to embodiments includes forming a resist film above an object to be etched, the resist film having a pattern with notches provided in the vicinity of corners having an angle of less than 180 degrees on an opening side, and dry etching the object to be etched using the resist film as a mask, thereby transferring the pattern of the resist film. | 10-08-2009 |
20090250818 | VIA ELECTROMIGRATION IMPROVEMENT BY CHANGING THE VIA BOTTOM GEOMETRIC PROFILE - An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer. | 10-08-2009 |
20090256259 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device has a first interlayer insulating film formed on a semiconductor substrate, a first plug and a second plug embedded in holes formed to open the first interlayer insulating film, a capacitor formed on the first interlayer insulating film so as to connect to the first plug, a hydrogen barrier film including an aluminum oxynitride material and formed so as to cover the capacitor, the first interlayer insulating film and the second plug, a second interlayer insulating film formed on the hydrogen barrier film, a third plug embedded in a hole formed so as to open the second interlayer insulating film and the hydrogen barrier film and expose an upper surface of the upper electrode, and a fourth plug embedded in a hole formed so as to open the second interlayer insulating film and the hydrogen barrier film and expose an upper surface of the second plug. | 10-15-2009 |
20090273084 | OPTICALLY TRANSPARENT WIRES FOR SECURE CIRCUITS AND METHODS OF MAKING SAME - A structure and a method. The method includes: forming a dielectric layer on a substrate; forming electrically conductive first and second wires in the dielectric layer, top surfaces of the first and second wires coplanar with a top surface of the dielectric layer; and either (i) forming an electrically conductive third wire on the top surface of the dielectric layer, and over the top surfaces of the first and second wires, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy or (ii) forming an electrically conductive third wire between the top surface of the dielectric layer and the substrate, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy. | 11-05-2009 |
20090273085 | CuSiN/SiN DIFFUSION BARRIER FOR COPPER IN INTEGRATED-CIRCUIT DEVICES - The present invention relates to an integrated-circuit device that has at least one Copper-containing feature in a dielectric layer, and a diffusion-barrier layer stack arranged between the feature and the dielectric layer. The integrated-circuit device of the invention has a diffusion-barrier layer stack, which comprises, in a direction from the Copper-containing feature to the dielectric layer, a CuSiN layer and a SiN layer. This layer combination provides an efficient barrier for suppressing Copper diffusion from the feature into the dielectric layer. Furthermore, a CuSiN/SiN layer sequence provides an improved adhesion between the layers of the diffusion-barrier layer stack and the dielectric layer, and thus improves the electromigration performance of the integrated-circuit device during operation. Therefore, the reliability of device operation and the lifetime of the integrate-circuit device are improved in comparison with prior-art devices. The invention further relates to a method for fabricating such an integrated-circuit device. | 11-05-2009 |
20090278258 | INTERCONNECT STRUCTURE WITH A MUSHROOM-SHAPED OXIDE CAPPING LAYER AND METHOD FOR FABRICATING SAME - An interconnect structure is provided that includes a dielectric material | 11-12-2009 |
20090278259 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes an insulation film formed above a semiconductor substrate, a conductor containing Cu formed in the insulation film, and a layer film formed between the insulation film and the conductor and formed of a first metal film containing Ti and a second metal film different from the first metal film, a layer containing Ti and Si is formed on the surface of the conductor. | 11-12-2009 |
20090283907 | LOW-RESISTANCE INTERCONNECTS AND METHODS OF MAKING SAME - Devices and methods for providing low-resistance interconnects in a semiconductor device are provided. Specifically, one or more embodiments of the present invention relate to disposing a conductive material in a trench without disposing a resistive barrier material between the conductive material and the sidewalls of the trench so that the conductive material takes up the full width of the trench. For example, the trench may be disposed over one or more contacts made of a barrier material such as titanium nitride that also acts as a seed, and the conductive material may be grown on top of the titanium nitride to fill the trench. | 11-19-2009 |
20090283908 | METAL LINE OF SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A metal line of a semiconductor device includes an insulation layer formed on a semiconductor substrate and a metal line forming region is formed in the insulation layer. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer, and the diffusion layer has a multi-layered structure of an Ru layer, an Ru | 11-19-2009 |
20090283909 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole. | 11-19-2009 |
20090283910 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device includes: a metal-containing compound layer on a semiconductor substrate; a dielectric film on the semiconductor substrate and the metal-containing compound layer; a contact hole penetrating through the dielectric film to reach the metal-containing compound layer; a contact plug in the contact hole. The semiconductor device further includes a manganese oxide layer extending between the contact plug and respective one of the dielectric film and the metal-containing compound layer. | 11-19-2009 |
20090289365 | STRUCTURE AND PROCESS FOR CONDUCTIVE CONTACT INTEGRATION - A semiconductor structure including a highly reliable high aspect ratio contact structure in which key-hole seam formation is eliminated is provided. The key-hole seam formation is eliminated in the present invention by providing a densified noble metal-containing liner within a high aspect ratio contact opening that is present in a dielectric material. The densified noble metal-containing liner is located atop a diffusion barrier and both those elements separate the conductive material of the inventive contact structure from a conductive material of an underlying semiconductor structure. The densified noble metal-containing liner of the present invention is formed by deposition of a noble metal-containing material having a first resistivity and subjecting the deposited noble metal-containing material to a densification treatment process (either thermal or plasma) that decreases the resistivity of the deposited noble metal-containing material to a lower resistivity. | 11-26-2009 |
20090289366 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In one aspect of the present invention, a semiconductor device may include an inter-wiring dielectric film in which a wiring trench is formed, a metal wiring layer formed in the wiring trench in the inter-wiring dielectric film, a first barrier layer formed on a side surface of the wiring trench, the first barrier layer being an oxide film made from a metal different from a main constituent metal element in the wiring layer, a second barrier layer formed on a side surface of the wiring layer, the second barrier layer having a Si atom of the metal used in the wiring layer, and a gap formed between the first barrier layer and the second barrier layer. | 11-26-2009 |
20090289367 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A copper interconnection layer is formed in an interconnection trench at a surface of an interlayer insulating film. A diffusion preventing insulating film is formed to cover the copper interconnection layer and is made of at least one of SiC and SiCN. An insulating film is formed on the copper interconnection layer with the diffusion preventing insulating film interposed and is made of SiN. | 11-26-2009 |
20090289368 | INTERCONNECT STRUCTURE HAVING ENHANCED ELECTROMIGRATION RELIABILTY AND A METHOD OF FABRICATING SAME - An interconnect structure having improved electromigration (EM) reliability is provided. The inventive interconnect structure avoids a circuit dead opening that is caused by EM failure by incorporating a EM preventing liner at least partially within a metal interconnect. In one embodiment, a “U-shaped” EM preventing liner is provided that abuts a diffusion barrier that separates conductive material from the dielectric material. In another embodiment, a space is located between the “U-shaped” EM preventing liner and the diffusion barrier. In yet another embodiment, a horizontal EM liner that abuts the diffusion barrier is provided. In yet a further embodiment, a space exists between the horizontal EM liner and the diffusion barrier. | 11-26-2009 |
20090302472 | Non-volatile memory devices including shared bit lines and methods of fabricating the same - Provided are non-volatile memory devices and methods of fabricating the same, including improved bit line and contact formation that may reduce resistance and parasitic capacitance, thereby reducing manufacturing costs and improving device performance. The non-volatile memory devices may include a substrate; a plurality of field regions formed on the substrate, each of the field regions including a homogeneous first field and a second field that is divided into two sub regions via a bridge region; an active region formed on the substrate and defined as having a string structure by the field regions, where at least two strings may be connected via one of the bridge regions; and a plurality of shared bit lines may be formed on the field regions and connected to the active region via bit line contacts, where the bit line contacts may be direct contacts. | 12-10-2009 |
20090302473 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a first interlayer insulating film formed over a semiconductor substrate; a plurality of interconnects formed in the first interlayer insulating film; and a via and a dummy via, which are formed in the first interlayer insulating film so as to connect to at least one of the plurality of interconnects. A void is selectively formed between adjacent ones of the interconnects in the first interlayer insulating film. The dummy via is formed under an interconnect which is in contact with the void, so as to connect to the interconnect. The via and the dummy via are surrounded by the first interlayer insulating film with no void interposed therebetween. | 12-10-2009 |
20090302474 | Atomic laminates for diffucion barrier applications - The present invention relates to a very thin multilayer diffusion barrier for a semiconductor device and fabrication method thereof. The multilayer diffusion barrier according to the present invention is fabricated by forming a very thin, multilayer diffusion barrier composed of even thinner sub-layers, where the sub-layers are only a few atoms thick. The present invention provides a diffusion barrier layer for a semiconductor device which is in a substantially amorphous state and thermodynamically stable, even at high temperatures. | 12-10-2009 |
20090309222 | METHOD AND SEMICONDUCTOR DEVICE HAVING COPPER INTERCONNECT FOR BONDING - An improved wire bond is provided with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductive lead of a TAB tape bond with the bond pad of a semiconductor device. More specifically, an improved wire bond is described wherein the bond pad on a surface of the semiconductor device comprises a layer of copper and at least one layer of metal and/or at least a barrier layer of material between the copper layer and one layer of metal on the copper layer to form a bond pad. | 12-17-2009 |
20090309223 | INTERCONNECT LAYERS WITHOUT ELECTROMIGRATION - A structure and a method for forming the same. The structure includes (a) an interlevel dielectric (ILD) layer; (b) a first electrically conductive line and a second electrically conductive line both residing in the ILD layer; (c) a diffusion barrier region residing in the ILD layer. The diffusion barrier region (i) physically isolates, (ii) electrically couples together, and (iii) are in direct physical contact with the first and second electrically conductive lines. The first and second electrically conductive lines each comprises a first electrically conductive material. The diffusion barrier region comprises a second electrically conductive material different from the first electrically conductive material. The diffusion barrier region is adapted to prevent a diffusion of the first electrically conductive material through the diffusion barrier region. | 12-17-2009 |
20090315180 | Multi-layer thick metallization structure for a microelectronic device, intergrated circuit containing same, and method of manufacturing an integrated circuit containing same - A multi-layer thick metallization structure for a microelectronic device includes a first barrier layer ( | 12-24-2009 |
20090315181 | Liquid phase molecular self-assembly for barrier deposition and structures formed thereby - Methods and associated structures of forming a microelectronic structure are described. Those methods may comprise dissolving a metal precursor in a non-aqueous solvent in a bath; placing a substrate comprising an interconnect opening in the bath, wherein the metal precursor forms a monolayer within the interconnect opening; and placing the substrate in a coreactant mixture, wherein the coreactant reacts with the metal precursor to form a thin barrier monolayer. | 12-24-2009 |
20090321933 | Structure to Facilitate Plating Into High Aspect Ratio Vias - Improved high aspect ratio vias and techniques for the formation thereof are provided. In one aspect, a method of fabricating a copper plated high aspect ratio via is provided. The method comprises the following steps. A high aspect ratio via is etched in a dielectric layer. A diffusion barrier layer is deposited into the high aspect ratio via and over one or more surfaces of the dielectric layer. A copper layer is deposited over the diffusion barrier layer. A ruthenium layer is deposited over the copper layer. The high aspect ratio via is filled with copper plated onto the ruthenium layer. A copper plated high aspect ratio via formed by this method is also provided. | 12-31-2009 |
20090321934 | SELF-ALIGNED CAP AND BARRIER - A semiconductor device comprising an insulator layer formed on a substrate; a via formed by etching into the insulator layer to a first depth; a first metal layer formed over the insulator layer; a second metal layer deposited on the first metal layer to substantially fill the via; a metal-dopant alloy layer deposited over the second metal, wherein the dopant is diffused by annealing through the second metal layer and the first metal layer deposited in the via, such that the dopant migrates to a boundary between the first metal layer and the insulator to form a barrier; and an etch stop layer deposited over the via after planarization of the via and the insulator layer to form a barrier cap. | 12-31-2009 |
20090321935 | Methods of forming improved electromigration resistant copper films and structures formed thereby - Methods and associated structures of forming a microelectronic structure are described. Those methods may comprise forming a doping material on an overburden region of a conductive structure, diffusing a portion of the doping material into a portion of the conductive structure, and then removing the overburden region. | 12-31-2009 |
20090321936 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS, SEMICONDUCTOR DEVICE, COMPUTER PROGRAM AND STORAGE MEDIUM - Provided is a semiconductor device which has excellent adhesiveness to a copper film and a base film thereof and has a small resistance between wirings. The semiconductor device includes a porous insulating layer (SIOC film | 12-31-2009 |
20090321937 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device includes an insulating film including oxygen formed over a semiconductor substrate, a recess formed in the insulating film, a refractory metal film formed on the inner wall of the recess, a metal film including copper, manganese, and nitrogen formed on the refractory metal film, and a copper film formed on the metal film to fill in the recess. | 12-31-2009 |
20090321938 | Methods of Manufacturing Copper Interconnect Systems - An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including copper within the at least one trench. A cap layer including metal may be provided on the first conductive region. A second dielectric layer may be over the first conductive region and the cap layer. A dielectric etch stop and diffusion barrier layer may be over the second dielectric layer, and a via may be over the first conductive region and through the second dielectric layer and the cap layer. A diffusion barrier layer may be on sidewalls of the via, and an alloy seed layer including copper and at least one of tantalum, molybdenum, chromium, and tungsten may be over the diffusion barrier. The allow seed layer may also be over the dielectric etch stop and diffusion barrier layer, and the alloy seed layer may be in contact with the first conductive region. | 12-31-2009 |
20100001400 | SOLDER CONTACT - A low melting temperature solder is provided for producing a solder contact between a connection element and a contact structure of a semiconductor component. | 01-07-2010 |
20100001401 | SEMICONDUCTOR DEVICE INCLUDING INTERCONNECT LAYER MADE OF COPPER - A semiconductor device includes an interlayer insulating film, a barrier metal layer, a conductive layer and a first insulating film. The barrier metal layer is formed on a bottom surface and a side face of a trench made in the interlayer insulating film. The conductive layer is formed on the barrier metal layer. The conductive layer has its upper surface lower than an upper surface of an opening of the trench and buries a part of the trench. The first insulating film is formed on the conductive layer and is formed on the barrier metal layer on a side face of the opening of the trench. The first insulating film is made of a material having a dielectric constant higher than that of the interlayer insulating film. | 01-07-2010 |
20100007021 | Methods of Fabricating Semiconductor Devices Including Porous Insulating Layers - Semiconductor devices including a substrate and an uppermost insulating layer formed on the substrate and having pores is provided. A conductive wiring is provided in the uppermost insulating layer. Dummy vias are provided, each penetrating the uppermost insulating layer, being adjacent to the conductive wiring, and having a space therein. Related methods of fabricating semiconductor devices are also provided. | 01-14-2010 |
20100007022 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes an insulating film formed on a semiconductor substrate, and a buried interconnect formed in the insulating film and made of copper or a copper alloy. A barrier metal layer made of a platinum group element or a platinum group element alloy is formed between the insulating film and the buried interconnect, and the barrier metal layer partially includes an amorphous structure having a degree of amorphousness that provides a relatively high barrier property. | 01-14-2010 |
20100007023 | MANUFACTURE METHOD FOR SEMICONDUCTOR DEVICE HAVING IMPROVED COPPER DIFFUSION PREVENTIVE FUNCTION OF PLUGS AND WIRINGS MADE OF COPPER OR COPPER ALLOY - (a) A copper alloy film containing at least two types of metal elements in addition to copper is formed on the surface of an insulator containing oxygen and formed on a semiconductor substrate. (b) A metal film made of pure copper or copper alloy is formed on the copper alloy film. (c) After the step (a) or (b), heat treatment is performed under the condition that a metal oxide film is formed on a surface of the insulator through reaction between the oxygen in the insulator and the metal elements in the copper alloy film. | 01-14-2010 |
20100013098 | METHOD OF FORMING AN INTERCONNECT STRUCTURE ON AN INTEGRATED CIRCUIT DIE - A method of forming an interconnect structure, comprising forming a first interconnect layer ( | 01-21-2010 |
20100013099 | MECHANICALLY STABLE DIFFUSION BARRIER STACK AND METHOD FOR FABRICATING THE SAME - A mechanically stable diffusion barrier stack structure and method of fabricating the same is disclosed. The fusion barrier stack structure having a molybdenum nitride layer deposited on a molybdenum layer and operates to prevent diffusion between a semiconductor layer and a metal interconnect. The method for fabricating includes depositing a molybdenum layer outwardly from the semiconductor layer in a deposition chamber, and depositing a molybdenum nitride layer outwardly from the molybdenum layer in the deposition chamber. | 01-21-2010 |
20100013100 | Method and System for Forming Conductive Bumping with Copper Interconnection - An integrated circuit system with one or more copper interconnects is provided. The one or more copper interconnects are in conductive contact with a substrate. The integrated circuit system includes a first dielectric layer, a copper material filling a first via through the first dielectric layer, a second dielectric layer in contact with the first dielectric layer, and a diffusion barrier layer. The diffusion barrier layer at least partially fills a second via through the second dielectric layer. At least a first part of the diffusion barrier layer is in direct contact with the copper material, and at least a second part of the diffusion barrier layer is in direct contact with the second dielectric layer. The integrated circuit system further includes a gold material at least partially filling the second via. The gold material is conductively connected with the copper material through the diffusion barrier layer and conductively connected with a substrate. Additionally, a method for making such an integrated circuit system with one or more copper interconnects is provided. | 01-21-2010 |
20100019386 | ELECTRICAL CONDUCTOR LINE HAVING A MULTILAYER DIFFUSION BARRIER FOR USE IN A SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - An electrical conductor having a multilayer diffusion barrier of use in a resultant semiconductor device is presented. The electrical conductor line includes an insulation layer, a diffusion barrier, and a metal line. The insulation layer is formed on a semiconductor substrate and having a metal line forming region. The diffusion barrier is formed on a surface of the metal line forming region of the insulation layer and has a multi-layered structure made of TaN layer, an Mo | 01-28-2010 |
20100025851 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same include forming a second copper-plated layer over a second IMD layer and inside a second aperture formed in the second IMD by an electroplating process that uses the exposed first copper-plated layer as a seed layer. With the method, the copper-plated layer may be more simply and rapidly formed and achieve superior gap filling characteristics. | 02-04-2010 |
20100032837 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device according to the present invention includes: a semiconductor substrate; a first copper interconnection provided on the semiconductor substrate; an insulating layer provided over the first copper interconnection and having a hole extending therethrough to the first copper interconnection; a barrier layer composed of a tantalum-containing material and covering at least a sidewall of the hole and a part of the first copper interconnection exposed in the hole; and a second copper interconnection provided in intimate contact with the barrier layer and electrically connected to the first copper interconnection via the barrier layer; wherein the barrier layer has a nitrogen concentration profile such that the concentration of nitrogen contained in the material varies to be lower in a boundary portion of the barrier layer adjacent to the first copper interconnection and in a boundary portion of the barrier layer adjacent to the second copper interconnection and higher in an intermediate portion of the barrier layer defined between the boundary portions. | 02-11-2010 |
20100032838 | AMORPHOUS CARBON FILM, SEMICONDUCTOR DEVICE, FILM FORMING METHOD, FILM FORMING APPARATUS AND STORAGE MEDIUM - Provided is an amorphous carbon film having a high elastic modulus and a low thermal contraction rate with a suppressed low dielectric constant, a semiconductor device including the amorphous carbon film and a technology for forming the amorphous carbon film. Since the amorphous carbon film is formed by controlling an additive amount of Si (silicon) during film formation, it is possible to form the amorphous carbon film having a high elastic modulus and a low thermal contraction rate with a suppressed dielectric constant as low as 3.3 or less. Accordingly, when the amorphous carbon film is used as a film in the semiconductor device, troubles such as a film peeling can be suppressed. | 02-11-2010 |
20100032839 | ELECTRODE STRUCTURE, SEMICONDUCTOR ELEMENT, AND METHODS OF MANUFACTURING THE SAME - According to the present invention, there is provided an electrode structure which includes: a nitride semiconductor layer; an electrode provided over the nitride semiconductor layer; and an electrode protective film provided over the electrode, wherein the nitride semiconductor layer contains a metal nitride containing Hb, Hf or Zr as a constitutive element, the electrode has a portion having a metal oxide containing Ti or V as a constitutive element formed therein, and the electrode protective film covers at least a portion of the electrode, and contains a protective layer having Au or Pt as a constitutive element. | 02-11-2010 |
20100032840 | Semiconductor Device with an Improved Solder Joint - A semiconductor device with an improved solder joint system is described. The solder system includes two copper contact pads connected by a body of solder and the solder is an alloy including tin, silver, and at least one metal from the transition groups IIIA, IVA, VA, VIA, VIIA, and VIIIA of the Periodic Table of the Elements. The solder joint system also includes, between the pads and the solder, layers of intermetallic compounds, which include grains of copper and tin compounds and copper, silver, and tin compounds. The compounds contain the transition metals. The inclusion of the transition metals in the compound grains reduce the compound grains size and prevent grain size increases after the solder joint undergoes repeated solid/liquid/solid cycles. | 02-11-2010 |
20100038782 | NITROGEN-CONTAINING METAL CAP FOR INTERCONNECT STRUCTURES - An interconnect structure is provided that has enhanced electromigration reliability without degrading circuit short yield, and improved technology extendibility. The inventive interconnect structure includes a dielectric material having a dielectric constant of about 3.0 or less. The dielectric material has at least one conductive material embedded therein. A nitrogen-containing noble metal cap is located predominately (i.e., essentially) on an upper surface of the at least one conductive region. The nitrogen-containing noble metal cap does not extend onto an upper surface of the dielectric material. In some embodiments, the nitrogen-containing noble metal cap is self-aligned to the embedded conductive material, while in other embodiments some portion of the nitrogen-containing noble metal cap extends onto an upper surface of a diffusion barrier that separates the at least one conductive material from the dielectric material. A method of fabricating such an interconnect structure utilizing a low temperature (about 200° C. or less) chemical deposition process is also provided. | 02-18-2010 |
20100038783 | METAL CAP FOR BACK END OF LINE (BEOL) INTERCONNECTS, DESIGN STRUCTURE AND METHOD OF MANUFACTURE - A structure is provided with a metal cap for back end of line (BEOL) interconnects that substantially eliminates electro-migration (EM) damage, a design structure and a method of manufacturing the IC. The structure includes a metal interconnect formed in a dielectric material and a metal cap selective to the metal interconnect. The metal cap includes RuX, where X is at Boron, Phosphorous or a combination of Boron and Phosphorous. | 02-18-2010 |
20100038784 | REDUNDANT BARRIER STRUCTURE FOR INTERCONNECT AND WIRING APPLICATIONS, DESIGN STRUCTURE AND METHOD OF MANUFACTURE - A redundant diffusion barrier structure and method of fabricated is provided for interconnect and wiring applications. The structure can also be a design structure. The structure includes a first liner lining at least one of a trench and a via and a second liner deposited over the first liner. The second liner comprises RuX. X is at least one of Boron and Phosphorous. The structure comprises a metal deposited on the second liner in the at least one trench and via to form a metal interconnect or wiring. | 02-18-2010 |
20100038785 | Materials for Adhesion Enhancement of Copper Film on Diffusion Barriers - We have used the state-of-the-art computational chemistry techniques to identify adhesion promoting layer materials that provide good adhesion of copper seed layer to the adhesion promoting layer and the adhesion promoting layer to the barrier layer. We have identified factors responsible for providing good adhesion of copper layer on various metallic surfaces and circumstances under which agglomeration of copper film occur. Several promising adhesion promoting layer materials based on chromium alloys have been predicted to be able to significantly enhance the adhesion of copper films. Chromium containing complexes of a polydentate β-ketoiminate have been identified as chromium containing precursors to make the alloys with chromium. | 02-18-2010 |
20100038786 | Method for manufacturing a semiconductor device - A method for manufacturing a semiconductor device is disclosed. A semiconductor substrate such as bare silicon is provided, and a dielectric layer is formed over the semiconductor substrate. An opening is provided within the dielectric layer by removing a portion of the dielectric layer. A conformal first conductive layer is formed over the dielectric layer and the opening. A conformal second conductive layer is formed over the first conductive layer. A conformal barrier layer is formed over the second conductive layer. | 02-18-2010 |
20100038787 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has an interlayer insulating film that is formed on a semiconductor substrate and has a trench formed therein; a first diffusion barrier film formed on an inner surface of the trench; a Cu wiring layer buried in the trench with the first diffusion barrier film interposed between the Cu wiring layer and the inner surface of the trench; a second diffusion barrier film formed on top of the interlayer insulating film and the Cu wiring layer; an alloy layer primarily containing Cu formed at a first interface between the Cu wiring layer and the second diffusion barrier film; a first reaction layer that is formed at a second interface between the interlayer insulating film and the second diffusion barrier film; and a second reaction layer that is formed on the alloy layer and the first reaction layer. | 02-18-2010 |
20100038788 | MULTI-LAYERED METAL LINE OF SEMICONDUCTOR DEVICE FOR PREVENTING DIFFUSION BETWEEN METAL LINES AND METHOD FOR FORMING THE SAME - A multi-layered metal line of a semiconductor device includes a semiconductor substrate; a lower metal line formed on the semiconductor substrate and recessed on a surface thereof; an insulation layer formed on the semiconductor substrate including the lower metal line and having a damascene pattern for exposing a recessed portion of the lower metal line and for delimiting an upper metal line forming region; a glue layer formed on a surface of the recessed portion of the lower metal line; a first diffusion barrier formed on the glue layer to fill the recessed portion of the lower metal line; a second diffusion barrier formed on the glue layer and the first diffusion barrier; a third diffusion barrier formed on the second diffusion barrier and a surface of the damascene pattern; and an upper metal line formed on the third diffusion barrier to fill the damascene pattern. | 02-18-2010 |
20100044864 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - The present invention aims at providing a method of manufacturing a semiconductor device capable of suppressing metal diffusion from the upper face of wiring. | 02-25-2010 |
20100044865 | FABRICATION OF A DIFFUSION BARRIER CAP ON COPPER CONTAINING CONDUCTIVE ELEMENTS - A method for fabricating a self-aligned diffusion-barrier cap on a Cu-containing conductive element in an integrated-circuit device comprises:—providing a substrate having a Cu-containing conductive element embedded laterally into a dielectric layer and having an exposed surface;—depositing a metal layer on the exposed surface of conductive element;—inducing diffusion of metal from the metal layer into a top section of the conductive element;—removing the remaining metal layer;—letting diffused metal in the top section of the conductive element and particles of a second constituent react with each other so as to build a compound covering the conductive element. The metal of the metal layer and the second constituent are chosen so that the compound forms a diffusion barrier against Cu diffusion. A reduction the dielectric constant of the dielectric material in an interconnect stack of an integrated-circuit device is achieved. | 02-25-2010 |
20100044866 | SEMICONDUCTOR DEVICE HAVING VIA CONNECTING BETWEEN INTERCONNECTS - A first insulating film is provided between a lower interconnect and an upper interconnect. The lower interconnect and the upper interconnect are connected to each other by way of a via formed in the first insulating film. A dummy via or an insulating slit is formed on/in the upper interconnect near the via. | 02-25-2010 |
20100044867 | METHODS OF POST-CONTACT BACK END OF LINE THROUGH-HOLE VIA INTEGRATION - Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention. | 02-25-2010 |
20100052168 | METAL LINE HAVING A MULTI-LAYERED DIFFUSION LAYER IN A SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A metal line having a multi-layered diffusion layer in a resultant semiconductor device is presented along with corresponding methods of forming the same. The metal line includes an insulation layer, a multi-layered diffusion barrier, and a metal layer. The insulation layer is formed on a semiconductor substrate and has a metal line forming region. The multi-layered diffusion barrier is formed on a surface of the metal line forming region defined in the insulation layer. The diffusion barrier includes a VB | 03-04-2010 |
20100052169 | METAL LINE OF SEMICONDUCTOR DEVICE HAVING A DIFFUSION BARRIER AND METHOD FOR FORMING THE SAME - An insulation layer is formed on a semiconductor substrate so as to define a metal line forming region. A diffusion barrier having a multi-layered structure of an Mo | 03-04-2010 |
20100052170 | METAL LINE OF SEMICONDUCTOR DEVICE HAVING A DIFFUSION BARRIER AND METHOD FOR FORMING THE SAME - A metal line of a semiconductor device includes an insulation layer formed on a semiconductor substrate. The insulation layer has a metal line forming region. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer. The diffusion barrier includes a multi-layered structure that includes an MoB | 03-04-2010 |
20100052171 | CU WIRE IN SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - A Cu wire in a semiconductor device according to the present invention is a Cu wire embedded into wiring gutters or interlayer connective channels formed in an insulating film on a semiconductor substrate and the Cu wire comprises: a barrier layer comprising TaN formed on the wiring gutter side or the interlayer connective channel side; and a wire main body comprising Cu comprising one or more elements selected from the group consisting of Pt, In, Ti, Nb, B, Fe, V, Zr, Hf, Ga, Tl, Ru, Re, and Os in a total content of 0.05 to 3.0 atomic percent. The Cu wire in a semiconductor device according to the present invention is excellent in adhesiveness between the wire main body and the barrier layer. | 03-04-2010 |
20100052172 | METHOD OF FABRICATING COPPER DAMASCENE AND DUAL DAMASCENE INTERCONNECT WIRING - An integrated circuit and a method of manufacturing the integrated circuit, the method including: (a) providing a substrate; (b) forming a copper diffusion barrier layer on the substrate; (c) forming a dielectric layer on a top surface of the copper diffusion barrier layer; (d) forming a copper damascene or dual damascene wire in the dielectric layer, a top surface of the copper damascene or dual damascene wire coplanar with a top surface of the dielectric layer; (e) forming a first capping layer on the top surface of the wire and the top surface of the dielectric layer; (f) after step (e) performing one or more characterization procedures in relation to said integrated circuit; and (g) after step (e) forming a second capping layer on a top surface of the first capping layer. | 03-04-2010 |
20100059889 | ADHESION OF DIFFUSION BARRIER ON COPPER-CONTAINING INTERCONNECT ELEMENT - The present invention relates to a method for fabricating a semiconductor device. For improving the adhesion between a copper-containing interconnect element and a diffusion barrier on top of it, a first dielectric layer ( | 03-11-2010 |
20100059890 | METAL LINE OF SEMICONDUCTOR DEVICE HAVING A DIFFUSION BARRIER INCLUDING CRxBy AND METHOD FOR FORMING THE SAME - A metal line of a semiconductor device having a diffusion barrier including Cr | 03-11-2010 |
20100065967 | Copper interconnection, method for forming copper interconnection structure, and semiconductor device - A copper interconnection structure includes an insulating layer, an interconnection body including copper and a barrier layer surrounding the interconnection body. The barrier layer includes a first barrier layer formed between a first portion of the interconnection body and the insulating layer. The first portion of the interconnection body is part of the interconnection body that faces the insulating layer. The barrier layer also includes a second barrier layer formed on a second portion of the interconnection body. The second portion of the interconnection body is part of the interconnection body not facing the insulating layer. Each of the first and the second barrier layers is formed of an oxide layer including manganese, and each of the first and the second barrier layers has a position where the atomic concentration of manganese is maximized in their thickness direction of the first and the second barrier layers. | 03-18-2010 |
20100072621 | ELECTRONIC COMPONENT - An electronic component has a metallic layer on a substrate made of a semiconductor material, a diffusion barrier layer that is made of a material that has a small diffusion coefficient for the metal of the metallic layer being formed between the metallic layer and the substrate. | 03-25-2010 |
20100072622 | Method for forming Barrier Layer and the Related Damascene Structure - A method for forming barrier layers comprises steps of forming a first metal barrier layer covering a first dielectric layer and contacting a conductive layer through a via of the first dielectric layer, forming a barrier layer of metalized materials on the first metal layer, optionally forming a second metal barrier layer on the barrier layer of metalized materials, removing portions of the barrier layer of metalized materials above the via bottom in the first dielectric layer, and leaving the barrier layer of metalized materials remaining on the via sidewall in the first dielectric layer; and forming a second metal layer covering the barrier layer of metalized materials. The accomplished barrier layers will have lower resistivity on the via bottom in the first dielectric layer and they are capable of preventing copper atoms from diffusing into the dielectric layer. | 03-25-2010 |
20100078817 | Interconnect Structure - One or more embodiments relate to a semiconductor device, comprising: a Si-containing layer; a barrier layer disposed over the Si-containing layer, the barrier layer comprising a compound including a metallic element; a metallic nucleation_seed layer disposed over the barrier layer, the nucleation_seed layer including the metallic element; and a metallic interconnect layer disposed over the nucleation_seed layer, the interconnect layer comprising at least one element selected from the group consisting of Cu (copper), Au (gold), and Ag (silver). | 04-01-2010 |
20100078818 | DIFFUSION BARRIER AND ADHESION LAYER FOR AN INTERCONNECT STRUCTURE - An interconnect structure is provided. The interconnect structure includes an interconnect opening formed within a dielectric material, a diffusion barrier on the dielectric material, where the diffusion barrier contains a compound from a thermal reaction between cobalt (Co) metal from at least a portion of a cobalt metal layer formed on the dielectric material and a dielectric reactant element from the dielectric material. The interconnect structure further includes a cobalt nitride adhesion layer in the interconnect opening, and a Cu metal fill in the interconnect opening, wherein the diffusion barrier and the cobalt nitride adhesion layer surround the Cu metal fill within the interconnect opening. | 04-01-2010 |
20100078819 | INTER CONNECTION STRUCTURE INCLUDING COPPER PAD AND PAD BARRIER LAYER, SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS INCLUDING THE SAME - A semiconductor device including an interconnection structure including a copper pad, a pad barrier layer and a metal redistribution layer, an interconnection structure thereof and methods of fabricating the same are provided. The semiconductor device includes a copper pad disposed on a first layer, a pad barrier layer including titanium disposed on the copper pad, an inorganic insulating layer disposed on the pad barrier layer, a buffer layer disposed on the inorganic insulating layer, wherein the inorganic insulating layer and the buffer layer expose a portion of the pad barrier layer, a seed metal layer disposed on the exposed buffer layer, a metal redistribution layer disposed on the seed metal layer, and a first protective layer disposed on the metal redistribution layer. | 04-01-2010 |
20100078820 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A metal barrier film which contains an additive element is formed on the side face and on the bottom of a trench formed in an insulating film; a seed film is formed over the metal barrier film; a plated layer (Cu film) is formed using the seed film as a seed so as to fill up the trench with a metal film; the metal barrier film and the metal film are annealed to thereby form therebetween an alloy layer which contains a metal composing the metal barrier film, the additive element, and a metal composing the metal film, and to thereby allow the additive element to diffuse into the metal film. | 04-01-2010 |
20100090342 | Metal Line Formation Through Silicon/Germanium Soaking - A method for forming interconnect structure includes providing a substrate; forming a low-k dielectric layer over the substrate; forming an opening in the low-k dielectric layer; after the step of forming the opening, performing a silicon/germanium soaking process to exposed surfaces of the low-k dielectric layer; and after the silicon/germanium soaking process, filling the opening. | 04-15-2010 |
20100096755 | Wiring structure and method for fabricating the same - A wiring structure has a silicon layer, a backing layer provided on the silicon layer, the backing layer comprising a copper alloy containing a manganese, and a copper layer provided on the backing layer, and a diffusion barrier layer having an electrical conductivity, the diffusion barrier layer being provided at a region including an interface between the silicon layer and the backing layer, in which a manganese in the diffusion barrier layer is enriched compared with the backing layer. | 04-22-2010 |
20100102448 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to one embodiment includes: a semiconductor element formed on a semiconductor substrate; a metal wiring formed above the semiconductor element; an amorphous silicon film formed above the semiconductor element, the amorphous silicon film being insulated from the metal wiring; and a metal diffusion blocking film formed above the amorphous silicon film, the metal diffusion blocking film having a property to suppress diffusion of metal atoms in the metal wiring. | 04-29-2010 |
20100102449 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - In a semiconductor device including: an insulating film ( | 04-29-2010 |
20100117232 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The semiconductor device according to the present invention includes a first insulating layer made of a material containing Si and O, a groove shaped by digging down the first insulating layer, an embedded body, embedded in the groove, made of a metallic material mainly composed of Cu, a second insulating layer, stacked on the first insulating layer and the embedded body, made of a material containing Si and O, and a barrier film, formed between the embedded body and each of the first insulating layer and the second insulating layer, made of Mn | 05-13-2010 |
20100117233 | METAL LINE IN SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A method includes forming a buffer lower metal line over a semiconductor substrate for absorbing an external impact, forming a pre-metal-dielectric layer which covers the buffer lower metal line, the pre-metal-dielectric layer having a via hole formed therein to expose a portion of the buffer lower metal line, forming a seed layer over a surface of the pre-metal-dielectric layer having the via hole formed therein, forming polyimide which exposes the via hole and the seed layer formed over the pre-metal-dielectric layer in the vicinity of the via hole, growing an upper metal line over the exposed seed layer, subjecting the semiconductor substrate having the upper metal line formed thereon to a thermal process, removing the polyimide by dry etching, and bonding a bonding portion onto the upper metal line. | 05-13-2010 |
20100117234 | Semiconductor device and method of manufacturing the same - A method includes burying a conductive pattern in an insulating film made of SiOH, SiCOH or organic polymer, treating surfaces of the insulating film and the conductive pattern with plasma which includes a hydrocarbon gas as a treatment gas, and forming a diffusion barrier film, which is formed of an SiCH film, an SiCHN film, an SiCHO film or an SiCHON film, over the insulating film and the conductive pattern with performing a plasma CVD by adding an Si-containing gas to the treatment gas while increasing an addition amount gradually or in a step by step manner. | 05-13-2010 |
20100117235 | METAL LINE IN SEMICONDUCTOR DEVICE - A metal line in a semiconductor device includes an insulation layer having trenches formed therein, a barrier metal layer formed over the insulation layer and the trenches, a metal layer formed over the barrier metal layer, wherein the metal layer fills the trenches, and an anti-galvanic corrosion layer formed on an interface between the metal layer and the barrier metal layer. | 05-13-2010 |
20100123249 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes an insulating film, a trench which is formed in the insulating film, a barrier metal film which is formed on a sidewall and a bottom surface of the trench, and is composed of an alloy of titanium (Ti) and tantalum (Ta), and a copper (Cu) wiring which is stacked on the barrier metal film, and located in the trench. A titanium concentration of the barrier metal film is equal to or more than 0.1 at % and equal to or less than 14 at %. | 05-20-2010 |
20100127394 | THROUGH SUBSTRATE VIAS FOR BACK-SIDE INTERCONNECTIONS ON VERY THIN SEMICONDUCTOR WAFERS - Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming ( | 05-27-2010 |
20100133690 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first interconnect | 06-03-2010 |
20100133691 | THERMALLY PROGRAMMABLE ANTI-REVERSE ENGINEERING INTERCONNECTS AND METHODS OF FABRICATING SAME - An interconnect and method of making the interconnect. The method includes forming a dielectric layer on a substrate, the dielectric layer having a top surface and a bottom surface; forming a first wire and a second wire in the dielectric layer, the first wire separated from the second wire by a region of the dielectric layer; and forming metallic nanoparticles in or on the top surface of the dielectric layer between the first and second wires, the metallic nanoparticles capable of electrically connecting the first wire and the second wire only while the nanoparticles are heated to a temperature greater than room temperature and a voltage is applied between the first and second wires. | 06-03-2010 |
20100133692 | PROCESS FOR PRODUCING SILICIC COATING, SILICIC COATING AND SEMICONDUCTOR DEVICE - A silicic coating of 2.4 g/cm | 06-03-2010 |
20100148366 | GRAIN GROWTH PROMOTION LAYER FOR SEMICONDUCTOR INTERCONNECT STRUCTURES - An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the electromigration problem that is exhibited by prior art interconnect structures, are provided. In accordance with the present invention, a grain growth promotion layer, which promotes the formation of a conductive region within the interconnect structure that has a bamboo microstructure and an average grain size of larger than 0.05 microns is utilized. The inventive structure has improved performance and reliability. | 06-17-2010 |
20100148367 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a die pad having a surface on which a first solder bonding layer is formed, and made of metal; and a semiconductor element fixed on the first solder bonding layer on the die pad by a solder material made mostly of bismuth. The first solder bonding layer is made of a softer material than the solder material, a recess is formed in a part of the first solder bonding layer by pressing the solder material against the first solder bonding layer, and the solder material partially fills the recess. | 06-17-2010 |
20100155949 | LOW COST PROCESS FLOW FOR FABRICATION OF METAL CAPPING LAYER OVER COPPER INTERCONNECTS - Semiconductor devices and methods are disclosed for improving electrical connections to integrated circuits. A process flow and device with a dual/single damascene interconnect structure overlying an existing interconnect structure in a semiconductor wafer is provided. A capping layer is formed thereon that comprises nickel/palladium layers within a bond pad opening. The layers are polished using a chemical mechanical polishing (CMP) technique so that the capping layers are within the opening. | 06-24-2010 |
20100155950 | IMPLEMENTATION OF A METAL BARRIER IN AN INTEGRATED ELECTRONIC CIRCUIT - A metal barrier is realized on top of a metal portion of a semiconductor product, by forming a metal layer on the surface of the metal portion, with this metal layer comprising a cobalt-based metal material. Then, after an optional deoxidation step, a silicidation step and a nitridation step of the cobalt-based metal material of the metal layer are performed. The antidiffusion properties of copper atoms (for example) and the antioxidation properties of the metal barrier are improved. | 06-24-2010 |
20100155951 | Copper interconnection structure and method for forming copper interconnections - A copper interconnection structure includes an insulating layer, an interconnection body including copper in an opening provided on the insulating layer, and a diffusion barrier layer formed between the insulating layer and the interconnection body. The diffusion barrier layer includes an oxide layer including manganese having a compositional ratio of oxygen to manganese (y/x) less than 2. | 06-24-2010 |
20100155952 | Copper interconnection structures and semiconductor devices - A copper interconnection structure includes an insulating layer, an interconnection body including copper in an opening provided on the insulating layer and a barrier layer including a metal element and copper, formed between the insulating layer and the interconnection body. An atomic concentration of the metal element in the barrier layer is accumulated toward an outer surface of the barrier layer facing the insulating layer, and an atomic concentration of copper in the barrier layer is accumulated toward an inner surface of the barrier layer facing the interconnection body. The inner surface of the barrier layer comprises copper surface orientation of {111} and {200}, and an intensity of X-ray diffraction peak from the inner surface of the barrier layer is stronger for the {111} peak than for the {200} peak. | 06-24-2010 |
20100155953 | Conductive oxide electrodes - Conductive oxide electrodes are described, including a bi-layer barrier structure electrically coupled with an adhesion layer, and an electrode layer, wherein the bi-layer barrier structure includes a first barrier layer electrically coupled with the adhesion layer, and a second barrier layer electrically coupled with the first barrier layer and to the electrode layer. The conductive oxide electrodes and their associated layers can be fabricated BEOL above a substrate that includes active circuitry fabricated FEOL and electrically coupled with the conductive oxide electrodes through an interconnect structure that can also be fabricated FEOL. The conductive oxide electrodes can be used to electrically couple a plurality of non-volatile re-writeable memory cells with conductive array lines in a two-terminal cross-point memory array fabricated BEOL over the substrate and its active circuitry, the active circuitry configured to perform data operations on the memory array. | 06-24-2010 |
20100164104 | Structures and Methods for Improving Solder Bump Connections in Semiconductor Devices - Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The method includes forming an upper wiring layer in a dielectric layer and depositing one or more dielectric layers on the upper wiring layer. The method further includes forming a plurality of discrete trenches in the one or more dielectric layers extending to the upper wiring layer. The method further includes depositing a ball limiting metallurgy or under bump metallurgy in the plurality of discrete trenches to form discrete metal islands in contact with the upper wring layer. A solder bump is formed in electrical connection to the plurality of the discrete metal islands. | 07-01-2010 |
20100164105 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An object is to prevent a failure, such as a wiring separation or a crack, in an insulating film under a copper wire, in a semiconductor device formed by wire-bonding the copper wire on a portion above the copper wiring. A semiconductor device according to the present invention includes a copper wiring formed above a semiconductor substrate, a plated layer formed so as to cover a top surface and side surfaces of the copper wiring, and a copper wire which is wire-bonded on the plated layer above the copper wiring. | 07-01-2010 |
20100164106 | CMP Slurry Composition for Barrier Polishing for Manufacturing Copper Interconnects, Polishing Method Using the Composition, and Semiconductor Device Manufactured by the Method - Provided is a CMP slurry composition for barrier polishing for manufacturing copper interconnects, the composition including abrasive particles, a copper surface protective agent, a copper corrosion inhibitor, an oxidizing agent, and a pH adjustor, wherein the abrasive particles are non-spherical colloidal silica having a ratio of an average primary particle size to an average secondary particle size of about 0.6 or less and the copper surface protective agent is a carboxyl-functionalized water-soluble polymer. | 07-01-2010 |
20100164107 | SEMICONDUCTOR DEVICE HAVING MULTILAYERED INTERCONNECTION STRUCTURE FORMED BY USING Cu DAMASCENE METHOD, AND METHOD OF FABRICATING THE SAME - Disclosed are a semiconductor device having a multilayered interconnection structure formed by using a Cu damascene method, and a method of fabricating the same. A Cu interconnection is buried on a first barrier metal layer in a trench formed in the surface of an insulating film. An interlayer dielectric film is formed on the insulating film, first barrier metal layer, and Cu interconnection, and a hole is formed in a position corresponding to the Cu interconnection. An Al-based interconnection is electrically connected to the Cu interconnection in the hole of the interlayer dielectric film. A stacked film is interposed at least between the Cu interconnection and Al-based interconnection. This stacked film includes a second barrier metal layer for preventing the reaction between Cu and Al, and a third barrier metal layer for increasing the fluidity of Al with respect to the second barrier metal layer. | 07-01-2010 |
20100164108 | INTEGRATING A BOTTOMLESS VIA TO PROMOTE ADSORPTION OF ANTISUPPRESSOR ON EXPOSED COPPER SURFACE AND ENHANCE ELECTROPLATING SUPERFILL ON NOBLE METALS - A method for forming a copper interconnect is described. An opening in a dielectric layer disposed on a substrate is formed. A barrier layer is formed on the opening. A seed layer is formed on the barrier layer. The seed layer includes a noble metal copper alloy, the copper having less than 50% of the atomic weight of the noble metal copper alloy. | 07-01-2010 |
20100171219 | EXTENDED LINER FOR LOCALIZED THICK COPPER INTERCONNECT - A dielectric layer overlies a semiconductor substrate. The substrate has components and appropriate contacts formed therein. The dielectric layer electrically insulates the substrate and components from overlying conductive interconnect layers. A barrier layer is arranged over the dielectric layer to isolate the interconnect layers from other structures. A copper layer is then deposited over the barrier layer and thick interconnect lines having a first width and a first height are realized. Then, the barrier layer is etched using one of many alternative techniques. The barrier layer has a second width and a second height wherein the second width of the barrier liner is selected to be greater than the first width of the thick copper interconnect. | 07-08-2010 |
20100171220 | Reducing Resistivity in Interconnect Structures of Integrated Circuits - An integrated circuit structure having improved resistivity and a method for forming the same are provided. The integrated circuit structure includes a dielectric layer, an opening in the dielectric layer, an oxide-based barrier layer directly on sidewalls of the opening, and conductive materials filling the remaining portion of the opening. | 07-08-2010 |
20100176511 | SEMICONDUCTOR DEVICE WITH A LINE AND METHOD OF FABRICATION THEREOF - A semiconductor device includes an interlayer insulation film, an underlying line provided in the interlayer insulation film, a liner film overlying the interlayer insulation film, an interlayer insulation film overlying the liner film. The underlying line has a lower hole and the liner film and the interlayer insulation film have an upper hole communicating with the lower hole, and the lower hole is larger in diameter than the upper hole. The semiconductor device further includes a conductive film provided at an internal wall surface of the lower hole, a barrier metal provided along an internal wall surface of the upper hole, and a Cu film filling the upper and lower holes. The conductive film contains a substance identical to a substance of the barrier metal. A highly reliable semiconductor device can thus be obtained. | 07-15-2010 |
20100181670 | CONTACT STRUCTURE FOR A SEMICONDUCTOR AND METHOD FOR PRODUCING THE SAME - A semiconductor component comprising a substrate with a first side and a second side a multi-layer contact structure arranged on at least one side of the substrate, the contact structure exhibiting a barrier layer to prevent the diffusion of ions from the side of barrier layer opposite to the substrate into the substrate. | 07-22-2010 |
20100181671 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device can include an insulation layer on that is on a substrate on which a plurality of lower conductive structures are formed, where the insulation layer has an opening. A barrier layer is on a sidewall and a bottom of the opening of the insulation layer, where the barrier layer includes a first barrier layer in which a constituent of a first deoxidizing material is richer than a metal material in the first barrier layer and a second barrier layer in which a metal material in the second barrier layer is richer than a constituent of a second deoxidizing material. An interconnection is in the opening of which the sidewall and the bottom are covered with the barrier layer, the interconnection is electrically connected to the lower conductive structure. | 07-22-2010 |
20100187693 | DIFFUSION BARRIER LAYERS - Provided are methods and apparatuses for depositing barrier layers for blocking diffusion of conductive materials from conductive lines into dielectric materials in integrated circuits. The barrier layer may contain copper. In some embodiments, the layers have conductivity sufficient for direct electroplating of conductive materials without needing intermediate seed layers. Such barrier layers may be used with circuits lines that are less than 65 nm wide and, in certain embodiments, less than 40 nm wide. The barrier layer may be passivated to form easily removable layers including sulfides, selenides, and/or tellurides of the materials in the layer. | 07-29-2010 |
20100187694 | Through-Silicon Via Sidewall Isolation Structure - A system and method for an improved through-silicon via isolation structure is provided. An embodiment comprises a semiconductor device having a substrate with electrical circuitry formed thereon. One or more dielectric layers are formed over the substrate, and an opening is etched into the structure extending from a surface of the one or more dielectric layers through the one or more dielectric layers into the substrate; the opening having sidewalls. A low-K dielectric layer is formed over the sidewalls of the opening. The opening is filled with a conductive material and/or a barrier layer creating a through-silicon via that is isolated from the surrounding substrate by the low-K dielectric layer. | 07-29-2010 |
20100187695 | OUT-OF-PLANE SPRING STRUCTURES ON A SUBSTRATE - A structure has at least one structure component formed of a first material residing on a substrate, such that the structure is out of a plane of the substrate. A first coating of a second material then coats the structure. A second coating of a non-oxidizing material coats the structure at a thickness less than a thickness of the second material. | 07-29-2010 |
20100193953 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A trench is formed in an insulation film formed on top of a semiconductor substrate, and a barrier metal film is formed on the surface of the trench. After a copper or copper alloy film is formed on the barrier metal film, an oxygen absorption film in which a standard energy of formation of an oxidation reaction in a range from room temperature to 400° C. is negative, and in which an absolute value of the standard energy of formation is larger than that of the barrier metal film is formed, and the assembly is heated in a temperature range of 200 to 400° C. A semiconductor device can thereby be provided that has highly reliable wiring, in which the adhesion to the barrier metal film in the copper interface is enhanced, copper diffusion in the interface is suppressed, and electromigration and stress migration are prevented. | 08-05-2010 |
20100193954 | Barrier Structures and Methods for Through Substrate Vias - Through substrate via barrier structures and methods are disclosed. In one embodiment, a semiconductor device includes a first substrate including an active device region disposed within isolation regions. A through substrate via is disposed adjacent to the active device region and within the first substrate. A buffer layer is disposed around at least a portion of the through substrate via, wherein the buffer layer is disposed between the isolation regions and the through substrate via. | 08-05-2010 |
20100193955 | PLASMA-ENHANCED ATOMIC LAYER DEPOSITION OF CONDUCTIVE MATERIAL OVER DIELECTRIC LAYERS - Methods of forming a conductive metal layer over a dielectric layer using plasma enhanced atomic layer deposition (PEALD) are provided, along with related compositions and structures. A plasma barrier layer is deposited over the dielectric layer by a non-plasma atomic layer deposition (ALD) process prior to depositing the conductive layer by PEALD. The plasma barrier layer reduces or prevents deleterious effects of the plasma reactant in the PEALD process on the dielectric layer and can enhance adhesion. The same metal reactant can be used in both the non-plasma ALD process and the PEALD process. | 08-05-2010 |
20100193956 | MULTI-LAYER METAL WIRING OF SEMICONDUCTOR DEVICE PREVENTING MUTUAL METAL DIFFUSION BETWEEN METAL WIRINGS AND METHOD FOR FORMING THE SAME - A multi-layer metal wiring of a semiconductor device and a method for forming the same are disclosed. The multi-layer metal wiring of the semiconductor device includes a lower Cu wiring, and an upper Al wiring formed to be contacted with the lower Cu wiring, and a diffusion barrier layer interposed between the lower Cu wiring and the upper Al wiring. The diffusion barrier layer is formed of a W-based layer. | 08-05-2010 |
20100193957 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - Provided, is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semiconductor substrate that the neighboring film is contacted with the conductor film. In the device, the materials for the conductor film and the neighboring film are so selected that the difference between the short side, a | 08-05-2010 |
20100200991 | Dopant Enhanced Interconnect - Techniques are disclosed that enable an interconnect structure that is resistance to electromigration. A liner is deployed underneath a seed layer of the structure. The liner can be a thin continuous and conformal layer, and may also limit oxidation of an underlying barrier (or other underlying surface). A dopant that is compatible (non-alloying, non-reactive) with the liner is provided to alloy the seed layer, and allows for dopant segregation at the interface at the top of the seed layer. Thus, electromigration performance is improved. | 08-12-2010 |
20100207274 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - A semiconductor device comprising a wiring suitable for miniaturization and manufacturing method thereof are disclosed. According to one aspect of the present invention, it is provided a semiconductor device comprising an insulator formed above a semiconductor substrate, and a wiring formed in the insulator and having surface roughness capable of suppressing surface scattering of electrons and reduction in electrical conductivity thereof. | 08-19-2010 |
20100219529 | METHOD AND APPARATUS FOR FORMING METAL-METAL OXIDE ETCH STOP/BARRIER FOR INTEGRATED CIRCUIT INTERCONNECTS - Described is a method and apparatus for forming interconnects with a metal-metal oxide electromigration barrier and etch-stop. In one embodiment of the invention, the method includes depositing a metal layer on the top of a planarized interconnect layer, the interconnect layer having an interlayer dielectric (ILD) with a top that is planar with the top of an electrically conductive interconnect. In one embodiment of the invention, the method includes reacting the metal layer with the ILD to form a metal oxide layer on the top of the ILD. At the same time, the metal layer will not be significantly oxidized by the electrically conductive interconnect, thus forming a metal barrier on the electrically conductive interconnect to improve electromigration performance. The metal barrier and metal oxide layer together comprise a protective layer. A second ILD may be subsequently formed on the protective layer, and the protective layer may act an etch-stop during a subsequent etch of the second ILD. | 09-02-2010 |
20100219530 | Contact Structure of a Semiconductor Device - A method for fabricating a contact of a semiconductor device includes the steps of forming a dielectric layer having a contact hole on a semiconductor substrate, forming an out-gassing barrier layer comprising a poly-silicon layer to cover at least inner walls of the contact hole in order to prevent undesired out-gassing from the dielectric layer, and depositing an aluminum layer on the out-gassing barrier layer. The contact structure of the semiconductor device includes the aluminum layer filled in the contact layer formed on the semiconductor substrate, and the out-gassing barrier layer formed under the aluminum layer to prevent out-gassing from the dielectric layer. A fine contact can be formed along with the aluminum layer, thereby realizing the contact structure of a lower contact resistance. As a result, it is possible to realize stabilization of an overall contact resistance of the semiconductor device. | 09-02-2010 |
20100224995 | SEMICONDUCTOR DEVICE HAVING SILICON-DIFFUSED METAL WIRING LAYER AND ITS MANUFACTURING METHOD - In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer. | 09-09-2010 |
20100224996 | METHODS OF MANUFACTURING COPPER INTERCONNECT SYSTEMS - An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including copper within the at least one trench. A cap layer including metal may be provided on the first conductive region. A second dielectric layer may be over the first conductive region and the cap layer. A dielectric etch stop and diffusion barrier layer may be over the second dielectric layer, and a via may be over the first conductive region and through the second dielectric layer and the cap layer. A diffusion barrier layer may be on sidewalls of the via, and an alloy seed layer including copper and at least one of tantalum, molybdenum, chromium, and tungsten may be over the diffusion barrier. The allow seed layer may also be over the dielectric etch stop and diffusion barrier layer, and the alloy seed layer may be in contact with the first conductive region. | 09-09-2010 |
20100230815 | SEMICONDUCTOR DEVICE - Semiconductor devices and methods for fabricating the same. An exemplary device includes a substrate, a dielectric layer, a protection layer, and a conformal barrier layer. The dielectric layer overlies the substrate and comprises an opening. The opening comprises a lower portion and a wider upper portion, exposing parts of the substrate. The bottoms of the upper portion act as shoulders of the opening. The protection layer overlies at least one shoulder of the opening. The conformal barrier layer is disposed in the opening and overlies the protection layer and the dielectric layer, wherein etching resistance of the protection layer against inert-gas plasma is higher than that of the barrier layer. | 09-16-2010 |
20100230816 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - Semiconductor devices and methods for forming the same in which damages to a low-k dielectric layer therein can be reduced or even prevented are provided. A semiconductor device is provided, comprising a substrate. A dielectric layer with at least one conductive feature therein overlies the substrate. An insulating cap layer overlies the top surface of the low-k dielectric layer adjacent to the conductive feature, wherein the insulating cap layer comprises metal ions. | 09-16-2010 |
20100230817 | Using Unstable Nitrides to Form Semiconductor Structures - Incompatible materials, such as copper and nitrided barrier layers, may be adhered more effectively to one another. In one embodiment, a precursor of copper is deposited on the nitrided barrier. The precursor is then converted, through the application of energy, to copper which could not have been as effectively adhered to the barrier in the first place. | 09-16-2010 |
20100230818 | Through Substrate Via Semiconductor Components - A structure and method of forming through substrate vias in forming semiconductor components are described. In one embodiment, the invention describes a method of forming a through substrate via by partially filling an opening with a fill material, and forming a first insulating layer over the first fill material thereby forming a gap over the opening. The method further includes forming a second insulating layer to close the gap thereby forming an enclosed cavity within the opening. | 09-16-2010 |
20100237502 | Barrier for Through-Silicon Via - A system and a method for protecting through-silicon vias (TSVs) is disclosed. An embodiment comprises forming an opening in a substrate. A liner is formed in the opening and a barrier layer comprising carbon or fluorine is formed along the sidewalls and bottom of the opening. A seed layer is formed over the barrier layer, and the TSV opening is filled with a conductive filler. Another embodiment includes a barrier layer formed using atomic layer deposition. | 09-23-2010 |
20100244252 | Self Forming Metal Fluoride Barriers for Fluorinated Low-K Dielectrics - A device and method of forming fluoride metal barriers at an interface of a fluorinated low-K dielectric and Cu or Cu alloy interconnects is disclosed. The fluoride metal barriers may prevent interconnects from reacting with the fluorinated low-K dielectric. The method may include depositing a thin film of metal or metal alloy on the fluorinated low-K dielectric. The thin film may include a metal or metal alloying element that reacts with free fluorine and/or fluorine compounds from the fluorinated low-K dielectric to form fluoride metal barriers. | 09-30-2010 |
20100244253 | COPPER LINE HAVING SELF-ASSEMBLED MONOLAYER FOR ULSI SEMICONDUCTOR DEVICES, AND A METHOD OF FORMING SAME - A copper line having self assembled monolayer for use in ULSI semiconductor devices and methods of making the same are presented. The copper line includes an interlayer dielectric, a self-assembled monolayer, catalytic particles on the monolayer, and a copper layer on the monolayer with the catalytic particles. The method includes the steps of forming an interlayer dielectric on a semiconductor substrate having a metal line forming region; forming a self-assembled monolayer on the metal line forming region; adsorbing catalytic particles on the self-assembled monolayer; forming using an electroless process a copper seed layer on the self-assembled monolayer having the catalytic particles adsorbed thereto; and forming a copper layer on the copper seed layer to fill in the metal line forming region. | 09-30-2010 |
20100244254 | Semiconductor device - A semiconductor device is disclosed, which includes a first interlayer insulating film, a lower-layer interconnection in a first groove in the first film, a second interlayer insulating film over the first film, having a normal via hole opening to the lower-layer interconnection, a normal plug in the normal hole, a third interlayer insulating film over the second film, having a second groove opening to the normal plug, an upper-layer interconnection in the second groove, and a first dummy plug in a first dummy via hole in the second film, the first dummy via hole opening to one of the lower-layer and upper-layer interconnections, wherein a short side of the first dummy plug is larger than a minimum width of a minimum width interconnection and smaller than a minimum diameter of a minimum diameter via hole and a long side is larger than a shortest length of a shortest length interconnection. | 09-30-2010 |
20100244255 | Wiring structures - A wiring structure includes a conductive pattern on a substrate, a first insulation layer pattern between adjacent conductive patterns and a second insulation layer pattern on the first insulation layer pattern. The first insulation layer pattern is separated from the conductive pattern by a first distance to provide a first air gap. The second insulation layer pattern is spaced apart from the conductive pattern by a second distance substantially smaller than the first distance to provide a second air gap. The wiring structure may have a reduced parasitic capacitance while simplifying processes for forming the wiring structure. | 09-30-2010 |
20100244256 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes an interlayer insulating film formed above a semiconductor substrate. The interlayer insulating film has a concave portion. A barrier metal layer is formed along a bottom and a sidewall of the concave portion. The barrier metal layer has a first portion provided along the sidewall of the concave portion and a second portion provided along the bottom of the concave portion. A metal wiring layer is formed in the concave portion via the barrier metal layer. The first portion of the barrier metal layer is composed of a titanium nitride layer whose titanium content is more than 50 at %, and the second portion of the barrier metal layer is composed of a titanium nitride layer whose titanium content is relatively larger than the titanium content of the first portion or of a Ti layer. | 09-30-2010 |
20100244257 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a plurality of mask patterns by anisotropically etching a mask-forming film until upper surfaces of core patterns are exposed. A facing pair includes a pair of the mask patterns facing the core pattern located between the paired mask patterns. The mask patterns of the facing pair have respective lower portions spaced from each other by a first distance. An adjacent pair includes a pair of mask patterns adjacent to each other with a space having no core pattern. The mask patterns of the adjacent pair have respective lower portions spaced from each other by a second distance. The mask patterns are formed so that the second distance is larger than the first distance. | 09-30-2010 |
20100244258 | SUBSTRATE AND MANUFACTURING METHOD THEREFOR - It is an object of the present invention to provide a substrate having a barrier film for preventing copper diffusion having both a barrier function and a catalytic function, wherein the barrier properties during high-temperature heating is excellent. | 09-30-2010 |
20100244259 | SUBSTRATE AND MANUFACTURING METHOD THEREFOR - It is an object of the present invention to provide a substrate having a barrier film for preventing copper diffusion having both a barrier function and a catalytic function, wherein the barrier properties during high-temperature heating is excellent. | 09-30-2010 |
20100244260 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a first insulting film formed on a semiconductor substrate; a contact including a conductive film buried in the first insulating film to reach the semiconductor substrate; and a first barrier layer including a high melting point metal, formed between the semiconductor substrate and the conductive film and between the first insulating film and the conductive film. The device also includes a second barrier layer lower in moisture permeability than the first barrier layer, formed between the first barrier layer and the conductive film. | 09-30-2010 |
20100244261 | THROUGH-HOLE CONTACTS IN A SEMICONDUCTOR DEVICE - Devices with conductive through-waver vias. In one embodiment, the device is formed by a method comprising providing a layer of semiconducting material, forming a layer of metal on a first side of the layer of semiconducting material, forming an opening in the layer of semiconducting material to thereby expose a portion of the layer of metal, the opening extending from at least a second side of the layer of semiconducting material to the layer of metal, and performing a deposition process to form a conductive contact in the opening using the exposed portion of the metal layer as a seed layer. | 09-30-2010 |
20100252928 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first conductor formed over a semiconductor device; an insulation film formed over the semiconductor substrate and the first conductor and having an opening arriving at the first conductor; a first film formed in the opening and formed of a compound containing Zr; a second film formed over the first film in the opening and formed of an oxide containing Mn; and a second conductor buried in the opening and containing Cu. | 10-07-2010 |
20100252929 | GROUP II ELEMENT ALLOYS FOR PROTECTING METAL INTERCONNECTS - A plurality of metal interconnects incorporating a Group II element alloy for protecting the metal interconnects and methods to form and incorporate the Group II element alloy are described. In one embodiment, a Group II element alloy is used as a seed layer, or a portion thereof, which decreases the line resistance and increases the mechanical strength of a metal interconnect. In another embodiment, a Group II element alloy is used to form a barrier layer, which, in addition to decreasing the line resistance and increasing the mechanical integrity, also increases the chemical integrity of a metal interconnect. | 10-07-2010 |
20100258941 | DAMASCENE INTERCONNECTION STRUCTURE AND DUAL DAMASCENE PROCESS THEREOF - A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF | 10-14-2010 |
20100264543 | INTERCONNECT STRUCTURE - An interconnect structure and methods for forming semiconductor interconnect structures are disclosed. In one embodiment, the interconnect structure includes: a substrate including a first liner layer and a first metal layer thereover; a dielectric barrier layer over the first metal layer and the substrate; an inter-level dielectric layer over the dielectric barrier layer; a via extending between the inter-level dielectric layer, the dielectric barrier layer, and the first metal layer, the via including a second liner layer and a second metal layer thereover; and a diffusion barrier layer located between the second liner layer and the first metal layer, wherein a portion of the diffusion barrier layer is located under the dielectric barrier layer. | 10-21-2010 |
20100276804 | SEMICONDUCTOR DEVICE INCLUDING RUTHENIUM ELECTRODE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate, an insulation pattern on the semiconductor substrate, and an etch stop layer on the insulating pattern, the insulation pattern and the etch stop layer defining a contact hole that exposes the substrate, a first plug filled in a portion of the contact hole, a diffusion barrier layer formed above the first plug and in a bottom portion and on sidewalls of a remaining portion of the contact hole, a second plug fainted on the diffusion barrier layer and filled in the contact hole, and a storage node coupled to and formed on the second plug. | 11-04-2010 |
20100283154 | SPUTTERING TARGET AND SEMICONDUCTOR DEVICE MANUFACTURED USING THE SAME - A sputtering target includes a tungsten (W)-nickel (Ni) alloy, wherein the nickel (Ni) is present in an amount of between about 0.01 weight % and about 1 weight %. | 11-11-2010 |
20100295181 | REDUNDANT METAL BARRIER STRUCTURE FOR INTERCONNECT APPLICATIONS - A redundant metal diffusion barrier is provided for an interconnect structure which improves the reliability and extendibility of the interconnect structure. The redundant metal diffusion barrier layer is located within an opening that is located within a dielectric material and it is between a diffusion barrier layer and a conductive material which are also present within the opening. The redundant diffusion barrier includes a single layered or multilayered structure comprising Ru and a Co-containing material including pure Co or a Co alloy including at least one of N, B and P. | 11-25-2010 |
20100295182 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided is a method for forming a Cu wiring that does not cause Cu elution during CMP when a Ru material is used as a barrier metal film for the Cu wiring. The method has a step (d) of removing a second barrier metal film (Ru film) formed on a first barrier metal film on an upper surface of an interlayer insulating film, and a step (e) of depositing a seed copper (Cu) film on the first and the second barrier metal films after the step (d). By removing the second barrier metal film on the upper surface before the seed copper film is formed, copper is prevented from eluding into a slurry due to a battery effect of the second barrier metal film and copper. | 11-25-2010 |
20100301480 | SEMICONDUCTOR DEVICE HAVING A CONDUCTIVE STRUCTURE - A semiconductor device includes an interlayer insulating layer disposed on a substrate, the interlayer insulating layer comprising an opening exposing the substrate, a barrier layer pattern disposed within the opening, and a conductive pattern disposed on the barrier layer pattern, the conductive pattern having an oxidized portion extending out of the opening and a non-oxidized portion within the opening, wherein a width of the conductive pattern is determined by a thickness of the barrier layer pattern. | 12-02-2010 |
20100301481 | JOINT STRUCTURE AND ELECTRONIC COMPONENT - A joint structure joins an electronic element | 12-02-2010 |
20100314764 | HYBRID METALLIC WIRE AND METHODS OF FABRICATING SAME - A structure and methods of fabricating the structure. The structure comprising: a trench in a dielectric layer; an electrically conductive liner, an electrically conductive core conductor and an electrically conductive fill material filling voids between said liner and said core conductor. | 12-16-2010 |
20100314765 | INTERCONNECTION STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR MAKING THE SAME - An interconnection structure includes a lower layer metal wire in a first inter-metal dielectric layer on a substrate; a second inter-metal dielectric layer on the first inter-metal dielectric layer and covering the lower layer metal wire; an upper layer metal wire on the second inter-metal dielectric layer; and a via interconnection structure in the second inter-metal dielectric layer for interconnecting the upper layer metal wire with the lower layer metal wire, wherein the via interconnection structure comprises a tungsten stud on the lower layer metal wire, and an aluminum plug stacked on the tungsten stud. | 12-16-2010 |
20100314766 | ULSI MICRO-INTERCONNECT MEMBER HAVING RUTHENIUM ELECTROPLATING LAYER ON BARRIER LAYER - An object of the present is to provide a ULSI micro-interconnect member having a seed layer which, particularly on the inner sidewalls of vias and trenches, is formed with a sufficient coverage and a film thickness uniform with that on surface portion, and which has a low level of impurities. Further objects of the invention are to provide a ULSI micro-interconnect member in which, by utilizing such a seed layer to subsequently effect copper electroplating, micro-interconnects have been formed without generating voids; a process for forming the same; and a semiconductor wafer in which such ULSI micro-interconnects have been formed. A ULSI micro-interconnect member having a substrate and a ULSI micro-interconnect formed on the substrate, wherein the ULSI micro-interconnect includes a barrier layer formed on the substrate and a ruthenium electroplating layer formed on the barrier layer; the ULSI micro-interconnect member further including a copper electroplating layer formed using the ruthenium electroplating layer as a seed layer; and a process for fabricating the ULSI micro-interconnect members. | 12-16-2010 |
20100320604 | APPLICATION OF MN FOR DAMAGE RESTORATION AFTER ETCHBACK - Back end of line interconnect structures and methods of making a back end of line interconnect structure are provided. The back end of line interconnect structure contains a first interconnect layer containing a first conductive feature and a first dielectric layer; a first cap layer over the first interconnect layer, and a second interconnect layer over the first cap layer. The second interconnect layer contains a second conductive feature, a second dielectric layer, and two or more barrier layers therebetween. The two or more barrier layers contain a first barrier layer over the second dielectric layer and a MnO | 12-23-2010 |
20100320605 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the semiconductor memory device. A contact plug is formed by wet etching. An aspect ratio of SAC is decreased and SAC fail is reduced so that a process margin is secured. The semiconductor device includes a semiconductor substrate comprising an active region and a device isolation layer defining the active region, a conductive pattern formed on the semiconductor substrate, and a nitride layer formed on the semiconductor substrate perpendicularly to the conductive pattern. | 12-23-2010 |
20100320606 | Method for Forming MEMS Devices Having Low Contact Resistance and Devices Obtained Thereof - The present disclosure proposes a method for manufacturing in a MEMS device a low-resistance contact between a silicon-germanium layer and a layer contacted by this silicon-germanium layer, such as a CMOS metal layer or another silicon-germanium layer, through an opening in a dielectric layer stack separating both layers. An interlayer is formed in this opening, thereby covering at least the sidewalls of the opening on the exposed surface of the another layer at the bottom of this opening. This interlayer may comprise a TiN layer in contact with the silicon-germanium layer. This interlayer can further comprise a Ti layer in between the TiN layer and the layer to be contacted. In another embodiment this interlayer comprises a TaN layer in contact with the silicon-germanium layer. This interlayer can then further comprise a Ta layer in between the TaN layer and the layer to be contacted. | 12-23-2010 |
20100320607 | INTERCONNECT STRUCTURES WITH A METAL NITRIDE DIFFUSION BARRIER CONTAINING RUTHENIUM - A method for forming an interconnect structure for copper metallization and an interconnect structure containing a metal nitride diffusion barrier are described. The method includes providing a substrate having a micro-feature opening formed within a dielectric material and forming a metal nitride diffusion barrier containing ruthenium, nitrogen, and a nitride-forming metal over the surfaces of the micro-feature. The nitride-forming metal is selected from Groups IVB, VB, VIB, and VIIB of the Periodic Table, and the metal nitride diffusion barrier is formed by exposing the substrate to a precursor of the nitride-forming metal, a nitrogen precursor, and a ruthenium precursor. | 12-23-2010 |
20100327445 | STRUCTURE OF POWER GRID FOR SEMICONDUCTOR DEVICES AND METHOD OF MAKING THE SAME - An embodiment of the invention provides a semiconductor structure, which may include a stud of a first conductive material formed inside a dielectric layer; a via of a second conductive material having a bottom and sidewalls with the bottom and the sidewalls being covered by a conductive liner, and the bottom being formed directly on top of the stud and being in contact with the via through the conductive liner; and one or more conductive paths of a third conductive material connecting to the via through the conductive liner at the sidewalls of said the. A method of making the semiconductor structure is also provided. | 12-30-2010 |
20100327446 | VIA GOUGED INTERCONNECT STRUCTURE AND METHOD OF FABRICATING SAME - An interconnect structure including a gouging feature at the bottom of a via opening and a method of forming the same are provided. The method of the present invention does not disrupt the coverage of the deposited trench diffusion barrier in a line opening that is located atop the via opening, and/or does not introduce damages caused by creating a gouging feature at the bottom of the via opening by sputtering into the interconnect dielectric material that includes the via and line openings. Such an interconnect structure is achieved by providing a gouging feature in the bottom of the via opening by first forming the line opening within the interconnect dielectric, followed by forming the via opening and then the gouging feature. | 12-30-2010 |
20100327447 | Method of manufacturing semiconductor device and semiconductor device - A method of manufacturing a semiconductor device includes forming a barrier metal film including a high melting point metal in a concave portion formed in an insulating film formed over a substrate; forming a seed alloy film including copper and an impurity metal different from the copper over the barrier metal film so as to fill a portion of the concave portion; forming a plated metal film containing copper as a major ingredient over the seed alloy film so as to fill the concave portion; first heat-treating the seed alloy film and the plated metal film at 200° C. or higher and for ten minutes or less; removing the plated metal film, the seed alloy film, and the barrier metal film which are exposed to the outside of the concave portion, after the first heat-treating; and second heat-treating the seed alloy film and the plated metal film. | 12-30-2010 |
20100327448 | Semiconductor with Bottom-Side Wrap-Around Flange Contact - A packaging technique for electronic devices includes wafer fabrication of flexible contacts on the bottom surface of the substrate underneath the active circuit. Inherently reliable contacts suitable for a variety of devices can be formed via a simple fabrication process with good wafer packing density. For one embodiment, a trench is formed from the back of the substrate, exposing an upper conductive layer on the top surface. A standoff is formed on the bottom surface of the substrate. A lower conductive layer is formed that runs from and electrically connects with the exposed portion of the upper conductive layer onto the substrate standoff. The standoff is removed, releasing the formed conductors, resulting in a flexible contact. | 12-30-2010 |
20100327449 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To provide a semiconductor device having a structure in which a barrier metal film containing nitrogen is formed in a connection surface between a copper alloy wiring and a via, in which the electric resistance between the copper alloy wiring and the via can be prevented from rising, and the electric resistance can be prevented from varying. A semiconductor device according to the present invention comprises a first copper alloy wiring, a via and a first barrier metal film. The first copper alloy wiring is formed in an interlayer insulation film and contains a predetermined additive element in a main component Cu. The via is formed in an interlayer insulation film and electrically connected to the upper surface of the first copper alloy wiring. The first barrier metal film is formed so as to be in contact with the first copper alloy wiring in the connection part between the first copper alloy wiring and the via and contains nitrogen. The predetermined additive element reacts with nitrogen to form a high-resistance part. In addition, the concentration of the predetermined additive element is not more than 0.04 wt %. | 12-30-2010 |
20110001242 | SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device capable of preventing occurrence of cracking and the like, taking a large area, where wiring and the like that function as elemental devices can be arranged, within a plurality of interlayer insulation films, and reducing production cost. The semiconductor device according to the present invention has a low dielectric constant film having a dielectric constant of not less than 2.7. In the low dielectric constant film and the like, materials (e.g., a first dummy pattern, a second dummy pattern) with a larger hardness than that of the low dielectric constant film are formed at a part under a pad part. | 01-06-2011 |
20110006426 | ELECTRONIC COMPONENT FORMED WITH BARRIER-SEED LAYER ON BASE MATERIAL - It is an object of the present invention to provide a technology for forming an ULSI fine copper wiring by a simpler method. An electronic component in which a thin alloy film of tungsten and a noble metal used as a barrier-seed layer for an ULSI fine copper wiring is formed on a base material, wherein the thin alloy film has a composition comprising tungsten at a ratio equal to or greater than 60 at. % and the noble metal at a ratio of equal to or greater than 5 at. % and equal to or less than 40 at. %. The noble metal is preferably one or more kinds of metals selected from the group consisting of platinum, gold, silver and palladium. | 01-13-2011 |
20110006427 | ELECTRONIC COMPONENT FORMED WITH BARRIER-SEED LAYER ON BASE MATERIAL - It is an object of the present invention to provide a technology for forming an ULSI fine copper wiring by a simpler method. An electronic component in which a thin alloy film of tungsten and a noble metal used as a barrier-seed layer for an ULSI fine copper wiring is formed on a base material, wherein the thin alloy film has a composition comprising tungsten at a ratio equal to or greater than 50 at. % and the noble metal at a ratio of equal to or greater than 5 at. % and equal to or less than 50 at. %. The noble metal is preferably one or more kinds of metals selected from the group consisting of ruthenium, rhodium, and iridium. | 01-13-2011 |
20110006428 | Liner Formation in 3DIC Structures - An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening. The bottom portion of the TSV liner has a bottom height greater than a middle thickness of the sidewall portion of the TSV liner. | 01-13-2011 |
20110006429 | BARRIER LAYERS FOR COPPER INTERCONNECT - A copper interconnect includes a copper layer formed in a dielectric layer, having a first portion and a second portion. A first barrier layer is formed between the first portion of the copper layer and the dielectric layer. A second barrier layer is formed at the boundary between the second portion of the copper layer and the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer. | 01-13-2011 |
20110006430 | COPPER DIFFUSION BARRIER - The invention concerns a method of forming a copper portion surrounded by an insulating material in an integrated circuit structure, the insulating material being a first oxide, the method having steps including forming a composite material over a region of the insulating material where the copper portion is to be formed, the composite material having first and second materials, annealing such that the second material reacts with the insulating material to form a second oxide that provides a diffusion barrier to copper; and depositing a copper layer over the composite material by electrochemical deposition to form the copper portion. | 01-13-2011 |
20110024907 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To provide a technique capable of improving the reliability on electric properties of a semiconductor device by devising the shape of the upper surface of a plug. A plug of the present invention has an upwardly convex dome-like shape in which the upper surface thereof projects from the surface (upper surface) of a contact interlayer insulating film. That is, the plug has the upper surface of an upwardly convex dome-like shape, wherein the height of the top edge portion of a barrier conductive film is larger than that of the upper surface of the contact interlayer insulating film, and the height of the top edge portion of a tungsten film is larger than that of the top edge portion of the barrier conductive film. | 02-03-2011 |
20110024908 | LOW RESISTANCE HIGH RELIABILITY CONTACT VIA AND METAL LINE STRUCTURE FOR SEMICONDUCTOR DEVICE - The structures and methods described above provide mechanisms to improve interconnect reliability and resistivity. The interconnect reliability and resistivity are improved by using a composite barrier layer, which provides good step coverage, good copper diffusion barrier, and good adhesion with adjacent layers. The composite barrier layer includes an ALD barrier layer to provide good step coverage. The composite barrier layer also includes a barrier-adhesion-enhancing film, which contains at least an element or compound that contains Mn, Cr, V, Ti, or Nb to improve adhesion. The composite barrier layer may also include a Ta or Ti layer between the ALD barrier layer and the barrier-adhesion-enhancing layer. | 02-03-2011 |
20110024909 | BILAYER METAL CAPPING LAYER FOR INTERCONNECT APPLICATIONS - The invention provides semiconductor interconnect structures that have improved reliability and technology extendibility. In the present invention, a second metallic capping layer is located on a surface of a first metallic cap layer which is, in turn, located on a surface of the conductive feature embedded within a first dielectric material. Both the first and second metallic capping layers are located beneath an opening, e.g., a via opening, the is present within an overlying second dielectric material. The second metallic capping layer protects the first dielectric capping layer from being removed (either completely or partially) during subsequent processing steps. Interconnect structures including via gouging features as well as non-via gouging features are disclosed. The present invention provides methods of fabricating such semiconductor interconnect structures. | 02-03-2011 |
20110031623 | INTERCONNECT STRUCTURE AND METHOD FOR Cu/ULTRA LOW k INTEGRATION - A semiconductor structure is provided that includes a lower interconnect level including a first dielectric material having at least one conductive feature embedded therein; a dielectric capping layer located on the first dielectric material and some, but not all, portions of the at least one conductive feature; and an upper interconnect level including a second dielectric material having at least one conductively filled via and an overlying conductively filled line disposed therein, wherein the conductively filled via is in contact with an exposed surface of the at least one conductive feature of the first interconnect level by an anchoring area. Moreover, the conductively filled via and conductively filled line of the inventive structure are separated from the second dielectric material by a single continuous diffusion barrier layer. As such, the second dielectric material includes no damaged regions in areas adjacent to the conductively filled line. A method of forming such an interconnect structure is also provided. | 02-10-2011 |
20110049716 | STRUCTURES OF AND METHODS AND TOOLS FOR FORMING IN-SITU METALLIC/DIELECTRIC CAPS FOR INTERCONNECTS - A structure, tool and method for forming in-situ metallic/dielectric caps for interconnects. The method includes forming wire embedded in a dielectric layer on a semiconductor substrate, the wire comprising a copper core and an electrically conductive liner on sidewalls and a bottom of the copper core, a top surface of the wire coplanar with a top surface of the dielectric layer; forming a metal cap on an entire top surface of the copper core; without exposing the substrate to oxygen, forming a dielectric cap over the metal cap, any exposed portions of the liner, and the dielectric layer; and wherein the dielectric cap is an oxygen diffusion barrier and contains no oxygen atoms. | 03-03-2011 |
20110049717 | INTEGRATED CIRCUITS HAVING TSVS INCLUDING METAL GETTERING DIELECTRIC LINERS - An IC includes a substrate having a semiconductor top surface and a bottom surface, wherein the semiconductor top surface includes one or more active circuit components and a plurality of through silicon vias (TSVs) extending through the substrate. The plurality of TSVs include an outer dielectric liner. The dielectric liner includes at least one halogen or a Group 15 element metal gettering agent in an average concentration from 1 to 10 atomic %. A metal diffusion barrier layer is on the dielectric liner and a metal filler is on the metal barrier layer. The metal gettering agent getters metal filler that escapes the metal barrier layer. | 03-03-2011 |
20110049718 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, ELECTRONIC INSTRUMENT, SEMICONDUCTOR MANUFACTURING APPARATUS, AND STORAGE MEDIUM - When a barrier film is formed on an exposed surface of an interlayer insulation film on a substrate, the interlayer insulation film having a recess formed therein, and a metal wiring to be electrically connected to a metal wiring in a lower layer is formed in the recess, a barrier film having an excellent step coverage can be formed and increase of a wiring resistance can be restrained. An oxide film on a surface of the lower copper wiring exposed to a bottom surface of the interlayer insulation film is reduced or edged so as to remove oxygen on the surface of the copper wiring. Then, by supplying an organic metal compound containing manganese and containing no oxygen, generation of manganese oxide as a self-forming barrier film is selectively allowed on an area containing oxygen, such as a sidewall of the recess and a surface of the interlayer insulation film, while generation of the manganese oxide is not allowed on the surface of the copper wiring. Thereafter, copper is embedded in the recess. | 03-03-2011 |
20110057316 | COPPER WIRING LINE OF SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A copper wiring of a semiconductor device is which is resistant to unwanted diffusion of copper from away from the copper wiring is presented. The copper wiring includes an interlayer dielectric, a self-assembly monolayer, a plurality of catalyst particles, a metal layer, and a copper layer. The interlayer dielectric on the semiconductor substrate has a wiring forming region. The self-assembly monolayer is the wiring forming region. The plurality of catalyst particles are adsorbed onto the surface of the self-assembly monolayer. The metal layer is formed on the self-assembly monolayer which has the adsorbed catalyst particles such that the metal layer serves as both a seed layer and as a diffusion barrier. The copper layer substantially fills in the wiring forming region. | 03-10-2011 |
20110057317 | Contact plug structure, semiconductor device, and method for forming contact plug - A contact plug structure formed on a contact hole of an insulating layer of a semiconductor device includes a metal silicide layer formed on a bottom part of the contact hole of the insulating layer, a manganese oxide layer formed on the metal silicide layer in the contact hole, and a buried copper formed on the manganese oxide layer which substantially fills the contact hole. | 03-10-2011 |
20110062587 | LARGE GRAIN SIZE CONDUCTIVE STRUCTURE FOR NARROW INTERCONNECT OPENINGS - An interconnect structure having reduced electrical resistance and a method of forming such an interconnect structure are provided. The interconnect structure includes a dielectric material including at least one opening therein. The at least one opening is filled with an optional barrier diffusion layer, a grain growth promotion layer, an agglomerated plating seed layer, an optional second plating seed layer a conductive structure. The conductive structure which includes a metal-containing conductive material, typically Cu, has a bamboo microstructure and an average grain size of larger than 0.05 microns. In some embodiments, the conductive structure includes conductive grains that have a (111) crystal orientation. | 03-17-2011 |
20110062588 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes: a trench formed on an interlayer insulating film on a semiconductor substrate; a first barrier metal film formed to cover the bottom and sidewalls of the trench, the first barrier metal film being comprised of an electric conductor containing a platinum-group element, a refractory metal, and nitrogen; and a metal film formed on the first barrier metal film in the trench. The amount of nitrogen decreases in the thickness direction of the first barrier metal film toward the metal film. | 03-17-2011 |
20110062589 | SEMICONDUCTOR DEVICE HAVING COPPER WIRING WITH INCREASED MIGRATION RESISTANCE - A semiconductor device has: a semiconductor substrate formed with a plurality of semiconductor elements, a plurality of interlevel insulating films laminated above the semiconductor substrate, including a first and a second interlevel insulating films adjacent to each other; a first wiring trench formed in the first interlevel insulating film; and a first damascene wiring including: a first barrier metal film having a diffusion preventive function, formed covering inner surface of the first wiring trench and defining a first main wiring trench; and a first main wiring layer filling the first main wiring trench, formed of first metal element, and added with second metal element having migration suppressing function, at spatially different concentration. | 03-17-2011 |
20110068471 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The method of manufacturing a semiconductor device includes forming an insulating film of a silicon compound-group insulation film; forming an opening in the insulation film, applying an active energy beam in an atmosphere containing hydrocarbon gas to form a barrier layer of a crystalline SiC, and forming an interconnection structure of copper in the opening with the barrier layer formed in. | 03-24-2011 |
20110068472 | SEMICONDUCTOR DEVICE - A trench is formed in an insulation film formed on top of a semiconductor substrate, and a barrier metal film is formed on the surface of the trench. After a copper or copper alloy film is formed on the barrier metal film, an oxygen absorption film in which a standard energy of formation of an oxidation reaction in a range from room temperature to 400° C. is negative, and in which an absolute value of the standard energy of formation is larger than that of the barrier metal film is formed, and the assembly is heated in a temperature range of 200 to 400° C. A semiconductor device can thereby be provided that has highly reliable wiring, in which the adhesion to the barrier metal film in the copper interface is enhanced, copper diffusion in the interface is suppressed, and electromigration and stress migration are prevented. | 03-24-2011 |
20110074030 | METHOD FOR PREVENTING Al-Cu BOTTOM DAMAGE USING TiN LINER - A semiconductor device and related method for fabricating the same include providing a stacked structure including an insulating base layer and lower and upper barrier layers with a conductive layer in between, etching the stacked structure to provide a plurality of conductive columns that each extend from the lower barrier layer, each of the conductive columns having an overlying upper barrier layer cap formed from the etched upper barrier layer, wherein the lower barrier layer is partially etched to provide a land region between each of the conductive lines, forming a liner layer over the etched stacked structure exposing the land region, and etching the liner layer and removing the exposed land region to form a plurality of conductive lines | 03-31-2011 |
20110074031 | BACK SIDE METALLIZATION WITH SUPERIOR ADHESION IN HIGH-PERFORMANCE SEMICONDUCTOR DEVICES - In sophisticated semiconductor devices, the metal-containing layer stack at the back side of the substrate may be provided so as to obtain superior adhesion to the semiconductor material in order to reduce the probability of creating leakage paths in a bump structure upon separating the substrate into individual semiconductor chips. For this purpose, in some illustrative embodiments, an adhesion layer including a metal and at least one non-metal species may be used, such as titanium oxide, in combination with further metal-containing materials, such as titanium, vanadium and gold. | 03-31-2011 |
20110079907 | SEMICONDUCTOR DEVICE HAVING A COPPER PLUG - Disclosed is a semiconductor device wherein an insulation layer has a copper plug in contact with the last wiring layer of the device. There may also be a barrier layer separating the copper plug from the insulation layer. In a further embodiment, there may also be an aluminum layer between the insulation layer and copper plug. Also disclosed is a process for making the semiconductor device. | 04-07-2011 |
20110084391 | Reducing Device Mismatch by Adjusting Titanium Formation - An integrated circuit structure includes a semiconductor substrate; a first titanium layer over the semiconductor substrate, wherein the first titanium layer has a first thickness less than 130 Å; a first titanium nitride layer over and contacting the first titanium layer; and an aluminum-containing layer over and contacting the first titanium nitride layer. | 04-14-2011 |
20110084392 | Electronic Structures Including Conductive Layers Comprising Copper and Having a Thickness of at Least 0.5 Micrometers - An electronic structure may include a conductive pad on a substrate, and an insulating layer on the substrate and on the conductive pad. The insulating layer may have a via therein so that a portion of the conductive pad opposite the substrate is free of the insulating layer. A conductive layer comprising copper may be on the portion of the conductive pad free of the insulating layer, on sidewalls of the via, and on surface portions of the insulating layer surrounding the via opposite the substrate and the conductive pad, and the conductive layer comprising copper may have a thickness of at least approximately 1.0 μm. A conductive barrier layer may be on the conductive layer comprising copper, and the conductive barrier layer may include at least one of nickel, platinum, palladium, and/or combinations thereof. A solder layer may be on the conductive barrier layer, the conductive layer comprising copper and the solder layer may comprise different materials, and the conductive barrier layer may be between the conductive layer comprising copper and the solder layer. | 04-14-2011 |
20110084393 | METHOD OF FORMING ELECTRODEPOSITED CONTACTS - A contact metallurgy structure comprising a patterned dielectric layer having vias on a substrate; a silicide layer of cobalt and/or nickel located at the bottom of vias; a contact layer comprising Ti located in vias on top of the silicide layer; a diffusion layer located in vias and on top of the contact layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer comprises at least one member selected from the group consisting of copper, ruthenium, rhodium platinum, palladium, iridium, rhenium, tungsten, gold, silver and osmium and alloys thereof. When the metal fill layer comprises rhodium, the diffusion layer is not required. Optionally a seed layer for the metal fill layer can be employed. | 04-14-2011 |
20110095427 | LOW-RESISTANCE INTERCONNECTS AND METHODS OF MAKING SAME - Devices and methods for providing low-resistance interconnects in a semiconductor device are provided. Specifically, one or more embodiments of the present invention relate to disposing a conductive material in a trench without disposing a resistive barrier material between the conductive material and the sidewalls of the trench so that the conductive material takes up the full width of the trench. For example, the trench may be disposed over one or more contacts made of a barrier material such as titanium nitride that also acts as a seed, and the conductive material may be grown on top of the titanium nitride to fill the trench. | 04-28-2011 |
20110095428 | SMALL AREA, ROBUST SILICON VIA STRUCTURE AND PROCESS - A semiconductor structure includes: at least one silicon surface wherein the surface can be a substrate, wafer or other device. The structure further includes at least one electronic circuit formed on each side of the at least one surface; and at least one conductive high aspect ratio through silicon via running through the at least one surface. Each through silicon via is fabricated from at least one etch step and includes: at least one thermal oxide dielectric for coating at least some of a sidewall of the through silicon via for a later etch stop in fabrication of the through silicon via. | 04-28-2011 |
20110095429 | METHODS FOR FABRICATING AND FILLING CONDUCTIVE VIAS AND CONDUCTIVE VIAS SO FORMED - Methods for forming conductive vias include foiling one or more via holes in a substrate. The via holes may be formed with a single mask, with protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof A barrier layer may be fowled over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed. | 04-28-2011 |
20110101528 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to one embodiment includes: a substrate; a wiring provided above the substrate and including a graphene nanoribbon layer comprising a plurality of laminated graphene nanoribbon sheets; and a wiring connecting member penetrating at least one of the plurality of graphene nanoribbon sheets for connecting the wiring and a conductive member above or below the wiring. | 05-05-2011 |
20110101529 | BARRIER LAYER FOR COPPER INTERCONNECT - A copper interconnect includes a copper layer formed in a dielectric layer. A glue layer is formed between the copper layer and the dielectric layer. A barrier layer is formed at the boundary between the glue layer and the dielectric layer. The barrier layer is a metal oxide. | 05-05-2011 |
20110101530 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF - A seal ring is provided between a region where a circuit is formed on a semiconductor substrate and a dicing region. The seal ring has a portion where sealing layers of which the cross sectional form is in T-shape are layered and a portion where sealing layers of which the cross sectional form is rectangular are layered. | 05-05-2011 |
20110101531 | THERMO-MECHANICAL STRESS IN SEMICONDUCTOR WAFERS - An apparatus for restricting the thermo-mechanical stress in semiconductor wafers both during manufacture, and during the operating lifetime of the semiconductor devices and systems formed on the wafer. An electrically conductive track | 05-05-2011 |
20110108985 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device comprises: etching a semiconductor substrate to form a plurality of pillar patterns; depositing an insulating layer on the surface of the pillar pattern; removing a portion of the insulating layer located at one side of the pillar pattern to form a contact hole that exposes the pillar pattern; forming a barrier film in the contact hole; and forming a junction in the pillar pattern that contacts with the contact hole. In the method, when a buried bit line is formed, a diffusion barrier is formed in the contact hole and a junction is formed in the lower portion of the pillar pattern, thereby improving characteristics of the device. | 05-12-2011 |
20110108986 | THROUGH-SILICON VIA STRUCTURE AND A PROCESS FOR FORMING THE SAME - A semiconductor substrate has a front surface and a back surface, and a TSV structure is formed to extend through the semiconductor substrate. The TSV structure includes a metal layer, a metal seed layer surrounding the metal layer, a barrier layer surrounding the metal seed layer, and a block layer formed in a portion sandwiched between the metal layer and the metal seed layer. The block layer includes magnesium (Mg), iron (Fe), cobalt (Co), nickel (Ni), titanium (Ti), chromium (Cr), tantalum (Ta), tungsten (W), cadmium (Cd), or combinations thereof. | 05-12-2011 |
20110108987 | SEMICONDUCTOR DEVICE - A semiconductor device, may include a first insulating layer formed on a semiconductor substrate, a contact provided in the first insulating layer, a second dielectric layer formed on the first insulating layer, the second insulating layer having lower dielectric constant than the first dielectric layer, a wiring formed in the second insulating layer and being electrically connected to the contact, a first barrier metal formed on a bottom of the contact and on a side surface of the wiring, and a second barrier metal formed on a side surface of the bottom and on the first barrier metal. | 05-12-2011 |
20110108988 | VIA STRUCTURES AND SEMICONDUCTOR DEVICES HAVING THE VIA STRUCTURES - A via structure may include a first conductive pattern, a buffer pattern, and a second conductive pattern. The first conductive pattern may be on an inner wall of a first substrate and the inner wall may define a via hole passing at least partially through the first substrate. The buffer pattern may be on the first conductive pattern and the buffer pattern may partially fill the via hole. The second conductive pattern may be on a top surface of the buffer pattern in the via hole. | 05-12-2011 |
20110121458 | Bonding Connection Between a Bonding Wire and a Power Semiconductor Chip - A bonding connection between a bonding wire and a power semiconductor chip is disclosed. The power semiconductor chip has a semiconductor body arranged in which is an active cell region with a multiplicity of cells arranged one following the other in a lateral direction and connected electrically in parallel. The semiconductor body has a surface portion arranged above the active cell region in a vertical direction perpendicular to the lateral direction. Applied to the surface portion is a metallization layer onto which a bonding wire is bonded. The bonding wire comprises an alloy containing at least 99% by weight aluminium and at least one further alloying constituent. The aluminum has a grain structure with a mean grain size which is less than 2 μm. | 05-26-2011 |
20110121459 | SEMICONDUCTOR INTERCONNECTION - Provided is a semiconductor interconnection wherein a barrier layer different from a TiO | 05-26-2011 |
20110127673 | WIRING STRUCTURE AND METHOD - Disclosed is an improved integrated circuit wiring structure configured to prevent migration of wiring metal ions (e.g., copper (Cu+) ions in the case of a copper interconnect scheme) onto the surface of an interlayer dielectric material at an interface between the interlayer dielectric material and an insulating cap layer. Specifically, the top surfaces of wires and the top surface of a dielectric layer within which the wires sit are not co-planar. Thus, the interfaces between the wires and an insulating cap layer and between the dielectric layer and the same insulating cap layer are also not co-planar. Such a configuration physically prevents migration of wiring metal ions from the top surface of the wires onto the top surface of the dielectric layer at the interface between the dielectric layer and cap layer and, thereby prevents time dependent dielectric breakdown (TDDB) and eventual device failure. Also disclosed herein are embodiments of a method of a forming such an integrated circuit wiring structure. | 06-02-2011 |
20110127674 | LAYER STRUCTURE FOR ELECTRICAL CONTACTING OF SEMICONDUCTOR COMPONENTS - A layer structure for the electrical contacting of a semiconductor component having integrated circuit elements and integrated connecting lines for the circuit elements, which is suitable in particular for use in a chemically aggressive environment and at high temperatures, i.e., in so-called “harsh environments,” and is simple to implement. This layer structure includes at least one noble metal layer, in which at least one bonding island is formed, the noble metal layer being electrically insulated from the substrate of the semiconductor component by at least one dielectric layer, and having at least one ohmic contact between the noble metal layer and an integrated connecting line. The noble metal layer is applied directly on the ohmic contact layer. | 06-02-2011 |
20110133338 | CONDUCTOR BUMP METHOD AND APPARATUS - Various semiconductor die conductor structures and methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a conductor structure on a conductor pad of a semiconductor die. The conductor layer has a surface. A polymeric layer is formed on the surface of the conductor layer while a portion of the surface is left exposed. A solder structure is formed on the exposed portion of the surface and a portion of the polymeric layer. | 06-09-2011 |
20110140275 | Semiconductor device and manufacturing method of the same - In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming insulative films and a barrier insulative film for a reservoir pattern, forming an insulative film capable of suppressing or preventing copper from diffusing on the upper surface and on the lateral surface of the interconnection and above the insulative film and the insulative film, forming insulative films of low dielectric constant, in which the insulative film is formed such that the deposition rate above the opposing lateral surfaces of the interconnections is larger than the deposition rate therebelow to form an air gap between the adjacent interconnections and, finally, planarizing the insulative film by interlayer CMP. | 06-16-2011 |
20110140276 | INTERLAYER INSULATING FILM, INTERCONNECTION STRUCTURE, AND METHODS OF MANUFACTURING THE SAME - This invention provides an interlayer insulating film for a semiconductor device, which has low permittivity, is free from the evolution of gas such as CFx and SiF | 06-16-2011 |
20110147936 | SEMICONDUCTOR DEVICE AND DAMASCENE STRUCTURE - The present invention provides a semiconductor device, including a silicon-containing material, a conductive layer deposited on the silicon-containing material, and a diffusion barrier layer interposed between the silicon-containing material and the conductive layer, wherein the diffusion barrier layer contains a rare earth scandate. The present invention further provides a damascene structure containing the rare earth scandate as diffusion barrier. | 06-23-2011 |
20110147937 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - In one exemplary embodiment, a method of manufacturing a semiconductor device is disclosed in which a damascene interconnect is formed above an underlying insulating film. The method includes forming an interconnect insulating film above the underlying insulating film such that a film density of the interconnect insulating film is relatively greater at a lower side thereof and relatively less at an upper side thereof. The interconnect insulating film is anisotropically dry etched to form an interconnect trench. The interconnect trench is wet etched such that an upper portion of a vertical cross section thereof exhibits a positive taper. A barrier metal film is formed along an inner surface of the interconnect trench including the positive taper. Further, the interconnect trench is filled with an interconnect conductor by plating over the barrier metal film. | 06-23-2011 |
20110147938 | CONDUCTIVE VIA HOLE AND METHOD FOR FORMING CONDUCTIVE VIA HOLE - Provided is a technology for forming a conductive via hole to implement a three dimensional stacked structure of an integrated circuit. A method for forming a conductive via hole according to an embodiment of the present invention comprises: filling inside of a via hole structure that is formed in one or more of an upper portion and a lower portion of a substrate with silver by using a reduction and precipitation of silver in order to connect a plurality of stacked substrates by a conductor; filling a portion that is not filled with silver inside of the via hole structure by flowing silver thereinto; and sublimating residual material of silver oxide series, which is generated during the flowing, on an upper layer inside of the via hole structure filled with silver. | 06-23-2011 |
20110156256 | ELECTROMIGRATION-RESISTANT UNDER-BUMP METALLIZATION OF NICKEL-IRON ALLOYS FOR SN-RICH SOLDER BUMPS OF PB-FREE FLIP-CHIP APPLICATIONS - A process comprises manufacturing an electromigration-resistant under-bump metallization (UBM) flip chip structure comprising a Cu layer by applying to the Cu layer a metallic reaction barrier layer comprising NiFe. The solder employed in the flip chip structure comprise substantially lead-free tin. A structure comprises a product produced by this process. In another embodiment a process comprises manufacturing an electromigration-resistant UBM Sn-rich Pb-free solder bump flip chip structure wherein the electromigration-resistant UBM structure comprises a four-layer structure, or a three-layer structure, wherein the four layer structure is formed by providing 1) an adhesion layer, 2) a Cu seed layer for plating, 3) a reaction barrier layer, and 4) a wettable layer for joining to the solder, and the three-layer structure is formed by providing 1) an adhesion layer, 2) a reaction barrier layer, and 3) a wettable layer. In a further embodiment, the reaction barrier layer comprises metals selected from Ni, Fe, Pd, Pt, Co, Cu and their alloys, and combinations thereof. A structure comprises a product produced by the immediately foregoing process. | 06-30-2011 |
20110156257 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device includes providing a substrate including pattern formed over the substrate and a first insulating layer formed over the pattern. A diffusion barrier layer is formed over the first insulation layer. A second insulating layer is formed over the diffusion barrier layer. The second insulating layer, the diffusion layer, and the first insulating layer are patterned to form a trench exposing the pattern. A metal layer is formed over the second insulating layer and within the trench to define a metal interconnection pattern coupling the pattern within the trench, the metal particles from the metal layer diffuse into the second insulating layer. The second insulation layer and the metal particles that have been diffused therein are removed. | 06-30-2011 |
20110156258 | SEMICONDUCTOR DEVICE HAVING THROUGH VIA AND METHOD FOR FABRICATING THE SAME - In one embodiment, a semiconductor device may includes a through via disposed within a substrate with a diffusion barrier layer disposed over the through via and the substrate. An insulation layer may be disposed over the diffusion barrier layer, a metal interconnection layer disposed within the insulation layer over at least a portion of the via contact, and a via contact disposed between the metal interconnection layer and the through via within the insulation layer. The via contact may have a cross-sectional area larger than a cross-sectional area of the through via so that the through via and the diffusion barrier layer do not contact each other. | 06-30-2011 |
20110163450 | INTEGRATED CIRCUIT LINE WITH ELECTROMIGRATION BARRIERS - A method for fabricating an integrated circuit comprising an electromigration barrier in a line of the integrated circuit includes forming a spacer; forming a segmented line adjacent to opposing sides of the spacer, the segmented line formed from a first conductive material; removing the spacer to form an empty line break; and filling the empty line break with a second conductive material to form an electromigration barrier that isolates electromigration effects within individual segments of the segmented line. An integrated circuit comprising an electromigration barrier includes a line, the line comprising a first conductive material, the line further comprising a plurality of line segments separated by one or more electromigration barriers, wherein the one or more electromigration barriers comprise a second conductive material that isolates electromigration effects within individual segments of the line. | 07-07-2011 |
20110163451 | FILM FORMING METHOD AND PROCESSING SYSTEM - Provided is a film-forming method for performing a film-forming process on a surface of a target substrate to be processed in an evacuable processing chamber, a recessed portion being formed on the surface of the target substrate. The method includes a transition metal-containing film processing process in which a transition metal-containing film is formed by a heat treatment by using a source gas containing a transition metal; and a metal film forming process in which a metal film containing an element of the group VIII of the periodic table is formed. | 07-07-2011 |
20110175226 | INTERCONNECT STRUCTURE FOR INTEGRATED CIRCUITS HAVING ENHANCED ELECTROMIGRATION RESISTANCE - An interconnect structure for an integrated circuit (IC) device includes a metal line formed within a dielectric layer, the metal line having one or more vertical diffusion barriers therein; wherein the one or more vertical diffusion barriers correspond to a liner material of a via formed above the metal line, with the via extending completely through a thickness of the metal line such that a bottom most portion of the via comprises a portion of the metal line | 07-21-2011 |
20110187000 | Integrated Circuits Having TSVS Including Metal Gettering Dielectric Liners - An IC includes a substrate having a semiconductor top surface and a bottom surface, wherein the semiconductor top surface includes one or more active circuit components and a plurality of through silicon vias (TSVs) extending through the substrate. The plurality of TSVs include an outer dielectric liner. The dielectric liner includes at least one halogen or a Group 15 element metal gettering agent in an average concentration from 1 to 10 atomic %. A metal diffusion barrier layer is on the dielectric liner and a metal filler is on the metal barrier layer. The metal gettering agent getters metal filler that escapes the metal barrier layer. | 08-04-2011 |
20110198756 | Organometallic Precursors and Related Intermediates for Deposition Processes, Their Production and Methods of Use - Vapor deposition precursors that can deposit conformal thin ruthenium films on substrates with a very high growth rate, low resistivity and low levels of carbon, oxygen and nitrogen impurities have been provided. The precursors described herein include a compound having the formula CMC′, wherein M comprises a metal or a metalloid; C comprises a substituted or unsubstituted acyclic alkene, cycloalkene or cycloalkene-like ring structure; and C′ comprises a substituted or unsubstituted acyclic alkene, cycloalkene or cycloalkene-like ring structure; wherein at least one of C and C′ further and individually is substituted with a ligand represented by the formula CH(X)R | 08-18-2011 |
20110204517 | Semiconductor Device with Vias Having More Than One Material - A semiconductor die includes a via within a substrate material of the semiconductor die. The via includes a first conductive material having a first Coefficient of Thermal Expansion (CTE) and a second conductive material between the first conductive material and the substrate material of the semiconductor die. The second conductive material has a second CTE between the first CTE and a CTE of the substrate material of the semiconductor die. The first conductive material can be copper. The second conductive material can be tungsten and/or nickel. The substrate material can be silicon. | 08-25-2011 |
20110204518 | SCALABILITY WITH REDUCED CONTACT RESISTANCE - Miniaturized semiconductor devices are formed with improved liner/barrier layer properties and, hence, improved contact resistance. Embodiments include semiconductor devices comprising contacts and vias with annealed liner/barrier layers having decreased carbon content and increased density. An embodiment includes depositing a metal containing layer, such as at least one member selected from the group consisting of titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), cobalt (Co), and ruthenium (Ru) to line an opening formed in a dielectric layer, and annealing the deposited metal containing layer, as in a non-oxidizing atmosphere, to increase its density, decrease defects, and alter its material composition, for example, reduce its carbon content. As a result, a metal, e.g., W or Cu, plug filing the contact/via exhibits a reduced surface roughness and defectivity, and thereby improved contact resistance and reliability. | 08-25-2011 |
20110204519 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first interconnect, a porous dielectric layer formed over the first interconnect, a second interconnect buried in the porous dielectric layer and electrically connected to the first interconnect, and a carbon-containing metal film that is disposed between the porous dielectric layer and the second interconnect and isolates these layers. | 08-25-2011 |
20110210445 | SEMICONDUCTOR DEVICE HAVING VIA CONNECTING BETWEEN INTERCONNECTS - A first insulating film is provided between a lower interconnect and an upper interconnect. The lower interconnect and the upper interconnect are connected to each other by way of a via formed in the first insulating film. A dummy via or an insulating slit is formed on/in the upper interconnect near the via. | 09-01-2011 |
20110215474 | INTEGRATED CIRCUIT STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing an integrated circuit structure is disclosed. First, a dielectric layer is formed on a substrate, the substrate has a transistor region and a diode region. Next, a contact hole and an opening are formed in the dielectric layer, a size of the opening being larger than that of the contact hole. Nest, a first metal layer is formed on the dielectric layer and filled into the contact hole and the opening. Next, a portion of the first metal layer is removed to form a contact plug above the transistor region and form a metal spacer on a sidewall of the opening. Next, an ion implantation process is performed to form a lightly doped region in the substrate at a bottom of the opening. Finally, a contact metal layer is formed on the lightly doped region. | 09-08-2011 |
20110221063 | Manufacturing Method of Semiconductor Device - A process for burying a tungsten member into a blind hole formed in a wafer, in which blind hole a through via is to be made. Film-formation (for forming the tungsten member) is carried out to position, at the periphery of the wafer, the outer circumference of the tungsten member inside the outer circumference of a barrier metal beneath the tungsten film. This process makes it possible to bury the tungsten member, which may be relatively thin, into the blind hole, which may be relatively large, so as to decrease a warp of the wafer and further prevent an underlying layer beneath the tungsten member from being peeled at the periphery of the wafer. | 09-15-2011 |
20110227224 | Semiconductor device and method for manufacturing the same - A semiconductor device includes an interlayer insulating film formed over a semiconductor substrate, a through hole formed in the interlayer insulating film, a Cu film filling the through hole, and a metal-containing base film formed on the sidewall inside the through hole and serving as a base of the Cu film. The metal-containing base film has a metal nitride layer at the interface with the Cu film in a first region including a sidewall area adjacent to the opening of the through hole. In a second region including a sidewall area nearer to the semiconductor substrate than is the first region, the metal-containing base film has a metal layer at the interface with the Cu film. The deposition rate of the Cu film on the surface of the metal layer is greater than the deposition rate of the Cu film on the surface of the metal nitride layer. | 09-22-2011 |
20110227225 | COPPER ALLOY VIA BOTTOM LINER - Improved mechanical and adhesive strength and resistance to breakage of copper integrated circuit interconnections is obtained by forming a copper alloy in a copper via/wiring connection in an integrated circuit while minimizing adverse electrical effects of the alloy by confining the alloy to an interfacial region of said via/wiring connection and not elsewhere by a barrier which reduces or substantially eliminates the thickness of alloy in the conduction path. The alloy location and composition are further stabilized by reaction of all available alloying material with copper, copper alloys or other metals and their alloys. | 09-22-2011 |
20110227226 | MULTI-CHIP STACK STRUCTURE HAVING THROUGH SILICON VIA - The invention discloses a multi-chip stack structure having through silicon via and a method for fabricating the same. The method includes: providing a wafer having a plurality of first chips; forming a plurality of holes on a first surface of each of the first chips and forming metal posts and solder pads corresponding to the holes so as to form a through silicon via (TSV) structure; forming at least one groove on a second surface of each of the first chips to expose the metal posts of the TSV structure so as to allow at least one second chip to be stacked on the first chip, received in the groove and electrically connected to the metal posts exposed from the groove; filling the groove with an insulating material for encapsulating the second chip; mounting conductive elements on the solder pads of the first surface of each of the first chips and singulating the wafer; and mounting and electrically connecting the stacked first and second chips to a chip carrier via the conductive elements. The wafer, which is not totally thinned but includes a plurality of first chips, severs a carrying purpose during the fabrication process and thereby solves problems, namely a complicated process, high cost, and adhesive layer contamination, facing the prior art that entails repeated use of a carrier board and an adhesive layer for vertically stacking a plurality of chips and mounting the stacked chips on a chip carrier. | 09-22-2011 |
20110233778 | FORMATION OF LINER AND BARRIER FOR TUNGSTEN AS GATE ELECTRODE AND AS CONTACT PLUG TO REDUCE RESISTANCE AND ENHANCE DEVICE PERFORMANCE - The invention provides a method of forming a film stack on a substrate, comprising depositing a tungsten nitride layer on the substrate, subjecting the substrate to a nitridation treatment using active nitrogen species from a remote plasma, and depositing a conductive bulk layer directly on the tungsten nitride layer without depositing a tungsten nucleation layer on the tungsten nitride layer as a growth site for tungsten. | 09-29-2011 |
20110233779 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes an interlayer insulation film provided on a substrate including a Cu wiring, a via hole formed in the interlayer insulation film on the Cu wiring, a first metal film selectively formed on the Cu wiring in the via hole, functioning as a barrier to the Cu wiring, and functioning as a promoter of carbon nanotube growth, a second metal film formed at least on the first metal film in the via hole, and functioning as a catalyst of the carbon nanotube growth, and carbon nanotubes buried in the via hole in which the first metal film and the second metal film are formed. | 09-29-2011 |
20110233780 | COBALT NITRIDE LAYERS FOR COPPER INTERCONNECTS AND METHODS FOR FORMING THEM - An interconnect structure for integrated circuits incorporates a layer of cobalt nitride that facilitates the nucleation, growth and adhesion of copper wires. The cobalt nitride may deposited on a refractory metal nitride or carbide layer, such as tungsten nitride or tantalum nitride, that serves as a diffusion barrier for copper and also increases the adhesion between the cobalt nitride and the underlying insulator. The cobalt nitride may be formed by chemical vapor deposition from a novel cobalt amidinate precursor. Copper layers deposited on the cobalt nitride show high electrical conductivity and can serve as seed layers for electrochemical deposition of copper conductors for microelectronics. | 09-29-2011 |
20110233781 | METAL LINE OF SEMICONDUCTOR DEVICE HAVING A DIFFUSION BARRIER WITH AN AMORPHOUS TaBN LAYER AND METHOD FOR FORMING THE SAME - A metal line in a semiconductor device includes an insulation layer formed on a semiconductor substrate. A metal line forming region is formed in the insulation layer. A metal line is formed to fill the metal line forming region of the insulation layer. And a diffusion barrier that includes an amorphous TaBN layer is formed between the metal line and the insulation layer. The amorphous TaBN layer prevents a copper component from diffusing into the semiconductor substrate, thereby improving upon the characteristics and the reliability of a device. | 09-29-2011 |
20110241209 | Substrate comprising alloy film of metal element having barrier function and metal element having catalytic power - It is an object of the present invention to provide a layer having a barrier function and catalytic power and excelling in formation uniformity and coverage of an ultrathin film, provide a pretreatment technique making it possible to form an ultrafine wiring and form a thin seed layer of uniform film thickness, and provide a substrate including a thin seed layer formed with a uniform film thickness by electroless plating by using the aforementioned technique. The present invention provides a substrate in which an alloy film of one or more metal elements, having a barrier function, selected from among tungsten, molybdenum and, niobium and a metal element or metal elements, having catalytic power with respect to electroless plating, composed of ruthenium and/or platinum is formed by chemical vapor deposition (CVD) on a base to a film thickness of 0.5 nm to 5 nm in a composition with a content ratio of the one or more metal element having a barrier function of equal to or greater than 5 at. % and equal to or less than 90 at. %. | 10-06-2011 |
20110241210 | COMPOSITION FOR SEALING SEMICONDUCTOR, SEMICONDUCTOR DEVICE, AND PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE - The invention provides a composition for sealing a semiconductor, the composition being able to form a thin resin layer, suppress the diffusion of a metal component to a porous interlayer dielectric layer, and exhibit superior adherence with respect to an interconnection material. The composition for sealing a semiconductor contains a resin having two or more cationic functional groups and a weight-average molecular weight of from 2,000 to 100,000; contains sodium and potassium each in an amount based on element content of not more than 10 ppb by weight; and has a volume average particle diameter, measured by a dynamic light scattering method, of not more than 10 nm. | 10-06-2011 |
20110241211 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device has forming, in a dielectric film, a first opening and a second opening located in the first opening, forming a first metal film containing a first metal over a whole surface, etching the first metal film at a bottom of the second opening using a sputtering process and forming a second metal film containing a second metal over the whole surface, and burying a conductive material in the second opening and the first opening. | 10-06-2011 |
20110248402 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided are a semiconductor device and a method for manufacturing the same. Since a plug is formed in a portion of a metal interconnection between a first metal contact and a second metal contact, an amount of a metal interconnection coupled to a second metal contact increases. Also, since the first metal contact is formed so that the upper width is narrower than the lower width by using insulation layers having a different etching selectivity when the first metal contact is formed, it is possible to substantially prevent copper ions of the meal interconnection from being migrated or separated according to the flow of a VPP electric field. Consequently, a contact-not-open phenomenon between the first metal contact and the second metal contact may be prevented. | 10-13-2011 |
20110254164 | SELF-ALIGNED BARRIER LAYERS FOR INTERCONNECTS - An interconnect structure for integrated circuits incorporates manganese silicate and manganese silicon nitride layers that completely surrounds copper wires in integrated circuits and methods for making the same are provided. The manganese silicate forms a barrier against copper diffusing out of the wires, thereby protecting the insulator from premature breakdown, and protecting transistors from degradation by copper. The manganese silicate and manganese silicon nitride also promote strong adhesion between copper and insulators, thus preserving the mechanical integrity of the devices during manufacture and use. The strong adhesion at the copper-manganese silicate and manganese silicon nitride interfaces also protect against failure by electromigration of the copper during use of the devices. The manganese-containing sheath also protects the copper from corrosion by oxygen or water from its surroundings. | 10-20-2011 |
20110254165 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PRODUCTION METHOD THEREOF - In processes after a TSV is formed, occasionally, cracks appear in an insulation film after the insulation film that is a film for preventing Cu from diffusing is formed and the exposed Cu discolors at a succeeding process of pattern forming such as etching or asking. It is estimated that the problems occur because the volume of Cu expands by heat history at the process of forming a diffusion preventive film. When such film cracking occurs, various problems such as the destruction of the function of a Cu diffusion preventive film and conduction fault with upper wiring caused by the oxidation of Cu at the upper part of a TSV are induced. In the invention of the present application, in a semiconductor integrated circuit device having a through electrode, when a through via is formed after a pre-metal wiring layer is formed, an insulation film of a kind of silicon nitride is used as a metal diffusion preventive insulation film at the interface of an interlayer insulation film touching the top end of the through electrode and an insulation film of kind of silicon carbide is used as a metal diffusion preventive insulation film at the interfaces of the other interlayer insulation films. | 10-20-2011 |
20110260323 | HYBRID INTERCONNECT STRUCTURE FOR PERFORMANCE IMPROVEMENT AND RELIABILITY ENHANCEMENT - The present invention provides an interconnect structure (of the single or dual damascene type) and a method of forming the same, in which a dense (i.e., non-porous) dielectric spacer is present on the sidewalls of a dielectric material. More specifically, the inventive structure includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance as compared with existing prior art interconnect structures which do not include such dense dielectric spacers. Moreover, the inventive hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing. | 10-27-2011 |
20110266676 | METHOD FOR FORMING INTERCONNECTION LINE AND SEMICONDUCTOR STRUCTURE - A semiconductor structure is formed by placing a thin barrier metal layer in an interconnection trench or via in a manner such that the opening of the trench or via is not obstructed by an overhang that interferes with the placement of copper into the interconnection trench or via. The material for forming a copper interconnection line contains copper and manganese. Upon annealing, a manganese oxide layer is formed having barrier properties against copper diffusion. | 11-03-2011 |
20110266677 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME - The present invention provides a semiconductor structure and a manufacturing method thereof. The method comprises; providing a semiconductor substrate comprising semiconductor devices; depositing a copper diffusion barrier layer on the semiconductor substrate; forming a copper composite layer on the copper diffusion barrier layer; decomposing the copper composite at corresponding positions, where copper interconnection is to be formed, into copper according to the shape of the copper interconnection; and etching off the undecomposed copper composite and the copper diffusion barrier layer underneath, to interconnect the semiconductor devices. The present invention is adaptive for manufacturing interconnection in integrated circuits. | 11-03-2011 |
20110266678 | Semiconductor device and method for manufacturing same - A semiconductor device includes a semiconductor substrate, an insulating film formed above the semiconductor substrate, and a multilayered wiring formed in a prescribed area within the insulating film. The multilayered wiring includes a dual damascene wiring positioned on at least one layer of the multilayered wiring. The dual damascene wiring includes an alloy having copper as a principal component. A concentration of at least one metallic element contained as an added component of the alloy in a via connected to the dual damascene wiring is 10% or more higher in a via connected to a wiring whose width exceeds by five or more times a diameter of the via than that in another via connected to another wiring of a smallest width in a same upper wiring layer of the multilayered wiring. | 11-03-2011 |
20110272811 | USING UNSTABLE NITRIDES TO FORM SEMICONDUCTOR STRUCTURES - Incompatible materials, such as copper and nitrided barrier layers, may be adhered more effectively to one another. In one embodiment, a precursor of copper is deposited on the nitrided barrier. The precursor is then converted, through the application of energy, to copper which could not have been as effectively adhered to the barrier in the first place. | 11-10-2011 |
20110285021 | NOBLE METAL CAP FOR INTERCONNECT STRUCTURES - An interconnect structure that includes a dielectric material having a dielectric constant of about 3.0 or less is provided. This low k dielectric material has at least one conductive material having an upper surface embedded therein. The dielectric material also has a surface layer that is made hydrophobic prior to the formation of the noble metal cap. The noble metal cap is located directly on the upper surface of the at least one conductive material. Because of the presence of the hydrophobic surface layer on the dielectric material, the noble metal cap does not substantially extend onto the hydrophobic surface layer of the dielectric material that is adjacent to the at least one conductive material and no metal residues from the noble metal cap deposition form on this hydrophobic dielectric surface. | 11-24-2011 |
20110291277 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING SEMICONDUCTOR DEVICE - A semiconductor device includes a wiring, a stack of first, second, and third films, and a contact plug. The stack of first, second, and third films is located over the wiring. The first, second, and third films are stacked in this order. The stack has an opening. The first film is made of the same material as the third film. The contact plug is in the opening. The contact plug is in contact with the wiring. | 12-01-2011 |
20110291278 | SEMICONDUCTOR DEVICES WITH LOW RESISTANCE BACK-SIDE COUPLING - Electronic elements with very low resistance back-side coupling are provided by forming one or more narrow trenches or pipes, preferably dielectric lined, in front sides of substrates, filling the trenches or pipes with a conductor having a coefficient of expansion not too different from that of the substrate but of higher conductivity, forming an epitaxial SC layer over the front side of the substrate in Ohmic contact with the conductor the trenches or pipes, forming various semiconductor (SC) devices in the epi-layer, back grinding the substrate to expose bottoms of the conductor filled trenches or pipes, and providing a back-side conductor contacting the conductor in the trenches or pipes. For silicon SCs, tungsten is a suitable conductor for filling the trenches or pipes to minimize substrate stress. Series ON-resistance of the elements due to the substrate resistance is substantially reduced. | 12-01-2011 |
20110298133 | SEMICONDUCTOR DEVICE - The reliability of a porous Low-k film is improved. The mean diameter of first pores and second pores in an interlayer insulation film of a second fine layer including a porous Low-k film is set at 1.0 nm or more and less than 1.45 nm. This prevents the formation of a modified layer over the surface of the interlayer insulation film by process damages. Further, the formation of the moisture-containing modified layer is inhibited to prevent oxidation of a barrier film and a main conductor film forming respective wirings. This prevents deterioration of breakdown voltage between respective wirings. This prevents deterioration of the EM lifetime of wirings formed adjacent to the interlayer insulation film and the inter-wiring TDDB lifetime of the wirings. | 12-08-2011 |
20110298134 | THREE DIMENSIONAL INTERCONNECT STRUCTURE AND METHOD THEREOF - A three-dimensional interconnect includes a first substrate bonded to a second substrate, the first substrate including a device layer and a bulk semiconductor layer, a metal pad disposed on the second substrate, an electrically insulating layer disposed between the first and second substrates. The structure has a via-hole extending through the device layer, the bulk semi-conductor layer and the electrically insulating layer to the metal pad on the second substrate. The structure has a dielectric coating on a sidewall of the via-hole, and a plasma-treated region of the metal pad disposed on the second substrate. The structure includes a via metal monolithically extending from the plasma-treated region of the metal pad through the via-hole and electrically interconnecting the device layer of the first substrate to the metal pad of the second substrate. | 12-08-2011 |
20110309508 | Method and Structure of Forming Silicide and Diffusion Barrier Layer With Direct Deposited Film on Silicon - A semiconductor device or a photovoltaic cell having a contact structure, which includes a silicon (Si) substrate; a metal alloy layer deposited on the silicon substrate; a metal silicide layer and a diffusion layer formed simultaneously from thermal annealing the metal alloy layer; and a metal layer deposited on the metal silicide and barrier layers. | 12-22-2011 |
20110309509 | SEMICONDUCTOR CHIP WITH CONDUCTIVE DIFFUSION REGIONS, METHOD FOR MANUFACTURING THE SAME, AND STACK PACKAGE USING THE SAME - A semiconductor chip includes a substrate with a barrier region and a conductive diffusion region formed in the substrate and is surrounded by the barrier region. The conductive diffusion region may provide a conductive oath from top of the substrate to bottom of the substrate. | 12-22-2011 |
20110309510 | ARRAY SUBSTRATE, DISPLAY DEVICE HAVING THE SAME AND METHOD OF MANUFACTURING THE SAME - An array substrate includes a switching element, a signal transmission line, a passivation layer and a pixel electrode. The switching element is disposed on an insulating substrate. The signal transmission line is connected to the switching element and includes a barrier layer, a conductive line, and a copper nitride layer. The barrier layer is disposed on the insulating substrate. The conductive line is disposed on the barrier layer and includes copper or copper alloy. The copper nitride layer covers the conductive line. The passivation layer covers the switching element and the signal transmission line and has a contact hole through which a drain electrode of the switching element is partially exposed. The pixel electrode is disposed on the insulating substrate, and is connected to the drain electrode of the switching element through the contact hole. | 12-22-2011 |
20110316160 | Semiconductor Arrangement, Semiconductor Module, and Method for Connecting a Semiconductor Chip to a Ceramic Substrate - A semiconductor arrangement includes a silicon body having a top surface and a bottom surface, and a thick metal layer arranged on the top surface of the silicon body. The thick metal layer has a bonding surface facing away from the top surface of the silicon body. A bonding wire or a ribbon is bonded to the thick metal layer at the bonding surface of the thick metal layer. The thickness of the thick metal layer is at least | 12-29-2011 |
20120001330 | Semiconductor Device Comprising Through Hole Vias Having a Stress Relaxation Mechanism - In a semiconductor device, through hole vias or through silicon vias (TSV) may be formed so as to include an efficient stress relaxation mechanism, for instance provided on the basis of a stress relaxation layer, in order to reduce or compensate for stress forces caused by a pronounced change in volume of the conductive fill materials of the through hole vias. In this manner, the high risk of creating cracks and delamination events in conventional semiconductor devices may be significantly reduced. | 01-05-2012 |
20120001331 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a plurality of first interconnects, a second interconnect, a third interconnect, and a plurality of conductive members. The plurality of first interconnects are arranged periodically to extend in one direction. The second interconnect is disposed outside a group of the plurality of first interconnects to extend in the one direction. The third interconnect is provided between the group and the second interconnect. The plurality of conductive members are disposed on a side opposite to the group as viewed from the second interconnect. A shortest distance between the first interconnect and the third interconnect, a shortest distance between the third interconnect and the second interconnect, and a shortest distance between the first interconnects are equal. A shortest distance between the second interconnect and the conductive member is longer than the shortest distance between the first interconnects. | 01-05-2012 |
20120001332 | Semiconductor Device and Manufacturing Method Thereof - A semiconductor film having an impurity region to which at least an n-type or p-type impurity is added and a wiring are provided. The wiring includes a diffusion prevention film containing a conductive metal oxide, and a low resistance conductive film over the diffusion prevention film. In a contact portion between the wiring and the semiconductor film, the diffusion prevention film and the impurity region are in contact with each other. The diffusion prevention film is formed in such a manner that a conductive film is exposed to plasma generated from a mixed gas of an oxidizing gas and a halogen-based gas to form an oxide of a metal material contained in the conductive film, the conductive film in which the oxide of the metal material is formed is exposed to an atmosphere containing water to be fluidized, and the fluidized conductive film is solidified. | 01-05-2012 |
20120001333 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the semiconductor memory device. A contact plug is formed by wet etching. An aspect ratio of SAC is decreased and SAC fail is reduced so that a process margin is secured. The semiconductor device includes a semiconductor substrate comprising an active region and a device isolation layer defining the active region, a conductive pattern formed on the semiconductor substrate, and a nitride layer formed on the semiconductor substrate perpendicularly to the conductive pattern. | 01-05-2012 |
20120001334 | Structure and Process for the Formation of TSVs - An integrated circuit structure includes a semiconductor substrate; an interconnect structure over the semiconductor substrate, wherein the interconnect structure comprises a top inter-metal dielectric (IMD); an opening penetrating the interconnect structure into the semiconductor substrate; a conductor in the opening; and an isolation layer having a vertical portion and a horizontal portion physically connected to each other. The vertical portion is on sidewalls of the opening. The horizontal portion is directly over the interconnect structure. The integrated circuit structure is free from passivation layers vertically between the top IMD and the horizontal portion of the isolation layer. | 01-05-2012 |
20120007239 | METHODS, DEVICES, AND MATERIALS FOR METALLIZATION - A method of making an electronic device which in one embodiment comprises providing a substrate, electrolessly depositing a barrier metal at least on portions of the substrate, and using wet chemistry such as electroless deposition to deposit a substantially gold-free wetting layer having solder wettability onto the barrier metal. An electronic device which in one embodiment comprises a metallization stack. The metallization stack comprises a barrier metal deposited electrolessly and a substantially gold-free wetting layer deposited on the barrier metal, and the wetting layer is wettable by solder. | 01-12-2012 |
20120007240 | METAL WIRE FOR A SEMICONDUCTOR DEVICE FORMED WITH A METAL LAYER WITHOUT VOIDS THEREIN AND A METHOD FOR FORMING THE SAME - A metal wiring of a semiconductor device includes a semiconductor substrate; an insulating layer provided with a damascene pattern formed over the semiconductor substrate; a diffusion barrier layer which contains a RuO | 01-12-2012 |
20120007241 | SEMICONDUCTOR DEVICE - The present teachings provides a semiconductor device which has a semiconductor substrate, and a lower electrode including a first layer in contact with a lower surface of the semiconductor substrate, a second layer in contact with a lower surface of the first layer, and a third layer stacked at a position farther from the semiconductor substrate than the second layer, wherein the first layer is an aluminum layer containing silicon, the second layer is a layer including silicon as a primary component, and the third layer is a solder joint layer. | 01-12-2012 |
20120007242 | INTERCONNECTS HAVING SEALING STRUCTURES TO ENABLE SELECTIVE METAL CAPPING LAYERS - Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect. | 01-12-2012 |
20120013008 | METALLIZATION PROCESSES, MIXTURES, AND ELECTRONIC DEVICES - One aspect of the present invention is a method of processing a substrate. In one embodiment, the method comprises forming an electrical conductor on or in the substrate by providing a mixture comprising metal particles and an electroless deposition solution and electrolessly depositing a metal matrix and co-depositing the metal particles. In another embodiment, the method comprises forming an electrical conductor on or in the substrate by providing a mixture comprising metal particles and an electrochemical plating solution and electrochemically plating a metal matrix and co-depositing the metal particles. Another aspect of the present invention is a mixture for the formation of an electrical conductor on or in a substrate. Another aspect of the present invention is an electronic device. | 01-19-2012 |
20120013009 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - The present invention discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a semiconductor substrate, a local interconnect structure connected to the semiconductor substrate, and at least one via stack structure electrically connected to the local interconnect structure, wherein the at least one via stack structure comprises a via having an upper via and a lower via, the width of the upper via being greater than that of the lower via; a via spacer formed closely adjacent to the inner walls of the lower via; an insulation layer covering the surfaces of the via and the via spacer; a conductive plug formed within the space surrounded by the insulation layer, and electrically connected to the local interconnect structure. The present invention is applicable to manufacture of a via stack in the filed of manufacturing semiconductor. | 01-19-2012 |
20120018888 | SEMICONDUCTOR DEVICES AND METHOD OF FORMING THE SAME - A method of forming semiconductor devices includes stacking an insulating layer and a polysilicon layer over a semiconductor substrate, forming a region where nitrogen (N) is scattered in a place adjacent to a surface of the polysilicon layer within the polysilicon layer using a plasma method, and depositing a doped polysilicon layer on the polysilicon layer including the region where nitrogen (N) is scattered. | 01-26-2012 |
20120025380 | MANGANESE OXIDE FILM FORMING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - There is provided a manganese oxide film forming method capable of forming a manganese oxide film having high adhesivity to Cu. In the manganese oxide film forming method, a manganese oxide film is formed on an oxide by supplying a manganese-containing gas onto the oxide. A film forming temperature for forming the manganese oxide film is set to be equal to or higher than about 100° C. and lower than about 400° C. | 02-02-2012 |
20120025381 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - An interlayer insulating film containing oxygen and carbon is formed on a semiconductor substrate. A groove is formed in the interlayer insulating film. An auxiliary film containing predetermined first and second metallic elements is formed on a bottom surface and a sidewall of the formed groove. Then, an interconnect body layer containing copper is formed to fill the groove. By performing a thermal treatment, a first barrier film containing a compound of the first metallic element and an oxygen element of the interlayer insulating film, and a second barrier film containing a compound of the second metallic element and carbon element of the interlayer insulating film are formed on the interlayer insulating film on the bottom surface and the sidewall of the groove. | 02-02-2012 |
20120025382 | Devices Formed With Dual Damascene Process - Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask. | 02-02-2012 |
20120032332 | Semiconductor Devices Having A Diffusion Barrier Layer and Methods of Manufacturing the Same - Methods of manufacturing a semiconductor device include forming a gate insulation layer including a high-k dielectric material on a substrate that is divided into a first region and a second region; forming a diffusion barrier layer including a first metal on a second portion of the gate insulation layer in the second region; forming a diffusion layer on the gate insulation layer and the diffusion barrier layer; and diffusing an element of the diffusion layer into a first portion of the gate insulation layer in the first region. | 02-09-2012 |
20120038049 | COMPONENT HAVING A VIA, AND A METHOD FOR MANUFACTURING SUCH A COMPONENT - A component including a via for electrical connection between a first and a second plane of a substrate is provided. The substrate has a borehole having an inner wall that is coated with a conductive layer made of an electrically conductive material, an intermediate layer being disposed between the inner wall and the conductive layer. The intermediate layer includes electrically insulating SiC. | 02-16-2012 |
20120043657 | METHOD FOR FABRICATING CONDUCTIVE LINES - Methods for fabricating conductive metal lines of a semiconductor device are described herein. In one embodiment, such a method may comprise depositing a conductive material over a substrate, and depositing a first barrier layer on the conductive layer. Such a method may also comprise patterning a mask on the first barrier layer, the pattern comprising a layout of the conductive lines. Such an exemplary method may also comprise etching the conductive material and the first barrier layer using the patterned mask to form the conductive lines. In addition, a low temperature post-flow may be performed on the structure. The method may also include depositing a dielectric material over and between the patterned conductive lines. | 02-23-2012 |
20120043658 | Semiconductor Constructions; And Methods For Providing Electrically Conductive Material Within Openings - Some embodiments include methods for depositing copper-containing material utilizing physical vapor deposition of the copper-containing material while keeping a temperature of the deposited copper-containing material at greater than 100° C. Some embodiments include methods in which openings are lined with a metal-containing composition, copper-containing material is physical vapor deposited over the metal-containing composition while a temperature of the copper-containing material is no greater than about 0° C., and the copper-containing material is then annealed while the copper-containing material is at a temperature in a range of from about 180° C. to about 250° C. Some embodiments include methods in which openings are lined with a composition containing metal and nitrogen, and the lined openings are at least partially filled with copper-containing material. Some embodiments include semiconductor constructions having a metal nitride liner along sidewall peripheries of an opening, and having copper-containing material within the opening and directly against the metal nitride liner. | 02-23-2012 |
20120043659 | INTERCONNECTS WITH IMPROVED TDDB - A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A first upper etch stop layer is formed on the dielectric layer. The first upper etch stop layer includes a first dielectric material. The dielectric layer and first upper etch stop layer are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The interconnect and first upper etch stop layer have coplanar top surfaces. A second upper etch stop layer is formed over the coplanar top surfaces. The second upper etch stop layer includes a second material having sufficient adhesion with the first material to reduce diffusion of the conductive material. | 02-23-2012 |
20120056323 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The application discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises: a semiconductor substrate comprising a first surface and a second surface opposite to each other; and a silicon via formed through the semiconductor substrate, wherein the silicon via comprises a first via formed through the first surface; and a second via formed through the second surface and electrically connected with the first via, wherein the first and second vias are formed individually. Embodiments of the invention are applicable to the manufacture of a 3D integrated circuit. | 03-08-2012 |
20120056324 | SUBSTRATE FOR A MICROELECTRONIC PACKAGE AND METHOD OF FABRICATING THEREOF - Substrates having molded dielectric layers and methods of fabricating such substrates are disclosed. The substrates may advantageously be used in microelectronic assemblies having high routing density. | 03-08-2012 |
20120056325 | METHODS OF FABRICATING ELECTRONIC DEVICES USING DIRECT COPPER PLATING - The present invention relates to methods and structures for the metallization of semiconductor devices. One aspect of the present invention is a method of forming a semiconductor device having copper metallization. In one embodiment, the method includes providing a patterned wafer having a diffusion barrier for copper; depositing a copperless seed layer on the diffusion barrier effective for electrochemical deposition of gapfill copper. The seed layer is formed by a conformal deposition process and by a nonconformal deposition process. The method further includes electroplating copper gapfill onto the seed layer. Another aspect of the invention includes electronic devices made using methods and structures according to embodiments of the present invention. | 03-08-2012 |
20120056326 | TITANIUM NITRIDE FILMS - The use of a monolayer or partial monolayer sequencing process to form conductive titanium nitride produces a reliable structure for use in a variety of electronic devices. In an embodiment, a structure can be formed by using ammonia and carbon monoxide reactant materials with respect to a titanium-containing precursor exposed to a substrate. Such a TiN layer has a number of uses including, but not limited to, use as a diffusion barrier underneath another conductor or use as an electro-migration preventing layer on top of a conductor. Such deposited TiN material may have characteristics associated with a low resistivity, a smooth topology, high deposition rates, excellent step coverage, and electrical continuity. | 03-08-2012 |
20120061838 | BARRIER LAYER FORMATION FOR METAL INTERCONNECTS THROUGH ENHANCED IMPURITY DIFFUSION - A method of forming a barrier layer for metal interconnects of an integrated circuit device includes forming a first cap layer over a top surface of a conductive line of the integrated circuit device in a manner that facilitates a controllable dose of oxygen provided to the top surface of the conductive line, the conductive line comprising a metal formed over a seed layer that is an impurity alloy of the metal; and annealing the integrated circuit device so as to combine diffused impurity atoms of the seed layer with the controllable dose of oxygen, thereby forming an impurity oxide layer at an interface between the first cap layer and the top surface of the conductive line. | 03-15-2012 |
20120061839 | METAL CAP LAYER WITH ENHANCED ETCH RESISTIVITY FOR COPPER-BASED METAL REGIONS IN SEMICONDUCTOR DEVICES - During the fabrication of sophisticated metallization systems of semiconductor devices, material deterioration of conductive cap layers may be significantly reduced by providing a noble metal on exposed surface areas after the patterning of the corresponding via openings. Hence, well-established wet chemical etch chemistries may be used while not unduly contributing to process complexity. | 03-15-2012 |
20120061840 | DAMASCENE INTERCONNECTION STRUCTURE AND DUAL DAMASCENE PROCESS THEREOF - A dual damascene structure is disclosed. The dual damascene structure includes: a substrate comprising thereon a base dielectric layer and a lower wiring layer inlaid in the base dielectric layer; a dielectric layer on the substrate; a via opening in the dielectric layer, wherein the via opening misaligns with the lower wiring layer thus exposing a portion of the lower wiring layer and a portion of the base dielectric layer, wherein the via opening comprises a bottom including a recessed area; a barrier layer lining interior surface of the via opening and covers the exposed lower wiring layer and the base dielectric layer, wherein only the barrier layer fills the recessed area; and a copper layer filling the via opening on the barrier layer. | 03-15-2012 |
20120068343 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a semiconductor substrate, an interlayer dielectric film, a contact hole, a contact plug and a nickel silicide film. The semiconductor substrate includes silicon. The interlayer dielectric film is formed on the semiconductor substrate. The contact hole is formed in the interlayer dielectric film. A contact plug is formed within the contact hole. A nickel silicide film is formed on a bottom part of the contact hole and electrically connected to the contact plug. A position of an interface between the nickel silicide and the contact plug is higher than a position of an interface between the semiconductor substrate and the interlayer dielectric film. | 03-22-2012 |
20120074570 | Method for Forming a Through Via in a Semiconductor Element and Semiconductor Element Comprising the Same - A method for forming a through via in a semiconductor element includes providing a semiconductor element having electronic circuitry integrated on the main side thereof. The semiconductor element further includes an etch stop layer and a conductive region, wherein the conductive region is arranged between the etch stop layer and the main side of the semiconductor element. The method also includes selectively etching a through via from a backside of the semiconductor element, opposite to the main side of the semiconductor element, to the etch stop layer and removing at least partly the etch stop layer, so that the conductive region is exposed to the backside and filling at least partly the through via with a conductive material, wherein the conductive material is electrically isolated from the semiconductor element. | 03-29-2012 |
20120074571 | METHODS AND ARCHITECTURES FOR BOTTOMLESS INTERCONNECT VIAS - An apparatus includes an interconnect in a recess. The interconnect includes a liner structure and the liner structure in the recess. The liner structure is breached at the recess bottom feature and a bottom interconnect makes a single-interface contact with a subsequent interconnect through the breach. | 03-29-2012 |
20120074572 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING SAME - One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a separation layer over the barrier layer; forming a conductive layer over the separation layer; and wet etching the conductive layer. | 03-29-2012 |
20120074573 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING SAME - One or more embodiments relate to a method of forming a semiconductor device, comprising: forming a structure, the structure including at least a first element and a second element; and forming a passivation layer over the structure, the passivation layer including at least the first element and the second element, the first element and the second element of the passivation layer coming from the structure. | 03-29-2012 |
20120074574 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING SAME - One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the barrier layer; forming an inhibitor layer over the seed layer; removing a portion of said inhibitor layer to expose a portion of the seed layer; and selectively depositing a fill layer on the exposed seed layer. | 03-29-2012 |
20120074575 | COPPER LINE HAVING SELF-ASSEMBLED MONOLAYER FOR ULSI SEMICONDUCTOR DEVICES, AND A METHOD OF FORMING SAME - A copper line having self assembled monolayer for use in ULSI semiconductor devices and methods of making the same are presented. The copper line includes an interlayer dielectric, a self-assembled monolayer, catalytic particles on the monolayer, and a copper layer on the monolayer with the catalytic particles. The method includes the steps of forming an interlayer dielectric on a semiconductor substrate having a metal line forming region; forming a self-assembled monolayer on the metal line forming region; adsorbing catalytic particles on the self-assembled monolayer; forming using an electroless process a copper seed layer on the self-assembled monolayer having the catalytic particles adsorbed thereto; and forming a copper layer on the copper seed layer to fill in the metal line forming region. | 03-29-2012 |
20120080791 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING SAME - One or more embodiments relate to a method of forming an electronic device, comprising: providing a workpiece; forming a first barrier layer over the workpiece; forming an intermediate conductive layer over the first barrier layer; forming a second barrier layer over the intermediate conductive layer; forming a seed layer over the second barrier layer; removing a portion of the seed layer to leave a remaining portion of the seed layer and to expose a portion of the second barrier layer; and electroplating a fill layer on the remaining portion of the seed layer. | 04-05-2012 |
20120080792 | Metal Interconnection Structure and Method For Forming Metal Interlayer Via and Metal Interconnection Line - There is provided a method for forming a metal interlayer via, comprising: forming a seed layer on a first dielectric layer and a first metal layer embedded in the first dielectric layer; forming a mask pattern on the seed layer to expose a portion of the seed layer covering some of the first metal layer; growing a second metal layer on the exposed portion of the seed layer; removing the mask pattern and a portion of the seed layer carrying the mask pattern to expose side walls of the second metal layer, a portion of the first metal layer and the first dielectric layer; forming an insulating barrier layer on the side walls, the portion of the first metal layer and the first dielectric layer. There is also provided a method for forming a metal interconnection line. Both of them can suppress the occurrence of voids. There is further provided a metal interconnection structure comprising a contact plug, a via and a metal interconnection line, wherein the via is formed on the metal interconnection line, the metal gate and/or the contact plug. | 04-05-2012 |
20120080793 | SUBTRACTIVE PATTERNING TO DEFINE CIRCUIT COMPONENTS - Certain embodiments pertain to local interconnects formed by subtractive patterning of blanket layer of tungsten or other conductive material. The grain sizes of tungsten or other deposited metal can be grown to relatively large dimensions, which results in increased electrical conductivity due to, e.g., reduced electron scattering at grain boundaries as electrons travel from one grain to the next during conduction. | 04-05-2012 |
20120080794 | METHOD FOR PRODUCING A METALLIZATION HAVING TWO MULTIPLE ALTERNATING METALLIZATION LAYERS FOR AT LEAST ONE CONTACT PAD AND SEMICONDUCTOR WAFER HAVING SAID METALLIZATION FOR AT LEAST ONE CONTACT PAD - The invention relates to a method for producing a metallization for at least one contact pad and a semiconductor wafer having metallization for at least one contact pad. The invention relates to a metallization (and a semiconductor wafer having corresponding metallization) and to a method for the production thereof that first of all can be produced by means of physical gas phase separation (dry separation) and secondly ensures sufficient adhesion of a lot bump. The method for producing a metallization ( | 04-05-2012 |
20120091588 | BARRIER LAYER, FILM FORMING METHOD, AND PROCESSING SYSTEM - There is provided a film forming method for forming a film on a target object having thereon an insulating layer | 04-19-2012 |
20120104612 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device has: a semiconductor substrate; and an upper surface electrode laminated on an upper surface of the semiconductor substrate, wherein at least one portion of the upper surface electrode includes a first layer formed on an upper surface side of the semiconductor substrate, a second layer formed on an upper surface side of the first layer, a third layer in contact with the upper surface of the second layer, and a fourth layer formed on an upper surface side of the third layer. The first layer is a barrier metal layer. The second layer is an Al (aluminum) layer. The third layer is one of an Al—Si (aluminum-silicon alloy) layer, an Al—Cu (aluminum-copper alloy) layer and an Al—Si—Cu (aluminum-silicon-copper alloy) layer. The fourth layer is a solder joint layer. | 05-03-2012 |
20120104613 | BONDING WIRE FOR SEMICONDUCTOR DEVICE - It is an object of the present invention to provide a copper-based bonding wire whose material cost is low, having excellent ball bondability, reliability in a heat cycle test or reflow test, and storage life, enabling an application to thinning of a wire used for fine pitch connection. The bonding wire includes a core material having copper as a main component and an outer layer which is provided on the core material and contains a metal M and copper, in which the metal M differs from the core material in one or both of components and composition. The outer layer is 0.021 to 0.12 μm in thickness. | 05-03-2012 |
20120112347 | FLEXIBLE ELECTRONIC DEVICES AND RELATED METHODS - A packaged electronic device includes a flexible circuit structure and a die. The flexible circuit structure includes a first structural layer and electrical conductors. The die is bonded to the flexible circuit structure by a flexible attachment layer. The die includes interconnects in electrical contact with die circuitry and extending through the die, through the flexible attachment layer, and into electrical contact with respective electrical conductors at first ends. A flexible second structural layer is disposed on the die and exposed portions of the electrical conductors, wherein the die and the electrical conductors are encapsulated by the first structural layer and the second structural layer. The first structural layer and/or the second structural layer include a plurality of openings defining respective exposed areas on the electrical conductors at second ends. | 05-10-2012 |
20120119366 | ELECTROMIGRATION RESISTANT VIA-TO-LINE INTERCONNECT - A liner-to-liner direct contact is formed between an upper metallic liner of a conductive via and a lower metallic liner of a metal line below. The liner-to-liner contact impedes abrupt electromigration failures and enhances electromigration resistance of the metal interconnect structure. The at least one dielectric material portion may include a plurality of dielectric material portions arranged to insure direct contact of between the upper metallic liner and the lower metallic liner. Alternatively, the at least one dielectric material portion may comprise a single dielectric portion of which the area has a sufficient lateral overlap with the area of the conductive via to insure that a liner-to-liner direct contact is formed within the range of allowed lithographic overlay variations. | 05-17-2012 |
20120126409 | SEED LAYERS FOR METALLIC INTERCONNECTS AND PRODUCTS - A method is disclosed for depositing multiple seed layers for metallic interconnects over a substrate, the substrate includes a patterned insulating layer which comprises an opening surrounded by a field, said opening has sidewalls and top corners, and the method including: depositing a continuous seed layer over the sidewalls, using a first set of deposition parameters; and depositing another seed layer over the substrate, including inside the at least one opening and over a portion of said field, using a second set of deposition parameters, wherein: the second set of deposition parameters includes one deposition parameter which is different from any parameters in the first set, or whose value is different in the first and second sets; the continuous seed layer has a thickness in a range from about 20 Å to not more than 250 Å over the field; and the combined seed layers leave sufficient room for electroplating inside the opening. | 05-24-2012 |
20120133044 | METAL CONTAINING SACRIFICE MATERIAL AND METHOD OF DAMASCENE WIRING FORMATION - According to one embodiment, a via and trench are formed in a semiconductor structure. The via and the trench are suitable for having a metal-based wire placed therein by damascene, dual damascene, plating and other suitable techniques. The via is etched into a dielectric layer of a semiconductor structure comprising a base cap layer, the dielectric layer formed over the base cap layer, and a hardmask formed over the dielectric layer. The via is filled with a sacrifice material, where the sacrifice material contains a metal or a metal compound, where the sacrifice material additionally forms a sacrifice layer over the hardmask layer. The sacrifice material placed in the via does not contain a material or film containing a Si—O bond. The sacrifice material is used as a support for a photomask that is placed over the sacrifice layer, where the photomask is developed to have a trench pattern formed therein. Then, one or more of the hardmask layer and the dielectric layer is etched with the trench pattern, and the sacrifice material and the sacrifice layer are removed by contact with a remover solution containing one or more selected from an acidic compound, water, a base compound, and an oxidant. | 05-31-2012 |
20120139113 | UNDERCUT-REPAIR OF BARRIER LAYER METALLURGY FOR SOLDER BUMPS AND METHODS THEREOF - A method of making a semiconductor structure includes patterning a barrier layer metallurgy (BLM) which forms an undercut beneath a solder material, and forming a repair material in the undercut and on the solder material. The method also includes removing the repair material from the solder material, and reflowing the solder material. | 06-07-2012 |
20120139114 | COPPER INTERCONNECT STRUCTURE HAVING A GRAPHENE CAP - A copper interconnect structure has an intrinsic graphene cap for improving back end of line (BEOL) reliability of the interconnect by reducing time-dependent dielectric breakdown (TDDB) failure and providing resistance to electromigration. Carbon atoms are selectively deposited onto a copper layer of the interconnect structure by a deposition process to form a graphene cap. The graphene cap increases the activation energy of the copper, thus allowing for higher current density and improved resistance to electromigration of the copper. By depositing the graphene cap on the copper, the dielectric regions remain free of conductors and, thus, current leakage within the interlayer dielectric regions is reduced, thereby reducing TDDB failure and increasing the lifespan of the interconnect structure. The reduction of TDDB failure and improved resistance to electromigration improves BEOL reliability of the copper interconnect structure. | 06-07-2012 |
20120139115 | Integrated Circuit Device - In an integrated circuit device and method of manufacturing the same, a conductive structure and a wiring structure are sequentially arranged on a substrate having a through hole. The conductive structure includes semiconductor chips and a contact structure. The wiring structure includes a metal line through which signals are transferred to the conductive structure. A penetration electrode is positioned in the through hole. The penetration electrode includes a conductive plug electrically connected to one of the conductive structure and the wiring structure, and a pair of a base layer and a gap interposed between the conductive plug and a sidewall of the through-hole, thereby enclosing the conductive plug. The base layer also includes a product of a solid reaction of reactants of which diffusion speeds are different. Accordingly, the dielectric characteristics of the penetration electrode are improved by using the gap as a dielectric gap. | 06-07-2012 |
20120146223 | MOS DEVICE WITH MEMORY FUNCTION AND MANUFACTURING METHOD THEREOF - A manufacturing method of a MOS device with memory function is provided, which includes: providing a semiconductor substrate, a surface of the semiconductor substrate being covered by a first dielectric layer, a metal interconnect structure being formed in the first dielectric layer; forming a second dielectric layer overlying a surface of the first dielectric layer and the metal interconnect structure; forming an opening in the second dielectric layer, a bottom of the opening revealing the metal interconnect structure; forming an alloy layer at the bottom of the opening, material of the alloy layer containing copper and other metal; and performing a thermal treatment to the alloy layer and the metal interconnect structure to form, on the surface of the metal interconnect structure, a compound layer containing oxygen element. The compound layer containing oxygen element and the MOS device formed in the semiconductor substrate constitute a MOS device with memory function. The method provides a processing which has high controllability and improves the performance of devices. | 06-14-2012 |
20120146224 | Semiconductor having interconnects with improved mechanical properties by insertion of nanoparticles - In a BEOL process, UV radiation is used in a curing process of ultra low-k (ULK) dielectrics. This radiation penetrates through the ULK material and reaches the cap film underneath it. The interaction between the UV light and the film leads to a change the properties of the cap film. Of particular concern is the change in the stress state of the cap from compressive to tensile stress. This leads to a weaker dielectric-cap interface and mechanical failure of the ULK film. A layer of nanoparticles is inserted between the cap and the ULK film. The nanoparticles absorb the UV light before it can damage the cap film, thus maintaining the mechanical integrity of the ULK dielectric. | 06-14-2012 |
20120146225 | DAMASCENE STRUCTURE - A damascene structure includes a conductive layer, a first dielectric layer, a first barrier metal layer, a barrier layer, and a second barrier metal layer sequentially formed on the conductive layer. The first dielectric layer having a via therein. The barrier layer is comprised of a material different with that of the first barrier metal layer. A bottom of the barrier layer disposed on the via bottom is not punched through. The accomplished barrier layers will have lower resistivity on the via bottom in the first dielectric layer and they are capable of preventing copper atoms from diffusing into the dielectric layer. | 06-14-2012 |
20120153477 | METHODS FOR METAL PLATING AND RELATED DEVICES - Methods for plating metal over features of a semiconductor wafer and devices that can be formed by these methods are disclosed. One such method includes forming a barrier layer over the substrate using electroless plating and forming a copper layer over the barrier layer. In some implementations, the semiconductor wafer is a GaAs wafer. Alternatively or additionally, the feature over which metal is plated can be a through-wafer via. In some implementations, a seed layer over the barrier layer can be formed using electroless plating. | 06-21-2012 |
20120153478 | LINER LAYERS FOR METAL INTERCONNECTS - Electrical interconnects for integrated circuits and methods of fabrication of interconnects are provided. Devices are provided comprising copper interconnects having metallic liner layers comprising silver and a second component, such as, lanthanum, titanium, tungsten, zirconium, antimony, or calcium. Methods include providing a substrate having a trench or via formed therein, forming a silver alloy layer, comprising silver and a second component selected from the group consisting of lanthanum, titanium, tungsten, zirconium, antimony, and calcium, onto surfaces of the feature, depositing a copper seed layer, and depositing copper into the feature. | 06-21-2012 |
20120153479 | Performance Enhancement in Metallization Systems of Microstructure Devices by Incorporating an Intermediate Barrier Layer - In metallization systems of complex semiconductor devices, an intermediate interface layer may be incorporated into the interconnect structures in order to provide superior electromigration performance. To this end, the deposition of the actual fill material may be interrupted at an appropriate stage and the interface layer may be formed, for instance, by deposition, surface treatment and the like, followed by the further deposition of the actual fill metal. In this manner, the grain size issue, in particular at lower portions of the scaled inter-connect features, may be addressed. | 06-21-2012 |
20120153480 | Metallization Systems of Semiconductor Devices Comprising a Copper/Silicon Compound as a Barrier Material - In sophisticated metallization systems of semiconductor devices, a sensitive core metal, such as copper, may be efficiently confined by a conductive barrier material comprising a copper/silicon compound, such as a copper silicide, which may provide superior electromigration behavior and higher electrical conductivity compared to conventionally used tantalum/tantalum nitride barrier systems. | 06-21-2012 |
20120153481 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed, which can prevent a short-circuit between a bit line contact plug and a storage node contact plug, resulting in improved semiconductor device characteristics. A method for manufacturing a semiconductor device includes: forming a bit line contact hole from which an active region is protruded, by etching a semiconductor substrate; forming a conductive material over the semiconductor substrate including the bit line contact hole; etching the conductive material to form a bit line contact plug and a bit line, each of which has a smaller width than the bit line contact hole; and forming a spacer insulation film over the entire surface of the semiconductor substrate including the bit line contact hole, the bit line contact plug, and the bit line. | 06-21-2012 |
20120161318 | MULTILAYER DIELECTRIC MEMORY DEVICE - A memory device has multiple dielectric barrier regions. A memory device has multiple barrier regions that provide higher or lower current-voltage slope compared to a memory device having a single barrier region. The device also has electrode regions that provide further control over the current-voltage relationship. | 06-28-2012 |
20120161319 | BALL GRID ARRAY METHOD AND STRUCTURE - A process for making an integrated circuit, a wafer level integrated circuit package or an embedded wafer level package includes forming copper contact pads on a substrate or substructure. The substructure may include devices and the contact pads may be used for forming electrical couplings to the devices. For example, copper plating may be applied to a substructure and the copper plating etched to form copper contact pads on the substructure. An etching process may be applied to remove barrier layer material on the substructure, such as adjacent to the copper pads. For example, a hydrogen peroxide etch may be applied to remove titanium-tungsten from a surface of the substructure. The pads are again etched to remove barrier layer etchant, byproducts and/or oxide from the pads. Contamination control steps may be performed, such as quick-dump-and-rinse (QDR) and spin-rinse-and-dry (SRD) processing. | 06-28-2012 |
20120161320 | COBALT METAL BARRIER LAYERS - Electrical interconnects for integrated circuits and methods of fabrication of interconnects are provided. Devices are provided comprising copper interconnects having metal liner layers comprising cobalt and a metal selected from the group consisting of Ru, Pt, Ir, Pd, Re, or Rh. Devices having barrier layers comprising ruthenium and cobalt are provided. Methods include providing a substrate having a trench or via formed therein, forming a metal layer, the metal being selected from the group consisting of Ru, Pt, Ir, Pd, Re, and Rh, onto surfaces of the feature, depositing a copper seed layer comprising a cobalt dopant, and depositing copper into the feature. | 06-28-2012 |
20120161321 | SEMICONDUCTOR DEVICE CONTACTS - Techniques are disclosed for forming contacts in silicon semiconductor devices. In some embodiments, a transition layer forms a non-reactive interface with the silicon semiconductor contact surface. In some such cases, a conductive material provides the contacts and the material forming a non-reactive interface with the silicon surface. In other cases, a thin semiconducting or insulting layer provides the non-reactive interface with the silicon surface and is coupled to conductive material of the contacts. The techniques can be embodied, for instance, in planar or non-planar (e.g., double-gate and tri-gate FinFETs) transistor devices. | 06-28-2012 |
20120161322 | ELECTRONIC COMPONENT MANUFACTURING METHOD INCLUDING STEP OF EMBEDDING METAL FILM - The present invention provides an electronic component manufacturing method including a step of embedding a metal film. An embodiment of the present invention includes a first step of depositing a barrier layer containing titanium nitride on an object to be processed on which a concave part is formed and a second step of filling a low-melting-point metal directly on the barrier layer under a temperature condition allowing the low-melting-point metal to flow, by a PCM sputtering method while forming a magnetic field by a magnet unit including plural magnets which are arranged at grid points of a polygonal grid so as to have different polarities between the neighboring magnets. | 06-28-2012 |
20120168949 | SEMICONDUCTOR DEVICE WITH A LINE AND METHOD OF FABRICATION THEREOF - A semiconductor device includes an interlayer insulation film, an underlying line provided in the interlayer insulation film, a liner film overlying the interlayer insulation film, an interlayer insulation film overlying the liner film. The underlying line has a lower hole and the liner film and the interlayer insulation film have an upper hole communicating with the lower hole, and the lower hole is larger in diameter than the upper hole. The semiconductor device further includes a conductive film provided at an internal wall surface of the lower hole, a barrier metal provided along an internal wall surface of the upper hole, and a Cu film filling the upper and lower holes. The conductive film contains a substance identical to a substance of the barrier metal. A highly reliable semiconductor device can thus be obtained. | 07-05-2012 |
20120175774 | WARPAGE CONTROL FEATURES ON THE BOTTOMSIDE OF TSV DIE LATERAL TO PROTRUDING BOTTOMSIDE TIPS - A through substrate via (TSV) die includes a substrate including a topside semiconductor surface having active circuitry. The die includes a plurality of TSVs that each include an inner metal core that extend from the topside semiconductor surface to protruding TSV tips that extend out from the bottomside surface. A metal cap is on the protruding TSV tips that includes at least one metal layer that has a metal that is not in the inner metal core. A plurality of protruding warpage control features are on the bottomside surface lateral to the protruding TSV tips, wherein the plurality of protruding warpage control features do not have the protruding TSV tips thereunder. The plurality of protruding warpage control features can include the same metal layer(s) used for the metal cap. | 07-12-2012 |
20120175775 | INTEGRATED CIRCUIT LINE WITH ELECTROMIGRATION BARRIERS - An integrated circuit comprising an electromigration barrier includes a line, the line comprising a first conductive material, the line further comprising a plurality of line segments separated by one or more electromigration barriers, wherein the one or more electromigration barriers comprise a second conductive material that isolates electromigration effects within individual segments of the line. | 07-12-2012 |
20120175776 | ELECTROLESS CU PLATING FOR ENHANCED SELF-FORMING BARRIER LAYERS - Methods and an apparatus are described for an integrated circuit within which an electroless Cu plated layer having an oxygen content is formed on the top of a seed layer comprising Cu and Mn. The integrated circuit is then exposed to a sufficient high temperature to cause the self-formation of a MnSiOx barrier layer. | 07-12-2012 |
20120181692 | HYBRID CONTACT STRUCTURE WITH LOW ASPECT RATIO CONTACTS IN A SEMICONDUCTOR DEVICE - In sophisticated semiconductor devices, superior contact resistivity may be accomplished for a given contact configuration by providing hybrid contact elements, at least a portion of which may be comprised of a highly conductive material, such as copper. To this end, a well-established contact material, such as tungsten, may be used as buffer material in order to preserve integrity of sensitive device areas upon depositing the highly conductive metal. | 07-19-2012 |
20120181693 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device may include an upper interconnection on a substrate and an anti-reflection pattern disposed on the upper interconnection. The anti-reflection pattern may include a compound including a metal, carbon and nitrogen. | 07-19-2012 |
20120181694 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The semiconductor device includes an interlayer insulating film, a wiring provided in the interlayer insulating film, and a SiN film provided over the interlayer insulating film and over the wiring. The peak positions of Si—N bonds of the SiN film, which are measured by FTIR, are within the range of 845 cm | 07-19-2012 |
20120181695 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, an oxygen-containing insulating film disposed above the above-described semiconductor substrate, a concave portion disposed in the above-described insulating film, a copper-containing first film disposed on an inner wall of the above-described concave portion, a copper-containing second film disposed above the above-described first film and filled in the above-described concave portion, and a manganese-containing oxide layer disposed between the above-described first film and the above-described second film. Furthermore, a copper interconnection is formed on the above-described structure by an electroplating method and, subsequently, a short-time heat treatment is conducted at a temperature of 80° C. to 120° C. | 07-19-2012 |
20120187563 | PLANARIZATION METHOD APPLIED IN PROCESS OF MANUFACTURING SEMICONDUCTOR COMPONENT - A planarization method of manufacturing a semiconductor component is provided. A dielectric layer is formed above a substrate and defines a trench therein. A barrier layer and a metal layer are formed in sequence in the trench. A first planarization process is applied to the metal layer by using a first reactant so that a portion of the metal layer is removed. An etching rate of the first reactant to the metal layer is greater than that of the first reactant to the barrier layer. A second planarization process is applied to the barrier layer and the metal layer by using a second reactant so that a portion of the barrier layer and the metal layer are removed to expose the dielectric layer. An etching rate of the second reactant to the barrier layer is greater than that of the second reactant to the metal layer. | 07-26-2012 |
20120193793 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - According to an embodiment, a semiconductor device includes a first wiring member, an opening portion and an electrode terminal portion. The first wiring member is provided on a first interlayer insulating film on a semiconductor substrate and used as a wiring layer. The opening portion is provided in a second interlayer insulating film on the first wiring member. The electrode terminal portion is provided on the opening portion and the second interlayer insulating film around the opening portion. In the electrode terminal portion, a barrier metal film in contact with the first wiring member, a seed metal film and a second wiring member are stacked and thus formed in such a manner as to cover the opening portion, and a coating metal film is formed on an upper portion and a side surface of the second wiring member. | 08-02-2012 |
20120193794 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and methods of fabricating the same, wherein insulation layers are interposed to sequentially dispose the semiconductor device on a semiconductor substrate. The semiconductor device includes a first conductive plate, a second conductive plate, a third conductive plate, and a fourth conductive plate. At least two of the first, second, third and fourth conductive plates are electrically connected and constitute at least two capacitors. | 08-02-2012 |
20120199976 | INTERCONNECT STRUCTURE HAVING A VIA WITH A VIA GOUGING FEATURE AND DIELECTRIC LINER SIDEWALLS FOR BEOL INTEGRATION - An interconnect structure including a lower interconnect level with a first dielectric layer having a first conductive material embedded therein; a dielectric capping layer located on the first dielectric layer and some portions of the first conductive material; an upper interconnect level including a second dielectric layer having at least one via opening filled with a second conductive material and at least one overlying line opening filled with the second conductive material disposed therein, wherein the at least one via opening is in contact with the first conductive material in the lower interconnect level by a via gouging feature; a dielectric liner on sidewalls of the at least one via opening; and a first diffusion barrier layer on sidewalls and a bottom of both the at least one via opening and the at least one overlying line opening. A method of forming the interconnect structure is also provided. | 08-09-2012 |
20120205804 | METHOD TO FABRICATE COPPER WIRING STRUCTURES AND STRUCTURES FORMED TEHREBY - Techniques formation of high purity copper (Cu)-filled lines and vias are provided. In one aspect, a method of fabricating lines and vias filled with high purity copper with is provided. The method includes the following steps. A via is etched in a dielectric. The via is lined with a diffusion barrier. A thin ruthenium (Ru) layer is conformally deposited onto the diffusion barrier. A Cu layer is deposited on the Ru layer by a sputtering process. A reflow anneal is performed to eliminate voids in the lines and vias. | 08-16-2012 |
20120205805 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first interlayer dielectric layer formed over a semiconductor substrate, contact holes formed to penetrate the first interlayer dielectric layer, contact plugs formed within the contact holes, respectively, and spacers formed to partially cover upper sidewalk of the contact plugs within the contact holes. | 08-16-2012 |
20120205806 | INTEGRATED CIRCUIT SYSTEM WITH THROUGH SILICON VIA AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: providing a substrate including an active device; forming a through-silicon-via into the substrate; forming an insulation layer over the through-silicon-via to protect the through-silicon-via; forming a contact to the active device after forming the insulation layer; and removing the insulation layer. | 08-16-2012 |
20120205807 | DEVICE WITH POST-CONTACT BACK END OF LINE THROUGH-HOLE VIA INTEGRATION - Presented are device structures and methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention. | 08-16-2012 |
20120211890 | METHOD FOR FORMING METAL THIN FILM, SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A metal thin film forming method includes depositing a Ti film on an insulating film formed on a substrate and depositing a Co film on the Ti film. The film forming method further includes modifying a laminated film of the Ti film and the Co film on the insulating film to a metal thin film containing Co | 08-23-2012 |
20120217640 | Semiconductor Device and Method of Forming Bump Structure with Insulating Buffer Layer to Reduce Stress on Semiconductor Wafer - A semiconductor wafer has a plurality of semiconductor die with contact pads for electrical interconnect. An insulating layer is formed over the semiconductor wafer. A bump structure is formed over the contact pads. The bump structure has a buffer layer formed over the insulating layer and contact pad. A portion of the buffer layer is removed to expose the contact pad and an outer portion of the insulating layer. A UBM layer is formed over the buffer layer and contact pad. The UBM layer follows a contour of the buffer layer and contact pad. A ring-shaped conductive pillar is formed over the UBM layer using a patterned photoresist layer filled with electrically conductive material. A conductive barrier layer is formed over the ring-shaped conductive pillar. A bump is formed over the conductive barrier layer. The buffer layer reduces thermal and mechanical stress on the bump and contact pad. | 08-30-2012 |
20120228771 | SEMICONDUCTOR INTERCONNECT STRUCTURE WITH MULTI-LAYERED SEED LAYER PROVIDING ENHANCED RELIABILITY AND MINIMIZING ELECTROMIGRATION - An interconnect structure and method for forming a multi-layered seed layer for semiconductor interconnections are disclosed. Specifically, the method and structure involves utilizing sequential catalytic chemical vapor deposition, which is followed by annealing, to form the multi-layered seed layer of an interconnect structure. The multi-layered seed layer will improve electromigration resistance, decrease void formation, and enhance reliability of ultra-large-scale integration (ULSI) chips. | 09-13-2012 |
20120228772 | Diode Array and Method for Producing a Diode Array - The present invention relates to a diode arrangement ( | 09-13-2012 |
20120235299 | SEMICONDUCTOR DEVICE CONTACT STRUCTURES AND METHODS FOR MAKING THE SAME - A semiconductor contact structure and method provide contact structures that extend through a dielectric material and provide contact to multiple different subjacent materials including a silicide material and a non-silicide material such as doped silicon. The contact structures includes a lower composite layer formed using a multi-step ionized metal plasma (IMP) deposition operation. A lower IMP film is formed at a high AC bias power followed by the formation of an upper IMP film at a lower AC bias power. The composite layer may be formed of titanium. A further layer is formed as a liner over the composite layer and the liner layer may advantageously be formed using CVD and may be TiN. A conductive plug material such as tungsten or copper fills the contact openings. | 09-20-2012 |
20120235300 | SEMICONDUCTOR HAVING A HIGH ASPECT RATIO VIA - The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having via sidewall surfaces defined by a semiconductor substrate. The via sidewall surfaces have a first portion and a second portion. A conductive layer is disposed in the via on the first portion of the via sidewall surfaces, and a dielectric layer is disposed on the second portion of the via sidewall surfaces. The dielectric layer is disposed between the second portion of the via sidewall surfaces and the conductive layer. In an example, the dielectric layer is an oxide layer. | 09-20-2012 |
20120241960 | SUBSTRATE FOR A MICROELECTRONIC PACKAGE AND METHOD OF FABRICATING THEREOF - Substrates having molded dielectric layers and methods of fabricating such substrates are disclosed. The substrates may advantageously be used in microelectronic assemblies having high routing density. | 09-27-2012 |
20120248608 | SELF-FORMING, SELF-ALIGNED BARRIERS FOR BACK-END INTERCONNECTS AND METHODS OF MAKING SAME - Processes of forming an insulated wire into an interlayer dielectric layer (ILD) of a back-end metallization includes thermally treating a metallic barrier precursor under conditions to cause at least one alloying element in the barrier precursor to form a dielectric barrier between the wire and the ILD. The dielectric barrier is therefore a self-forming, self-aligned barrier. Thermal processing is done under conditions to cause the at least one alloying element to migrate from a zone of higher concentration thereof to a zone of lower concentration thereof to further form the dielectric barrier. Various apparatus are made by the process. | 10-04-2012 |
20120248609 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An object of the invention is to fully fill a wiring material in via holes formed in a low-hardness interlayer insulating film and a high-hardness interlayer insulating film, respectively, upon forming a Cu wiring in interlayer insulating films by using the dual damascene process. According to the invention, a second interlayer insulating film has therein both a wiring trench and a via hole. The via hole has, at the opening portion thereof, a recess portion having a tapered cross-sectional shape. It is formed by causing the second interlayer insulating film to retreat obliquely downward. The diameter of the opening portion of the via hole therefore becomes greater than the diameter of a region below the opening portion and it becomes possible to fully fill a wiring material in the via hole even if the via hole has a fine diameter. | 10-04-2012 |
20120248610 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - According to one embodiment, a semiconductor memory device comprises: a semiconductor substrate; a first contact plug and a second contact plug on the semiconductor substrate; a first bit line being in contact with the first contact plug; and a second bit line on the second contact plug, wherein the first contact plug is in contact with a top surface of the first bit line and is electrically insulated from the second bit line, and a bottom surface of the second bit line is higher in height than the top surface of the first bit line. | 10-04-2012 |
20120248611 | INTERCONNECTING STRUCTURE PRODUCTION METHOD, AND INTERCONNECTING STRUCTURE - An interconnecting structure production method includes providing a substrate, forming a semiconductor layer on the substrate, forming a doped semiconductor layer on the semiconductor layer, the doped semiconductor layer containing a dopant, forming an oxide layer in a surface of the doped semiconductor layer by heating the surface of the doped semiconductor layer in atmosphere of an oxidizing gas with a water molecule contained therein, forming an alloy layer on the oxide layer, and forming an interconnecting layer on the alloy layer. | 10-04-2012 |
20120248612 | METHOD FOR THE PRODUCTION OF AN ELECTRONIC COMPONENT AND ELECTRONIC COMPONENT PRODUCED ACCORDING TO THIS METHOD - The invention relates to an electronic component having a GaAs semiconductor substrate (HS), semiconductor components (BE) being implemented on the front side thereof, and the back side thereof having a multilayer backside metallization (RM), wherein an advantageous construction of the layer sequence of the backside metallization is proposed, the backside metallization in particular comprising an Au layer as a bonding layer. | 10-04-2012 |
20120248613 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed. | 10-04-2012 |
20120256317 | Barrier Layer for Integrated Circuit Contacts - Plug contacts may be formed with barrier layers having thicknesses of less than 50 Å in some embodiments. In one embodiment, the barrier layer may be formed by the chemical vapor deposition of diborane, forming a boron layer between a metallic contact and the surrounding dielectric and between a metallic contact and the substrate and/or substrate contact. This boron layer may be substantially pure boron and boron silicide. | 10-11-2012 |
20120261823 | INTERCONNECT STRUCTURES WITH ENGINEERED DIELECTRICS WITH NANOCOLUMNAR POROSITY - A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described. | 10-18-2012 |
20120267785 | METHODS OF FORMING INTEGRATED CIRCUIT DEVICES HAVING DAMASCENE INTERCONNECTS THEREIN WITH METAL DIFFUSION BARRIER LAYERS AND DEVICES FORMED THEREBY - Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique. | 10-25-2012 |
20120273948 | INTEGRATED CIRCUIT STRUCTURE INCLUDING A COPPER-ALUMINUM INTERCONNECT AND METHOD FOR FABRICATING THE SAME - An integrated circuit structure including a copper-aluminum interconnect with a barrier layer including a titanium nitride layer and a method for fabricating the same are disclosed. The method for fabricating an integrated circuit structure including a copper-aluminum interconnect according to the present invention comprises the steps of providing a copper (Cu) layer; forming a barrier layer connected to the copper layer, wherein the barrier layer comprises a first layer including a tantalum layer and a tantalum nitride layer and a second layer including a titanium nitride layer, the first layer contacts the copper layer and is disposed between the copper layer and the second layer, and the barrier layer has a recess correspondingly above the copper layer; and forming an aluminum (Al) layer disposed in the recess. | 11-01-2012 |
20120273949 | METHOD OF FORMING OXIDE ENCAPSULATED CONDUCTIVE FEATURES - Semiconductor devices are formed with a Cu or Cu alloy interconnect encapsulated by a substantially uniform MnO or Al | 11-01-2012 |
20120273950 | INTEGRATED CIRCUIT STRUCTURE INCLUDING COPPER-ALUMINUM INTERCONNECT AND METHOD FOR FABRICATING THE SAME - An integrated circuit structure including a copper-aluminum interconnect with a CuSiN layer and a method for fabricating the same are provided. The method for fabricating an integrated circuit structure including a copper-aluminum interconnect according to the present invention comprises the steps of providing a copper (Cu) layer; forming a barrier layer including a CuSiN layer on the copper layer; forming a wetting layer on the barrier layer; and forming an aluminum (Al) layer on the wetting layer. | 11-01-2012 |
20120273951 | Contact Metal for Hybridization and Related Methods - A contact structure for interconnecting a first substrate to an indium interconnect structure on a second substrate. The contact structure comprises a diffusive layer and a non-oxidizing layer, with a thickness of less than approximately 150 nm, positioned on the diffusive layer for alignment with the indium interconnect. | 11-01-2012 |
20120273952 | MICROELECTRONIC CHIP, COMPONENT CONTAINING SUCH A CHIP AND MANUFACTURING METHOD - Microelectronic chip including a semiconductor substrate; at least one area of its surface which is suitable to be electrically connected to a metal frame designed to accommodate the chip; at least one interconnect area formed by a copper-based conductive layer and comprising a connecting device, the interconnect area being connected to the area by a conductor, wherein the area is formed by a layer forming a copper diffusion barrier inserted between interconnect area and the substrate. | 11-01-2012 |
20120280391 | SEMICONDUCTOR DEVICE CONDUCTIVE PATTERN STRUCTURES AND METHODS OF MANUFACTURING THE SAME - A conductive pattern structure includes a first insulating interlayer on a substrate, metal wiring on the first insulating interlayer, a second insulating interlayer on the metal wiring, and first and second metal contacts extending through the second insulating interlayer. The first metal contacts contact the metal wiring in a cell region and the second metal contact contacts the metal wiring in a peripheral region. A third insulating interlayer is disposed on the second insulating interlayer. Conductive segments extend through the third insulating interlayer in the cell region and contact the first metal contacts. Another conductive segment extends through the third insulating interlayer in the peripheral region and contacts the second metal contact. The structure facilitates the forming of uniformly thick wiring in the cell region using an electroplating process. | 11-08-2012 |
20120280392 | Semiconductor Component Havin a Plated Through-Hole and method for the Production Thereof - A connection contact layer ( | 11-08-2012 |
20120280393 | Electromechanical Microswitch for Switching an Electrical Signal, Microelectromechanical System, Integrated Circuit, and Method for Producing an Integrated Circuit - The invention relates to a microelectromechanical system with an electromechanical microswitch for switching an electrical signal in particular a radio frequency signal, in particular in a GHz range, comprising a multi-level conductive path layer stack arranged on a substrate, wherein conductive paths of the multi-level conductive path layer stack arranged in different conductive levels are insulated from one another through electrically insulating layers and electrically connected with one another through via contacts, an electromechanical switch which is integrated in a recess of the multi-level conductive path layer stack and which includes a contact pivot, an opposite contact and at least one drive electrode for the contact pivot, wherein the contact pivot, the opposite contact and the at least one drive electrode respectively form a portion of a conductive level of the multi-level layer stack. | 11-08-2012 |
20120280394 | SEMICONDUCTOR DEVICE WITH SEG FILM ACTIVE REGION - A semiconductor device and a method for manufacturing the same are provided. A barrier film is formed in a device separating structure, and the device separating structure is etched at a predetermined thickness to expose a semiconductor substrate. Then, a SEG film is grown to form an active region whose area is increased. As a result, a current driving power of a transistor located at a cell region and peripheral circuit regions is improved. | 11-08-2012 |
20120292767 | Novel Approach for Reducing Copper Line Resistivity - A method for fabricating an integrated circuit structure and the resulting integrated circuit structure are provided. The method includes forming a low-k dielectric layer; form an opening in the low-k dielectric layer; forming a barrier layer covering a bottom and sidewalls of the low-k dielectric layer; performing a treatment to the barrier layer in an environment comprising a treatment gas; and filling the opening with a conductive material, wherein the conductive material is on the barrier layer. | 11-22-2012 |
20120292768 | VIA/CONTACT AND DAMASCENE STRUCTURES - A semiconductor structure is provided and includes a dielectric layer disposed over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is disposed in the opening. | 11-22-2012 |
20120292769 | SEMICONDUCTOR ELEMENT MOUNTING MEMBER, METHOD OF PRODUCING THE SAME, AND SEMICONDUCTOR DEVICE - A semiconductor element mounting member is arranged to infiltrate a matrix metal into a porous body that is formed by sintering diamond particles being in direct contact with each other and that has an infiltration auxiliary layer selectively formed only on the exposed surface of each diamond particle. A production method includes a step at which a mixture of diamond particles, a powder of a chemical element out of which the infiltration auxiliary layer is made, and an ammonium chloride powder is compressed and molded, is then heated to 900° C. or more, and is formed into the porous body. A semiconductor device has a semiconductor element mounted on an element mounting surface of the semiconductor element mounting member with a connecting layer therebetween. | 11-22-2012 |
20120299184 | SYSTEM AND METHOD FOR MONITORING COPPER BARRIER LAYER PRECLEAN PROCESS - A monitor wafer for use in monitoring a preclean process and method of making same are described. One embodiment is a monitor wafer comprising a silicon base layer; a capping layer disposed on the silicon base layer; and a barrier layer disposed on the USG layer. The monitor wafer further comprises a copper (“Cu”) seed layer disposed on the barrier layer; and a thick Cu layer disposed on the Cu seed layer. | 11-29-2012 |
20120299185 | Slit Recess Channel Gate and Method of Forming the Same - A slit recess channel gate is further provided. The slit recess channel gate includes a substrate, a gate dielectric layer, a first conductive layer and a second conductive layer. The substrate has a first trench. The gate dielectric layer is disposed on a surface of the first trench and the first conductive layer is embedded in the first trench. The second conductive layer is disposed on the first conductive layer and aligned with the first conductive layer above the main surface, wherein a bottom surface area of the second conductive layer is substantially smaller than a top surface area of the second conductive layer. The present invention also provides a method of forming the slit recess channel gate. | 11-29-2012 |
20120306080 | Packaging Structures and Methods - A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier. | 12-06-2012 |
20120306081 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - According to one embodiment, a semiconductor device includes an interconnect provided on a first interlayer insulating film covering a semiconductor substrate in which an element is formed, a cap layer provided on the upper surface of the interconnect, and a barrier film provided between the interconnect and a second interlayer insulating film covering the interconnect. The interconnect includes a high-melting-point conductive layer, and the width of the interconnect is smaller than the width of the cap layer. The barrier film includes a compound of a contained element in the high-melting-point conductive layer. | 12-06-2012 |
20120319278 | GAP FILLING METHOD FOR DUAL DAMASCENE PROCESS - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of first openings. The method includes forming a conductive liner layer over the patterned dielectric layer, the conductive liner layer partially filling the first openings. The method includes forming a trench mask layer over portions of the conductive liner layer outside the first openings, thereby forming a plurality of second openings, a subset of which are formed over the first openings. The method includes depositing a conductive material in the first openings to form a plurality of vias and in the second openings to form a plurality of metal lines. The method includes removing the trench mask layer. | 12-20-2012 |
20120319279 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - According to one embodiment, a semiconductor device includes a semiconductor substrate, wiring lines formed above the semiconductor substrate, and an air gap formed between the adjacent wiring lines. In the semiconductor device, top surfaces and side walls of the wiring lines are covered with the diffusion prevention film, and the air gap is in contact with the interconnects via a diffusion prevention film. | 12-20-2012 |
20120319280 | SEMICONDUCTOR DEVICE AND BONDING MATERIAL FOR SEMICONDUCTOR DEVICE - In a semiconductor device | 12-20-2012 |
20120326311 | ENHANCED DIFFUSION BARRIER FOR INTERCONNECT STRUCTURES - Alternative methods of fabricating an interconnect structure in which an enhanced diffusion barrier including an in-situ formed metal nitride liner formed between an interconnect dielectric material and an overlying metal diffusion barrier liner are provided. In one embodiment, the method includes forming at least one opening into an interconnect dielectric material. A nitrogen enriched dielectric surface layer is formed within exposed surfaces of the interconnect dielectric material utilizing thermal nitridation. A metal diffusion barrier liner is formed on the nitrogen enriched dielectric surface. During and/or after the formation of the metal diffusion barrier liner, a metal nitride liner forms in-situ in a lower region of the metal diffusion barrier liner. A conductive material is then formed on the metal diffusion barrier liner. The conductive material, the metal diffusion barrier liner and the metal nitride liner that are located outside of the at least one opening are removed to provide a planarized conductive material, a planarized metal diffusion barrier liner and a planarized metal nitride liner, each of which includes an upper surface that is co-planar with the nitrogen enriched dielectric surface layer of the interconnect dielectric material. | 12-27-2012 |
20120326312 | In-Situ Formation of Silicon and Tantalum Containing Barrier - A method includes forming an opening in a dielectric layer, and forming a silicon rich layer on a surface of the dielectric layer. A portion of the silicon rich layer extends into the opening and contacts the dielectric layer. A tantalum-containing layer is formed over and the contacting the silicon rich layer. An annealing is performed to react the tantalum-containing layer with the silicon rich layer, so that a tantalum-and-silicon containing layer is formed. | 12-27-2012 |
20120326313 | SINGLE EXPOSURE IN MULTI-DAMASCENE PROCESS - Methods of fabricating a multi-layer semiconductor device such as a multi-layer damascene or inverted multi-layer damascene structure using only a single or reduced number of exposure steps. The method may include etching a precursor structure formed of materials with differential removal rates for a given removal condition. The method may include removing material from a multi-layer structure under different removal conditions. Further disclosed are multi-layer damascene structures having multiple cavities of different sizes. The cavities may have smooth inner wall surfaces. The layers of the structure may be in direct contact. The cavities may be filled with a conducting metal or an insulator. Multi-layer semiconductor devices using the methods and structures are further disclosed. | 12-27-2012 |
20130001782 | LAMINATED HIGH MELTING POINT SOLDERING LAYER AND FABRICATION METHOD FOR THE SAME, AND SEMICONDUCTOR DEVICE - The laminated high melting point soldering layer includes: a laminated structure which laminated a plurality of three-layered structures, the respective three-layered structures including a low melting point metal thin film layer and a high melting point metal thin film layers disposed on a surface and a back side surface of the low melting point metal thin film layer; a first high melting point metal layer disposed on the surface of the laminated structure; and a second high melting point metal layer disposed on the back side surface of the laminated structure. The low melting point metal thin film layer and the high melting point metal thin film layer are mutually alloyed by TLP, and the laminated structure, and the first high melting point metal layer and the second high melting point metal layer are mutually alloyed by the TLP bonding. | 01-03-2013 |
20130001783 | Interconnect Barrier Structure and Method - A system and method for forming through substrate vias is provided. An embodiment comprises forming an opening in a substrate and lining the opening with a first barrier layer. The opening is filled with a conductive material and a second barrier layer is formed in contact with the conductive material. The first barrier layer is formed with different materials and different methods of formation than the second barrier layer so that the materials and methods may be tuned to maximize their effectiveness within the device. | 01-03-2013 |
20130001784 | METHOD AND STRUCTURE OF FORMING SILICIDE AND DIFFUSION BARRIER LAYER WITH DIRECT DEPOSITED FILM ON SI - A semiconductor device or a photovoltaic cell having a contact structure, which includes a silicon (Si) substrate; a metal alloy layer deposited on the silicon substrate; a metal silicide layer and a diffusion layer formed simultaneously from thermal annealing the metal alloy layer; and a metal layer deposited on the metal silicide and barrier layers. | 01-03-2013 |
20130001785 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes an interlayer insulating film, a wiring formed on the interlayer insulating film so as to protrude therefrom and made of a material having copper as a main component, and a passivation film formed so as to cover the wiring. The passivation film is made of a laminated film in which a first nitride film, an intermediate film, and a second nitride film are laminated in that order from the wiring side. The intermediate film is made of an insulating material (for example, an oxide) differing from those of the first and second nitride films. | 01-03-2013 |
20130015580 | REPLACEMENT METAL GATE STRUCTURE AND METHODS OF MANUFACTUREAANM JAIN; SAMEER HAACI BeaconAAST NYAACO USAAGP JAIN; SAMEER H Beacon NY USAANM Johnson; Jeffrey B.AACI Essex JunctionAAST VTAACO USAAGP Johnson; Jeffrey B. Essex Junction VT USAANM Li; YingAACI NewburghAAST NYAACO USAAGP Li; Ying Newburgh NY USAANM Nayfeh; Hasan M.AACI PoughkeepsieAAST NYAACO USAAGP Nayfeh; Hasan M. Poughkeepsie NY USAANM Ramachandran; RavikumarAACI PleasantvilleAAST NYAACO USAAGP Ramachandran; Ravikumar Pleasantville NY US - A replacement metal gate structure and methods of manufacturing the same is provided. The method includes forming at least one trench structure and forming a liner of high-k dielectric material in the at least one trench structure. The method further includes adjusting a height of the liner of high-k dielectric material. The method further includes forming at least one workfunction metal over the liner, and forming a metal gate structure in the at least one trench structure, over the at least one workfunction metal and the liner of high-k dielectric material. | 01-17-2013 |
20130015581 | STRUCTURE AND METHOD FOR HIGH PERFORMANCE INTERCONNECTAANM Wann; HsingjenAACI CarmelAAST NYAACO USAAGP Wann; Hsingjen Carmel NY USAANM Ko; Ting-ChuAACI HsinchuAACO TWAAGP Ko; Ting-Chu Hsinchu TW - The present disclosure provides an integrated circuit structure. The integrated circuit structure includes a substrate having an IC device formed therein; a first dielectric material layer disposed on the substrate and having a first trench formed therein; and a first composite interconnect feature disposed in the first trench and electrically coupled with the IC device. The first composite interconnect feature includes a first barrier layer disposed on sidewalls of the first trench; a first metal layer disposed on the first barrier layer; and a first graphene layer disposed on the metal layer. | 01-17-2013 |
20130037953 | THROUGH SILICON VIA STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method for a through silicon via structure includes the following steps. First, a substrate is provided, and a through silicon hole is formed in the substrate. An outer plasma enhanced oxide layer is formed on the surface of the through silicon hole, and then a liner layer is formed on the surface of the outer plasma enhanced oxide layer. An inner plasma enhanced oxide layer is formed on the surface of the liner layer. Finally, a conductor is formed on the surface of the inner plasma enhanced oxide layer to completely fill the through silicon hole. | 02-14-2013 |
20130037954 | Metallization and Its Use In, In Particular, an IGBT or a Diode - A vertical power semiconductor component includes a semiconductor chip and at least one layer serving as a heat sink. The semiconductor chip has a top main surface at a front side of the semiconductor chip, wherein the top main surface is in a heat exchanging relationship with the at least one layer serving as the heat sink. This layer has a layer thickness of at least 15 μm and has a specific heat capacity per volume that is at least a factor of 1.3 higher than the specific heat capacity per volume of the semiconductor chip. The component further includes metallizations between the at least one layer and the top main surface. | 02-14-2013 |
20130043591 | TUNGSTEN METALLIZATION: STRUCTURE AND FABRICATION OF SAME - A local interconnect structure is provided in which a tungsten region, i.e., tungsten stud, that is formed within a middle-of-the-line (MOL) dielectric material is not damaged and/or contaminated during a multiple interconnect patterning process. This is achieved in the present disclosure by forming a self-aligned tungsten nitride passivation layer within a topmost surface and upper sidewalls portions of the tungsten region that extend above a MOL dielectric material which includes a first interconnect pattern formed therein. During the formation of the self-aligned tungsten nitride passivation layer, a nitrogen enriched dielectric surface also forms within exposed surface of the MOL dielectric material. A second interconnect pattern is then formed adjacent to, but not connect with, the first interconnect pattern. Because of the presence of the self-aligned tungsten nitride passivation layer on the tungsten region, no damaging and/or contamination of the tungsten region can occur. | 02-21-2013 |
20130062769 | Microstructure Modification in Copper Interconnect Structures - A metal interconnect structure and a method of manufacturing the metal interconnect structure. Manganese (Mn) is incorporated into a copper (Cu) interconnect structure in order to modify the microstructure to achieve bamboo-style grain boundaries in sub-90 nm technologies. Preferably, bamboo grains are separated at distances less than the “Blech” length so that copper (Cu) diffusion through grain boundaries is avoided. The added Mn also triggers the growth of Cu grains down to the bottom surface of the metal line so that a true bamboo microstructure reaching to the bottom surface is formed and the Cu diffusion mechanism along grain boundaries oriented along the length of the metal line is eliminated. | 03-14-2013 |
20130062770 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING SAME - One or more embodiments relate to a semiconductor structure, comprising: a barrier layer overlying a workpiece surface; a seed layer overlying the barrier layer; an inhibitor layer overlying said seed layer, the inhibitor layer having a opening exposing a portion of the seed layer, and a fill layer overlying the exposed portion of the seed layer. | 03-14-2013 |
20130069233 | Reverse Damascene Process - The present disclosure relates to a method of forming a back-end-of-the-line metallization layer. The method is performed by forming a plurality of freestanding metal layer structures (i.e., metal layer structures not surrounded by a dielectric material) on a semiconductor substrate within an area defined by a patterned photoresist layer. A diffusion barrier layer is deposited onto the metal layer structure in a manner such that the diffusion barrier layer conforms to the top and sides of the metal layer structure. A dielectric material is formed on the surface of the substrate to fill areas between metal layer structures. The substrate is planarized to remove excess metal and dielectric material and to expose the top of the metal layer structure. | 03-21-2013 |
20130069234 | STRUCTURE AND METHOD FOR TUNABLE INTERCONNECT SCHEME - The present disclosure provides one embodiment of a method to form an interconnect structure. The method includes forming a first dielectric material layer on a substrate; patterning the first dielectric material layer to form a plurality of vias therein; forming a metal layer on the first dielectric layer and the substrate, wherein the metal layer fills in the plurality of vias; and etching the metal layer such that portions of the metal layer above the first dielectric material layer are patterned to form a plurality of metal lines, aligned with plurality of vias, respectively. | 03-21-2013 |
20130075908 | SEMICONDUCTOR INTERCONNECT STRUCTURE HAVING ENHANCED PERFORMANCE AND RELIABILITY - An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by minimizing oxygen intrusion into a seed layer and an electroplated copper layer of the interconnect structure, are disclosed. At least one opening in a dielectric layer is formed. A sacrificial oxidation layer disposed on the dielectric layer is formed. The sacrificial oxidation layer minimizes oxygen intrusion into the seed layer and the electroplated copper layer of the interconnect structure. A barrier metal layer disposed on the sacrificial oxidation layer is formed. A seed layer disposed on the barrier metal layer is formed. An electroplated copper layer disposed on the seed layer is formed. A planarized surface is formed, wherein a portion of the sacrificial oxidation layer, the barrier metal layer, the seed layer, and the electroplated copper layer are removed. In addition, a capping layer disposed on the planarized surface is formed. | 03-28-2013 |
20130075909 | SEMICONDUCTOR DEVICE INCLUDING METAL-CONTAINING CONDUCTIVE LINE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor substrate having a trench therein, a metal-containing barrier layer extending along an inner wall of the trench and defining a wiring space in the trench, the wiring space having a first width along a first direction, and a metal-containing conductive line on the metal-containing barrier layer in the wiring space, and including at least one metal grain having a particle diameter of about the first width along the first direction. | 03-28-2013 |
20130075910 | MODULATED DEPOSITION PROCESS FOR STRESS CONTROL IN THICK TiN FILMS - A multi-layer TiN film with reduced tensile stress and discontinuous grain structure, and a method of fabricating the TiN film are disclosed. The TiN layers are formed by PVD or IMP in a nitrogen plasma. Tensile stress in a center layer of the film is reduced by increasing N | 03-28-2013 |
20130075911 | Semiconductor Device Having Electrode/Film Opening Edge Spacing Smaller Than Bonding Pad/Electrode Edge Spacing - A semiconductor device has a conductive member coupled to the surface of a bonding pad exposed from an opening formed in a passivation film. A second planar distance between a first end of an electrode layer and a first end of a bonding pad is greater than a first planar distance between the first end of the electrode layer and a first end of an opening. Since the second planar distance between the first end of the electrode layer and the first end of the bonding pad is long, even when a coupled position of wire is deviated to the first end side of the electrode layer, stress caused by coupling of the wire to a stepped portion of the electrode layer can be prevented from being transmitted to the first end portion of the bonding pad. | 03-28-2013 |
20130082385 | DIE HAVING COEFFICIENT OF THERMAL EXPANSION GRADED LAYER - A semiconductor die includes a substrate including a topside including circuit elements configured to provide a circuit function. The die includes at least one multi-layer structure including a first material having a first CTE, a second material including a metal having a second CTE, wherein the second CTE is higher than the first CTE. A coefficient of thermal expansion (CTE) graded layer includes at least a dielectric portion that is between the first material and the second material having a first side facing the first material and a second side facing the second material. The CTE graded layer includes a non-constant composition profile across its thickness that provides a graded CTE which increases in CTE from the first side to the second side. The multi-layer structure can be a through-substrate-vias (TSV) that extends through the thickness of the substrate. | 04-04-2013 |
20130093089 | Interconnect Structure With An Electromigration and Stress Migration Enhancement Liner - An electromigration and stress migration enhancement liner is provided for use in an interconnect structure. The liner includes a metal that has a thickness at a bottom of the at least one via opening and on an exposed portion of an underlying conductive feature that is greater than a remaining thickness that is located on exposed sidewalls of the interconnect dielectric material. The thinner portion of the electromigration and stress migration enhancement liner is located between the interconnect dielectric material and an overlying diffusion barrier. The thicker portion of the electromigration and stress migration enhancement liner is located between the underlying conductive feature and the diffusion barrier as well as between an adjacent dielectric capping layer and the diffusion barrier. The remainder of the at least one via opening is filled with an adhesion layer and a conductive material. | 04-18-2013 |
20130093090 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a first film containing a metal whose energy for forming silicide thereof is lower than that of Cu silicide inside the opening; forming a second film that is conductive and contains copper (Cu) in the opening in which the first film containing the metal is formed; and forming a compound film containing Cu and silicon (Si) selectively on the second film in an atmosphere in which a temperature of the substrate is below 300° C. | 04-18-2013 |
20130093091 | Three-Dimensional Vertical Interconnecting Structure and Manufacturing Method Thereof - The present invention discloses a three-dimensional vertically interconnected structure and a fabricating method for the same. The structure comprises at least two layers of chips which are stacked in sequence or stacked together face to face, and an adhesive material is used for adhesion between adjacent layers of said chips, each layer of chips contains a substrate layer and a dielectric layer sequentially bottom to top; an front surface of the chip has a first concave with an annular cross section, and the first concave is filled with metal inside to form a first electrical conductive ring connecting to microelectronic devices inside the chip via a redistribution layer; a first through layers of chips hole having the same radius and center as inner ring of the first electrical conductive ring penetrates the stacked chips and has a first micro electrical conductive pole inside that is electrically connected to the first electrical conductive ring. The three-dimensional vertically interconnected structure of the present invention enhances the strength of the electric interconnection and the adhesion between adjacent layers of chips, and in the meantime the disclosed fabricating method simplifies the process difficulty and therefore improves the yield. | 04-18-2013 |
20130105977 | Electronic Device and Method for Fabricating an Electronic Device | 05-02-2013 |
20130105978 | SILICON SUBMOUNT FOR LIGHT EMITTING DIODE AND METHOD OF FORMING THE SAME | 05-02-2013 |
20130113101 | Use of Gas Cluster Ion Beam To Reduce Metal Void Formation In Interconnect Structures - A gas cluster ion beam process is used to reduce and/or even eliminate metal void formation in an interconnect structure. In one embodiment, gas cluster ion beam etching forms a chamfer opening in an interconnect dielectric material. In another embodiment, gas cluster ion beam etching reduces the overhang profile of a diffusion barrier or a multilayered stack of a diffusion barrier and a plating seed layer that is formed within an opening located in an interconnect dielectric material. In yet another embodiment, a gas cluster ion beam process deactivates a surface of an interconnect dielectric material that is located at upper corners of an opening that is formed therein. In this embodiment, the gas cluster ion beam process deposits a material that deactivates the upper corners of each opening that is formed into an interconnect dielectric material. | 05-09-2013 |
20130113103 | DEVICE HAVING TSVs WITH GETTERING LAYER LATERAL TO TSV TIPS - An integrated circuit (IC) includes a substrate having a topside semiconductor surface including active circuitry configured to provide functionality and a bottomside surface. A plurality of through substrate vias (TSVs) extend from the topside semiconductor surface to beyond the bottomside surface to provide protruding TSV tips. The TSVs include an outer dielectric liner, a metal comprising diffusion barrier layer on the dielectric liner, and a metal filler on the metal comprising barrier layer. A dielectric metal gettering layer (MGL) is on the bottomside surface lateral to and on sidewalls of the protruding TSV tips. The MGL includes at least one metal gettering agent selected from a halogen or a Group 15 element in an average concentration from 0.1 to 10 atomic %. | 05-09-2013 |
20130113104 | STRUCTURE FOR PICKING UP A BURIED LAYER AND METHOD THEREOF - A structure for picking up a buried layer is disclosed. The buried layer is formed in a substrate and has an epitaxial layer formed thereon. One or more isolation regions are formed in the epitaxial layer. The structure for picking up the buried layer includes a contact-hole electrode formed in each of the isolation regions. A bottom of the contact-hole electrode is in contact with the buried layer. As the structure of the present invention is formed in the isolation region without occupying any portion of the active region, its size is much smaller than that of a sinker region of the prior art. Therefore, device area is tremendously reduced. Moreover, as the contact-hole electrode picks up the buried layer by a metal contact, the series resistance of the device can be greatly reduced. A method of forming the above structure is also disclosed. | 05-09-2013 |
20130113105 | Barrier For Through-Silicon Via - A system and a method for protecting vias is disclosed. An embodiment comprises forming an opening in a substrate. A barrier layer disposed in the opening including along the sidewalls of the opening. The barrier layer may include a metal component and an alloying material. A conductive material is formed on the barrier layer and fills the opening. The conductive material to form a via (e.g., TSV). | 05-09-2013 |
20130119545 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device and a method for forming the same are disclosed, which can protect a polysilicon layer of a bit line contact plug even when a critical dimension (CD) of the bit line is reduced by a fabrication change, thereby preventing defective resistivity caused by a damaged bit line contact plug from being generated. The semiconductor device includes one or more interlayer insulation film patterns formed over a semiconductor substrate, a bit line contact plug formed over the semiconductor substrate between the interlayer insulation films, and located below a top part of the interlayer insulation film pattern, and a bit line formed over the bit line contact plug. | 05-16-2013 |
20130119546 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - The method of the present invention comprises forming a word line crossing with an active region on a semiconductor substrate; forming a diffusion layer region; forming a first insulating film as high as a bit line to be formed; etching the first insulating film, while using, as a mask, a pattern having a linear aperture extending to the active region on the first insulating film so as to form a groove pattern for exposing the surface of the semiconductor substrate; embedding a conductive film in the groove pattern; forming a mask pattern passing over a portion, in which a bit contact is formed, on the first insulating film; and removing the first insulating film and the conductive layer until the upper layer insulating film of the word line is exposed, while using the mask pattern as a mask so as to isolate a bit contact from another contact. | 05-16-2013 |
20130119547 | INTEGRATED CIRCUIT DEVICE INCLUDING THROUGH-SILICON VIA STRUCTURE HAVING OFFSET INTERFACE - An integrated circuit device includes a substrate through which a first through-hole extends, and an interlayer insulating film on the substrate, the interlayer insulating film having a second through-hole communicating with the first through-hole. A Through-Silicon Via (TSV) structure is provided in the first through-hole and the second through-hole. The TSV structure extends to pass through the substrate and the interlayer insulating film. The TSV structure comprises a first through-electrode portion having a top surface located in the first through-hole, and a second through-electrode portion having a bottom surface contacting with the top surface of the first through-electrode portion and extending from the bottom surface to at least the second through-hole. Related fabrication methods are also described. | 05-16-2013 |
20130127055 | MECHANISMS OF FORMING DAMASCENE INTERCONNECT STRUCTURES - The mechanisms of forming an interconnect structures described above involves using a reflowed conductive layer. The reflowed conductive layer is thicker in smaller openings than in wider openings. The mechanisms may further involve forming a metal cap layer over the reflow conductive layer, in some embodiments. The interconnect structures formed by the mechanisms described have better electrical and reliability performance. | 05-23-2013 |
20130127056 | SEMICONDUCTOR DEVICES INCLUDING DUAL DAMASCENE METALLIZATION STRUCTURES - A semiconductor device can include a dual-damascene metallization structure that may provide a reduced resistance by providing barrier layers that are different materials. The semiconductor device can include a device layer and a lower conductive layer that can be electrically connected to the device layer. A lower barrier layer can surround the lower conductive layer and an upper conductive layer can be disposed on the lower conductive layer and can be electrically connected to the lower conductive layer. An upper barrier layer can surround the upper conductive layer and can including material that is different from a material included in the lower barrier layer. | 05-23-2013 |
20130127057 | SEED LAYER PASSIVATION - A microfeature workpiece generally includes a first conducting layer, a chemisorbed layer or a monolayer directly on the first conducting layer, and a second conducting layer. The chemisorbed layer or monolayer includes a first material that may be selected from the group consisting of nitrogen-containing compounds, sulfur-containing compounds, and mixtures thereof. | 05-23-2013 |
20130134592 | WIRE AND SEMICONDUCTOR DEVICE - A wire of an embodiment includes: a substrate; a metal film provided on the substrate; a metal part provided on the metal film; and graphene wires formed on the metal part, wherein the graphene wire is electrically connected to the metal film, and the metal film and the metal part are formed using different metals or alloys from each other. | 05-30-2013 |
20130140697 | Electrode Connecting Structures Containing Copper - Provided are electrode-connecting structures or semiconductor devices, including a lower device including a lower substrate, a lower insulating layer formed on the lower substrate, and a lower electrode structure formed in the lower insulating layer, wherein the lower electrode structure includes a lower electrode barrier layer and a lower metal electrode formed on the lower electrode barrier layer, and an upper device including an upper substrate, an upper insulating layer formed under the upper substrate, and an upper electrode structure formed in the upper insulating layer, wherein the upper electrode structure includes an upper electrode barrier layer extending from the inside of the upper insulating layer under a bottom surface thereof and an upper metal electrode formed on the upper electrode barrier layer. The lower metal electrode is in direct contact with the upper metal electrode. | 06-06-2013 |
20130140698 | Doped Tantalum Nitride for Copper Barrier Applications - Described are doped TaN films, as well as methods for providing the doped TaN films. Doping TaN films with Ru, Cu, Co, Mn, Al, Mg, Cr, Nb, Ti and/or V allows for enhanced copper barrier properties of the TaN films. Also described are methods of providing films with a first layer comprising doped TaN and a second layer comprising one or more of Ru and Co, with optional doping of the second layer. | 06-06-2013 |
20130140699 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCTION OF SEMICONDUCTOR DEVICE - A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto. | 06-06-2013 |
20130140700 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a TSV structure, which prevents a substrate from warping even if it is made thin. A method of manufacturing a semiconductor device comprises integrating semiconductor elements on a surface of a semiconductor substrate to form at least a part of a circuit, forming holes from the surface of the semiconductor substrate, forming an insulating film and a barrier film on an inner surface of each hole, forming a conductive metal on a surface of the barrier film to fill each hole, processing a back surface of the semiconductor substrate to reduce the thickness thereof to thereby protrude the conductive metal, and providing a SiCN film on the back surface of the semiconductor substrate. | 06-06-2013 |
20130147046 | Integrated Technology for Partial Air Gap Low K Deposition - A semiconductor device includes a semiconductor body and a low K dielectric layer overlying the semiconductor body. A first portion of the low K dielectric layer comprises a dielectric material, and a second portion of the low K dielectric layer comprise an air gap, wherein the first portion and the second portion are laterally disposed with respect to one another. A method for forming a low K dielectric layer is also disclosed and includes forming a dielectric layer over a semiconductor body, forming a plurality of air gaps laterally disposed from one another in the dielectric layer, and forming a capping layer over the dielectric layer and air gaps. | 06-13-2013 |
20130154096 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a manufacturing method of a barrier layer, a via hole is formed in an insulating layer that covers a conductive layer over a substrate, and then the barrier layer is formed in the via hole. The barrier layer is provided by forming a second titanium nitride film after forming a first titanium nitride film. The second titanium nitride film is formed using a method having a weak anisotropy than the first titanium nitride film. | 06-20-2013 |
20130154097 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME - The present invention provides a semiconductor structure and a manufacturing method thereof. The method comprises: providing a semiconductor substrate comprising semiconductor devices; depositing a copper diffusion barrier layer on the semiconductor substrate; forming a copper composite layer on the copper diffusion barrier layer; decomposing the copper composite at corresponding positions, where copper interconnection is to be formed, into copper according to the shape of the copper interconnection; and etching off the undecomposed copper composite and the copper diffusion barrier layer underneath, to interconnect the semiconductor devices. The present invention is adaptive for manufacturing interconnection in integrated circuits. | 06-20-2013 |
20130154098 | LINER-FREE TUNGSTEN CONTACT - An electrical structure comprises a dielectric layer present on a semiconductor substrate. A contact opening is present through the dielectric layer. A nickel-tungsten alloy silicide is formed over the semiconductor substrate within the contact opening. A tungsten-containing nucleation layer formed within the contact opening covers the nickel-tungsten alloy silicide and at least a portion of a sidewall of the contact opening. A tungsten contact is formed within the contact opening and separated from the nickel-tungsten alloy silicide and at least a portion of the sidewall by the tungsten-containing nucleation layer. | 06-20-2013 |
20130161818 | 3-D NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A three-dimensional (3-D) nonvolatile memory device includes channel layers protruding perpendicular to a surface of a substrate, interlayer insulating layers and conductive layer patterns alternately formed to surround each of the channel layers, a slit formed between the channel layers, the slit penetrating the interlayer insulating layers and the conductive layer patterns, and an etch-stop layer formed on the surface of the substrate at the bottom of the slit. | 06-27-2013 |
20130168862 | METHOD OF MANUFACTURING BARRIER LAYER PATTERNS OF A SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE OF BARRIER LAYER PATTERNS OF SEMICONDUCTOR MEMORY DEVICE - A method of manufacturing a semiconductor memory and a structure of the semiconductor memory device, where the semiconductor memory device includes a material layer and a barrier layer. The barrier layer has a structure in which a horizontal cross-section of an upper portion thereof is larger than that of a lower portion thereof so that a fine pattern may be formed on the material layer using the barrier layer pattern without a structural damage or collapse in etching the underlying material layer. | 07-04-2013 |
20130168863 | ENHANCED DIFFUSION BARRIER FOR INTERCONNECT STRUCTURES - Alternative methods of fabricating an interconnect structure in which an enhanced diffusion barrier including an in-situ formed metal nitride liner formed between an interconnect dielectric material and an overlying metal diffusion barrier liner are provided. In one embodiment, at least one opening is formed into an interconnect dielectric material. A nitrogen enriched dielectric surface layer is formed within exposed surfaces of the interconnect dielectric material utilizing thermal nitridation. A metal diffusion barrier liner is the formed. During and/or after the formation of the metal diffusion barrier liner, a metal nitride liner forms in-situ in a lower region of the metal diffusion barrier liner. A conductive material is then formed on the metal diffusion barrier liner. The conductive material, the metal diffusion barrier liner and the metal nitride liner that are located outside of the at least one opening are removed to provide a planarized structure. | 07-04-2013 |
20130175689 | BONDING PAD AND METHOD OF MAKING SAME - The description relates to a bonding pad for a semiconductor device deposited. The first region comprising aluminum deposited at a high temperature having a large grain size. The second region comprising aluminum deposited at a lower temperature having a smaller grain size. | 07-11-2013 |
20130175690 | Power Semiconductor Device with Reduced Contact Resistance - A semiconductor device that includes an electrode of one material and a conductive material of lower resistivity formed over the electrode and a process for fabricating the semiconductor device. | 07-11-2013 |
20130187273 | SEMICONDUCTOR DEVICES WITH COPPER INTERCONNECTS AND METHODS FOR FABRICATING SAME - Semiconductor devices having copper interconnects and methods for their fabrication are provided. In one embodiment, a semiconductor device is fabricated with a copper interconnect on substrate such as an FEOL processed substrate. The method includes forming a copper layer on a substrate. The copper layer is formed from grains. The copper layer is modified such that the modified copper layer has an average grain size of larger than about 0.05 microns. In the method, the modified copper layer is etched to form a line along the substrate and a via extending upwards from the line. | 07-25-2013 |
20130187274 | SEMICONDUCTOR DEVICE HAVING A NANOTUBE LAYER AND METHOD FOR FORMING - A method of forming a semiconductor device includes forming a first conductive layer over the substrate. A dielectric layer, having a first opening, is formed over the first conductive layer. A seed layer is deposited over the first dielectric layer and in the first opening. A layer is formed of conductive nanotubes from the seed layer over the first dielectric layer and over the first opening. A second dielectric is formed over the layer of conductive nanotubes. An opening is formed in the second dielectric layer over the first opening. Conductive material is deposited in the second opening. | 07-25-2013 |
20130193575 | OPTIMIZATION OF COPPER PLATING THROUGH WAFER VIA - Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. To improve the copper plating, a seed layer formed in the through-wafer vias can be modified to increase water affinity, rinsed to remove contaminants, and activated to facilitate copper deposition. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices. | 08-01-2013 |
20130193576 | ENCAPSULANT WITH COROSION INHIBITOR - A packaged electronic device including an electronic device, a conductive structure, and an encapsulant. The encapsulant has chlorides and a negatively-charged corrosion inhibitor for preventing corrosion of the conductive structure. | 08-01-2013 |
20130193577 | STRUCTURE OF ELECTRICAL CONTACT AND FABRICATION METHOD THEREOF - A method of fabricating an electrical contact comprises the following steps. A substrate having at least a silicon region is provided. At least an insulation layer is formed on the substrate, wherein the insulation layer comprises at least a contact hole which exposes the silicon region. A metal layer is formed on sidewalls and bottom of the contact hole. An annealing process is performed to form a first metal silicide layer in the silicon region nearby the bottom of the contact hole. A conductive layer covering the metal layer and filling up the contact hole is then formed, wherein the first metal silicide layer is transformed into a second metal silicide layer when the conductive layer is formed. | 08-01-2013 |
20130193578 | THROUGH-SILICON VIAS FOR SEMICONDCUTOR SUBSTRATE AND METHOD OF MANUFACTURE - A semiconductor component includes a semiconductor substrate having a top surface. An opening extends from the top surface into the semiconductor substrate. The opening includes an interior surface. A first dielectric liner having a first compressive stress is disposed on the interior surface of the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. A metal barrier layer is disposed on the third dielectric liner. A conductive material is disposed on the metal barrier layer and fills the opening. | 08-01-2013 |
20130200519 | Through silicon via structure and method of fabricating the same - The present invention relates to a method of fabricating a through silicon via (TSV) structure, in which, a dielectric layer is disposed to cover surface of each of a device region of a substrate and a sidewall and a bottom of a via hole in a TSV region of the substrate, and the via hole having the dielectric layer covering the sidewall and the bottom is filled with a conductive material. The present invention also relates to a TSV structure, in which, a dielectric layer disposed in the device region of a substrate extends to the via hole in a TSV region of the substrate to cover surface of the sidewall of the via hole to serve as a dielectric liner, and a conductive material is filled into the via hole having the dielectric layer covering the sidewall. | 08-08-2013 |
20130207267 | INTERCONNECTION STRUCTURES IN A SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING THE SAME - Methods of fabricating interconnection structures of a semiconductor device are provided. The method includes, inter alia: forming a first insulation layer on a semiconductor substrate, forming a mold layer having trenches on the first insulation layer, forming a sidewall protection layer including a first metal silicide layer on sidewalls of the trenches, forming second metal lines that fill the trenches, forming upper protection layers on the second metal lines, removing the mold layer after formation of the upper protection layers to provide gaps between second metal lines, and forming a second insulation layer in the gaps and on the upper protection layers. The second insulation layer is formed to include air gaps between the second metal lines. Related interconnection structures are also provided. | 08-15-2013 |
20130207268 | CHIP ASSEMBLY SYSTEM - An assembly of semiconductor wafers/chips wherein the adjacent surfaces of the two wafers/chips comprise an insulating layer having opposite copper pads inserted therein. The insulating layer is made of a material selected from the group including silicon nitride and silicon carbon nitride. | 08-15-2013 |
20130214414 | INTERCONNECT STRUCTURES AND METHODS OF MANUFACTURING OF INTERCONNECT STRUCTURES - Interconnect structures and methods of manufacturing the same are disclosed herein. The method includes forming a barrier layer within a structure and forming an alloy metal on the barrier layer. The method further includes forming a pure metal on the alloy metal, and reflowing the pure metal such that the pure metal migrates to a bottom of the structure, while the alloy metal prevents exposure of the barrier layer. The method further includes completely filling in the structure with additional metal. | 08-22-2013 |
20130214415 | Metal Layer Air Gap Formation - Air gaps are provided to reduce interference and resistance between metal bit lines in non-volatile memory structures. Metal vias can be formed that are electrically coupled with the drain region of an underlying device and extend vertically with respect to the substrate surface to provide contacts for bit lines that are elongated in a column direction above. The metal vias can be separated by a dielectric fill material. Layer stack columns extend in a column direction over the dielectric fill and metal vias. Each layer stack column includes a metal bit line over a nucleation line. Each metal via contacts one of the layer stack columns at its nucleation line. A low temperature dielectric liner extends along sidewalls of the layer stack columns. A non-conformal dielectric overlies the layer stack columns defining a plurality of air gaps between the layer stack columns. | 08-22-2013 |
20130214416 | INTERCONNECT STRUCTURES AND METHODS OF MANUFACTURING OF INTERCONNECT STRUCTURES - Interconnect structures and methods of manufacturing the same are disclosed herein. The method includes forming a barrier layer within a structure and forming an alloy metal on the barrier layer. The method further includes forming a pure metal on the alloy metal, and reflowing the pure metal such that the pure metal migrates to a bottom of the structure, while the alloy metal prevents exposure of the barrier layer. The method further includes completely filling in the structure with additional metal. | 08-22-2013 |
20130221527 | METALLIC CAPPED INTERCONNECT STRUCTURE WITH HIGH ELECTROMIGRATION RESISTANCE AND LOW RESISTIVITY - An interconnect structure including a metallic cap that covers 80 to 99% of the entire surface of an underlying conductive metal feature is provided utilizing a metal reflow process. Laterally extending portions of the conductive metal feature are located on vertical edges of the metallic cap, and each of the laterally extending portions of the conductive metal feature has an uppermost surface that is coplanar with an uppermost surface of the metallic cap. | 08-29-2013 |
20130221528 | DEVICES AND METHODS RELATED TO A SPUTTERED TITANIUM TUNGSTEN LAYER FORMED OVER A COPPER INTERCONNECT STACK STRUCTURE - Disclosed are devices and methods related to metallization of semiconductors. A metalized structure can include a stack disposed over a compound semiconductor, with the stack including a barrier, a copper (Cu) layer disposed over the barrier, and a first titanium (Ti) layer disposed over the Cu layer. The metalized structure can further include a sputtered titanium tungsten (TiW) layer disposed over the first Ti layer. The barrier can include an assembly of titanium nitride (TiN) and Ti layers. The metalized structure can further include a second Ti layer disposed over the sputtered TiW layer. | 08-29-2013 |
20130221529 | HYBRID INTERCONNECT STRUCTURE FOR PERFORMANCE IMPROVEMENT AND RELIABILITY ENHANCEMENT - A hybrid interconnect structure (of the single or dual damascene type) is provided in which a dense (i.e., non-porous) dielectric spacer is present on the sidewalls of a dielectric material. More specifically, the structure includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance. Moreover, the hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing. | 08-29-2013 |
20130228923 | METHODS AND LAYERS FOR METALLIZATION - One aspect of the present invention is a method of making an electronic device. According to one embodiment, the method comprises depositing a cap layer containing at least one dopant onto a gapfill metal and annealing so that the at least one dopant migrates to grain boundaries and/or interfaces of the gapfill metal. Another aspect of the present invention is an electronic device. | 09-05-2013 |
20130228924 | COPPER INTERCONNECTS HAVING A TITANIUM-PLATINUM-TITANIUM ASSEMBLY BETWEEN COPPER AND COMPOUND SEMICONDUCTOR - Disclosed are devices and methods related to metallization of semiconductors. A metalized structure can include a first titanium (Ti) layer disposed over a compound semiconductor, a first barrier layer disposed over the first Ti layer, a second Ti layer disposed over the first barrier layer, and a copper (Cu) layer disposed over the second Ti layer. The second Ti layer can be configured to inhibit or reduce alloying of the Cu layer and the first barrier layer. The first Ti layer, the first barrier layer, and the second Ti layer can be configured to yield a barrier between the Cu layer and an ohmic metal layer formed on the compound semiconductor. The metalized structure can further include a third Ti layer disposed over the Cu layer and a second barrier layer disposed over the third Ti layer. The first and second barrier layers can include platinum (Pt) and/or palladium (Pd). | 09-05-2013 |
20130228925 | HYBRID INTERCONNECT STRUCTURE FOR PERFORMANCE IMPROVEMENT AND RELIABILITY ENHANCEMENT - A hybrid interconnect structure is provided that includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance. Moreover, the hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing. | 09-05-2013 |
20130228926 | INTERCONNECTION STRUCTURE - Provided is an interconnection structure that, in a display device such as an organic EL display or a liquid crystal display, has superior workability during wet etching even without providing an etch stop layer. The interconnection structure has, in the given order, a substrate, a semiconductor layer of a thin film transistor, and a metal interconnection film, and has a barrier layer between the semiconductor layer and the metal interconnection film. The semiconductor layer comprises an oxide semiconductor, the barrier layer has a layered structure of a high-melting-point metal thin film and a Si thin film, and the Si thin film is directly connected to the semiconductor layer. | 09-05-2013 |
20130234332 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked. The semiconductor device includes a plurality of contact electrodes, a plurality of first insulating portions, and a plurality of second insulating portions. The plurality of contact electrodes extends in a stacking direction of the stacked body. Each of the contact electrodes reaches corresponding one of the conductive layers. The plurality of first insulating portions respectively is provided between the plurality of contact electrodes and the stacked body. The plurality of second insulating portions respectively is provided between the plurality of first insulating portions and the stacked body. | 09-12-2013 |
20130234333 | COPPER INTERCONNECTS HAVING A TITANIUM-TITANIUM NITRIDE ASSEMBLY BETWEEN COPPER AND COMPOUND SEMICONDUCTOR - Disclosed are devices and methods related to metallization of semiconductors. A metalized structure can include a first titanium (Ti) layer disposed over a compound semiconductor, a first titanium nitride (TiN) layer disposed over the first Ti layer, and a copper (Cu) layer disposed over the first TiN layer. The first Ti layer and the first TiN layer can be configured as a barrier between the Cu layer and the compound semiconductor. The metalized structure can further include a second TiN layer disposed over the Cu layer and a first platinum (Pt) layer disposed over the second TiN layer. | 09-12-2013 |
20130234334 | SEMICONDUCTOR DEVICE WITH A LINE AND METHOD OF FABRICATION THEREOF - A semiconductor device includes an interlayer insulation film, an underlying line provided in the interlayer insulation film, a liner film overlying the interlayer insulation film, an interlayer insulation film overlying the liner film. The underlying line has a lower hole and the liner film and the interlayer insulation film have an upper hole communicating with the lower hole, and the lower hole is larger in diameter than the upper hole.. The semiconductor device further includes a conductive film provided at an internal wall surface of the lower hole, a barrier metal provided along an internal wall surface of the upper hole, and a Cu film filling the upper and lower holes. The conductive film contains a substance identical to a substance of the barrier metal. A highly reliable semiconductor device can thus be obtained. | 09-12-2013 |
20130241063 | THROUGH-SILICON VIA AND FABRICATION METHOD THEREOF - A through-silicon via (TSV) includes an insulation layer continuously lining a straight sidewall of a recessed via feature; a barrier layer continuously covering the insulation layer; a first portion of a non-continuous seed layer disposed at one end of the recessed via feature; a non-continuous dielectric layer partially covering the straight sidewall of the recessed via feature; and a conductive layer filling the recessed via feature. | 09-19-2013 |
20130241064 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a substrate, a bond pad over the substrate, and a passivation layer over the substrate and a peripheral region of the bond pad. The bond pad has a bonding region and the peripheral region surrounding the bonding region. The passivation layer has an opening defined therein, and the opening exposes the bonding region of the bond pad. A first vertical distance between an upper surface of the passivation layer and a surface of the bonding region ranges from 30% to 40% of a second vertical distance between a lower surface of the passivation layer and an upper surface of the peripheral region. | 09-19-2013 |
20130241065 | SEMICONDUCTOR DEVICE - A semiconductor device may include a semiconductor layer including at least one unit device, a first interconnection on the semiconductor layer and electrically connected to the at least one unit device, a diffusion barrier layer on the first interconnection, an intermetallic dielectric layer on the diffusion barrier layer, a plug in a first region of the intermetallic dielectric layer and passing through the diffusion barrier layer so that a bottom surface thereof contacts the first interconnection, and a first dummy plug in a second region of the intermetallic dielectric layer, passing through the diffusion barrier layer, and disposed apart from the first interconnection so that a bottom surface of the first dummy plug does not contact the first interconnection. | 09-19-2013 |
20130241066 | BARRIER LAYER FOR INTEGRATED CIRCUIT CONTACTS - Plug contacts may be formed with barrier layers having thicknesses of less than 50 Å in some embodiments. In one embodiment, the barrier layer may be formed by the chemical vapor deposition of diborane, forming a boron layer between a metallic contact and the surrounding dielectric and between a metallic contact and the substrate and/or substrate contact. This boron layer may be substantially pure boron and boron silicide. | 09-19-2013 |
20130249095 | GALLIUM ARSENIDE DEVICES WITH COPPER BACKSIDE FOR DIRECT DIE SOLDER ATTACH - Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. Direct die solder (DDS) attach can be achieved by use of electroless nickel plating of the copper contact layer followed by a palladium flash. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices. | 09-26-2013 |
20130249096 | THROUGH SILICON VIA FILLING - A method for forming a through silicon via (TSV) in a substrate comprising: depositing a seed layer in a TSV hole; and annealing the seed layer. | 09-26-2013 |
20130249097 | Schemes for Forming Barrier Layers for Copper in Interconnect Structures - A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided. | 09-26-2013 |
20130256891 | SEMICONDUCTOR DEVICE WITH A COPPER LINE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device with a copper line comprises a lower portion of a copper pattern buried in an interlayer insulating film, an upper portion of the copper disposed over the upper portion of the lower copper pattern, and an upper barrier metal layer disposed over upper and side surfaces of the upper copper pattern. As a result, the copper pattern is protected by the barrier metal layers, providing a metal line with a stable structure. | 10-03-2013 |
20130256892 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - It is an object of the present invention to prevent an influence of voltage drop due to wiring resistance, trouble in writing of a signal into a pixel, and trouble in gray scales, and provide a display device with higher definition, represented by an EL display device and a liquid crystal display device. | 10-03-2013 |
20130270702 | COPPER INTERCONNECT STRUCTURE AND METHOD FOR FORMING THE SAME - A copper interconnect structure in a semiconductor device including an opening formed in a dielectric layer of the semiconductor device, the opening having sidewalls and a bottom. A first barrier layer is conformally deposited on the sidewalls and the bottom of the opening. A first seed layer is conformally deposited on the first barrier layer. A second barrier layer is conformally deposited on the first seed layer. A second seed layer is conformally deposited on the second barrier layer and a conductive plug is deposited in the opening of the dielectric layer. | 10-17-2013 |
20130270703 | ELECTROLESS FILLED CONDUCTIVE STRUCTURES - Techniques are disclosed that enable interconnects, vias, metal gates, and other conductive features that can be formed through electroless material deposition techniques. In some embodiments, the techniques employ electroless fill in conjunction with high growth rate selectivity between an electroless nucleation material (ENM) and electroless suppression material (ESM) to generate bottom-up or otherwise desired fill pattern of such features. Suitable ENM may be present in the underlying or otherwise existing structure, or may be provided. The ESM is provisioned so as to prevent or otherwise inhibit nucleation at the ESM covered areas of the feature which in turn prevents or otherwise slows down the rate of electroless growth on those areas. As such, the electroless growth rate on the ENM sites is higher than the electroless growth rate on the ESM sites. | 10-17-2013 |
20130277842 | COPPER INTERCONNECT WITH CVD LINER AND METALLIC CAP - A structure having a diffusion barrier positioned adjacent to a sidewall and a bottom of an opening being etched in a layer of dielectric material. The structure also having a metal liner positioned directly on top of the diffusion barrier, a seed layer positioned directly on top of the metal liner, wherein the seed layer is made from a material comprising copper, a copper material positioned directly on top of the seed layer, a metallic cap positioned directly on top of and selective to the copper material, and a capping layer positioned directly on top of and adjacent to the metallic cap. | 10-24-2013 |
20130277843 | FLIP CHIP MOUNTED MONOLITHIC MICROWAVE INTEGRATED CIRCUIT (MMIC) STRUCTURE - A MMIC flip chip mounted to a circuit board having an underfill material disposed between the MMIC and the circuit board and a barrier structure for preventing the underfill material from being disposed under an electronic device of the MMIC while providing a cavity under the electronic device. | 10-24-2013 |
20130285244 | Through Silicon Via with Embedded Barrier Pad - A system and method are disclosed for providing a through silicon via (TSV) with a barrier pad deposited below the top surface of the TSV, the top surface having reduced topographic variations. A bottom TSV pad is deposited into a via and then polished so the top surface is below the substrate top surface. A barrier pad is then deposited in the via, and a top TSV pad deposited on the barrier pad. The top TSV barrier pad is polished to bring the top surface of the top TSV pad about level with the substrate. The barrier pad may be less than about 1 microns thick, and the top TSV pad may be less than about 6 microns thick. The barrier pad may be a dissimilar metal from the top and bottom TSV pads, and may be selected from a group comprising titanium, tantalum, cobalt, nickel and the like. | 10-31-2013 |
20130285245 | MICROSTRUCTURE MODIFICATION IN COPPER INTERCONNECT STRUCTURES - A metal interconnect structure and a method of manufacturing the metal interconnect structure. Manganese (Mn) is incorporated into a copper (Cu) interconnect structure in order to modify the microstructure to achieve bamboo-style grain boundaries in sub- | 10-31-2013 |
20130299988 | GRAPHENE CAP FOR COPPER INTERCONNECT STRUCTURES - Interconnect structures including a graphene cap located on exposed surfaces of a copper structure are provided. In some embodiments, the graphene cap is located only atop the uppermost surface of the copper structure, while in other embodiments the graphene cap is located along vertical sidewalls and atop the uppermost surface of the copper structure. The copper structure is located within a dielectric material. | 11-14-2013 |
20130299989 | CHIP CONNECTION STRUCTURE AND METHOD OF FORMING - Chip connection structures and related methods of forming such structures are disclosed. In one case, an interconnect structure is disclosed, the structure including: a pillar connecting an integrated circuit chip and a substrate, the pillar including a barrier layer, a first copper layer over the barrier layer, and a first solder layer over the first copper layer. | 11-14-2013 |
20130299990 | SINGLE METAL DAMASCENE STRUCTURE AND METHOD OF FORMING THE SAME - A single metal damascene structure including an insulating layer, a metal filling layer and a barrier layer is provided. The insulating layer has an opening therein, and the metal filling layer is positioned in the opening. The barrier layer is located between the filling metal layer and the insulating layer. The material of the barrier layer includes an alloy, and the ally includes a copper element and at least one another metal. | 11-14-2013 |
20130299991 | Semiconductor Device and Manufacturing Method Thereof - A semiconductor film having an impurity region to which at least an n-type or p-type impurity is added and a wiring are provided. The wiring includes a diffusion prevention film containing a conductive metal oxide, and a low resistance conductive film over the diffusion prevention film. In a contact portion between the wiring and the semiconductor film, the diffusion prevention film and the impurity region are in contact with each other. The diffusion prevention film is framed in such a manner that a conductive film is exposed to plasma generated from a mixed gas of an oxidizing gas and a halogen-based gas to form an oxide of a metal material contained in the conductive film, the conductive film in which the oxide of the metal material is formed is exposed to an atmosphere containing water to be fluidized, and the fluidized conductive film is solidified. | 11-14-2013 |
20130299992 | Bump Structure for Stacked Dies - A bump structure that may be used for stacked die configurations is provided. Through-silicon vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-silicon vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-silicon vias. The isolation film is thinned to re-expose the through-silicon vias. Bump pads and redistribution lines are formed on the backside of the semiconductor substrate providing an electrical connection to the through-silicon vias. Another isolation film is deposited and patterned, and a barrier layer is formed to provide contact pads for connecting to an external device, e.g., another die/wafer or circuit board. | 11-14-2013 |
20130307153 | INTERCONNECT WITH TITANIUM-OXIDE DIFFUSION BARRIER - An interconnect structure located on a semiconductor substrate within a dielectric material positioned atop the semiconductor substrate is provided having an opening within the dielectric material, the opening includes an electrically conductive material extending from the bottom to the top, and contacting the sidewall; a first layer located on the sidewall of the opening, the first layer is made from a material including titanium oxide or titanium silicon oxide; a second layer located between the first layer and the electrically conductive material, the second layer is made from a material selected from the group TiXO | 11-21-2013 |
20130307154 | INTEGRATED CIRCUIT WIRING FABRICATION AND RELATED METHODS AND APPARATUS - Integrated circuits having electrically conductive traces are described. The electrically conductive traces may be formed of multiple electrically conductive layers. One or more of the multiple electrically conductive layers may have a cut formed therein to form a gap in that electrically conductive layer. One or more electrical conductive layers of the electrical conductive traces may bridge the gap. | 11-21-2013 |
20130313710 | Semiconductor Constructions and Methods of Forming Semiconductor Constructions - Some embodiments include semiconductor constructions. The constructions have an electrically conductive post extending through a semiconductor die. The post has an upper surface above a backside surface of the die, and has a sidewall surface extending between the backside surface and the upper surface. A photosensitive material is over the backside surface and along the sidewall surface. Electrically conductive material is directly against the upper surface of the post. The electrically conductive material is configured as a cap over the post. The cap has an edge that extends laterally outwardly beyond the post and encircles the post. An entirety of the edge is directly over the photosensitive material. Some embodiments include methods of forming semiconductor constructions having photosensitive material adjacent through-wafer interconnects, and having electrically conductive material caps over and directly against upper surfaces of the interconnects and directly against an upper surface of the photosensitive material. | 11-28-2013 |
20130320536 | INTEGRATED CIRCUIT INCLUDING WIRE STRUCTURE, RELATED METHOD AND DESIGN STRUCTURE - An integrated circuit (IC), design structure, and a method of making the same. In one embodiment, the IC includes: a substrate; a dielectric layer disposed on the substrate; a set of wire components disposed on the dielectric layer, the set of wire components including a first wire component disposed proximate a second wire component; a bond pad disposed on the first wire component, the bond pad including an exposed portion; a passivation layer disposed on the dielectric layer about a portion of the bond pad and the set of wire components, the passivation layer defining a wire structure via connected to the second wire component; and a wire structure disposed on the passivation layer proximate the bond pad and connected to the second wire component through the wire structure via. | 12-05-2013 |
20130320537 | THROUGH SILICON VIA (TSV) STRUCTURE AND PROCESS THEREOF - A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided. | 12-05-2013 |
20130320538 | Integrated Circuit Substrates Comprising Through-Substrate Vias And Methods Of Forming Through-Substrate Vias - A method of forming a through-substrate via includes forming a through-substrate via opening at least partially through a substrate from one of opposing sides of the substrate. A first material is deposited to line and narrow the through-substrate via opening. The first material is etched to widen at least an elevationally outermost portion of the narrowed through-substrate via opening on the one side. After the etching, a conductive second material is deposited to fill the widened through-substrate via opening. Additional implementations are disclosed. Integrated circuit substrates are disclosed independent of method of manufacture. | 12-05-2013 |
20130320539 | Method and Apparatus for Back End of Line Semiconductor Device Processing - Methods and apparatus are disclosed for the back end of line process for fabrication of integrated circuits (ICs). The inter-metal dielectric (IMD) layer between two metal layers may comprise an etching stop layer over a metal layer, a low-k dielectric layer over the etching stop layer, a dielectric hard mask layer over the low-k dielectric layer, an nitrogen free anti-reflection layer (NFARL) over the dielectric hard mask layer, and a metal-hard-mask (MHM) layer of a thickness in a range from about 180 Å to about 360 Å over the NFARL. The MHM layer thickness is optimized at the range from about 180 Å to about 360 Å to reduce the Cu pits while avoiding the photo overlay shifting issue. | 12-05-2013 |
20130320540 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a substrate, a conductive material, and a material layer. The substrate includes a through hole. The conductive material fills the through hole. The material layer is formed in the conductive material, wherein an electrical resistance of the conductive material is lower than an electrical resistance of the material layer. | 12-05-2013 |
20130320541 | SEMICONDUCTOR DEVICE CONTACT STRUCTURES - Semiconductor contact structures extend through a dielectric material and provide contact to multiple different subjacent materials including a silicide material and a non-silicide material such as doped silicon. The contact structures includes a lower composite layer formed using a multi-step ionized metal plasma (IMP) deposition operation. A lower IMP film is formed at a high AC bias power followed by the formation of an upper IMP film at a lower AC bias power. The composite layer may be formed of titanium. A further layer is formed as a liner over the composite layer and the liner layer may advantageously be formed using CVD and may be TiN. A conductive plug material such as tungsten or copper fills the contact openings. | 12-05-2013 |
20130320542 | Method of fabricating a self-aligned buried bit line for a vertical channel dram - A method of fabricating a self-aligned buried bit line in a structure which makes up a portion of a vertical channel DRAM. The materials and processes used enable self-alignment of elements of the buried bit line during the fabrication process. In addition, the materials and processes used enable for formation of individual DRAM cells which have a buried bit line width which is 16 nm or less. | 12-05-2013 |
20130328196 | SEMICONDUCTOR DEVICE WITH MULTI-LAYERED STORAGE NODE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a first dielectric structure over a second region of a substrate to expose a first region of the substrate, forming a barrier layer over an entire surface including the first dielectric structure, forming a second dielectric structure over the barrier layer in the first region, forming first open parts and second open parts in the first region and the second region, respectively, by etching the second dielectric structure, the barrier layer and the first dielectric structure, forming first conductive patterns filled in the first open parts and second conductive patterns filled in the second open parts, forming a protective layer to cover the second region, and removing the second dielectric structure. | 12-12-2013 |
20130328197 | ELECTRONIC DEVICE AND METHOD FOR PRODUCTION - An electronic device and method for production is disclosed. One embodiment provides an integrated component having a first layer which is composed of copper or a copper alloy or which contains copper or a copper alloy, and having an electrically conductive second layer, whose material differs from the material of the first layer, and a connection apparatus which is arranged on the first layer and on the second layer. | 12-12-2013 |
20130328198 | REVERSE DAMASCENE PROCESS - The present disclosure relates to a method of forming a back-end-of-the-line metallization layer. The method is performed by forming a plurality of freestanding metal layer structures (i.e., metal layer structures not surrounded by a dielectric material) on a semiconductor substrate within an area defined by a patterned photoresist layer. A diffusion barrier layer is deposited onto the metal layer structure in a manner such that the diffusion barrier layer conforms to the top and sides of the metal layer structure. A dielectric material is formed on the surface of the substrate to fill areas between metal layer structures. The substrate is planarized to remove excess metal and dielectric material and to expose the top of the metal layer structure. | 12-12-2013 |
20130334690 | SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF - A semiconductor structure includes a work function metal layer, a (work function) metal oxide layer and a main electrode. The work function metal layer is located on a substrate. The (work function) metal oxide layer is located on the work function metal layer. The main electrode is located on the (work function) metal oxide layer. Moreover a semiconductor process forming said semiconductor structure is also provided. | 12-19-2013 |
20130334691 | SIDEWALLS OF ELECTROPLATED COPPER INTERCONNECTS - A structure formed in an opening having a substantially vertical sidewall defined by a non-metallic material and having a substantially horizontal bottom defined by a conductive pad, the structure including a diffusion barrier covering the sidewall and a fill composed of conductive material. The structure including a first intermetallic compound separating the diffusion barrier from the conductive material, the first intermetallic compound comprises an alloying material and the conductive material, and is mechanically bound to the conductive material, the alloying material is at least one of the materials selected from the group of chromium, tin, nickel, magnesium, cobalt, aluminum, manganese, titanium, zirconium, indium, palladium, and silver; and a first high friction interface located between the diffusion barrier and the first intermetallic compound and parallel to the sidewall of the opening, wherein the first high friction interface results in a mechanical bond between the diffusion barrier and the first intermetallic compound. | 12-19-2013 |
20130341793 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To improve reliability of a semiconductor device by improving an EM characteristic, a TDDB characteristic, and a withstand voltage characteristic of the semiconductor device. | 12-26-2013 |
20130341794 | ULTRA-THIN COPPER SEED LAYER FOR ELECTROPLATING INTO SMALL FEATURES - An apparatus and process are described that allow electroplating to fill sub-micron, high aspect ratio semiconductor substrate features using a non-copper/pre-electroplating layer on at least upper portions of side walls of the features, thereby providing reliable bottom up accumulation of the electroplating fill material in the feature. This apparatus and process eliminates feature filling material voids and enhances reliability of the electroplating in the diminishing size of features associated with future technology nodes of 22, 15, 11, and 8 nm. The presence of non-copper pre-electroplating material on the side walls allows the feature whose side walls, but not bottom surface, are lined with such pre-electroplating material (such as cobalt) to fill the feature using electroplated fill material accumulating from the bottom of the feature up to reliability and predictability and substantially void-free. | 12-26-2013 |
20140001634 | CHIP PACKAGE AND METHODS FOR MANUFACTURING A CHIP PACKAGE | 01-02-2014 |
20140001635 | Package with Passive Devices and Method of Forming the Same | 01-02-2014 |
20140008799 | METHOD FOR FABRICATING METAL LINE AND DEVICE WITH METAL LINE - A metal line fabricating method includes the following steps. Firstly, a substrate is provided. Then, a first barrier layer is formed over the substrate. A first dielectric layer is formed over the first barrier layer. An opening is formed in the first dielectric layer, wherein the opening runs through the first dielectric layer, so that the first barrier layer is exposed to the opening. A metal deposition process is performed to form a metal line over the exposed first barrier layer at a bottom of the opening. The first dielectric layer and the first barrier layer underlying the first dielectric layer are removed, but the metal line and the first barrier layer underlying the metal line are remained. Afterwards, a second dielectric layer is formed over the substrate which is provided with the metal line and the first barrier layer. | 01-09-2014 |
20140008800 | METHOD FOR MANUFACTURING THROUGH SUBSTRATE VIA (TSV), STRUCTURE AND CONTROL METHOD OF TSV CAPACITANCE - A method for manufacturing a through substrate via (TSV) structure, a TSV structure, and a control method of a TSV capacitance are provided. The method for manufacturing the TSV structure includes: providing a substrate having a first surface and a second surface; forming a trench in the first surface of the substrate; filling a low resistance material into the trench; forming an insulating layer on the first surface of the substrate; forming at least one opening in the first surface of the substrate, wherein the opening is located differently the trench; forming an oxide liner layer, a barrier layer and a conductive seed layer on a sidewall and a bottom of the opening and on the insulating layer of the first surface; and filling a conductive material into the opening, wherein the opening is used to form at least one via. | 01-09-2014 |
20140008801 | SUBMICRON CONNECTION LAYER AND METHOD FOR USING THE SAME TO CONNECT WAFERS - A submicron connection layer and a method for using the same to connect wafers is disclosed. The connection layer comprises a bottom metal layer formed on a connection surface of a wafer, an intermediary diffusion-buffer metal layer formed on the bottom metal layer, and a top metal layer formed on the intermediary diffusion-buffer metal layer. The melting point of the intermediary diffusion-buffer metal layer is higher than the melting points of the top and bottom metal layers. The top and bottom metal layers may form a eutectic phase. During bonding wafers, two top metal layers are joined in a liquid state; next the intermediary diffusion-buffer metal layers are distributed uniformly in the molten top metal layers; then the top and bottom metal layers diffuse to each other to form a low-resistivity eutectic intermetallic compound until the top metal layers are completely exhausted by the bottom metal layers. | 01-09-2014 |
20140015136 | IC DEVICE INCLUDING PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME - Various embodiments provide semiconductor devices including a package structure and methods of forming the semiconductor devices. In one embodiment, the package structure can include a through-hole at least partially filled by one or more layers of material(s) to form a through-hole interconnect between semiconductor devices in the package structure. The through-hole can be filled by an insulating layer, a diffusion barrier layer, a metal interconnect layer, and/or a protective layer having a total thickness from the sidewall of the through-hole of less than or equal to the radius of the through-hole. | 01-16-2014 |
20140015137 | SEMICONDUCTOR DEVICES AND THE METHOD OF MANUFACTURING THE SAME - A semiconductor device may include a first interlayer dielectric layer including a plurality of contacts, a plurality of interconnection patterns disposed on the first interlayer dielectric layer and connected to the contacts, respectively, and a second interlayer dielectric layer disposed on the first interlayer dielectric layer and covering the interconnection patterns. Each of the interconnection patterns may include a first metal pattern, a second metal pattern disposed on the first metal pattern, a first barrier pattern between the contact and the first metal pattern, and a second barrier pattern between the first metal pattern and the second metal pattern. The second metal pattern may expose a portion of a top surface of the second barrier pattern, and the second interlayer dielectric layer may include an air gap between the interconnection patterns adjacent to each other. | 01-16-2014 |
20140021611 | Novel Copper Etch Scheme for Copper Interconnect Structure - The present disclosure is directed to a method of manufacturing an interconnect structure in which a low-k dielectric layer is formed over a semiconductor substrate followed by formation of a copper or copper alloy layer over the low-k dielectric layer. The copper or copper alloy layer is patterned and etched to form a copper body having recesses, which are then filled with a low-k dielectric material. The method allows for formation of a damascene structures without encountering the various problems presented by non-planar features and by porus low-K dielectric damage. | 01-23-2014 |
20140021612 | SEMICONDUCTOR DEVICE AND FABRICATING PROCESS FOR THE SAME - A semiconductor device and a fabricating process for the same are provided. The semiconductor device includes a base layer having a part of a reactive material; and a self-assembled protecting layer of a self-assembled molecule reacting with the reactive material formed over the part. | 01-23-2014 |
20140021613 | MULTI-LAYER BARRIER LAYER FOR INTERCONNECT STRUCTURE - A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate. An adhesion barrier layer is formed to line the recess. A first stress level is present across a first interface between the adhesion barrier layer and the dielectric layer. A stress-reducing barrier layer is formed over the adhesion barrier layer. The stress-reducing barrier layer reduces the first stress level to provide a second stress level, less than the first stress level, across a second interface between the adhesion barrier layer, the stress-reducing barrier layer, and the dielectric layer. The recess is filled with a fill layer. | 01-23-2014 |
20140021614 | Hybrid interconnect scheme including aluminum metal line in low-k dielectric - A device includes a first low-k dielectric layer, and a copper-containing via in the first low-k dielectric layer. The device further includes a second low-k dielectric layer over the first low-k dielectric layer, and an aluminum-containing metal line over and electrically coupled to the copper-containing via. The aluminum-containing metal line is in the second low-k dielectric layer. | 01-23-2014 |
20140021615 | MULTI-LAYER BARRIER LAYER STACKS FOR INTERCONNECT STRUCTURES - The present disclosure is generally directed to multi-layer barrier layer stacks for interconnect structures that may be used to reduce mechanical stress levels between the interconnect structure and a dielectric material layer in which the interconnect structure is formed. One illustrative method disclosed herein includes forming a recess in a dielectric layer of a substrate and forming an adhesion barrier layer including an alloy of tantalum and at least one transition metal other than tantalum to line the recess, wherein forming the adhesion barrier layer includes creating a first stress level across a first interface between the adhesion barrier layer and the dielectric layer. The method also includes forming a stress-reducing barrier layer including tantalum over the adhesion barrier layer, wherein the stress-reducing barrier layer reduces the first stress level to a second stress level less than the first stress level, and filling the recess with a fill layer. | 01-23-2014 |
20140027908 | Integrated Circuit Interconnects and Methods of Making Same - A copper alloy layer is blanket deposited over a low k dielectric layer and in via openings within the low k dielectric layer. The blanket deposited layer is then anisotropically etch to form horizontal interconnects. The interconnects are annealed to form a metal oxide barrier lining. A second low k dielectric layer is then depositing over the horizontal interconnects. Air gaps can be formed between adjacent interconnects to lower parasitic capacitance therebetween. | 01-30-2014 |
20140027909 | METALLIZATION OF FLUOROCARBON-BASED DIELECTRIC FOR INTERCONNECTS - Embodiments of the present disclosure are directed towards metallization of a fluorocarbon-based dielectric material for interconnect applications. In one embodiment, an apparatus includes a semiconductor substrate, a device layer disposed on the semiconductor substrate, the device layer including one or more transistor devices, and an interconnect layer disposed on the device layer, the interconnect layer comprising a fluorocarbon-based dielectric material, where x represents a stoichiometric quantity of fluorine relative to carbon in the dielectric material, and one or more interconnect structures configured to route electrical signals to or from the one or more transistor devices, the one or more interconnect structures comprising cobalt (Co), or ruthenium (Ru), or combinations thereof. Other embodiments may be described and/or claimed. | 01-30-2014 |
20140027910 | METHOD FOR REDUCING WETTABILITY OF INTERCONNECT MATERIAL AT CORNER INTERFACE AND DEVICE INCORPORATING SAME - A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate, forming a first transition metal layer in the recess on corner portions of the recess, and forming a second transition metal layer in the recess over the first transition metal layer to line the recess. The method further includes filling the recess with a fill layer and annealing the substrate so that the first transition metal layer and the second transition metal layer form an alloy portion proximate the corner portions during the annealing, the alloy portion having a reduced wettability for a material of the fill layer than the second transition metal. Additionally, the method includes polishing the substrate to remove portions of the fill layer extending above the recess. | 01-30-2014 |
20140027911 | SIDEWALLS OF ELECTROPLATED COPPER INTERCONNECTS - A structure formed in an opening having a substantially vertical sidewall defined by a non-metallic material and having a substantially horizontal bottom defined by a conductive pad, the structure including a diffusion barrier covering the sidewall and a fill composed of conductive material. The structure including a first intermetallic compound separating the diffusion barrier from the conductive material, the first intermetallic compound comprises an alloying material and the conductive material, and is mechanically bound to the conductive material, the alloying material is at least one of the materials selected from the group of chromium, tin, nickel, magnesium, cobalt, aluminum, manganese, titanium, zirconium, indium, palladium, and silver; and a first high friction interface located between the diffusion barrier and the first intermetallic compound and parallel to the sidewall of the opening, wherein the first high friction interface results in a mechanical bond between the diffusion barrier and the first intermetallic compound. | 01-30-2014 |
20140027912 | SIDEWALLS OF ELECTROPLATED COPPER INTERCONNECTS - A structure formed in an opening having a substantially vertical sidewall defined by a non-metallic material and having a substantially horizontal bottom defined by a conductive pad, the structure including a diffusion barrier covering the sidewall and a fill composed of conductive material. The structure including a first intermetallic compound separating the diffusion barrier from the conductive material, the first intermetallic compound comprises an alloying material and the conductive material, and is mechanically bound to the conductive material, the alloying material is at least one of the materials selected from the group of chromium, tin, nickel, magnesium, cobalt, aluminum, manganese, titanium, zirconium, indium, palladium, and silver; and a first high friction interface located between the diffusion barrier and the first intermetallic compound and parallel to the sidewall of the opening, wherein the first high friction interface results in a mechanical bond between the diffusion barrier and the first intermetallic compound. | 01-30-2014 |
20140035141 | SELF ALIGNED BORDERLESS CONTACT - A method of fabricating a semiconductor structure having a borderless contact, the method including providing a first semiconductor device adjacent to a second semiconductor device, the first and second semiconductor devices being formed on a semiconductor substrate, depositing a non-conductive liner on top of the semiconductor substrate and the first and second semiconductor devices, depositing a contact level dielectric layer on top of the non-conductive liner, etching a contact hole in the contact-level dielectric between the first semiconductor device and the second semiconductor device, and selective to the non-conductive liner, converting a portion of the non-conductive liner exposed in the contact hole into a conductive liner; and forming a metal contact in the contact hole. | 02-06-2014 |
20140035142 | PROFILE CONTROL IN INTERCONNECT STRUCTURES - The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of the line opening prevents rounding of the corners of a dielectric material portion that is present beneath the line opening and adjacent the via opening. | 02-06-2014 |
20140035143 | METHOD OF REDUCING CONTACT RESISTANCE OF A METAL - A structure for an integrated circuit with reduced contact resistance is disclosed. The structure includes a substrate, a cap layer deposited on the substrate, a dielectric layer deposited on the cap layer, and a trench embedded in the dielectric layer. The trench includes an atomic layer deposition (ALD) TaN or a chemical vapor deposition (CVD) TaN deposited on a side wall of the trench, a physical vapor deposition (PVD) Ta or a combination of the PVD Ta and a PVD TaN deposited on the ALD TaN or CVD TaN, and a Cu deposited on the PVD Ta or the combination of the PVD Ta and the PVD TaN deposited on the ALD TaN or the CVD TaN. The structure further includes a via integrated into the trench at bottom of the filled trench. | 02-06-2014 |
20140035144 | Semiconductor Devices Having Through Electrodes and Methods of Fabricating the Same - Provided are semiconductor devices having through electrodes and methods of fabricating the same. The method includes providing a substrate including top and bottom surfaces facing each other, forming a hole and a gap extending from the top surface of the substrate toward the bottom surface of the substrate, the gap surrounding the hole and being shallower than the hole, filling the hole with an insulating material, forming a metal interconnection line on the top surface of the substrate on the insulating material, recessing the bottom surface of the substrate to expose the insulating material, removing the insulating material to expose the metal interconnection line via the hole, filling the hole with a conductive material to form a through electrode connected to the metal interconnection line, recessing the bottom surface of the substrate again to expose the gap, and forming a lower insulating layer on the bottom surface of the substrate. | 02-06-2014 |
20140035145 | SEMICONDUCTOR DEVICE - A semiconductor device includes a GaAs substrate having a first major surface and a second major surface opposite to each other; a nickel diffusion barrier disposed on the first major surface of the GaAs substrate. The nickel diffusion barrier consists of a single layer of Pd. A nickel-containing layer is disposed on the nickel diffusion barrier and the nickel diffusion barrier is interposed between the first major surface of the GaAs substrate and the nickel-containing layer. The nickel diffusion barrier prevents nickel from diffusing from the nickel-containing layer into the GaAs substrate. | 02-06-2014 |
20140042625 | BONDING LAYER STRUCTURE AND METHOD FOR WAFER TO WAFER BONDING - A structure comprises a first semiconductor substrate, a first bonding layer deposited on a bonding side the first semiconductor substrate, a second semiconductor substrate stacked on top of the first semiconductor substrate and a second bonding layer deposited on a bonding side of the second semiconductor substrate, wherein the first bonding layer is of a horizontal length greater than a horizontal length of the second semiconductor substrate, and wherein there is a gap between an edge of the second bonding layer and a corresponding edge of the second semiconductor substrate. | 02-13-2014 |
20140042626 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a plurality of mask patterns by anisotropically etching a mask-forming film until upper surfaces of core patterns are exposed. A facing pair includes a pair of the mask patterns facing the core pattern located between the paired mask patterns. The mask patterns of the facing pair have respective lower portions spaced from each other by a first distance. An adjacent pair includes a pair of mask patterns adjacent to each other with a space having no core pattern. The mask patterns of the adjacent pair have respective lower portions spaced from each other by a second distance. The mask patterns are formed so that the second distance is larger than the first distance. | 02-13-2014 |
20140048937 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate having two surfaces. First side faces second side and includes recesses, and a plurality of through silicon vias (TSV), which penetrate through the semiconductor substrate, are exposed by the recesses. Even when the TSVs have different heights from each other or the degree of back-grinding is changed, due to a process parameters, yield of the semiconductor device is improved by reducing failure caused when a TSV is not exposed. | 02-20-2014 |
20140048938 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method for fabricating the same are disclosed, which can prevent migration of copper (Cu) ion when forming a Through Silicon Via (TSV). The semiconductor device includes a through silicon via (TSV) formed to pass through a semiconductor substrate; an oxide film located at a lower sidewall of the TSV; and a first prevention film formed to cover an upper portion of the TSV, an upper sidewall of the TSV, and an upper surface of the oxide film. | 02-20-2014 |
20140048939 | SEMICONDUCTOR DEVICE HAVING METAL PLUG AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first insulating layer on a substrate; a first contact hole passing through the first insulating layer and exposing an upper surface of the substrate; a first barrier metal layer disposed on a sidewall and at a bottom of the first contact hole and a first metal plug disposed on the first barrier metal layer and in the first contact hole. A recess region is between the first insulating layer and the first metal plug. A gap-fill layer fills the recess region; and a second insulating layer is on the gap-fill layer. A second contact hole passes through the second insulating layer and exposes the upper surface of the first metal plug. A second barrier metal layer is on a sidewall and at the bottom of the second contact hole; and a second metal plug is on the second barrier metal layer. | 02-20-2014 |
20140048940 | Conductive Lines and Pads and Method of Manufacturing Thereof - A semiconductor device and method are disclosed. The semiconductor device includes a substrate having a first region and a second region and an insulating layer arranged on the substrate. A first conductive layer is arranged in or on insulating layer in the first region and a second conductive layer is arranged in or on the insulating layer in the second region. The first conductive layer comprises a first conductive material and the second conductive layer comprises a second conductive material wherein the first conductive material is different than the second conductive material. A metal layer is arranged on the first conductive layer. | 02-20-2014 |
20140054774 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A first through hole | 02-27-2014 |
20140054775 | SEMICONDUCTOR DEVICES INCLUDING METAL-SILICON-NITRIDE PATTERNS AND METHODS OF FORMING THE SAME - A semiconductor memory device can include a first conductive line crossing over a field isolation region and crossing over an active region of the device, where the first conductive line can include a first conductive pattern being doped, a second conductive pattern, and a metal-silicon-nitride pattern between the first and second conductive patterns and can be configured to provide a contact at a lower boundary of the metal-silicon-nitride pattern with the first conductive pattern and configured to provide a diffusion barrier at an upper boundary of the metal-silicon-nitride pattern with the second conductive pattern. | 02-27-2014 |
20140054776 | METHODS, DEVICES, AND MATERIALS FOR METALLIZATION - A method of making an electronic device which in one embodiment comprises providing a substrate, electrolessly depositing a barrier metal at least on portions of the substrate, and using wet chemistry such as electroless deposition to deposit a substantially gold-free wetting layer having solder wettability onto the barrier metal. An electronic device which in one embodiment comprises a metallization stack. The metallization stack comprises a barrier metal deposited electrolessly and a substantially gold-free wetting layer deposited on the barrier metal, and the wetting layer is wettable by solder. | 02-27-2014 |
20140054777 | SEMICONDUCTOR DEVICE WITH COPPER WIREBOND SITES AND METHODS OF MAKING SAME - Semiconductor devices with external wirebond sites that include copper and methods for fabricating such semiconductor devices are disclosed. One embodiment of a method for fabricating a semiconductor device comprises forming a dielectric layer on an active side of a semiconductor substrate. The dielectric layer has openings aligned with corresponding wirebond sites at the active side of the substrate. The method further includes forming a plurality of wirebond sites located at the openings in the dielectric layer. The wirebond sites are electrically coupled to an integrated circuit in the semiconductor substrate and electrically isolated from each other. Individual wirebond sites are formed by electrolessly depositing nickel into the openings and forming a wirebond film on the nickel without forming a seam between the nickel and the dielectric layer. | 02-27-2014 |
20140054778 | SEMICONDUCTOR DEVICE HAVING A COPPER PLUG - Disclosed is a semiconductor device wherein an insulation layer has a via opening with an aluminum layer in the via opening and in contact with the last wiring layer of the device. There is a barrier layer on the aluminum layer followed by a copper plug which fills the via opening. Also disclosed is a process for making the semiconductor device. | 02-27-2014 |
20140054779 | Semiconductor Having a High Aspect Ratio Via - The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having via sidewall surfaces defined by a semiconductor substrate. The via sidewall surfaces have a first portion and a second portion. A conductive layer is disposed in the via on the first portion of the via sidewall surfaces, and a dielectric layer is disposed on the second portion of the via sidewall surfaces. The dielectric layer is disposed between the second portion of the via sidewall surfaces and the conductive layer. In an example, the dielectric layer is an oxide layer. | 02-27-2014 |
20140061913 | Aluminum Interconnection Apparatus - An aluminum interconnection apparatus comprises a metal structure formed over a substrate, wherein the metal structure is formed of a copper and aluminum alloy, a first alloy layer formed underneath the metal structure and a first barrier layer formed underneath the first alloy layer, wherein the first barrier layer is generated by a reaction between the first alloy layer and an adjacent dielectric layer during a thermal process. | 03-06-2014 |
20140061914 | DOPING OF COPPER WIRING STRUCTURES IN BACK END OF LINE PROCESSING - A method of forming a metal interconnect structure includes forming a copper line within an interlevel dielectric (ILD) layer; directly doping a top surface of the copper line with a copper alloy material; and forming a dielectric layer over the ILD layer and the copper alloy material; wherein the copper alloy material serves an adhesion interface layer between the copper line and the dielectric layer. | 03-06-2014 |
20140061915 | PREVENTION OF THRU-SUBSTRATE VIA PISTONING USING HIGHLY DOPED COPPER ALLOY SEED LAYER - A method of forming an integrated circuit device includes forming a diffusion barrier layer in an opening defined in a substrate; forming a highly doped copper alloy seed layer over the diffusion barrier layer, the copper alloy seed layer having a minority alloy component having a concentration greater than 0.5% atomic; and forming a copper layer over the copper alloy seed layer so as to define a wiring structure of the integrated circuit device. | 03-06-2014 |
20140061916 | SEMICONDUCTOR DEVICE WITH LOW RESISTANCE WIRING AND MANUFACTURING METHOD FOR THE DEVICE - According to one embodiment, a semiconductor device includes an insulating film, a catalytic layer and a wiring layer. The insulating film has a hole. The catalytic layer is formed at the bottom of the hole, at the peripheral wall of the hole, and on the upper surface of the insulating film outside the hole. A contact is formed of a carbon nanotube provided on the portion of the catalytic layer at the bottom of the hole. The wiring layer is formed of graphene and provided on the catalytic layer outside the hole in contact with the carbon nanotube. The catalytic layer at the bottom of the hole is a perforated film, and the catalytic layer outside the hole is a continuous film. | 03-06-2014 |
20140061917 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device includes a lower conductor having a lower conductor sidewall, a barrier film having a barrier film sidewall formed directly on the lower conductor sidewall, and a via formed on a top surface of the lower conductor. A top portion of the barrier film sidewall is recessed, such that a top surface of the barrier film sidewall is at a level lower than the top surface of the lower conductor. | 03-06-2014 |
20140061918 | METHOD OF FORMING LOW RESISTIVITY TaNx/Ta DIFFUSION BARRIERS FOR BACKEND INTERCONNECTS - The present disclosure relates diffusion barrier layers for backend layers for interconnects and their methods of manufacturing. A TaN | 03-06-2014 |
20140061919 | Electroplated Metallic Interconnects And Products - One embodiment of the present invention is a device including at least a portion of a void-free electroplated metallic interconnect embedded in an opening, said opening having sidewalls, said sidewalls include at least one dielectric layer, wherein the opening has an aspect ratio in a range from 7:1 to 20:1, and wherein the portion of the electroplated metallic interconnect includes a material selected from a group consisting of Cu, Ag, and alloys including at least one of these metals. | 03-06-2014 |
20140061920 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first insulating film formed on a semiconductor substrate; a first interconnect formed on the first insulating film; a second insulating film formed on the first insulating film to cover the first interconnect; and a second interconnect formed on the second insulating film. The second interconnect includes a barrier layer formed on the second insulating film, and a plated layer formed on the barrier layer. The barrier layer prevents diffusion of atoms forming the plated layer into the second insulating film, and has a greater width than the plated layer. | 03-06-2014 |
20140070417 | SEMICONDUCTOR DEVICE HAVING BARRIER METAL LAYER - According to one embodiment, a semiconductor device having an interlayer insulating film, a molybdenum containing layer, a barrier metal layer and a plug material layer is provided. The interlayer insulating film is formed on a substrate or on a conductive layer formed on a substrate. The interlayer insulating film has a hole reaching the substrate or the conductive layer. The molybdenum containing layer is formed in the substrate or in the conductive layer at a bottom portion of the hole. The barrier metal layer is formed on the molybdenum containing layer and on a side surface of the hole. A portion of the barrier metal layer is formed on the side surface contains at least molybdenum. A portion of the barrier metal layer is formed on the molybdenum containing layer includes at least a molybdenum silicate nitride film. The plug material layer is formed via the barrier metal layer. | 03-13-2014 |
20140070418 | SEMICONDUCTOR INTERCONNECT STRUCTURE HAVING ENHANCED PERFORMANCE AND RELIABILITY - An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by minimizing oxygen intrusion into a seed layer and an electroplated copper layer of the interconnect structure, are disclosed. At least one opening in a dielectric layer is formed. A sacrificial oxidation layer disposed on the dielectric layer is formed. The sacrificial oxidation layer minimizes oxygen intrusion into the seed layer and the electroplated copper layer of the interconnect structure. A barrier metal layer disposed on the sacrificial oxidation layer is formed. A seed layer disposed on the barrier metal layer is formed. An electroplated copper layer disposed on the seed layer is formed. A planarized surface is formed, wherein a portion of the sacrificial oxidation layer, the barrier metal layer, the seed layer, and the electroplated copper layer are removed. In addition, a capping layer disposed on the planarized surface is formed. | 03-13-2014 |
20140077377 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - According to one embodiment, the semiconductor device in the embodiment has an assembly substrate, a semiconductor chip, and a jointing layer. The semiconductor chip is joined to the assembly substrate via the jointing layer. An intervening diffusion barrier layer may be interposed between the chip and jointing layer. The jointing layer is an alloy layer mainly made of any metal selected from Sn, Zn and In or an alloy of Sn, Zn and In, and any metal selected from Cu, Ni, Ag, Cr, Zr, Ti and V or an alloy of any metal selected from Cu, Ni, Ag, Cr, Zr, Ti and V and any metal selected from Sn, Zn and In, where the alloy has a higher melting temperature than that of Sn, Zn and In or an alloy of Sn, Zn and/or In. | 03-20-2014 |
20140084469 | METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A patterned dielectric layer with a plurality of openings is formed on the substrate. A barrier layer is deposited in the openings by a first tool and a sacrificing protection layer is deposited on the barrier layer by the first tool. The sacrificing layer is removed and a metal layer is deposited on the barrier layer by a second tool. | 03-27-2014 |
20140084470 | Seed Layer Structure and Method - A seed layer comprises a bottom seed layer portion formed on the bottom of a via opening, a sidewall seed layer portion formed on an upper portion of the sidewall of the via opening and a corner seed layer portion formed between the bottom seed layer portion and the sidewall seed layer portion. The sidewall seed layer portion is of a first thickness. The corner seed layer portion is of a second thickness and the second thickness is greater than the first thickness. | 03-27-2014 |
20140084471 | Interconnect Structures Comprising Flexible Buffer Layers - A structure includes a substrate, a low-k dielectric layer over the substrate, and a conductive barrier layer extending into the low-k dielectric layer. The conductive barrier layer includes a sidewall portion. A metal line in the low-k dielectric layer adjoins the conductive barrier layer. An organic buffer layer is between the sidewall portion of the conductive barrier layer and the low-k dielectric layer. | 03-27-2014 |
20140084472 | COMPOUND DIELECTRIC ANTI-COPPER-DIFFUSION BARRIER LAYER FOR COPPER CONNECTION AND MANUFACTURING METHOD THEREOF - The disclosure belongs to the field of manufacturing and interconnection of integrated circuits, and in particular relates to compound dielectric anti-copper-diffusion barrier layer for copper interconnection and a manufacturing method thereof The disclosure uses compound dielectric (oxide & metal) as the anti-copper-diffusion barrier layer. First, it can enhance the capable of metal for anti-copper-diffusion efficiently, and prevent the barrier layer for valid owing to oxidized and prolong the life of the barrier layer. Second, it can reduce the effective dielectric constant of the interconnection circuits and furthermore reduce the RC delay of the whole interconnection circuits. Besides, the alloy is firmly adhered to the copper, and the metal copper can be directly electroplated without growing a layer of seed crystal copper. The method is simple and feasible and is expected to be applied to manufacturing of the anti-copper-diffusion barrier layers for copper interconnections. | 03-27-2014 |
20140084473 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - Provided are semiconductor devices and methods of fabricating the same. The device may include a substrate including a first surface and a second surface opposing each other, a through-silicon-via (TSV) electrode provided in a via hole that may be formed to penetrate the substrate, and an integrated circuit provided adjacent to the through electrode on the first surface. The through electrode includes a metal layer filling a portion of the via hole and an alloy layer filling a remaining portion of the via hole. The alloy layer contains at least two metallic elements, one of which may be the same as that contained in the metal layer, and the other of which may be different from that contained in the metal layer. | 03-27-2014 |
20140084474 | METHOD FOR FORMING A VERTICAL ELECTRICAL CONNECTION IN A LAYERED SEMICONDUCTOR STRUCTURE - The invention proposes a method for forming a vertical electrical connection ( | 03-27-2014 |
20140091467 | FORMING BARRIER WALLS, CAPPING, OR ALLOYS /COMPOUNDS WITHIN METAL LINES - Described herein are techniques structures related to forming barrier walls, capping, or alloys/compounds such as treating copper so that an alloy or compound is formed, to reduce electromigration (EM) and strengthen metal reliability which degrades as the length of the lines increases in integrated circuits. | 04-03-2014 |
20140097538 | SEMICONDUCTOR DEVICE HAVING A SELF-FORMING BARRIER LAYER AT VIA BOTTOM - An approach for forming a semiconductor device is provided. In general, the device is formed by providing a metal layer, a cap layer over the metal layer, and an ultra low k layer over the cap layer. A via is then formed through the ultra low k layer and the cap layer. Once the via is formed, a barrier layer (e.g., cobalt (Co), tantalum (Ta), cobalt-tungsten-phosphide (CoWP), or other metal capable of acting as a copper (CU) diffusion barrier) is selectively applied to a bottom surface of the via. A liner layer (e.g., manganese (MN) or aluminum (AL)) is then applied to a set of sidewalls of the via. The via may then be filled with a subsequent metal layer (with or without a seed layer), and the device may the then be further processed (e.g., annealed). | 04-10-2014 |
20140103529 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS AND STORAGE MEDIUM - In order to obtain a semiconductor device having an embedded electrode with low cost and high reliability, a semiconductor device manufacturing method includes forming a first film made of a metal oxide within an opening which is formed in an insulating film formed on a surface of a substrate; performing a hydrogen radical treatment by irradiating atomic hydrogen to the first film; forming a second film made of a metal within the opening after the performing of the hydrogen radical treatment; and forming an electrode made of a metal within the opening after the forming of the second film. | 04-17-2014 |
20140110844 | WIRE BONDABLE SURFACE FOR MICROELECTRONIC DEVICES - The present invention concerns thin diffusion barriers in metal and metal alloy layer sequences of contact area/barrier layer/first bonding layer type for metal wire bonding applications. The diffusion barrier is selected from Co-M-P. Co-M-B and Co-M-B—P alloys wherein M is selected from Mn, Zr, Re, Mo, Ta and W having a thickness in the range 0.03 to 0.3 μm. The first bonding layer is selected from palladium and palladium alloys. | 04-24-2014 |
20140117545 | COPPER HILLOCK PREVENTION WITH HYDROGEN PLASMA TREATMENT IN A DEDICATED CHAMBER - A copper layer is formed without copper hillocks. Embodiments includes providing a copper layer above a substrate, planarizing the copper layer, performing hydrogen (H | 05-01-2014 |
20140117546 | HYBRID BONDING MECHANISMS FOR SEMICONDUCTOR WAFERS - The embodiments of diffusion barrier layer described above provide mechanisms for forming a copper diffusion barrier layer to prevent device degradation for hybrid bonding of wafers. The diffusion barrier layer(s) encircles the copper-containing conductive pads used for hybrid bonding. The diffusion barrier layer can be on one of the two bonding wafers or on both bonding wafers. | 05-01-2014 |
20140117547 | BARRIER LAYER FOR COPPER INTERCONNECT - A method for forming an interconnect structure includes forming a dielectric layer overlying a substrate, forming a metal-containing layer in the dielectric layer, forming a barrier layer overlying the metal-containing layer, and performing a thermal process to form a metal oxide layer underlying the conductive layer. The metal oxide layer is a barrier layer formed at the boundary between the dielectric layer and the metal-containing layer. | 05-01-2014 |
20140117548 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device of an embodiment includes: a substrate on which a semiconductor circuit is formed; an interlayer insulating film in which a contact hole is formed on the substrate; a catalyst metal film on a side wall of the contact hole; catalyst metal particles on a bottom of the contact hole; graphene on the catalyst metal film; and carbon nanotubes, which penetrates the contact hole, on the catalyst metal particles. | 05-01-2014 |
20140117549 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes the steps of immersing a substrate in a solution containing metal ions to adhere a metal catalyst to a surface of the substrate, immersing the substrate with the metal catalyst adhered thereto in an electroless plating solution to electrolessly plate a layer on the substrate, immersing the substrate in an electroplating solution to electroplate a layer on the electrolessly plated layer using the electrolessly plated layer as a power feeding layer, and forming a metal layer of Cu or Ag on the electroplated layer. The electroplated layer is formed of a different material than the metal layer. | 05-01-2014 |
20140117550 | SEMICONDUCTOR DEVICE INCLUDING AN INSULATING LAYER, AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE - A method of forming a semiconductor device, includes depositing first copper material by physical vapor deposition (PVD) on an insulating layer and on a barrier material formed on a sidewall and a bottom of a trench in the insulating layer, heating the first copper material to reflow the first copper material into the trench, depositing a second copper material by PVD on the insulating layer, on the barrier material and on the first copper material, and heating the second copper material to reflow the second copper material into the trench such that the second copper material is formed on the first copper material and on the sidewall of the trench, the first and second copper materials forming a copper layer in the trench, an amount of sulfur and chlorine in the copper layer being less than 1ppm. | 05-01-2014 |
20140117551 | PROCESSING SYSTEM FOR FORMING FILM ON TARGET OBJECT - A processing system for forming a film on a target object having thereon an insulating layer that is made of a low-k film and having a recess is provided. The processing system comprises: a processing apparatus configured to form a first-metal-containing film containing a first metal on a surface of the target object; a processing apparatus configured to form a second-metal-containing film containing Mn as a second metal having a barrier property against a filling metal to be filled in the recess; a processing apparatus configured to form a thin film made of a third metal as the filling metal to be filled; a common transfer chamber connected with each of the processing apparatuses; a transfer unit for transferring the target object into each of the processing apparatuses; and a system controller that controls the whole processing system so as to perform a film forming method. | 05-01-2014 |
20140124932 | INTEGRATED CIRCUIT DEVICE HAVING A COPPER INTERCONNECT - A method of forming an interconnect structure of an integrated circuit including providing a first dielectric layer disposed on a semiconductor substrate. A via (or via hole) is etched in the first dielectric layer. A conductive layer including copper is formed that fills the via hole and has a first portion that is disposed on a top surface of the first dielectric layer. A trench is formed in the first portion of the conductive layer to pattern a copper interconnect line disposed on the first dielectric layer. The trench is filled with a second dielectric material. In an embodiment, a barrier layer is self-formed during the removal of a masking element used in the etching of the trench. | 05-08-2014 |
20140124933 | COPPER INTERCONNECT STRUCTURES AND METHODS OF MAKING SAME - A structure and method of making the structure. The structure includes a dielectric layer on a substrate; a first wire formed in a first trench in the dielectric layer, a first liner on sidewalls and a bottom of the first trench and a first copper layer filling all remaining space in the first trench; a second wire formed in a second trench in the dielectric layer, a second liner on sidewalls and a bottom of the second trench and a second copper layer filling all remaining space in the second trench; and an electromigration stop formed in a third trench in the dielectric layer, a third liner on sidewalls and a bottom of the third trench and a third copper layer filling all remaining space in the third trench, the electromigration stop between and abutting respective ends of the first and second wires. | 05-08-2014 |
20140124934 | INTERCONNECT WITH TITANIUM-OXIDE DIFFUSION BARRIER - An interconnect structure located on a semiconductor substrate within a dielectric material positioned atop the semiconductor substrate is provided having an opening within the dielectric material, the opening includes an electrically conductive material extending from the bottom to the top, and contacting the sidewall; a first layer located on the sidewall of the opening, the first layer is made from a material including titanium oxide or titanium silicon oxide; a second layer located between the first layer and the electrically conductive material, the second layer is made from a material selected from the group TiXO | 05-08-2014 |
20140131872 | COPPER ETCHING INTEGRATION SCHEME - The present disclosure is directed to a method of manufacturing an interconnect structure in which a sacrificial layer is formed over a semiconductor substrate followed by etching of the sacrificial layer to form a first feature. The metal layer is patterned and etched to form a second feature, followed by deposition of a low-k dielectric material. The method allows for formation of an interconnect structure without encountering the various problems presented by porous low-k dielectric damage. | 05-15-2014 |
20140131873 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes an insulation film formed above a semiconductor substrate, a conductor containing Cu formed in the insulation film, and a layer film formed between the insulation film and the conductor and formed of a first metal film containing Ti and a second metal film different from the first metal film, a layer containing Ti and Si is formed on the surface of the conductor. | 05-15-2014 |
20140138832 | COPPER SEED LAYER FOR AN INTERCONNECT STRUCTURE HAVING A DOPING CONCENTRATION LEVEL GRADIENT - A trench is opened in a dielectric layer. The trench is then lined with a barrier layer and a metal seed layer. The metal seed layer is non-uniformly doped and exhibits a vertical doping gradient varying as a function of trench depth. The lined trench is then filled with a metal fill material. A dielectric cap layer is then deposited over the metal filled trench. Dopant from the non-uniformly doped metal seed layer is then migrated to an interface between the metal filled trench and the dielectric cap layer to form a self-aligned metal cap. | 05-22-2014 |
20140138833 | Semiconductor Device Assembly Including a Chip Carrier, Semiconductor Wafer and Method of Manufacturing a Semiconductor Device - A semiconductor device includes a chip carrier and a semiconductor die with a semiconductor portion and a conductive structure. A soldered layer mechanically and electrically connects the chip carrier and the conductive structure at a soldering side of the semiconductor die. At the soldering side an outermost surface portion along an edge of the semiconductor die has a greater distance to the chip carrier than a central surface portion. The conductive structure covers the central surface portion and at least a section of an intermediate surface portion tilted to the central surface portion. Solder material is effectively prevented from coating such semiconductor surfaces that are prone to damages and solder-induced contamination is significantly reduced. | 05-22-2014 |
20140138834 | PREVENTING SHORTING DENDRITIC MIGRATION BETWEEN ELECTRODES - In a general aspect, an integrated circuit package includes a first electrode and a second electrode on a support substrate. The first electrode and the second electrode are configured to be electrically coupled to a voltage differential. A dendritic migration of a migratory species can develop under the voltage differential and a non-hermetic environment. The dendritic migration is interrupted by a floating electrical barrier mounted onto the support substrate between the first electrode and the second electrode. The electrical barrier includes a dam for preventing the metal migration. The dam has a height approximately equal to or greater than the largest dimension of a single atom of the migratory species. The first electrode and the second electrode can be mounted on the same side of the support substrate, or on two opposite sides of the support substrate. | 05-22-2014 |
20140145332 | METHODS OF FORMING GRAPHENE LINERS AND/OR CAP LAYERS ON COPPER-BASED CONDUCTIVE STRUCTURES - One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a graphene liner layer in at least the trench/via, forming a copper-based seed layer on the graphene liner layer, depositing a bulk copper-based material on the copper-based seed layer so as to overfill the trench/via, and performing at least one chemical mechanical polishing process to remove at least excess amounts of the bulk copper-based material and the copper-based seed layer positioned outside of the trench/via to thereby define a copper-based conductive structure with a graphene liner layer positioned between the copper-based conductive structure and the layer of insulating material. | 05-29-2014 |
20140145333 | Device Comprising a Ductile Layer and Method of Making the Same - Device comprising a ductile layer, a method for making a component comprising a ductile layer and a method for testing a component are disclosed. An embodiment includes an electronic device including a first conductive layer, a ductile layer and a brittle layer between the first conductive layer and the ductile layer. | 05-29-2014 |
20140145334 | METHODS AND APPARATUSES FOR THREE DIMENSIONAL INTEGRATED CIRCUITS - Methods and apparatuses for fabricating three-dimensional integrated circuits having through hole vias are provided. One aspect of the present invention is a method of gapfill for through hole vias for three-dimensional integrated circuits. The method comprises providing a semiconductor wafer having a plurality of holes for through hole vias and depositing a conformal metal layer to partially fill the holes to leave open voids. The method also includes purging the voids and cleaning the surface of the voids and using a dry deposition process to fill or close the voids. Another aspect of the present invention is an electronic device structure for a three-dimensional integrated circuit. | 05-29-2014 |
20140151884 | SELF-FORMING BARRIER STRUCTURE AND SEMICONDUCTOR DEVICE HAVING THE SAME - A self-forming barrier structure and a semiconductor device using the same are disclosed. The self-forming barrier structure includes a silicon-containing substrate; a first barrier layer formed on the silicon-containing substrate; and a second barrier layer formed of a copper-containing alloy on the first barrier layer; wherein the copper-containing alloy comprises copper and at least one other metal which diffuses faster than copper and is not inter-miscible with copper. | 06-05-2014 |
20140151885 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate which has at least one doped contact area and at least one line which is formed on the substrate and which is electrically connected to the at least one contact area, and at least one diffusion barrier, which includes at least one metal applied on a contact surface of the associated contact area, being formed between the at least one line and the at least one associated contact area, the at least one metal forming multiple metal-plated subareas which contact the contact surface of the same contact area and which are separated from one another. Furthermore, a manufacturing method for a semiconductor device is described. | 06-05-2014 |
20140151886 | SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT - Provided is a semiconductor element in which atomic interdiffusion between a semiconductor region and an electrode is suppressed and increase in the contact resistance is suppressed even in cases where the semiconductor element is exposed to high temperatures during the production processes or the like. A semiconductor element of the present invention is provided with: a semiconductor region that contains silicon; an electrode that contains aluminum; and a diffusion barrier layer that is interposed between the semiconductor region and the electrode and contains germanium. The germanium content in at least a part of the diffusion barrier layer is 4 at % or more. | 06-05-2014 |
20140159241 | Structures and Methods to Enhance Copper Metallization - Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary structure includes an inhibiting layer between an insulator and a metallization layer. The insulator includes a polymer or an insulating oxide compound. And, the inhibiting layer has a compound formed from a reaction between the polymer or insulating oxide compound and a transition metal, a representative metal, or a metalloid. | 06-12-2014 |
20140167267 | METHOD AND STRUCTURES FOR HEAT DISSIPATING INTERPOSERS - A method for making an interconnect element includes depositing a thermally conductive layer on an in-process unit. The in-process unit includes a semiconductor material layer defining a surface and edges surrounding the surface, a plurality of conductive elements, each conductive element having a first portion extending through the semiconductor material layer and a second portion extending from the surface of the semiconductor material layer. Dielectric coatings extend over at least the second portion of each conductive element. The thermally conductive layer is deposited on the in-process unit at a thickness of at least 10 microns so as to overlie a portion of the surface of the semiconductor material layer between the second portions of the conductive elements with the dielectric coatings positioned between the conductive elements and the thermally conductive layer. | 06-19-2014 |
20140175650 | INTERCONNECTION WIRES OF SEMICONDUCTOR DEVICES - Disclosed are a method to fabricate interconnection wires of a semiconductor device in a way to utilize benefits of copper interconnection and low k dielectric insulation while avoiding the problem of low k damage due to etching processes, and so fabricated interconnection wires. The method saves fabrication time and cost by reduced number of steps and also resolves metal gap fill issue. The method may comprise providing layers of a substrate, an etch stop layer and a sacrificial layer, forming first spacers, forming first copper interconnecting wires, removing the first spacers; forming polymer-like second spacers by depositing plasma gases in an etching chamber, forming second metal interconnecting wires, removing the second spacers to define channels interwoven with alternating first and second metal interconnecting wires, forming an anti-diffusion barrier around each of the first and second metal interconnecting wires, and filling the channels with a dielectric material for insulation. | 06-26-2014 |
20140175651 | LANDING STRUCTURE FOR THROUGH-SILICON VIA - Embodiments of the present disclosure describe techniques and configurations associated with forming a landing structure for a through-silicon via (TSV) using interconnect structures of interconnect layers. In eon embodiment, an apparatus includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a device layer disposed on the first surface of the semiconductor substrate, the device layer including one or more transistor devices, interconnect layers disposed on the device layer, the interconnect layers including a plurality of interconnect structures and one or more through-silicon vias disposed between the first surface and the second surface, wherein the plurality of interconnect structures include interconnect structures that are electrically coupled with the one or more TSVs and configured to provide one or more corresponding landing structures of the one or more TSVs. Other embodiments may be described and/or claimed. | 06-26-2014 |
20140175652 | Barrier for Through-Silicon Via - A system and a method for protecting vias is disclosed. An embodiment comprises forming an opening in a substrate. A barrier layer disposed in the opening including along the sidewalls of the opening. The barrier layer may include a metal component and an alloying material. A conductive material is formed on the barrier layer and fills the opening. The conductive material to form a via (e.g., TSV). | 06-26-2014 |
20140183737 | Diffusion Barriers - Embodiments of the present invention include diffusion barriers, methods for forming the barriers, and semiconductor devices utilizing the barriers. The diffusion barrier comprises a self-assembled monolayer (SAM) on a semiconductor substrate, where one surface of the SAM is disposed in contact with and covalently bonded to the semiconductor substrate, and one surface of the monolayer is disposed in contact with and covalently bonded to a metal layer. In some embodiments, the barrier comprises an assembly of one or more monomeric subunits of the following structure: Si—(C | 07-03-2014 |
20140183738 | COBALT BASED INTERCONNECTS AND METHODS OF FABRICATION THEREOF - A metal interconnect comprising cobalt and method of forming a metal interconnect comprising cobalt are described. In an embodiment, a metal interconnect comprising cobalt includes a dielectric layer disposed on a substrate, an opening formed in the dielectric layer such that the substrate is exposed. The embodiment further includes a seed layer disposed over the substrate and a fill material comprising cobalt formed within the opening and on a surface of the seed layer. | 07-03-2014 |
20140183739 | DUAL DAMASCENE STRUCTURE WITH LINER - A dual damascene structure with an embedded liner and methods of manufacture are disclosed. The method includes forming a dual damascene structure in a substrate. The method further includes reflowing a seed layer such that material of the seed layer flows into a via of the dual damascene structure. The method further includes forming a liner material on the material over or within the via of the dual damascene structure. The method further includes filling any remaining portions of the via and a trench of the dual damascene structure with additional material. | 07-03-2014 |
20140183740 | METHODS OF EXPOSING CONDUCTIVE VIAS OF SEMICONDUCTOR DEVICES AND ASSOCIATED STRUCTURES - Methods of exposing conductive vias of semiconductor devices may comprise conformally forming a barrier material over conductive vias extending from a backside surface of a substrate. A self-planarizing isolation material may be formed over the barrier material. An exposed surface of the self-planarizing isolation material may be substantially planar. A portion of the self-planarizing isolation material, a portion of the barrier material, and a portion of protruding material of the conductive vias may be removed to expose the conductive vias. Removal of the self-planarizing isolation material, the barrier material, and the conductive vias may be stopped after exposing at least one laterally extending portion of the barrier material. | 07-03-2014 |
20140183741 | MASK READ-ONLY MEMORY (ROM) AND METHOD FOR FABRICATING THE SAME - A mask ROM includes a plurality of conductive pads disposed on a substrate, an insulating film disposed on the conductive pads, a plurality of via holes disposed in the insulating film exposing the conductive pads, a plurality of first wirings disposed side by side and spaced apart from each other on the insulating film, a plurality of vias disposed in the via holes electrically connecting the conductive pads to the first wirings, respectively, and a plurality of barrier conductive films disposed on a bottom surface of a part of the plurality of via holes between the vias and the conductive pads. | 07-03-2014 |
20140183742 | MANGANESE-CONTAINING FILM FORMING METHOD, PROCESSING SYSTEM, ELECTRONIC DEVICE MANUFACTURING METHOD AND ELECTRONIC DEVICE - A manganese-containing film forming method for forming a manganese-containing film on an underlying layer containing silicon and oxygen includes: degassing the underlying layer formed on a processing target by thermally treating the processing target, the underlying layer containing silicon and oxygen; and forming a manganese metal film on the degassed underlying layer by chemical deposition using a gas containing a manganese compound. Forming a manganese metal film includes: setting a film formation temperature to be higher than a degassing temperature; introducing a reducing reaction gas; and forming a manganese-containing film including an interfacial layer formed in an interface with the underlying layer and a manganese metal film formed on the interfacial layer, the interfacial layer being made up of a film of at least one of a manganese silicate and a manganese oxide. | 07-03-2014 |
20140183743 | MANGANESE METAL FILM FORMING METHOD, PROCESSING SYSTEM, ELECTRONIC DEVICE MANUFACTURING METHOD AND ELECTRONIC DEVICE - A manganese metal film forming method includes: degassing an underlying layer formed on a processing target by thermally treating the processing target, the underlying layer containing silicon and oxygen; and forming a manganese metal film on the degassed underlying layer by chemical deposition using a gas containing a manganese compound. Forming a manganese metal film includes introducing a gas containing an oxidizing agent to form a partially-oxidized manganese metal film. | 07-03-2014 |
20140191400 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a workpiece including an insulating material layer disposed thereon. The insulating material layer includes a trench formed therein. The method includes forming a barrier layer on the sidewalls of the trench using a surface modification process and a surface treatment process. | 07-10-2014 |
20140191401 | AIRGAP INTERCONNECT WITH HOOD LAYER AND METHOD OF FORMIING - An airgap interconnect structure with hood layer and methods for forming such an airgap interconnect structure are disclosed. A substrate having a dielectric layer with a plurality of interconnects formed therein is provided. Each interconnect is encapsulated by a barrier layer. A hardmask is formed on the dielectric layer and patterned to expose the dielectric layer between adjacent interconnects where an airgap is desired. The dielectric layer is etched to form a trench, wherein the etching process additionally etches at least a portion of the barrier layer to expose a portion of the side surface of each adjacent copper interconnect. A hood layer is electrolessly plated onto an exposed portion of the top surface and the exposed portion of the side surface to reseal the interconnect. A gap-sealing dielectric layer is formed over the device, sealing the trench to form an airgap. | 07-10-2014 |
20140191402 | Barrier Layer for Copper Interconnect - A device including a dielectric layer overlying a substrate, a conductive line with a sidewall in the dielectric layer, a Ta layer adjoining the sidewall of the conductive line, and a metal oxide formed between the Ta layer and the dielectric layer. | 07-10-2014 |
20140197537 | Void-Free Metallic Filled High Aspect Ratio Openings - One embodiment is a device which includes at least one filled via or trench wherein the at least one filled via or trench includes void-free filled metal or alloy, and the filled via or trench has an aspect ratio in a range from 9:1 to about 28:1. | 07-17-2014 |
20140197538 | COPPER ETCHING INTEGRATION SCHEME - The present disclosure is directed to an interconnect structure. The metal interconnect structure has a metal body disposed over a semiconductor substrate and a projection extending from the metal body. A barrier layer continuously extends over the projection from a first sidewall of metal body to an opposing second sidewall of the metal body. A layer of dielectric material is disposed over the semiconductor substrate at a position abutting the metal body and the projection. | 07-17-2014 |
20140203435 | SELECTIVE LOCAL METAL CAP LAYER FORMATION FOR IMPROVED ELECTROMIGRATION BEHAVIOR - A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines. | 07-24-2014 |
20140203436 | SELECTIVE LOCAL METAL CAP LAYER FORMATION FOR IMPROVED ELECTROMIGRATION BEHAVIOR - A method of forming a wiring structure for an integrated circuit device includes forming a first metal line within an interlevel dielectric (ILD) layer, and forming a second metal line in the ILD layer adjacent the first metal line; masking selected regions of the first and second metal lines; selectively plating metal cap regions over exposed regions of the first and second metal lines at periodic intervals such that a spacing between adjacent metal cap regions of an individual metal line corresponds to a critical length, L, at which a back stress gradient balances an electromigration force in the individual metal line, so as to suppress mass transport of electrons; and wherein the metal cap regions of the first metal line are formed at staggered locations with respect to the metal cap regions of the second metal line, along a common longitudinal axis. | 07-24-2014 |
20140210085 | Capping Layer for Improved Deposition Selectivity - The present disclosure relates to a method and apparatus for improving back-end-of-the-line (BEOL) reliability. In some embodiments, the method forms an extreme low-k (ELK) dielectric layer having one or more metal layer structures over a semiconductor substrate. A first capping layer is formed over the ELK dielectric layer at a position between the one or more metal layer structures. A second capping layer is then deposited over the one or more metal layer structures at a position that is separated from the ELK dielectric layer by the first capping layer. The first capping layer has a high selectivity that limits interaction between the second capping layer and the ELK dielectric layer, reducing diffusion of the atoms from the second capping layer to the ELK dielectric layer and improving dielectric breakdown of the ELK dielectric layer. | 07-31-2014 |
20140210086 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a barrier metal film on a surface of at least one of a first electrode of a wiring board and a second electrode of a semiconductor element, providing a connection terminal between the first and second electrodes, the connection terminal being made of solder containing tin, bismuth and zinc, and bonding the connection terminal to the barrier metal film by heating the connection terminal and maintaining the temperature of the connection terminal at a constant temperature not lower than a melting point of the solder for a certain period of time. | 07-31-2014 |
20140210087 | INTERCONNECTION STRUCTURES FOR SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - An interconnection structure includes an underlying layer including a lower interconnection, and an interlayered dielectric layer including a contact hole and a trench therein. The contact hole exposes a portion of the lower interconnection, and the trench extends along a first direction to be connected to the contact hole. A contact plug extends through the contact hole in the interlayered dielectric layer, and an upper interconnection line extends in the trench of the interlayered dielectric layer and connects to the contact plug. The contact plug includes lower and upper sidewalls inclined at first and second angles, respectively, relative to the underlying layer, and the second angle is less than the first angle. Related devices and fabrication methods are also discussed. | 07-31-2014 |
20140210088 | METHOD FOR REDUCING WETTABILITY OF INTERCONNECT MATERIAL AT CORNER INTERFACE AND DEVICE INCORPORATING SAME - A semiconductor device includes a recess defined in a dielectric layer, the recess having an upper sidewall portion extending to an upper corner of the recess and a lower sidewall portion below the upper sidewall portion. An interconnect structure is positioned in the recess. The interconnect structure includes a continuous liner layer having upper and lower layer portions positioned laterally adjacent to the upper and lower sidewall portions, respectively. The upper layer portion includes an alloy of a first transition metal and a second transition metal and the lower layer portion includes the second transition metal but not the first transition metal. The interconnect structure also includes a fill material substantially filling the recess, wherein the second transition metal has a higher wettability for the fill material than the alloy. | 07-31-2014 |
20140210089 | COPPER INTERCONNECT STRUCTURE AND ITS FORMATION - A structure with improved electromigration resistance and methods for making the same. A structure having improved electromigration resistance includes a bulk interconnect having a dual layer cap and a dielectric capping layer. The dual layer cap includes a bottom metallic portion and a top metal oxide portion. Preferably the metal oxide portion is MnO or MnSiO and the metallic portion is Mn or CuMn. The structure is created by doping the interconnect with an impurity (Mn in the preferred embodiment), and then creating lattice defects at a top portion of the interconnect. The defects drive increased impurity migration to the top surface of the interconnect. When the dielectric capping layer is formed, a portion reacts with the segregated impurities, thus forming the dual layer cap on the interconnect. Lattice defects at the Cu surface can be created by plasma treatment, ion implantation, a compressive film, or other means. | 07-31-2014 |
20140217588 | METHODS OF FORMING COPPER-BASED NITRIDE LINER/PASSIVATION LAYERS FOR CONDUCTIVE COPPER STRUCTURES AND THE RESULTING DEVICE - One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in the trench/via, forming a copper-based seed layer on the barrier layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device disclosed herein includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based silicon or germanium nitride layer positioned between the copper-based conductive structure and the layer of insulating material. | 08-07-2014 |
20140217589 | SUPPORT STRUCTURE FOR BARRIER LAYER OF SEMICONDUCTOR DEVICE - Among other things, one or more support structures and techniques for forming such support structures within semiconductor devices are provided. The support structure comprises an oxide infused silicon layer that is formed within a trench of a dielectric layer on a substrate of a semiconductor device. The oxide infused silicon layer results from a silicon layer that is exposed to oxide during an ultraviolet (UV) curing process. The oxide infused silicon layer is configured to support a barrier layer against a conductive structure formed on the barrier layer within the trench. In this way, the support structure provides pressure against the barrier layer so that the barrier layer substantially maintains contact with the conductive structure, to promote improved performance and reliability of the conductive structure. | 08-07-2014 |
20140217590 | THROUGH SILICON VIA METALLIZATION - To achieve the foregoing and in accordance with the purpose of the present invention, a method for filling through silicon vias is provided. A dielectric layer is formed over the through silicon vias. A barrier layer, comprising tungsten, is deposited by CVD or ALD over the dielectric layer. The through silicon vias are filled with a conductive material. | 08-07-2014 |
20140217591 | MULTI-LAYER BARRIER LAYER FOR INTERCONNECT STRUCTURE - A semiconductor device includes a dielectric layer positioned above a substrate of the semiconductor device and a recess defined in the dielectric layer. An adhesion barrier layer is positioned on and in direct contact with at least the sidewalls of the recess, a barrier layer interface being defined where the adhesion barrier layer directly contacts the dielectric layer. A stress-reducing barrier layer is positioned adjacent to the adhesion barrier layer, wherein the stress-reducing barrier layer is adapted to reduce a stress level across the barrier layer interface from a first stress level to a second stress level that is less than the first stress level. At least one layer of a conductive fill material is positioned over the stress-reducing barrier layer, the at least one layer of the conductive fill material substantially filling the recess. | 08-07-2014 |
20140217592 | INTERCONNECT STRUCTURE AND METHOD OF MAKING SAME - An interconnect structure and method of fabricating the same is provided. More specifically, the interconnect structure is a defect free capped interconnect structure. The structure includes a conductive material formed in a trench of a planarized dielectric layer which is devoid of cap material. The structure further includes the cap material formed on the conductive material to prevent migration. The method of forming a structure includes selectively depositing a sacrificial material over a dielectric material and providing a metal capping layer over a conductive layer within a trench of the dielectric material. The method further includes removing the sacrificial material with any unwanted deposited or nucleated metal capping layer thereon. | 08-07-2014 |
20140231998 | Back End of the Line (BEOL) Interconnect Scheme - The present disclosure relates to a method of forming a back-end-of-the-line metal interconnect layer. The method is performed by depositing one or more self-assembled monolayers on a semiconductor substrate to define a metal interconnect layer area. A metal interconnect layer having a plurality of metal structures is formed on the semiconductor substrate within the metal interconnect layer area. An inter-level dielectric layer is then formed onto the surface of the semiconductor substrate in areas between the plurality of metal structures. | 08-21-2014 |
20140231999 | Schemes for Forming Barrier Layers for Copper in Interconnect Structures - A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided. | 08-21-2014 |
20140239500 | INTEGRATED CIRCUIT (IC) HAVING ELECTRICALLY CONDUCTIVE CORROSION PROTECTING CAP OVER BOND PADS - An integrated circuit (IC) die has a top side surface providing circuitry including active circuitry configured to provide a function, including at least one bond pad formed from a bond pad metal coupled to a node in the circuitry. A dielectric passivation layer is over a top side surface of a substrate providing a contact area which exposes the bond pad. A metal capping layer includes an electrically conductive metal or an electrically conductive metal compound over at least the contact area to provide corrosion protection to the bond pad metal, which is in electrical contact with the bond pad metal. The metal capping layer can extend over structures other than the bond pads, such as to cover at least 80% of the area of the IC die to provide structures on the IC die protection from incident radiation. | 08-28-2014 |
20140239501 | INTEGRATED CIRCUIT INTERCONNECTS AND METHODS OF MAKING SAME - A dielectric layer is formed on a substrate and patterned to form an opening. The opening is filled and the dielectric layer is covered with a metal layer. The metal layer is thereafter planarized so that the metal layer is co-planar with the top of the dielectric layer. The metal layer is etched back a predetermined thickness from the top of the dielectric layer to expose the inside sidewalls thereof. A sidewall barrier layer is formed on the sidewalls of the dielectric layer. A copper-containing layer is formed over the metal layer, the dielectric layer, and the sidewall barrier layers. The copper-containing layer is etched to form interconnect features, wherein the etching stops at the sidewall barrier layers at approximately the juncture of the sidewall of the dielectric layer and the copper-containing layer and does not etch into the underlying metal layer. | 08-28-2014 |
20140246775 | METHODS OF FORMING NON-CONTINUOUS CONDUCTIVE LAYERS FOR CONDUCTIVE STRUCTURES ON AN INTEGRATED CIRCUIT PRODUCT - One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a non-continuous layer comprised of a plurality of spaced-apart conductive structures on the layer of insulating material in the trench/via, wherein portions of the layer of insulating material not covered by the plurality of spaced-apart conductive structures remain exposed, forming at least one barrier layer on the non-continuous layer, wherein the barrier layer contacts the spaced-apart conductive structures and the exposed portions of the layer of insulating material, forming at least one liner layer above the barrier layer, and forming a conductive structure in the trench/via above the liner layer. | 09-04-2014 |
20140252616 | ELECTROLESS FILL OF TRENCH IN SEMICONDUCTOR STRUCTURE - A trench in an inter-layer dielectric formed on a semiconductor substrate is defined by a bottom and sidewalls. A copper barrier lines the trench with a copper-growth-promoting liner over the barrier. The trench has bulk copper filling it, and includes voids in the copper. The copper with voids is removed, including from the sidewalls, leaving a void-free copper portion at the bottom. Immersion in an electroless copper bath promotes upward growth of copper on top of the void-free copper portion without inward sidewall copper growth, resulting in a void-free copper fill of the trench. | 09-11-2014 |
20140252617 | BARRIER LAYER CONFORMALITY IN COPPER INTERCONNECTS - A process of modulating the thickness of a barrier layer deposited on the sidewalls and floor of a recessed feature in a semiconductor substrate is disclosed. The process includes altering the surface of the conductive feature on which the barrier layer is deposited by annealing in a reducing atmosphere and optionally additionally, silylating the dielectric surface that forms the sidewalls of the recessed feature. | 09-11-2014 |
20140252618 | METHOD FOR FORMING INTERCONNECT STRUCTURE THAT AVOIDS VIA RECESS - A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. The dielectric material layer is patterned to form a plurality of vias therein. A first metal layer is formed on the dielectric material layer, wherein the first metal layer fills the plurality of vias. The first metal layer is planarized so that the top thereof is co-planar with the top of the dielectric material layer to form a plurality of first metal features. A stop layer is formed on top of each of the plurality of first metal features, wherein the stop layer stops a subsequent etch from etching into the plurality of the first metal features. | 09-11-2014 |
20140252619 | INTERCONNECT STRUCTURE THAT AVOIDS INSULATING LAYER DAMAGE AND METHODS OF MAKING THE SAME - A method for forming an interconnect structure includes forming an insulating layer on a substrate. A damascene opening is formed through a thickness portion of the insulating layer. A diffusion barrier layer is formed to line the damascene opening. A conductive layer is formed overlying the diffusion barrier layer to fill the damascene opening. A carbon-containing metal oxide layer is formed on the conductive layer and the insulating layer. | 09-11-2014 |
20140252620 | MATERIAL AND PROCESS FOR COPPER BARRIER LAYER - A method of fabricating a semiconductor device comprises forming a first dielectric material layer on a semiconductor substrate. The first dielectric material layer is patterned to form a plurality of vias therein. A metal layer is formed on the first dielectric material layer, wherein the metal layer fills the plurality of vias. The metal layer is etched such that portions of the metal layer above the first dielectric material layer are patterned to form a plurality of metal features aligned with the plurality of vias respectively. A self-assembled monolayer film is formed on surfaces of the plurality of metal features. | 09-11-2014 |
20140252621 | Method For Forming Interconnect Structure - A method for forming interconnect structures comprises forming a metal line made of a first conductive material over a substrate, depositing a dielectric layer over the metal line, patterning the dielectric layer to form an opening, depositing a first barrier layer on a bottom and sidewalls of the opening using an atomic layer deposition technique, depositing a second barrier layer over the first barrier layer, wherein the first barrier layer is coupled to ground and forming a pad made of a second conductive material in the opening. | 09-11-2014 |
20140252622 | Method for Forming Recess-Free Interconnect Structure - A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. An oxygen-rich layer is formed over the dielectric material layer. The dielectric material layer and the oxygen-rich layer are patterned to form a plurality of vias in the semiconductor substrate. A barrier layer is formed in the plurality of vias and on the dielectric material layer leaving a portion of the oxygen-rich layer exposed. A metal layer is formed on the barrier layer and on the exposed portion of the oxygen-rich layer, wherein the metal layer fills the plurality of vias. The semiconductor substrate is annealed at a predetermined temperature range and at a predetermined pressure to transform the exposed portion of the oxygen-rich layer into a metal-oxide stop layer. | 09-11-2014 |
20140252623 | SEMICONDUCTOR DEVICE WITH ADVANCED PAD STRUCTURE RESISTANT TO PLASMA DAMAGE AND METHOD FOR FORMING THE SAME - A connective structure for bonding semiconductor devices and methods for forming the same are provided. The bonding structure includes an alpad structure, i.e., a thick aluminum-containing connective pad, and a substructure beneath the aluminum-containing pad that includes at least a pre-metal layer and a barrier layer. The pre-metal layer is a dense material layer and includes a density greater than the barrier layer and is a low surface roughness film. The high density pre-metal layer prevents plasma damage from producing charges in underlying dielectric materials or destroying subjacent semiconductor devices. | 09-11-2014 |
20140252624 | Semiconductor Devices and Methods of Forming Same - A semiconductor device structure and methods of forming the same are disclosed. An embodiment is a method of forming a semiconductor device, the method comprising forming a first conductive line over a substrate, and conformally forming a first dielectric layer over a top surface and a sidewall of the first conductive line, the first dielectric layer having a first porosity percentage and a first carbon concentration. The method further comprises forming a second dielectric layer on the first dielectric layer, the second dielectric layer having a second porosity percentage and a second carbon concentration, the second porosity percentage being different from the first porosity percentage, and the second carbon concentration being less than the first carbon concentration. | 09-11-2014 |
20140252625 | Method of Preventing a Pattern Collapse - A device includes a substrate and at least three conducting features embedded into the substrate. Each conducting feature includes a top width x and a bottom width y, such that a top and bottom width (x1, y1) of a first conducting feature has a dimension of (x1y2), and a top and bottom width (x3, y3) of a third conducting feature has a dimension of (x3>y3). The device also includes a gap structure isolating the first and second conducting features. The gap structure can include such things as air or dielectric. | 09-11-2014 |
20140252626 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package and a method for fabricating the same are provided. The semiconductor package includes a wafer, a plurality of semiconductor chips each having a connection pad and being stacked on the wafer, resin layers formed to expose top surfaces of the connection pads and to cover lateral surfaces and top surfaces of the semiconductor chips, through lines formed in at least one side of opposite sides of each of the semiconductor chips, to be spaced apart from the semiconductor chips, and to extend in a first direction, and redistribution lines arranged between the through lines, formed to extend in a second direction on the resin layers, and connected to the connection pads, wherein the through lines and the redistribution lines include barrier layers formed on lateral surfaces and bottom surfaces of the through lines and the redistribution lines, and conductive layers formed on the barrier layers. | 09-11-2014 |
20140252627 | SEMICONDUCTOR COMPONENT COMPRISING COPPER METALLIZATIONS - A semiconductor component having improved thermomechanical durability has in a semiconductor substrate at least one cell comprising a first main electrode zone, a second main electrode zone and a control electrode zone lying in between. For making contact with the main electrode zone, at least one metallization layer composed of copper or a copper alloy is provided which is connected to at least one bonding electrode which likewise comprises copper or a copper alloy. | 09-11-2014 |
20140264864 | INTEGRATED CIRCUIT STRUCTURE AND FORMATION - One or more integrated circuit structures and techniques for forming such integrated circuit structures are provided. The integrated circuit structures comprise a conductive structure that is formed within a trench in a dielectric layer on a substrate. The conductive structure is formed over a barrier layer formed within the trench, or the conductive structure is formed over a liner formed over the barrier layer. At least some of the dielectric layer, the barrier layer, the liner and the conductive structure are removed, for example, by chemical mechanical polishing, such that a step height exists between a top surface of the substrate and a top surface of the dielectric layer. Removing these layers in this manner removes areas where undesired interlayer peeling is likely to occur. A conductive cap is formed on the conductive structure. | 09-18-2014 |
20140264865 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device may include: a barrier layer; an adhesion layer disposed over the barrier layer; a metallization layer disposed over the adhesion layer, wherein the metallization layer is part of a final metallization level of the semiconductor device. | 09-18-2014 |
20140264866 | CHEMICAL DIRECT PATTERN PLATING INTERCONNECT METALLIZATION AND METAL STRUCTURE PRODUCED BY THE SAME - A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described. | 09-18-2014 |
20140264867 | METHOD OF FORMING HYBRID DIFFUSION BARRIER LAYER AND SEMICONDUCTOR DEVICE THEREOF - In a method of fabricating a semiconductor device, an opening is formed inside a dielectric layer above a semiconductor substrate. The opening has a wall. At least one diffusion barrier material is then formed over the wall of the opening by at least two alternating steps, which are selected from the group consisting of a process of physical vapor deposition (PVD) and a process of atomic layer deposition (ALD). A liner layer is formed over the at least one diffusion barrier material. | 09-18-2014 |
20140264868 | WAFER-LEVEL DIE ATTACH METALLIZATION - Embodiments of a semiconductor wafer having wafer-level die attach metallization on a back-side of the semiconductor wafer, resulting semiconductor dies, and methods of manufacturing the same are disclosed. In one embodiment, a semiconductor wafer includes a semiconductor structure and a front-side metallization that includes front-side metallization elements for a number of semiconductor die areas. The semiconductor wafer also includes vias that extend from a back-side of the semiconductor structure to the front-side metallization elements. A back-side metallization is on the back-side of the semiconductor structure and within the vias. For each via, one or more barrier layers are on a portion of the back-side metallization that is within the via and around a periphery of the via. The semiconductor wafer further includes wafer-level die attach metallization on the back-side metallization other than the portions of the back-side metallization that are within the vias and around the peripheries of the vias. | 09-18-2014 |
20140264869 | Semiconductor Device - A semiconductor device comprises a substrate having a first side with a first surface and a second side with a second surface, a recessed through silicon via (TSV) penetrating the substrate and forming a first step height with respect to the first surface of the first side, a first extruded backside redistribution line (RDL) filling in the first step height and engaging with the recessed through silicon via. | 09-18-2014 |
20140264870 | METHOD OF BACK-END-OF-LINE (BEOL) FABRICATION, AND DEVICES FORMED BY THE METHOD - In a method for forming a semiconductor device, an interconnect structure over a semiconductor substrate is provided. The interconnect structure includes a first dielectric layer and a conductive pattern inside a trench in the first dielectric layer. An etch stop layer (ESL) is formed over the interconnect structure. An interface layer comprising elemental silicon is deposited over the ESL. A second dielectric layer is then formed over the interface layer. | 09-18-2014 |
20140264871 | Method to Increase Interconnect Reliability - Methods to increase metal interconnect reliability are provided. Methods include forming a conformal barrier layer within an opening in a semiconductor device structure and forming a copper alloy material above the conformal barrier layer. Next, removing the copper alloy material that extends beyond the opening. Removing native oxide from a top surface of the copper alloy material. Further, annealing or applying a plasma treatment to the copper alloy material. Finally, forming a capping layer above the copper alloy material. Notably, near the top of the copper alloy material, smaller copper grain growth may be present. Furthermore, more non-copper alloy atoms are present near the top of the copper alloy material than the bulk of the copper alloy material. | 09-18-2014 |
20140264872 | Metal Capping Layer for Interconnect Applications - An integrated circuit structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The integrated circuit structure further includes a conductive wiring in the dielectric layer. The integrated circuit structure also includes a first metallic capping layer over the conductive wiring and a second metallic capping layer over the first metallic capping layer. The second metallic capping layer has a width substantially the same as a width of the first metallic capping layer. | 09-18-2014 |
20140264873 | Interconnection Structure And Method For Semiconductor Device - A semiconductor device is disclosed. The device includes a substrate, a first dielectric layer disposed over the substrate and a metal structure disposed in the first dielectric layer and below a surface of the first dielectric layer. The metal structure has a such shape that having an upper portion with a first width and a lower portion with a second width. The second width is substantially larger than the first width. The semiconductor device also includes a sub-structure of a second dielectric positioned between the upper portion of the metal structure and the first dielectric layer. | 09-18-2014 |
20140264874 | Electro-Migration Barrier for Cu Interconnect - Integrated circuit devices and method of forming them. The devices include a dielectric barrier layer formed over a copper-containing metal interconnect structure. The dielectric barrier layer inhibits electro-migration of Cu. The dielectric barrier layer includes a metal-containing layer that forms an interface with the interconnect structure. Incorporating metal within the interfacial layer improves adhesion of the dielectric barrier layer to copper lines and the like and provides superior electro-migration resistance over the operating lifetime of the devices. | 09-18-2014 |
20140264875 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a copper interconnect provided in a trench in an insulation film, a metal film provided on the insulation film along a boundary between the insulation film and the copper interconnect, a barrier metal provided between an inner wall of the trench and the copper interconnect and extending over the metal layer, a first metal cap to cover the copper interconnect and the barrier metal located over the metal film, and a second metal cap to continuously cover the first metal cap, the barrier metal and the metal film. | 09-18-2014 |
20140264876 | MULTI-LAYER BARRIER LAYER STACKS FOR INTERCONNECT STRUCTURES - A semiconductor device includes a recess defined in a dielectric layer and an interconnect structure defined in the recess. The interconnect structure includes a first barrier layer lining the recess, the first barrier layer including an alloy of tantalum and a first transition metal other than tantalum, wherein a first interface between the first barrier layer and the dielectric layer has a first stress level. A second barrier layer is positioned on the first barrier layer, the second barrier layer including at least one of tantalum and tantalum nitride, wherein a second interface between the second barrier layer and the first barrier layer has a second stress level that is less than the first stress level. The interconnect structure further includes a fill material substantially filling the recess. | 09-18-2014 |
20140264877 | METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES COMPRISING A COPPER/SILICON COMPOUND AS A BARRIER MATERIAL - A semiconductor device includes a first metallization layer positioned above a substrate of the semiconductor device, the metallization layer including a dielectric material and a copper-containing metal region embedded in the dielectric material. The semiconductor device also includes a conductive barrier layer positioned along substantially an entirety of an interface between the copper-containing metal region and the dielectric material, the conductive barrier layer including a copper/silicon compound that is in direct contact with the dielectric material along substantially the entirety of the interface. | 09-18-2014 |
20140264878 | COPPER INTERCONNECT STRUCTURES AND METHODS OF MAKING SAME - A structure and method of making the structure. The structure includes a dielectric layer on a substrate; a first wire formed in a first trench in the dielectric layer, a first liner on sidewalls and a bottom of the first trench and a first copper layer filling all remaining space in the first trench; a second wire formed in a second trench in the dielectric layer, a second liner on sidewalls and a bottom of the second trench and a second copper layer filling all remaining space in the second trench; and an electromigration stop formed in a third trench in the dielectric layer, a third liner on sidewalls and a bottom of the third trench and a third copper layer filling all remaining space in the third trench, the electromigration stop between and abutting respective ends of the first and second wires. | 09-18-2014 |
20140291847 | METHODS OF FORMING A BARRIER SYSTEM CONTAINING AN ALLOY OF METALS INTRODUCED INTO THE BARRIER SYSTEM, AND AN INTEGRATED CIRCUIT PRODUCT CONTAINING SUCH A BARRIER SYSTEM - One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier system comprised of at least one barrier material and at least two metallic elements, and performing a heating process to form a metal alloy comprised of the at least two metallic elements in the barrier system. Also disclosed is a device that comprises a trench/via in a layer of insulating material, a barrier system positioned in the trench/via, wherein the barrier system comprises at least one barrier material and a metal alloy comprised of at least two metallic elements that are comprised of materials other than the at least one barrier material, and a conductive structure positioned in the trench/via above the barrier system. | 10-02-2014 |
20140291848 | SEMICONDUCTOR DEVICE - A semiconductor device may include pillars and a plurality of conductive layers being stacked while surrounding the pillars and including a plurality of first regions including non-conductive material layers and a plurality of second regions including conductive material layers, wherein the first regions and the second regions are alternately arranged. | 10-02-2014 |
20140299988 | SELF-FORMING EMBEDDED DIFFUSION BARRIERS - Interconnect structures containing metal oxide embedded diffusion barriers and methods of forming the same. Interconnect structures may include an M | 10-09-2014 |
20140299989 | SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a first conductive structure including a first conductive pattern that is formed over a substrate, a second conductive structure formed adjacent to a sidewall of the first conductive structure, and an insulation structure including an air gap that is formed between the first conductive structure and the second conductive structure, wherein the second conductive structure includes a second conductive pattern, an ohmic contact layer that is formed over the second conductive pattern, and a third conductive pattern that is formed over the ohmic contact layer and is separated from the first conductive pattern through the air gap. | 10-09-2014 |
20140299990 | SEMICONDUCTOR DEVICE - The semiconductor device of the present invention includes an insulating layer, a copper wiring for wire connection formed on the insulating layer, a shock absorbing layer formed on an upper surface of the copper wiring, the shock absorbing layer being made of a metallic material with a hardness higher than copper, a bonding layer formed on the shock absorbing layer, the bonding layer having a connection surface for a wire, and a side protecting layer covering a side surface of the copper wiring, wherein the side protecting layer has a thickness thinner than a distance from the upper surface of the copper wiring to the connection surface of the bonding layer. | 10-09-2014 |
20140299991 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - It is an object of the present invention to prevent an influence of voltage drop due to wiring resistance, trouble in writing of a signal into a pixel, and trouble in gray scales, and provide a display device with higher definition, represented by an EL display device and a liquid crystal display device. | 10-09-2014 |
20140299992 | FILLING CAVITIES IN SEMICONDUCTOR STRUCTURES HAVING ADHESION PROMOTING LAYER IN THE CAVITIES - High aspect ratio trenches may be filled with metal that grows more from the bottom than the top of the trench. As a result, the tendency to form seams or to close of the trench at the top during filling may be reduced in sonic embodiments. Material that encourages the growth of metal may be formed in the trench at the bottom, while leaving the region of the trench near the top free of such material to encourage growth upwardly from the bottom. | 10-09-2014 |
20140306344 | WIRING STRUCTURE, SEMICONDUCTOR DEVICE INCLUDING WIRING STRUCTURE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - There is provided with a wiring structure. The wiring stracture has a damascene wiring structure including a metal wiring. The metal wiring is provided in direct contact with an upper surface of a barrier film (SiC(O, N) film) containing silicon (Si), carbon (C), and at least one of oxygen (O) and nitrogen (N) as constituent components. | 10-16-2014 |
20140306345 | SEMICONDUCTOR DEVICE INCLUDING COPPER WIRING AND VIA WIRING HAVING LENGTH LONGER THAN WIDTH THEREOF AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first interconnect formed over the semiconductor substrate. An interlayer dielectric film is formed over the first interconnect, and a hole is formed in the interlayer dielectric film such that the hole reaches the first interconnect. A trench is formed in the interlayer dielectric film, and a conductive film is embedded in the hole and the trench, thereby a via is formed in the hole and a second interconnect in the trench. In a planar view, the first interconnect extends in a first direction, the second interconnect extends in a second direction which is perpendicular to the first direction, and a maximum width of the via in the second direction is larger than a maximum width of the via in the first direction. | 10-16-2014 |
20140319685 | Hybrid Graphene-Metal Interconnect Structures - Hybrid metal-graphene interconnect structures and methods of forming the same. The structure may include a first end metal, a second end metal, a conductive line including one or more graphene portions extending from the first end metal to the second end metal, and one or more line barrier layers partially surrounding each of the one or more graphene portions. The conductive line may further include one or more intermediate metals separating each of the one or more graphene portions. Methods of forming said interconnect structures may include forming a plurality of metals including a first end metal and a second end metal in a dielectric layer, forming one or more line trenches between each of the plurality of metals, forming a line barrier layer in each of the one or more line trenches, and filling the one or more line trenches with graphene. | 10-30-2014 |
20140319686 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An object is to use an electrode made of a less expensive material than gold (Au). A semiconductor device comprises: a first titanium layer that is formed to cover at least part of a semiconductor layer and is made of titanium; an aluminum layer that is formed on the first titanium layer on opposite side of the semiconductor layer and mainly consists of aluminum; a titanium nitride layer that is formed on the aluminum layer on opposite side of the first titanium layer and is made of titanium nitride; and an electrode layer that is formed on the titanium nitride layer on opposite side of the aluminum layer and is made of silver. | 10-30-2014 |
20140319687 | SUBSTRATE WITH A FUNCTIONAL LAYER COMPRISING A SULPHUROUS COMPOUND - The invention relates to a substrate ( | 10-30-2014 |
20140327139 | CONTACT LINER AND METHODS OF FABRICATION THEREOF - Contact structures and methods of fabricating contact structures of semiconductor devices are provided. One method includes, for instance: obtaining a substrate including a dielectric layer over the substrate; patterning the dielectric layer with at least one contact opening; providing a contact liner within the at least one contact opening in the dielectric layer; and filling the contact liner with a conductive material. In enhanced aspects, providing the contact liner within the at least one contact opening includes: depositing a first layer within the at least one contact opening in the dielectric layer; depositing a second layer over the first layer within the at least one contact opening; depositing at least one intermediate layer over the second layer within the at least one contact opening; and depositing a top layer over the at least one intermediate layer within the at least one contact opening. | 11-06-2014 |
20140327140 | INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH IMPROVED CONTACT STRUCTURES - Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a semiconductor substrate disposed with a device therein and/or thereon. A contact structure including a barrier layer and a plug metal overlying the barrier layer is formed in electrical contact with the device. A hardmask is formed overlying the contact structure. The method includes performing an etch to form a via opening through the hardmask and to expose the barrier layer and the plug metal. Further, the method removes a remaining portion of the hardmask with a wet etchant, while the contact structure is configured to inhibit the wet etchant from etching the barrier layer. In the method, the via opening is filled with a conductive material to form an interconnect to the contact structure. | 11-06-2014 |
20140327141 | COPPER INTERCONNECT STRUCTURE AND METHOD FOR FORMING THE SAME - A copper interconnect structure in a semiconductor device comprises a dielectric layer having sidewalls and a surface defining an opening in the dielectric layer. The copper interconnect structure also comprises a barrier layer deposited on the sidewalls and the surface of the dielectric layer defining the opening. The copper interconnect structure further comprises a barrier/seed mixed layer deposited on the barrier layer. The copper interconnect structure additionally comprises an adhesive layer deposited on the barrier/seed mixed layer. The copper interconnect structure also comprises a seed layer deposited on the adhesive layer. | 11-06-2014 |
20140332959 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes: a groove portion formation step of forming a groove portion in a base; a barrier layer formation step of forming a barrier layer that covers at least an inner wall surface of the groove portion; a seed layer formation step of forming a seed layer that covers the barrier layer; and a burial step of burying a conductive material in an inside region of the seed layer, wherein the seed layer is made of Cu, and the conductive material is made of Cu. | 11-13-2014 |
20140332960 | INTERCONNECT STRUCTURES CONTAINING NITRIDED METALLIC RESIDUES - A metal cap is formed on an exposed upper surface of a conductive structure that is embedded within an interconnect dielectric material. During the formation of the metal cap, metallic residues simultaneously form on an exposed upper surface of the interconnect dielectric material. A thermal nitridization process or plasma nitridation process is then performed which partially or completely converts the metallic residues into nitrided metallic residues. During the nitridization process, a surface region of the interconnect dielectric material and a surface region of the metal cap also become nitrided. | 11-13-2014 |
20140332961 | Cu/CuMn BARRIER LAYER AND FABRICATING METHOD THEREOF - In the present invention, the pure Cu film is deposited on the CuMn film and the Mn atoms are induced to diffuse within the dielectric layer. The barrier properties of this self-forming barrier are sensitive to the thickness, the annealing temperature, the annealing time and the impurity concentration of itself. The bi-layer structure reduces the resistance of the barrier and improves the surface morphology during the electroplating process because the Mn atoms will be more easily corroded and oxidized in sulfuric acid with respect to the Cu. After annealing, the thermal stability and the barrier properties of the Cu/CuMn films is better than either single Cu film or single CuMn film. | 11-13-2014 |
20140332962 | Device and Method for Reducing Contact Resistance of a Metal - A structure for an integrated circuit with reduced contact resistance is disclosed. The structure includes a substrate, a cap layer deposited on the substrate, a dielectric layer deposited on the cap layer, and a trench embedded in the dielectric layer. The trench includes a TaN layer deposited on a side wall of the trench wherein the TaN layer has a greater concentration of nitrogen than tantalum, a Ta layer deposited on the TaN layer, and a Cu deposited on the Ta layer. The structure further includes a via integrated into the trench at bottom of the filled trench. In an embodiment, both the TaN layer and the Ta layer are formed with physical vapor deposition (PVD) wherein the TaN layer is formed with plasma sputtering a Ta target with an N | 11-13-2014 |
20140339700 | GRAPHENE-BASED METAL DIFFUSION BARRIER - Contacts for semiconductor devices are formed where a barrier layer comprising graphene is situated between a first layer comprising a conductor, and a second layer comprising a second conductor or a semiconductor. For example, a metal layer can be formed on a graphene layer residing on a semiconductor. The barrier layer can be directly formed on some second layers, for example, graphene can be transferred from an organic polymer/graphene bilayer structure and the organic polymer removed and replaced with a metal or other conductor that comprises the first layer of the contact. The bilayer can be formed by CVD deposition on a metallic second layer, or the graphene can be formed on a template layer, for example, a metal layer, and bound by a binding layer comprising an organic polymer to form an organic polymer/graphene/metal trilayer structure. The template layer can be removed to yield the bilayer structure. Contacts with the graphene barrier layer display enhanced reliability as the graphene layer inhibits diffusion and reaction between the layers contacting the barrier layer. | 11-20-2014 |
20140339701 | METHOD OF FORMING METAL INTERCONNECTIONS OF SEMICONDUCTOR DEVICE - A method of forming a metal interconnection of semiconductor device is provided. The method includes forming a low-k dielectric layer including an opening; forming a barrier metal pattern conformally covering a bottom surface and an inner sidewall of the opening; forming a metal pattern exposing a part of the inner sidewall of the barrier metal pattern in the opening; forming a metal capping layer on the top surfaces of the metal pattern and the low-k dielectric layer using a selective chemical vapor deposition process, wherein the thickness of the metal capping layer on the metal pattern is greater than the thickness of the metal capping layer on the low-k dielectric layer; and forming a metal capping pattern covering the top surface of the metal pattern by planarizing the metal capping layer down to the top surface of the low-k dielectric layer. | 11-20-2014 |
20140353827 | BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES - Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed. | 12-04-2014 |
20140353828 | SUBSTRATE BONDING WITH DIFFUSION BARRIER STRUCTURES - A metallic dopant element having a greater oxygen-affinity than copper is introduced into, and/or over, surface portions of copper-based metal pads and/or surfaces of a dielectric material layer embedding the copper-based metal pads in each of two substrates to be subsequently bonded. A dopant-metal silicate layer may be formed at the interface between the two substrates to contact portions of metal pads not in contact with a surface of another metal pad, thereby functioning as an oxygen barrier layer, and optionally as an adhesion material layer. A dopant metal rich portion may be formed in peripheral portions of the metal pads in contact with the dopant-metal silicate layer. A dopant-metal oxide portion may be formed in peripheral portions of the metal pads that are not in contact with a dopant-metal silicate layer. | 12-04-2014 |
20140353829 | SEMICONDUCTOR DEVICE HAVING INSULATING LAYERS CONTAINING OXYGEN AND A BARRIER LAYER CONTAINING MANGANESE - A semiconductor device includes an insulating layer formed over a semiconductor substrate, the insulating layer including oxygen, a first wire formed in the insulating layer, and a second wire formed in the insulating layer over the first wire and containing manganese, oxygen, and copper, the second wire having a projection portion formed in the insulating layer and extending downwardly but spaced apart from the first wire. | 12-04-2014 |
20140361435 | METHODS OF FORMING COPPER-BASED NITRIDE LINER/PASSIVATION LAYERS FOR CONDUCTIVE COPPER STRUCTURES AND THE RESULTING DEVICE - One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in the trench/via, forming a copper-based seed layer on the barrier layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device disclosed herein includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based silicon or germanium nitride layer positioned between the copper-based conductive structure and the layer of insulating material. | 12-11-2014 |
20140367857 | Method and Apparatus for Back End of Line Semiconductor Device Processing - Methods and apparatus are disclosed for the back end of line process for fabrication of integrated circuits (ICs). A barrier layer comprising a bottom part and a side part is formed within an opening for a metal contact, wherein the bottom part comprises a graphene material, the side part comprises an amorphous carbon material and covers a sidewall of the opening, and the bottom part and the side part are formed at a same time. A capping layer comprising a first part and a second part is formed on a dielectric layer and a metal contact, wherein the first part comprises a graphene material, the second part of the capping layer comprises an amorphous carbon material on the dielectric layer, and the first part and the second part are formed at a same time. | 12-18-2014 |
20140374906 | METHOD FOR PROCESSING A CARRIER AND AN ELECTRONIC COMPONENT - In various embodiments, a method for processing a carrier is provided. The method for processing a carrier may include: forming a first catalytic metal layer over a carrier; forming a source layer over the first catalytic metal layer; forming a second catalytic metal layer over the source layer, wherein the thickness of the second catalytic metal layer is larger than the thickness of the first catalytic metal layer; and subsequently performing an anneal to enable diffusion of the material of the source layer forming an interface layer adjacent to the surface of the carrier from the diffused material of the source layer. | 12-25-2014 |
20140374907 | ULTRA-THIN COPPER SEED LAYER FOR ELECTROPLATING INTO SMALL FEATURES - An apparatus and process are described that allow electroplating to fill sub-micron, high aspect ratio semiconductor substrate features using a non-copper/pre-electroplating layer on at least upper portions of side walls of the features, thereby providing reliable bottom up accumulation of the electroplating fill material in the feature. This apparatus and process eliminates feature filling material voids and enhances reliability of the electroplating in the diminishing size of features associated with future technology nodes of 22, 15, 11, and 8 nm. Modification of an upper portion of a metal seed layer allows for filling of the feature using electroplated fill material accumulating from the bottom of the feature up to reliability and predictability and substantially void-free. | 12-25-2014 |
20140374908 | Semiconductor Device and Manufacturing Method Thereof - To improve the reliability of a semiconductor device including a low-resistance material such as copper, aluminum, gold, or silver as a wiring. Provided is a semiconductor device including a pair of electrodes electrically connected to a semiconductor layer which has a stacked-layer structure including a first protective layer in contact with the semiconductor layer and a conductive layer containing the low-resistance material and being over and in contact with the first protective layer. The top surface of the conductive layer is covered with a second protective layer functioning as a mask for processing the conductive layer. The side surface of the conductive layer is covered with a third protective layer. With this structure, entry or diffusion of the constituent element of the pair of conductive layers containing the low-resistance material into the semiconductor layer is suppressed. | 12-25-2014 |
20140374909 | METHOD FOR FILLING TRENCH WITH METAL LAYER AND SEMICONDUCTOR STRUCTURE FORMED BY USING THE SAME - A method for filling a trench with a metal layer is disclosed. A deposition apparatus having a plurality of supporting pins is provided. A substrate and a dielectric layer disposed thereon are provided. The dielectric layer has a trench. A first deposition process is performed immediately after the substrate is placed on the supporting pins to form a metal layer in the trench, wherein during the first deposition process a temperature of the substrate is gradually increased to reach a predetermined temperature. When the temperature of the substrate reaches the predetermined temperature, a second deposition process is performed to completely fill the trench with the metal layer. The present invention further provides a semiconductor device having an aluminum layer with a reflectivity greater than 1, wherein the semiconductor device is formed by using the method. | 12-25-2014 |
20140374910 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device has a semiconductor substrate, a first insulating film formed on a surface of the semiconductor substrate, a first recess formed in the first insulating film, a first barrier film formed on an inner surface of the first insulating film except a top peripheral region of the first trench, a first conductive film formed in the first trench, and a covering film formed on an upper surface and a top peripheral region of the first conductive film and an upper surface of the first barrier film. The first conductive film includes copper. | 12-25-2014 |
20150008582 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a transistor formed on a semiconductor chip, a lower-layer wiring connected to a diffusion layer of the transistor, and drawn outside the diffusion layer, and an upper-layer wiring drawn out from a pad electrode formed on the semiconductor chip, connected to the lower-layer wiring, and having resistivity lower than that of the lower-layer wiring. | 01-08-2015 |
20150014854 | WAFER LEVEL PACKAGE SOLDER BARRIER USED AS VACUUM GETTER - An electronic device and methods of manufacture thereof. One or more methods may include providing a lid wafer having a cavity and a surface surrounding the cavity and a device wafer having a detector device and a reference device. In certain examples, a solder barrier layer of titanium material may be deposited onto the surface of the lid wafer. The solder barrier layer of titanium material may further be activated to function as a getter. In various examples, the lid wafer and the device wafer may be bonded together using solder, and the solder barrier layer of titanium material may prevent the solder from contacting the surface of the lid wafer. | 01-15-2015 |
20150021770 | BACK-END-OF-LINE (BEOL) INTERCONNECT STRUCTURE - A method of fabricating an interconnect structure on a wafer and an interconnect structure are provided. A dielectric layer is provided on the wafer, with the dielectric layer having a recess therein. A silicon (Si) layer is deposited in the recess. An interconnect is formed by providing a barrier layer and a conductive layer in the recess over the Si layer. The Si layer has a density that prevents or substantially prevents the barrier layer from moving away from the conductive layer and towards the dielectric layer during subsequent processing of the interconnect structure. | 01-22-2015 |
20150021771 | MECHANISMS FOR FORMING THREE-DIMENSIONAL INTEGRATED CIRCUIT (3DIC) STACKING STRUCTURE - Embodiments of mechanisms of forming a semiconductor device are provided. The semiconductor device includes a first semiconductor wafer comprising a first transistor formed in a front-side of the first semiconductor wafer. The semiconductor device also includes a second semiconductor wafer comprising a second transistor formed in a front-side of the second semiconductor wafer, and a backside of the second semiconductor wafer is bonded to the front-side of the first semiconductor wafer. The semiconductor device further includes an first interconnect structure formed between the first semiconductor wafer and the second semiconductor wafer, and the first interconnect structure comprises a first cap metal layer formed over a first conductive feature. The first interconnect structure is electrically connected to first transistor, and the first cap metal layer is configured to prevent diffusion and cracking of the first conductive feature. | 01-22-2015 |
20150021772 | Mixed-metal barrier films optimized by high-productivity combinatorial PVD - A barrier film including at least one ferromagnetic metal (e.g., nickel) and at least one refractory metal (e.g., tantalum) effectively blocks copper diffusion and facilitates uniform contiguous (non-agglomerating) deposition of copper layers less than 100 Å thick. Methods of forming the metal barrier include co-sputtering the component metals from separate targets. Using high-productivity combinatorial (HPC) apparatus and methods, the proportions of the component metals can be optimized. Gradient compositions can be deposited by varying the plasma power or throw distance of the separate targets. | 01-22-2015 |
20150021773 | Through Semiconductor via Structure with Reduced Stress Proximity Effect - An integrated circuit device and associated fabrication process are disclosed for forming a through semiconductor via (TSV) conductor structure in a semiconductor substrate with active circuitry formed on a first substrate surface where the TSV conductor structure includes multiple small diameter conductive vias extending through the first substrate surface and into the semiconductor substrate by a predetermined depth and a large diameter conductive via formed to extend from the multiple small diameter conductive vias and through a second substrate surface opposite to the first substrate surface. | 01-22-2015 |
20150021774 | Molecular Self-Assembly in Substrate Processing - Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, flouroalkyl groups, heteroarlyl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming. | 01-22-2015 |
20150021775 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND APPARATUS FOR PRODUCING SEMICONDUCTOR - A method for manufacturing a semiconductor device for forming a metal element-containing layer on an insulating layer in which a concave portion is formed, includes: forming an oxide layer including mainly an oxide of the metal element on the insulating layer including the concave portion; and forming a silicate layer including mainly a silicate of the metal element by making the oxide layer into silicate by annealing under a reducing atmosphere. | 01-22-2015 |
20150035151 | Capping Layer Interface Interruption for Stress Migration Mitigation - A semiconductor device includes a substrate, a dielectric layer supported by the substrate, an interconnect adjacent the dielectric layer, the interconnect including a conduction material and a barrier material disposed along sidewalls of the interconnect between the conduction material and the dielectric layer, and a layer disposed over the interconnect to establish an interface between the conduction material, the barrier material, and the layer. A plate is disposed along a section of the interconnect to interrupt the interface. | 02-05-2015 |
20150035152 | Interconnection structures for semiconductor devices and fabrication methods of forming interconnection structures for semiconductor devices utilizing to-be-etched layer made of porous low-K dielectric material and a first hard mask layer made of nitrogen-doped silicon oxycarbide (SiOC(N)) - A method is provided for fabricating a semiconductor structure. The method includes providing a substrate; and forming a to-be-etched layer made of porous low dielectric constant material on one surface of the semiconductor substrate. The method also includes forming a first hard mask layer made of nitrogen-doped silicon oxycarbide (SiOC(N)) on the to-be-etched layer; and etching the first hard mask layer to have patterns corresponding to positions of subsequently formed openings. Further, the method includes forming the plurality of openings without substantial undercut between the to-be-etched layer and the first hard mask layer in the to-be-etched layer using the first hard mask layer as an etching mask; and forming a conductive structure in each of the openings. | 02-05-2015 |
20150035153 | REMOVING METAL FILLS IN A WIRING LAYER - The present invention relates to a semiconductor manufacturing method, a mask forming method and a semiconductor structure. According to one aspect of the invention, a semiconductor manufacturing method is provided, comprising: forming a metal wiring layer on a semiconductor substrate, the metal wiring layer comprising dielectrics and metal wires and metal FILLs within the dielectrics; removing the metal FILLs in the metal wiring layer completely to form the metal wiring layer without the metal FILLs. With the technical solution according to embodiments of the invention, undesirable influences due to metal FILLs will be eliminated. | 02-05-2015 |
20150035154 | PROFILE CONTROL IN INTERCONNECT STRUCTURES - The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of the line opening prevents rounding of the corners of a dielectric material portion that is present beneath the line opening and adjacent the via opening. | 02-05-2015 |
20150035155 | DUAL DAMASCENE STRUCTURE WITH LINER - A dual damascene structure with an embedded liner and methods of manufacture are disclosed. The method includes forming a dual damascene structure in a substrate. The method further includes reflowing a seed layer such that material of the seed layer flows into a via of the dual damascene structure. The method further includes forming a liner material on the material over or within the via of the dual damascene structure. The method further includes filling any remaining portions of the via and a trench of the dual damascene structure with additional material. | 02-05-2015 |
20150041981 | SEMICONDUCTOR INTERCONNECT STRUCTURE HAVING A GRAPHENE-BASED BARRIER METAL LAYER - An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by utilizing a graphene-based barrier metal layer to block oxygen intrusion from a dielectric layer into the interconnect structure and block copper diffusion from the interconnect structure into the dielectric layer, are disclosed. At least one opening is formed in a dielectric layer. A graphene-based barrier metal layer disposed on the dielectric layer is formed. A seed layer disposed on the graphene-based barrier metal layer is formed. An electroplated copper layer disposed on the seed layer is formed. A planarized surface is formed, wherein a portion of the graphene-based barrier metal layer, the seed layer, and the electroplated copper layer are removed. In addition, a capping layer disposed on the planarized surface is formed. | 02-12-2015 |
20150048507 | CONDUCTIVE DIFFUSION BARRIER STRUCTURE FOR OHMIC CONTACTS - An integrated circuit includes a p-type region formed beneath a surface of a semiconductor substrate, and an n-type region formed beneath the surface of the semiconductor substrate. The n-type region meets the p-type region at a p-n junction. A diffusion barrier structure, which is beneath the surface of the semiconductor substrate and extends along a side of the p-n junction, limits lateral diffusion between the p-type region and n-type region. | 02-19-2015 |
20150048508 | NANOWIRES COATED ON TRACES IN ELECTRONIC DEVICES - Methods and devices including the formation of a layer of nanowires on wiring line traces are described. One device comprises a first dielectric layer and a plurality of traces on the first dielectric layer, the traces comprising Cu. The traces include a layer of ZnO nanowires positioned thereon. A second dielectric layer is positioned on the first dielectric layer and on the traces, wherein the second dielectric layer is in direct contact with the ZnO nanowires. Other embodiments are described and claimed. | 02-19-2015 |
20150048509 | CMOS COMPATIBLE WAFER BONDING LAYER AND PROCESS - A wafer bonding layer and a process for using the same for bonding wafers are presented. The wafer bonding process includes providing a first wafer, providing a second type wafer and providing a water bonding layer. The wafer bonding layer is provided separately on a contact surface layer of the first or second wafer as part of a CMOS compatible processing recipe. | 02-19-2015 |
20150061134 | SEMICONDUCTOR DEVICES INCLUDING AIR GAP SPACERS AND METHODS OF MANUFACTURING THE SAME - A spacer covering a sidewall of a contact plug includes a relatively more damaged first portion and a relatively less damaged second portion. An interface of the first and second portions of the spacer is spaced apart from a metal silicide layer of the contact plug. Thus reliability of the semiconductor device may be improved. Related fabrication methods are also described. | 03-05-2015 |
20150061135 | COPPER INTERCONNECT WITH CVD LINER AND METALLIC CAP - A structure having a diffusion barrier positioned adjacent to a sidewall and a bottom of an opening being etched in a layer of dielectric material. The structure also having a metal liner positioned directly on top of the diffusion barrier, a seed layer positioned directly on top of the metal liner, wherein the seed layer is made from a material comprising copper, a copper material positioned directly on top of the seed layer, a metallic cap positioned directly on top of and selective to the copper material, and a capping layer positioned directly on top of and adjacent to the metallic cap. | 03-05-2015 |
20150069611 | METAL NANOPARTICLES GROWN ON AN INNER SURFACE OF OPEN VOLUME DEFECTS WITHIN A SUBSTRATE - The present invention provides a method for forming metal nanoparticle(s) onto an inner surface of one or more open volume defects within a substrate by providing the substrate containing the one or more open volume defects, depositing an immiscible metal on a surface of the substrate, and forming the metal nanoparticle(s) by diffusing the immiscible metal from the surface onto the inner surface of each open volume defect using a heat treatment. The method can be used to produce a substrate having at least one open volume defect with a metal nanoparticle formed onto an inner surface of the open volume defect, a solar cell, an optical switch, a radiation detector, or other similar device. | 03-12-2015 |
20150076694 | INTERPOSER STRUCTURE AND MANUFACTURING METHOD THEREOF - An interposer structure including a semiconductor substrate, a plurality of shallow trenches, a plurality of deep trenches and a plurality of metal damascene structures is provided. The semiconductor substrate has a first surface and a second surface opposite to each other. The shallow trenches are formed on the first surface in both of a first area and a second area of the semiconductor substrate and correspondingly a plurality of respective openings are formed on the first surface. The deep trenches extend from at least one of the shallow trenches toward the second surface in the second area and correspondingly a plurality of respective openings are formed on the second surface. The metal damascene structures are filled in both of the shallow trenches and the deep trenches. A manufacturing method for the aforementioned interposer structure is also provided. | 03-19-2015 |
20150076695 | SELECTIVE PASSIVATION OF VIAS - A method of forming an integrated circuit structure includes forming a cap layer above a first ILD layer of a first metal level, the first ILD layer includes a recess filled with a first conductive material to form a first interconnect structure. Next, a second ILD layer is formed above the cap layer and a via is formed within the second ILD layer as a second interconnect structure of a second metal level. The via is aligned with the first interconnect structure. Subsequently, a portion of the cap layer is removed to extend the via to expose a top portion of the first conductive material then a passivation cap is selectively formed at a bottom portion of the via in the second ILD layer and the passivation cap contacting the top portion of the first conductive material. The passivation cap includes a metal alloy to form an interface between the bottom portion of the via and the first conductive material. | 03-19-2015 |
20150076696 | MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A memory device comprises a substrate, a plurality of buried word lines, a plurality of digital contacts, a patterned insulating layer, a liner layer, a plurality of buried bit lines, and a cap layer. The buried word lines are arranged in the substrate in parallel along a first direction. Each of the digital contacts is arranged between one pair of the neighboring buried word lines. The patterned insulating layer is arranged on the buried word lines, having a plurality of contact holes opposite to the digital contacts. The liner layer is arranged on the substrate, and abuts the patterned insulating layer. The buried bit lines are arranged in parallel along a second direction different from the first direction. The cap layer arranged to cover the buried bit lines. | 03-19-2015 |
20150076697 | DUMMY BARRIER LAYER FEATURES FOR PATTERNING OF SPARSELY DISTRIBUTED METAL FEATURES ON THE BARRIER WITH CMP - A semiconductor device comprises a plurality of device features formed on a substrate and a plurality of dummy features formed on the substrate and across an open region between the device features. Adjacent device features are spaced apart by a distance of 100 microns or more. Each device feature includes a barrier island and a metal layer on top of the barrier island. Each dummy feature has a structure that corresponds to the structure of the barrier island. This abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 03-19-2015 |
20150084195 | SEMICONDUCTOR DEVICE HAVING FEATURES TO PREVENT REVERSE ENGINEERING - An electronic device includes: a base layer; a first layer located at least partially over the base layer; a second layer located at least partially over the first layer; a first metal layer located at least partially over the second layer, wherein one or more signal outputs of the electronic device are formed in the first metal layer; and a second metal layer located at least partially over the first metal layer, wherein one or more gate connection is formed in the second metal layer, wherein removing a portion of the second metal layer disrupts at least one gate connection and deactivates the device. | 03-26-2015 |
20150084196 | Devices Formed With Dual Damascene Process - Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask. | 03-26-2015 |
20150091173 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND POWER SUPPLY APPARATUS - A semiconductor device includes an electrode material diffusion suppression layer provided either between a gate electrode and a gate insulation film, between Al-containing ohmic electrodes and an Au interconnection, and below the gate electrode and above the Al-containing ohmic electrodes, the electrode material diffusion suppression layer having a structure wherein a first the TaN layer, a Ta layer, and a second the TaN layer are stacked in sequence. | 04-02-2015 |
20150097289 | HYBRID PHOTONIC AND ELECTRONIC INTEGRATED CIRCUITS - A sequence of processing steps presented herein is used to embed an optical signal path within an array of nanowires, using only one lithography step. Using the techniques disclosed, it is not necessary to mask electrical features while forming optical features, and vice versa. Instead, optical and electrical signal paths can be created substantially simultaneously in the same masking cycle. This is made possible by a disparity in the widths of the respective features, the optical signal paths being significantly wider than the electrical ones. Using a damascene process, the structures of disparate widths are plated with metal that over-fills narrow trenches and under-fills a wide trench. An optical cladding material can then be deposited into the trench so as to surround an optical core for light transmission. | 04-09-2015 |
20150097290 | COMPOSITE METAL TRANSMISSION LINE BRIDGE STRUCTURE FOR MONOLITHIC MICROWAVE INTEGRATED CIRCUITS (MMICs) - A structure having first and second electrical conductors disposed on a surface of the structure and a bridging conductor connected between the first electrical conductor and the second electrical conductor with portions disposed over the surface of the structure. The bridging conductor includes a plurality of stacked, multi-metal layers, each one of the multi-metal layers having: an electrically conductive layer; and a pair of barrier metal layers, the electrically conductive layer being disposed between and in direct contact with the pair of barrier metal layers. | 04-09-2015 |
20150097291 | INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH CAPPING LAYERS BETWEEN METAL CONTACTS AND INTERCONNECTS - Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a metal contact structure, an electrically conductive capping layer formed on the metal contact structure, and a conductive via electrically connected to the metal contact structure through the electrically conductive capping layer. | 04-09-2015 |
20150102491 | Semiconductor Device Including A Contact Plug With Barrier Materials - Disclosed herein is a semiconductor device that comprises a plug including an upper portion, a lower portion and a side surface and comprising tungsten, a barrier metal comprising tungsten nitride and covering the side surface and the lower portion of the contact plug, a conductive layer, and a barrier layer comprising titanium and intervening between the barrier metal and the first conductive layer. | 04-16-2015 |
20150108644 | 3D Integrated Circuit and Methods of Forming the Same - An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer. | 04-23-2015 |
20150108645 | INTEGRATED CRACKSTOP - A method including forming a first dielectric layer above a conductive pad and above a metallic structure, the conductive pad and the metallic structure are each located within an interconnect level above a substrate, forming a first opening and a second opening in the first dielectric layer, the first opening is aligned with and exposes the conductive pad and the second opening is aligned with and exposes the metallic structure, and forming a metallic liner on the conductive pad, on the metallic structure, and above the first dielectric layer. The method may further include forming a second dielectric layer above the metallic liner, and forming a third dielectric layer above the second dielectric layer, the third dielectric layer is thicker than either the first dielectric layer or the second dielectric layer. | 04-23-2015 |
20150108646 | ELECTRO-MIGRATION ENHANCING METHOD FOR SELF-FORMING BARRIER PROCESS IN COPPER METTALIZATION - A method of forming a barrier on both the sidewalls and bottom of a via and the resulting device are provided. Embodiments include forming a metal line in a substrate; forming a Si-based insulating layer over the metal line and the substrate; forming a via in the Si-based insulating layer down to the metal line; forming a dual-layer Mn/MnN on sidewalls and a bottom surface of the via; and filling the via with metal. | 04-23-2015 |
20150108647 | HYBRID MANGANESE AND MANGANESE NITRIDE BARRIERS FOR BACK-END-OF-LINE METALLIZATION AND METHODS FOR FABRICATING THE SAME - A method for fabricating an integrated circuit includes providing a conductive material overlying a semiconductor substrate and a dielectric material overlying the conductive material, wherein an opening exposes a surface of the conductive material and sidewalls of the dielectric material and selectively depositing a first layer of a first barrier material on the surface of the conductive material with the sidewalls of the dielectric material remaining exposed, the first barrier material being such that, if annealed in an annealing process, the first barrier material would diffuse into the conductive material. The method further includes modifying the first barrier material on the exposed surface to form a second barrier material, the second barrier material being such that, during an annealing process, the second barrier material does not diffuse into the conductive material and depositing a second layer of the first barrier material along the sidewalls of the opening. Still further, the method includes annealing the semiconductor substrate. Integrated circuits fabricated in accordance with the foregoing method are also disclosed. | 04-23-2015 |
20150108648 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes first and second semiconductor members and a first barrier film. The first semiconductor member includes a first insulating film, and a first wiring film in the first insulating film, the surface of which is exposed in the first insulating film. The second semiconductor member includes a second insulating film, and a second wiring film in the second insulating film, the surface of which is exposed in the second insulating film. The first barrier film forms a barrier to diffusion of the material of the first wiring film into the second insulating film and is formed of a compound of metal element of the first wiring film and an element of the second insulating film in a region where the first wiring film and the second insulating film are in contact with each other at the junction interface of the first and second semiconductor members. | 04-23-2015 |
20150108649 | METHOD OF FORMING HYBRID DIFFUSION BARRIER LAYER AND SEMICONDUCTOR DEVICE THEREOF - In a method of fabricating a semiconductor device, an opening is formed inside a dielectric layer above a semiconductor substrate. The opening has a wall. At least one diffusion barrier material is then formed over the wall of the opening by at least two alternating steps, which are selected from the group consisting of a process of physical vapor deposition (PVD) and a process of atomic layer deposition (ALD). A liner layer is formed over the at least one diffusion barrier material. | 04-23-2015 |
20150115447 | INTERCONNECTS FOR SEMICONDUCTOR DEVICES - A semiconductor substructure with improved performance and a method of forming the same is described. The method includes providing a semiconductor dielectric layer having a recess formed therein; forming an interconnect structure with a metal liner and a conductive fill within the recess; and applying an electron beam treatment to the substructure. | 04-30-2015 |
20150115448 | METHOD FOR PROCESSING WAFER - A method for processing a wafer including a plurality of chips is provided. The method may include: forming a trench in the wafer between the plurality of chips; forming a diffusion barrier layer at least over the sidewalls of the trench; forming encapsulation material over the plurality of chips and in the trench; and singularizing the plurality of chips from a side opposite the encapsulation material. | 04-30-2015 |
20150115449 | Semiconductor Device Having a Corrosion-Resistant Metallization and Method for Manufacturing Thereof - A semiconductor device includes a semiconductor substrate having a first side, a second side opposite the first side, an active area, an outer rim, and an edge termination area arranged between the outer rim and the active area. A metallization structure is arranged on the first side of the semiconductor substrate and comprising at least a first metal layer comprised of a first metallic material and a second metal layer comprised of a second metallic material, wherein the first metallic material is electrochemically more stable than the second metallic material. The first metal layer extends laterally further towards the outer rim than the second metal layer. | 04-30-2015 |
20150115450 | In-Situ Formation of Silicon and Tantalum Containing Barrier - A method includes forming an opening in a dielectric layer, and forming a silicon rich layer on a surface of the dielectric layer. A portion of the silicon rich layer extends into the opening and contacts the dielectric layer. A tantalum-containing layer is formed over and the contacting the silicon rich layer. An annealing is performed to react the tantalum-containing layer with the silicon rich layer, so that a tantalum-and-silicon containing layer is formed. | 04-30-2015 |
20150123278 | SEMICONDUCTOR DEVICES, METHODS OF MANUFACTURING THE SAME, MEMORY CARDS INCLUDING THE SAME AND ELECTRONIC SYSTEMS INCLUDING THE SAME - Semiconductor devices are provided. The semiconductor device includes a through electrode penetrating a substrate such that an end portion of the through electrode protrudes from a surface of the substrate, a passivation layer covering the surface of the substrate and defining a plug hole that exposes the end portion of the through electrode, and a barrier plug filling the plug hole. Related methods, related memory cards and related electronic systems are also provided. | 05-07-2015 |
20150123279 | Structure and Method for Forming Interconnect Structure - A method for forming a semiconductor structure includes providing a semiconductor substrate and forming a dielectric layer over the semiconductor substrate. An opening is formed in the dielectric layer. A conductive line is formed in the opening, wherein the conductive line has an open void formed therein. A sealing metal layer is formed overlying the conductive line, the dielectric layer, and the open void, wherein the sealing metal layer substantially fills the open void. The sealing metal layer is planarized so that a top surface thereof is substantially level with a top surface of the conductive line. An interconnect feature is formed above the semiconductor substrate, wherein the interconnect feature is electrically coupled with the conductive line and the sealing metal layer-filled open void. | 05-07-2015 |
20150130063 | METHOD TO USE SELF-REPAIR CU BARRIER TO SOLVE BARRIER DEGRADATION DUE TO RU CMP - A method of forming a doped TaN Cu barrier adjacent to a Ru layer of a Cu interconnect structure and the resulting device are provided. Embodiments include forming a cavity in a SiO-based ILD; conformally forming a doped TaN layer in the cavity and over the ILD; conformally forming a Ru layer on the doped TaN layer; depositing Cu over the Ru layer and filling the cavity; planarizing the Cu, Ru layer, and doped TaN layer down to an upper surface of the ILD; forming a dielectric cap over the Cu, Ru layer, and doped TaN layer; and filling spaces formed between the dielectric cap and the doped TaN layer | 05-14-2015 |
20150130064 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES AND A SEMICONDUCTOR STRUCTURE - Processes for improving adhesion of films to semiconductor wafers and a semiconductor structure are provided. By implementing the processes of the invention, it is possible to significantly suppress defect creation, e.g., decrease particle generation, during wafer fabrication processes. More specifically, the processes described significantly reduce flaking of a TaN film from edges or extreme edges (bevel) of the wafer by effectively increasing the adhesion properties of the TaN film on the wafer. The method increasing a mol percent of nitride with respect to a total tantalum plus nitride to 25% or greater during a barrier layer fabrication process. | 05-14-2015 |
20150137372 | SELF FORMING BARRIER LAYER AND METHOD OF FORMING - Methods for forming a self-forming barrier layer and the resulting devices are disclosed. Embodiments may include forming a metal line above a substrate, forming a reagent layer above the metal line and the substrate, forming a dielectric layer on the reagent layer, and transforming the reagent layer into a self-forming barrier layer. | 05-21-2015 |
20150137373 | INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH IMPROVED CONTACT STRUCTURES - Integrated circuits with improved contact structures and methods for fabricating integrated circuits with improved contact structures are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a device in and/or on a semiconductor substrate. Further, the method includes forming a contact structure in electrical contact with the device. The contact structure includes silicate barrier portions overlying the device, a barrier metal overlying the device and positioned between the silicate barrier portions, and a fill metal overlying the barrier metal and positioned between the silicate barrier portions. | 05-21-2015 |
20150137374 | COPPER WIRE AND DIELECTRIC WITH AIR GAPS - Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers. | 05-21-2015 |
20150137375 | COPPER WIRE AND DIELECTRIC WITH AIR GAPS - Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers. | 05-21-2015 |
20150137376 | Semiconductor Structure and Semiconductor Fabricating Process for the Same - A semiconductor structure and a fabricating process for the same are provided. The semiconductor fabricating process includes providing a first dielectric layer, a transitional layer formed on the first dielectric layer, and a conductive fill penetrated through the transitional layer and into the first dielectric layer; removing the transitional layer; and forming a second dielectric layer over the conductive fill and the first dielectric layer. | 05-21-2015 |
20150145134 | Method for Forming Recess-Free Interconnect Structure - A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. An oxygen-rich layer is formed over the dielectric material layer. The dielectric material layer and the oxygen-rich layer are patterned to form a plurality of vias in the semiconductor substrate. A barrier layer is formed in the plurality of vias and on the dielectric material layer leaving a portion of the oxygen-rich layer exposed. A metal layer is formed on the bather layer and on the exposed portion of the oxygen-rich layer, wherein the metal layer fills the plurality of vias. The semiconductor substrate is annealed at a predetermined temperature range and at a predetermined pressure to transform the exposed portion of the oxygen-rich layer into a metal-oxide stop layer. | 05-28-2015 |
20150294950 | METHOD FOR TERNARY WAFER BONDING AND STRUCTURE THEREOF - The present invention relates to a method for ternary wafer bonding and the structure thereof. According to the present invention, silver island structures in the second bonding layer are distributed on the first bonding layer deposited on the surface of a single silicon wafer for forming a gold-silver combination structure, which is then bonded with another silicon wafer without any metal layers thereon at a low-temperature thermal process of 250° C. for completing gold-silver-silicon ternary wafer bonding. Thus, the temperature required for gold-silicon bonding is lowered and the process of wafer bonding is simplified as well. In addition, the quality of wafer bonding is also assured. | 10-15-2015 |
20150303100 | Semiconductor Constructions and Methods of Forming Electrically Conductive Contacts - Some embodiments include methods of forming electrically conductive contacts. An opening is formed through an insulative material to a conductive structure. A conductive plug is formed within a bottom region of the opening. A spacer is formed to line a lateral periphery of an upper region of the opening, and to leave an inner portion of an upper surface of the plug exposed. A conductive material is formed against the inner portion of the upper surface of the plug. Some embodiments include semiconductor constructions having a conductive plug within an insulative stack and against a copper-containing material. A spacer is over an outer portion of an upper surface of the plug and not directly above an inner portion of the upper surface. A conductive material is over the inner portion of the upper surface of the plug and against an inner lateral surface of the spacer. | 10-22-2015 |
20150311150 | Metal Contact Structure and Method of Forming the Same - A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer. | 10-29-2015 |
20150311152 | Interconnection Structure And Method For Semiconductor Device - A semiconductor device is disclosed. The device includes a substrate, a first dielectric layer disposed over the substrate and a metal structure disposed in the first dielectric layer and below a surface of the first dielectric layer. The metal structure has a such shape that having an upper portion with a first width and a lower portion with a second width. The second width is substantially larger than the first width. The semiconductor device also includes a sub-structure of a second dielectric positioned between the upper portion of the metal structure and the first dielectric layer. | 10-29-2015 |
20150311161 | SELECTIVE PLATING WITHOUT PHOTORESIST - A method including forming a stack of layers on top of a dielectric layer and within an opening in the dielectric layer, the stack of layers comprising a first layer, a second layer, a third layer, and a fourth layer, each formed successively one on top of another, removing a first portion of the fourth layer outside the opening to expose a portion of the third layer, a second portion of the fourth layer remains within the opening, filling the opening with a metal by applying an electrical potential to the second layer during an electroplating technique in which the metal plates out on the fourth layer but does not plate out on the third layer, and removing portions of the first layer, the second layer, and the third layer to expose an upper surface of the dielectric layer between the opening and an adjacent opening. | 10-29-2015 |
20150318207 | BACK-END-OF-LINE (BEOL) INTERCONNECT STRUCTURE - A method of fabricating an interconnect structure on a wafer and an interconnect structure are provided. A dielectric layer is provided on the wafer, with the dielectric layer having a recess therein. A silicon (Si) layer is deposited in the recess. An interconnect is formed by providing a barrier layer and a conductive layer in the recess over the Si layer. The Si layer has a density that prevents or substantially prevents the barrier layer from moving away from the conductive layer and towards the dielectric layer during subsequent processing of the interconnect structure. | 11-05-2015 |
20150318243 | Composite Contact Plug Structure and Method of Making Same - An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer structure includes a conductive core and a conductive liner on a sidewall and a bottom surface of the conductive core. In the embodiment contact plug, the conductive liner comprises cobalt or ruthenium. | 11-05-2015 |
20150325523 | CHIP WITH PROGRAMMABLE SHELF LIFE - A method includes forming a first interconnect structure and a second interconnect structure each located within an interlevel dielectric (ILD). A first top metal layer and a second top metal layer are formed disposed on and in direct electrical connection with the first interconnect. Similarly, a third top metal layer and a fourth top metal layer are formed disposed on and in direct electrical connection with the second interconnect. A silicon layer is deposited above the first, second, third and fourth top metal layers in direct contact with the first and fourth top metal layers and separated from each of the second and third top metal layers by a barrier layer. The silicon layer is exposed to an oxygen-containing environment to form a silicon dioxide layer. | 11-12-2015 |
20150333006 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device comprises releasing an oxidation source included in an interlayer dielectric film having an opening portion formed on a surface thereof and being present on the surface of the interlayer dielectric film at a first substrate temperature, forming a first layer containing Ti and N to contact with at least a part of the interlayer dielectric film at a second substrate temperature lower than the first substrate temperature, wherein a Ti content in the first layer is more than 50 at % in all components, provided that oxygen and precious metals are excluded from the all components, and forming a Cu metal layer above the first layer. | 11-19-2015 |
20150333009 | ENHANCING BARRIER IN AIR GAP TECHNOLOGY - A method of forming a semiconductor structure including a barrier layer between a metal line and an air gap oxide layer. The barrier layer may be formed in-situ or by a thermal annealing process and may prevent diffusion or electrical conduction. | 11-19-2015 |
20150333011 | SEMICONDUCTOR DEVICE HAVING AIR GAP STRUCTURES AND METHOD OF FABRICATING THEREOF - One method includes forming a conductive feature in a dielectric layer on a substrate. A first hard mask layer and an underlying second hard mask layer are formed on the substrate. The second hard mask layer has a higher etch selectivity to a plasma etch process than the first hard mask layer. The second hard mask layer may protect the dielectric layer during the formation of a masking element. The method continues to include performing plasma etch process to form a trench in the dielectric layer, which may also remove the first hard mask layer. A cap is then formed over the trench to form an air gap structure adjacent the conductive feature. | 11-19-2015 |
20150333012 | METHOD OF FORMING A COPPER LAYER USING PHYSICAL VAPOR DEPOSITION - A method of forming a semiconductor structure includes the steps: providing a substrate; forming a dielectric over the substrate; forming an opening recessed under a top surface of the dielectric; forming a barrier layer on a sidewall of the opening; performing a physical vapor deposition (PVD) to form a copper layer over the barrier layer, a corner of the opening intersecting with the top surface and the top surface with a predetermined resputter ratio so that the ratio of the thickness of the copper layer on the barrier layer and the thickness of the copper layer over the top surface is substantially greater than 1. | 11-19-2015 |
20150340269 | METHOD OF PLANARIZING RECESSES FILLED WITH COPPER - A structure includes a substrate having an upper surface provided with recesses and coated with a continuous barrier layer topped with a continuous copper layer filling at least the recesses. The structure is planarized by: a) chemical-mechanical polishing of the copper, such a polishing being selective with respect to the barrier layer so that copper remains in the recesses and is set back with respect to the upper surface of the substrate; b) depositing on the exposed surface of the structure a material covering at least the copper at the level of the recesses; and c) chemical-mechanical planarizing of the structure to expose the substrate with the copper remaining buried under the material. Two such structures are then direct bonded to each other with opposite areas of material having a same topology. | 11-26-2015 |
20150340323 | SELF-FORMING EMBEDDED DIFFUSION BARRIERS - Interconnect structures containing metal oxide embedded diffusion barriers and methods of forming the same. Interconnect structures may include an M | 11-26-2015 |
20150345045 | METHOD FOR ELECTROCHEMICALLY DEPOSITING METAL ON A REACTIVE METAL FILM - In accordance with one embodiment of the present disclosure, a method for depositing metal on a reactive metal film on a workpiece includes electrochemically depositing a metallization layer on a seed layer formed on a workpiece using a plating electrolyte having at least one plating metal ion, a pH range of about 1 to about 6, and applying a cathodic potential in the range of about −0.5 V to about −4 V. The workpiece includes a barrier layer disposed between the seed layer and a dielectric surface of the workpiece, the barrier layer including a first metal having a standard electrode potential more negative than 0 V and the seed layer including a second metal having a standard electrode potential more positive than 0 V. | 12-03-2015 |
20150348826 | METHOD FOR ELECTROCHEMICALLY DEPOSITING METAL ON A REACTIVE METAL FILM - In accordance with one embodiment of the present disclosure, a method for depositing metal on a reactive metal film on a workpiece includes obtaining a workpiece including a dielectric surface; forming a barrier layer on the dielectric surface; depositing a seed layer on the barrier layer, wherein the barrier and seed stack includes at least one metal having a standard electrode potential of less than 0.34 V; and depositing a metallization layer on the seed layer using a diluted acid bath in a pH range of about 1 to about 5 and a current density in the range of about 10 mA/cm2 to about 30 mA/cm2. | 12-03-2015 |
20150348833 | Method to etch cu/Ta/TaN selectively using dilute aqueous Hf/hCl solution - Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper film can be recessed more than the liner to further enhance the protection. Wet etch solutions including a mixture of HF and HCl can be used for selective etching copper with respect to the liner material, for example, the copper film can be recessed between 2 and 3 nm, and the barrier liner film can be recessed between 1.5 and 2 nm. | 12-03-2015 |
20150348835 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for forming an interconnect device is provided by the present disclosure. The method includes providing a dielectric layer on a substrate, forming openings in the dielectric layer to expose a portion of a surface of the substrate at a bottom of each opening and forming a metal layer to fill up the openings. The method also includes forming a semiconductor cover layer on the metal layer and on the dielectric layer, and performing a thermal annealing reaction to convert portions of the semiconductor cover layer that are on the metal layer into a metal capping layer. The method further includes performing a nitridation process on the metal capping layer and a remaining semiconductor cover layer to convert the metal capping layer into a metal nitride capping layer and the remaining semiconductor cover layer into a semiconductor nitride layer. | 12-03-2015 |
20150348836 | METHODS FOR DEPOSITING METAL ON A REACTIVE METAL FILM - In accordance with one embodiment of the present disclosure, a method for depositing metal on a reactive metal film on a workpiece includes obtaining a workpiece including a dielectric surface; forming a barrier layer on the dielectric surface; depositing a seed layer on the barrier layer, wherein the barrier and seed stack includes at least one metal having a negative standard electrode potential; and depositing a metallization layer on the seed layer using a bath having a pH range of about 6 to about 11 and a current density in the range of about 1 mA/cm2 to about 5 mA/cm2. | 12-03-2015 |
20150348871 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a substrate having a first side and a second side opposite to the first side; a through substrate via (TSV) structure protruding from a surface of the substrate on the second side; a block layer conformally covering the surface of the substrate and the TSV structure; a first dielectric layer covering the block layer except for a portion of the block layer that is directly on the TSV structure; a second dielectric layer on the first dielectric layer; and a damascened circuit pattern in the second dielectric layer. The second dielectric layer is in direct contact with the first dielectric layer. The damascened circuit pattern is in direct contact with the TSV structure. | 12-03-2015 |
20150348910 | SELECTIVE PLATING WITHOUT PHOTORESIST - A structure including a stack of conformal layers on top of a dielectric layer and within an opening in the dielectric layer, the stack of layers including a first layer, a second layer, a third layer, and a fourth layer, each formed successively one on top of another with the first layer being in direct contact with the dielectric layer, and a conductive feature located directly on top of the fourth layer within the opening. | 12-03-2015 |
20150348911 | INTERCONNECT STRUCTURES AND FABRICATION METHOD THEREOF - A method is provided for fabricating an interconnect structure. The method includes providing a substrate; and forming a first conductive layer; and forming a sacrificial layer on the substrate and the first conductive layer. The method also includes forming an opening exposing a surface of the first conductive layer in the sacrificial layer; and forming a catalyst layer on the exposed portion of the surface of the first conductive layer and a top surface of the sacrificial layer. Further, the method includes forming carbon nanotube bundles perpendicular to the surface of the substrate on the catalyst layer; and removing the sacrificial layer and the carbon bundles on the sacrificial layer. Further, the method also includes forming a first dielectric material layer covering top surfaces of the carbon nanotube bundles and a portion the surface of the substrate without carbon nanotubes to seal the carbon nanotube bundles in a space. | 12-03-2015 |
20150348924 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device comprises an insulative resin, an interconnect, a plurality of semiconductor elements, a first conductive unit, a first connector, and a first metal layer. The insulative resin includes a first region and a second region. At least a portion of the interconnect is arranged with at least a portion of the first region in a first direction. The first conductive unit pierces the second region in the first direction. At least a portion of the first connector is arranged with at least a portion of the first conductive unit in the first direction. At least a portion of the first connector is arranged with at least a portion of the interconnect in a second direction intersecting the first direction. The first metal layer is provided between the first conductive unit and the first connector. The first metal layer contacts the insulative resin. | 12-03-2015 |
20150357236 | Ultrathin Multilayer Metal Alloy Liner for Nano Cu Interconnects - Compositions of matter, compounds, articles of manufacture and processes to reduce or substantially eliminate EM and/or stress migration, and/or TDDB in copper interconnects in microelectronic devices and circuits, especially a metal liner around copper interconnects comprise an ultra thin layer or layers of Mn alloys containing at least one of W and/or Co on the metal liner. This novel alloy provides EM and/or stress migration resistance, and/or TDDB resistance in these copper interconnects, comparable to thicker layers of other alloys found in substantially larger circuits and allows the miniaturization of the circuit without having to use thicker EM and/or TDDB resistant alloys previously used thereby enhancing the miniaturization, i.e., these novel alloy layers can be miniaturized along with the circuit and provide substantially the same EM and/or TDDB resistance as thicker layers of different alloy materials previously used that lose some of their EM and/or TDDB resistance when used as thinner layers. | 12-10-2015 |
20150357286 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a conductive layer, a via, and a barrier layer disposed between the conductive layer and the via. The barrier layer is stuffed with oxygen. | 12-10-2015 |
20150364411 | GALLIUM ARSENIDE DEVICES WITH COPPER BACKSIDE FOR DIRECT DIE SOLDER ATTACH - Electronic devices, and methods of manufacturing the electronic devices, utilizing direct die soldering of GaAs integrated circuit dies. In some embodiments, the GaAs integrated circuit die can have a footprint approximately the same size as a die attach pad. Further, the GaAs integrated circuit die can self-align with the die attach pad after reflow of any solder layer used to attach the die. | 12-17-2015 |
20150364423 | BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES - Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed. | 12-17-2015 |
20150364427 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - Provided is a highly reliable semiconductor device and a method for manufacturing same. The method for manufacturing the semiconductor device includes forming an interlayer insulating film on a semiconductor substrate, forming a conductive plug in the interlayer insulating film, the conductive plug having a top surface for forming the same plane as the top surface of the interlayer insulating film, forming a first titanium film on the interlayer insulating film and the conductive plug, forming an aluminum diffusion-preventing film on the first titanium film, forming a second titanium film on the aluminum diffusion-preventing film, forming an aluminum film on the second titanium film, and shaping the area from the aluminum film to the first titanium film by etching to form wiring. | 12-17-2015 |
20150364462 | SEMICONDUCTOR DEVICE - An ESD protection device including a Si substrate with an ESD protection circuit formed at the surface of the substrate; pads formed on the Si substrate; a rewiring layer opposed to the surface of the Si substrate, which includes terminal electrodes electrically connected to the pads. The rewiring layer includes a SiN protection film formed on the surface of the Si substrate to cover parts of the pads except regions in contact with openings (contact holes) formed in a resin layer, and the resin layer that is lower in dielectric constant than the SiN protection film, and formed between the SiN protection film and the terminal electrodes. Thus, provided is a semiconductor device which can reduce the generation of parasitic capacitance, and eliminates variation in parasitic capacitance generated. | 12-17-2015 |
20150371925 | THROUGH ARRAY ROUTING FOR NON-VOLATILE MEMORY - Technologies for routing access lines in non-volatile memory are described. In some embodiments the technologies include forming one or more through array vias in a portion of a memory array in a non-volatile memory, such as in an array region or peripheral region, one or more access lines may be routed through the through array via, instead of within a region above or below an array or peripheral region of the memory array. This can enable alternative routing configurations, and may enable additional access lines to be routed without increasing or substantially increasing the block height of the non-volatile memory. Non-volatile memory employing such technologies is also described. | 12-24-2015 |
20150371939 | Combination Interconnect Structure and Methods of Forming Same - An embodiment semiconductor device includes a substrate and a dielectric layer over the substrate. The dielectric layer includes a first conductive line and a second conductive line. The second conductive line comprises a different conductive material than the first conductive line. | 12-24-2015 |
20150371943 | SEMICONDUCTOR DEVICE - Semiconductor devices and methods for forming the same in which damages to a low-k dielectric layer therein can be reduced or even prevented are provided. A semiconductor device is provided, comprising a substrate. A dielectric layer with at least one conductive feature therein overlies the substrate. An insulating cap layer overlies the top surface of the low-k dielectric layer adjacent to the conductive feature, wherein the insulating cap layer includes metal ions. | 12-24-2015 |
20150371953 | Schemes for Forming Barrier Layers for Copper in Interconnect Structures - A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided. | 12-24-2015 |
20160005692 | INTERCONNECTS WITH FULLY CLAD LINES - A metallization layer including a fully clad interconnect and a method of forming a fully clad interconnect. An opening is formed in a dielectric layer, wherein the dielectric layer has a surface and the opening includes walls and a bottom. A diffusion barrier layer and an adhesion layer are deposited on the dielectric layer. An interconnect material is deposited on the dielectric layer and reflowed into the opening forming an interconnect. An adhesion capping layer and diffusion barrier capping layer are deposited over the interconnect. The interconnect is surrounded by the adhesion layer and the adhesion capping layer and the adhesion layer and the adhesion capping layer are surrounded by the diffusion barrier layer and the diffusion capping layer. | 01-07-2016 |
20160013072 | CONDUCTIVE PATTERN FORMING METHOD, SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS | 01-14-2016 |
20160013111 | SUBSTRATE STRUCTURE AND DEVICE EMPLOYING THE SAME | 01-14-2016 |
20160013128 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | 01-14-2016 |
20160013135 | SEMICONDUCTOR STRUCTURES AND FABRICATION METHOD THEREOF | 01-14-2016 |
20160013142 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | 01-14-2016 |
20160013160 | WAFER-TO-WAFER BONDING STRUCTURE | 01-14-2016 |
20160020178 | STRUCTURE OF BACKSIDE COPPER METALLIZATION FOR SEMICONDUCTOR DEVICES AND A FABRICATION METHOD THEREOF - An improved structure of backside copper metallization for semiconductor devices and a fabrication method thereof, wherein the improved structure comprises sequentially from top to bottom an active layer, a substrate, a backside metal seed layer, a high-temperature sustaining buffer layer, a backside metal layer and at least one oxidation resistant layer, wherein the backside metal seed layer contains Pd and P, the high-temperature sustaining buffer layer is made of Ni, Ag or Ni alloys, and the backside metal layer is made of Cu. The semiconductor chip using the structure provided by the present invention can sustain high-temperature operations. | 01-21-2016 |
20160027726 | SEMICONDUCTOR DEVICE HAVING AN AIRGAP DEFINED AT LEAST PARTIALLY BY A PROTECTIVE STRUCTURE - An apparatus includes a first interconnect and a first barrier structure. The first barrier structure is in contact with a dielectric material. The apparatus further includes a first protective structure in contact with the first barrier structure and an etch stop layer. An airgap is defined at least in part by the first protective structure and the etch stop layer. | 01-28-2016 |
20160027738 | SEMICONDUCTOR DEVICE WITH REDUCED VIA RESISTANCE - A semiconductor interconnect structure having a first electrically conductive structure having a plurality of bottom portions; a dielectric capping layer, at least a portion of the dielectric capping layer being in contact with a first bottom portion of the plurality of bottom portions; and a second electrically conductive structure in electrical contact with a second bottom portion of the plurality of bottom portions. A method of forming the interconnect structure is also provided. | 01-28-2016 |
20160027746 | Semiconductor Chip and Method for Forming a Chip Pad - A semiconductor chip with different chip pads and a method for forming a semiconductor chip with different chip pads are disclosed. In some embodiments, the method comprises depositing a barrier layer over a chip front side, depositing a copper layer after depositing the barrier layer, and removing a part of the copper layer located outside a first chip pad region, wherein a remaining portion of the copper layer within the first chip pad region forms a surface layer of the chip pad. The method further comprises removing a part of the barrier layer located outside the first chip pad region. | 01-28-2016 |
20160035675 | LOW RESISTIVITY DAMASCENE INTERCONNECT - A damascene interconnect structure may be formed by forming a trench in an ILD. A diffusion barrier may be deposited on trench surfaces, followed by a first liner material. The first liner material may be removed from a bottom surface of the trench. A second liner material may be directionally deposited on the bottom. A conductive seed layer may be deposited on the first and second liner materials, and a conductive material may fill in the trench. A CMP process can remove excess material from the top of the structure. A damascene interconnect may include a dielectric having a trench, a first liner layer arranged on trench sidewalls, and a second liner layer arranged on a trench bottom. A conductive material may fill the trench. The first liner material may have low wettability and the second liner material may have high wettability with respect to the conductive material. | 02-04-2016 |
20160043035 | Contact Structure and Method of Forming - Contact structures and methods of forming contacts structures are contemplated by this disclosure. A structure includes a dielectric layer over a substrate, an adhesion layer, a silicide, a barrier layer, and a conductive material. The dielectric layer has an opening to a surface of the substrate. The adhesion layer is along sidewalls of the opening. The silicide is on the surface of the substrate. The barrier layer is on the adhesion layer and the silicide, and the barrier layer directly adjoins the silicide. The conductive material is on the barrier layer in the opening. | 02-11-2016 |
20160049328 | METHOD FOR IMPROVING ADHESION BETWEEN POROUS LOW K DIELECTRIC AND BARRIER LAYER - A semiconductor device and method for manufacturing the same are provided. The method includes providing a semiconductor substrate, forming a porous low-k dielectric layer on the semiconductor substrate, forming a through-hole and a trench of a copper interconnect structure, performing a helium plasma treatment on an exposed surface of the porous low-k dielectric layer, performing a nitrogen plasma treatment on the exposed surface of the porous low-k dielectric layer to form a silicon nitride layer, performing an argon plasma treatment on the silicon nitride layer, and forming a diffusion barrier layer on bottoms and sidewalls of the through-hole and the trench of the copper interconnect structure. Through the successive helium, nitrogen and argon plasma treatments, the low-k dielectric layer has a smooth and dense surface that increases the adhesion strength between the low-k dielectric layer and the diffusion barrier layer to improve reliability and yield of the semiconductor device. | 02-18-2016 |
20160049362 | Interconnect Structure and Method of Forming the Same - An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a contact layer over a substrate; a dielectric layer over the contact layer, wherein the dielectric layer has an opening, the opening exposing a portion of the contact layer; a silicide layer over the exposed portion of the contact layer; a barrier layer along sidewalls of the opening; an alloy layer over the barrier layer; a glue layer over the alloy layer; and a conductive plug over the glue layer. | 02-18-2016 |
20160049373 | VIA PRE-FILL ON BACK-END-OF-THE-LINE INTERCONNECT LAYER - In some embodiments, the present disclosure relates to a conductive interconnect layer. The conductive interconnect layer has a dielectric layer disposed over a substrate. An opening with an upper portion above a horizontal plane and a lower portion below the horizontal plane extends downwardly through the dielectric layer. A first conductive layer fills the lower portion of the opening. An upper barrier layer is disposed over the first conductive layer covering bottom and sidewall surfaces of the upper portion of the opening. A second conductive layer is disposed over the upper barrier layer filling the upper portion of the opening. | 02-18-2016 |
20160056106 | STRUCTURE WITH SELF ALIGNED RESIST LAYER ON AN INTERCONNECT SURFACE AND METHOD OF MAKING SAME - A structure is provided with a self-aligned resist layer on a surface of metal interconnects for use in forming air gaps in an insulator material and method of fabricating the same. The non-lithographic method includes applying a resist on a structure comprising at least one metal interconnect formed in an insulator material. The method further includes blanket-exposing the resist to energy and developing the resist to expose surfaces of the insulator material while protecting the metal interconnects. The method further includes forming air gaps in the insulator material by an etching process, while the metal interconnects remain protected by the resist. | 02-25-2016 |
20160056112 | INTERCONNECT STRUCTURE - Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer. | 02-25-2016 |
20160056258 | SEMICONDUCTOR DEVICES HAVING POLYSILICON GATE PATTERNS AND METHODS OF FABRICATING THE SAME - A semiconductor device including a gate insulation pattern on a substrate, and a semiconductor gate pattern including an amorphous silicon pattern and a polycrystalline silicon pattern stacked on a side of the gate insulation pattern opposite to the substrate. The amorphous silicon pattern includes anti-diffusion impurities that suppress diffusion of impurity ions in the semiconductor gate pattern. | 02-25-2016 |
20160064269 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device according to an embodiment includes a first wire and a second wire, a bottom nitride film, a side nitride film, and a top layer. The first and second wires are arranged on a base layer. The bottom nitride film is arranged on the base layer between the first and second wires. The side nitride film is respectively arranged on side surfaces of the first and second wires. The top layer is arranged on the first and second wires. An air gap exists between the first and second wires. The air gap is enclosed by the bottom nitride film, the side nitride film, and the top layer in a cross section orthogonal to an extending direction of the wires. | 03-03-2016 |
20160064278 | ELECTRIC CONNECTION ELEMENT MANUFACTURING METHOD - A surface of a silicon substrate is coated with a silicon oxide layer. A manganese silicate layer is then deposited on the silicon oxide layer using a process of performing at least one step of dipping the substrate into a manganese amidinate solution. A copper layer is then deposited on the manganese silicate layer using a process of performing a step of dipping the substrate into a copper amidinate solution. An anneal is performed to stabilize one or both of the manganese silicate layer and copper layer. | 03-03-2016 |
20160064321 | METHOD AND STRUCTURE TO REDUCE THE ELECTRIC FIELD IN SEMICONDUCTOR WIRING INTERCONNECTS - Embodiments of the present invention provide increased distance between vias and neighboring metal lines in a back end of line (BEOL) structure. A copper alloy seed layer is deposited in trenches that are formed in a dielectric layer. The trenches are then filled with copper. An anneal is then performed to create a self-forming barrier using a seed layer constituent, such as manganese, as the manganese is drawn to the dielectric layer during the anneal. The self-forming barrier is disposed on a shoulder region of the dielectric layer, increasing the effective distance between the via and its neighboring metal lines. | 03-03-2016 |
20160064323 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A connection portion connects a copper-based first wiring layer with a copper-based second wiring layer arranged on the upper side of a first diffusion barrier film. The first diffusion barrier film includes a first opening region formed in a semiconductor circuit region that is a partial region in a two-dimensional view and a second opening region formed as an opening region different from the first opening region in a two-dimensional view. The opening regions are formed in a region different from an opening region formed to allow the connection portion to pass through the first diffusion barrier film. A mark wiring layer is arranged immediately above the second opening region as the same layer as the second wiring layer. A second diffusion barrier film is arranged in contact with the upper surface of the mark wiring layer. | 03-03-2016 |
20160064330 | METHOD AND STRUCTURE TO REDUCE THE ELECTRIC FIELD IN SEMICONDUCTOR WIRING INTERCONNECTS - Embodiments of the present invention provide increased distance between vias and neighboring metal lines in a back end of line (BEOL) structure. A copper alloy seed layer is deposited in trenches that are formed in a dielectric layer. The trenches are then filled with copper. An anneal is then performed to create a self-forming barrier using a seed layer constituent, such as manganese, as the manganese is drawn to the dielectric layer during the anneal. The self-forming barrier is disposed on a shoulder region of the dielectric layer, increasing the effective distance between the via and its neighboring metal lines. | 03-03-2016 |
20160064331 | CHIP WITH PROGRAMMABLE SHELF LIFE - A structure includes a first interconnect structure and a second interconnect structure each located within an interlevel dielectric (ILD), a first top metal layer and a second top metal layer disposed on and in direct electrical connection with the first interconnect, a third top metal layer and a fourth top metal layer disposed on and in direct electrical connection with the second interconnect, a silicon dioxide layer above the first, second, third and fourth top metal layers, the silicon layer is in direct contact with the first and fourth top metal layers, and a barrier layer separating the silicon dioxide layer from each of the second and third top metal layers, a high resistance connection exist between the third top metal layer and the fourth top metal layer due to the presence of the silicon dioxide layer. | 03-03-2016 |
20160064333 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes a semiconductor substrate, an interlayer insulating film that is formed on the semiconductor substrate and is provided with a first hole, and a contact portion that is formed in the first hole of the interlayer insulating film. The contact portion includes a first silicon film along an inner surface of the first hole of the interlayer insulating film. | 03-03-2016 |
20160064344 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - The present invention makes it possible to: reduce the manufacturing cost of a semiconductor device having a redistribution layer; and further improve the reliability of a semiconductor device having a redistribution layer. | 03-03-2016 |
20160071801 | SEMICONDUCTOR DEVICE ETCHING FOR RC DELAY IMPROVEMENT - In an etching method for fabricating a semiconductor device, at first, a semiconductor substrate including a contact region is provided. Then, a metallic nitride layer is formed on the semiconductor substrate to prevent over-etching. Thereafter, a dielectric layer is formed on the metallic nitride layer. Then, an etching process is performed to form an opening passing through the metallic nitride layer and the dielectric layer to expose the contact region. The etching method may further include forming a diffusion barrier layer between the metallic nitride layer and the semiconductor substrate to prevent diffusion of a material of the contact region. | 03-10-2016 |
20160071802 | SINGLE DAMASCENE INTERCONNECT STRUCTURE - A single damascene interconnect structure which includes a first layer that includes a first dielectric material having a first filled opening that has a barrier layer of a refractory material with Cu filling the first filled opening. Also included is a second layer of a second dielectric material having a second filled opening that has a sidewall layer which includes a compound of a metal, O, and Si such that the metal is Mn, Ti and Al, and with Cu filling the second filled opening. The compound is in direct contact with the second dielectric material. The first layer is adjacent to the second layer and the first filled opening is aligned with the second filled opening so that the first filled opening is a via and the second filled opening is a trench. | 03-10-2016 |
20160079168 | INTEGRATED CIRCUITS WITH METAL-TITANIUM OXIDE CONTACTS AND FABRICATION METHODS - Devices and methods for forming semiconductor devices with metal-titanium oxide contacts are provided. One intermediate semiconductor device includes, for instance: a substrate, at least one field-effect transistor disposed on the substrate, a first contact region positioned over at least a first portion of the at least one field-effect transistor between a spacer and an interlayer dielectric, and a second contact region positioned over at least a second portion of the at least one field-effect transistor between a spacer and an interlayer dielectric. One method includes, for instance: obtaining an intermediate semiconductor device and forming at least one contact on the intermediate semiconductor device. | 03-17-2016 |
20160079172 | ADHESION LAYER FOR INTERCONNECT STRUCTURE - Alternative methods of fabricating an interconnect structure having an adhesion layer, wherein the surfaces of the adhesion layer may be altered to correspond to the materials that are adhered to that surface. | 03-17-2016 |
20160079173 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an ultra low-k (ULK) dielectric layer on the substrate; forming a hard mask on the ULK dielectric layer; forming an opening in the hard mask and the ULK dielectric layer; forming a conductive layer in the opening and on the hard mask; planarizing the conductive layer; and removing the hard mask to expose the ULK dielectric layer so that the top surface of the ULK dielectric layer is lower than the top surface of the conductive layer. | 03-17-2016 |
20160086874 | SEMICONDUCTOR DEVICES INCLUDING THROUGH-SILICON-VIAS AND METHODS OF MANUFACTURING THE SAME AND SEMICONDUCTOR PACKAGES INCLUDING THE SEMICONDUCTOR DEVICES - A semiconductor device can include a substrate that has a surface. A via structure can extend through the substrate toward the surface of the substrate, where the via structure includes an upper surface. A pad structure can be on the surface of the substrate, where the pad structure can include a lower surface having at least one protrusion that is configured to protrude toward the upper surface of the via structure. | 03-24-2016 |
20160104638 | SEMICONDUCTOR STRUCTURE INCLUDING A LAYER OF A FIRST METAL BETWEEN A DIFFUSION BARRIER LAYER AND A SECOND METAL AND METHOD FOR THE FORMATION THEREOF - A method includes providing a semiconductor structure including a recess. The recess includes at least one of a contact via and a trench. A layer of a first metal is deposited over the semiconductor structure. An electroless deposition process is performed. The electroless deposition process removes a first portion of the layer of first metal from the semiconductor structure and deposits a first layer of a second metal over the semiconductor structure. An electroplating process is performed. The electroplating process deposits a second layer of the second metal over the first layer of second metal. A second portion of the layer of first metal remains in the semiconductor structure. | 04-14-2016 |
20160104639 | SURFACE TREATMENT TO IMPROVE CCTBA BASED CVD CO NUCLEATION ON DIELECTRIC SUBSTRATE - Embodiments of the present invention generally relate to a method of forming a cobalt layer on a dielectric material without incubation delay. Prior to depositing the cobalt layer using CVD, the surface of the dielectric material is pretreated at a temperature between 100° C. and 250° C. Since the subsequent CVD cobalt process is also performed at between 100° C. and 250° C., one processing chamber is used for pretreating the dielectric material and forming of the cobalt layer. The combination of processing steps enables use of two processing chambers to deposit cobalt. | 04-14-2016 |
20160104680 | METHOD OF FORMING METAL INTERCONNECTIONS OF SEMICONDUCTOR DEVICE - A method of forming a metal interconnection of semiconductor device is provided. The method includes forming a low-k dielectric layer including an opening; forming a barrier metal pattern conformally covering a bottom surface and an inner sidewall of the opening; forming a metal pattern exposing a part of the inner sidewall of the barrier metal pattern in the opening; forming a metal capping layer on the top surfaces of the metal pattern and the low-k dielectric layer using a selective chemical vapor deposition process, wherein the thickness of the metal capping layer on the metal pattern is greater than the thickness of the metal capping layer on the low-k dielectric layer; and forming a metal capping pattern covering the top surface of the metal pattern by planarizing the metal capping layer down to the top surface of the low-k dielectric layer. | 04-14-2016 |
20160111371 | STRUCTURE AND FORMATION METHOD OF DAMASCENE STRUCTURE - A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first conductive feature over the semiconductor substrate. The semiconductor device also includes a first dielectric layer over the semiconductor substrate and surrounding the first conductive feature. The semiconductor device further includes a second conductive feature over the first conductive feature, and the second conductive feature extends into the first conductive feature. In addition, the semiconductor device includes a second dielectric layer over the first dielectric layer and surrounding the second conductive feature. | 04-21-2016 |
20160111383 | METHOD OF USING ALUMINUM LAYER AS ETCHING STOP LAYER FOR PATTERNING A PLATINUM LAYER - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a dielectric layer; forming an aluminum layer on the dielectric layer; forming a platinum layer on the aluminum layer; performing a first etching process to remove part of the platinum layer and part of the aluminum layer for forming a patterned platinum layer; and performing a second etching process to remove part of the aluminum layer exposed by the patterned platinum layer and part of the dielectric layer. | 04-21-2016 |
20160118340 | Low-Resistance Interconnects and Methods of Making Same - Devices and methods for providing low-resistance interconnects in a semiconductor device are provided. Specifically, one or more embodiments of the present invention relate to disposing a conductive material in a trench without disposing a resistive barrier material between the conductive material and the sidewalls of the trench so that the conductive material takes up the full width of the trench. For example, the trench may be disposed over one or more contacts made of a barrier material such as titanium nitride that also acts as a seed, and the conductive material may be grown on top of the titanium nitride to fill the trench. | 04-28-2016 |
20160126135 | METHODS OF FORMING AN IMPROVED VIA TO CONTACT INTERFACE BY SELECTIVE FORMATION OF A METAL SILICIDE CAPPING LAYER - One illustrative method disclosed herein includes, among other things, forming an opening in at least one layer of insulating material so as to thereby expose at least a portion of a conductive contact, performing a selective metal silicide formation process to selectively form a metal silicide layer in the opening and on the conductive contact, depositing at least one conductive material above the selectively formed metal silicide layer so as to over-fill the opening, and performing at least one planarization process so as to remove excess materials and thereby define a conductive via that is positioned in the opening and conductively coupled to the selectively formed metal silicide layer and to the conductive contact. | 05-05-2016 |
20160126186 | BOND PAD STRUCTURE WITH DUAL PASSIVATION LAYERS - A bond pad structure with dual passivation layers is disclosed. The bond pad structure includes: a pad material layer on a first passivation layer; a protection layer on the top surface of the pad material layer; a second passivation layer covering on the first passivation layer and the protection layer; and an opening formed through the second passivation layer and the protection layer to expose the pad material layer. | 05-05-2016 |
20160126190 | METHODS OF FORMING AN IMPROVED VIA TO CONTACT INTERFACE BY SELECTIVE FORMATION OF A CONDUCTIVE CAPPING LAYER - One illustrative method disclosed herein includes, among other things, forming an opening in a layer of insulating material so as to thereby expose at least a portion of a conductive contact, performing a selective deposition process to selectively form a layer of conductive material in the opening and on the conductive contact, performing an anneal process, depositing at least one conductive material above the selectively formed conductive material layer so as to over-fill the opening, and performing at least one planarization process so as to remove excess materials to thereby define a conductive via that is positioned in the opening and conductively coupled to the conductive contact. | 05-05-2016 |
20160133546 | METHOD OF MAKING A SEMICONDUCTOR DEVICE PACKAGE - A semiconductor device package includes a first substrate, which has a lower substrate surface and an upper substrate surface. A conductive dummy gate structure is disposed over the upper substrate surface. An interconnect structure is disposed over the conductive dummy gate structure. The interconnect structure includes a plurality of metal layers disposed within a dielectric structure and at least one of the metal layers is electrically coupled to the conductive dummy gate structure. A conductive through-substrate via extends from the lower substrate surface to an underside of the conductive dummy gate structure and is electrically coupled to the conductive dummy gate structure. | 05-12-2016 |
20160133576 | ULTRATHIN SUPERLATTICE OF MnO/Mn/MnN AND OTHER METAL OXIDE/METAL/METAL NITRIDE LINERS AND CAPS FOR COPPER LOW DIELECTRIC CONSTANT INTERCONNECTS - An electrical device comprising including an opening in a low-k dielectric material, and a copper including structure present within the opening for transmitting electrical current. A liner is present between the opening and the copper including structure. The liner includes a superlattice structure comprised of a metal oxide layer, a metal layer present on the metal oxide layer, and a metal nitride layer that is present on the metal layer. A first layer of the superlattice structure that is in direct contact with the low-k dielectric material is one of said metal oxide layer and a final layer of the superlattice structure that is in direct contact with the copper including structure is one of the metal nitride layers. | 05-12-2016 |
20160133577 | Wiring Structures and Methods of Forming the Same - A wiring structure includes a first insulation layer, a plurality of wiring patterns, a protection layer pattern and a second insulation layer. The first insulation layer may be formed on a substrate. A plurality of wiring patterns may be formed on the first insulation layer, and each of the wiring patterns may include a metal layer pattern and a barrier layer pattern covering a sidewall and a bottom surface of the metal layer pattern. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen. | 05-12-2016 |
20160141178 | High Speed Electroplating Metallic Conductors - One embodiment is a method for producing void-free electroplated metallic conductors inside openings by electrochemical deposition (ECD), said method including steps of: forming at least one opening in a substrate, said at least one opening having an aspect ratio in a range from 8:1 to 28:1; forming at least one barrier layer over the sidewalls of the at least one opening; depositing at least one seed layer over the at least one barrier layer; immersing the substrate in an electrolyte contained in an ECD cell, the ECD cell including at least one anode and a cathode, wherein the electrolyte includes plating metallic ions and at least one inhibitor additive; providing agitation of the electrolyte across the surface of the substrate by moving multiple non-contacting wiping blades relative to the substrate, wherein the agitation facilitates a limiting current density larger by at least an order of magnitude than a limiting current density without the agitation; and applying an average electroplating current density on the substrate, wherein the agitation, the concentrations of the metallic ions and the inhibitor additive, and the average electroplating current density are such as to produce void-free, electroplated metallic filling inside the at least one opening. | 05-19-2016 |
20160141241 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - The reliability of a copper wire is improved without inhibiting the wiring resistance of the copper wire. For example, another metallic element segregates in the boundary region between a copper film CUF | 05-19-2016 |
20160141247 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor device includes forming an opening in a first substrate and filling the opening with a metal to form a first connection electrode. The first substrate is then polished by chemical mechanical polishing under conditions such that a polishing rate of the metal is less that of the region surrounding the metal. The chemical mechanical polishing thereby causes the first connection electrode to protrude from the surface of the first substrate. The first substrate is stacked with a second substrate having a second connection electrode. The first and second connection electrodes are bonded by applying pressure and heating to a temperature that is below the melting point of the metal of the first connection electrode. | 05-19-2016 |
20160141249 | Semiconductor Devices - Semiconductor devices are provided. A semiconductor device includes a substrate, a first conductive structure on the substrate, and a second conductive structure on the first conductive structure. The semiconductor device includes first and second metal-diffusion-blocking layers on respective sidewalls of the first and second conductive structures. The semiconductor device includes an insulating layer between the first and second metal-diffusion-blocking layers. Moreover, the semiconductor device includes a metal-diffusion-shield pattern in the insulating layer and spaced apart from the first conductive structure. | 05-19-2016 |
20160141250 | BARRIER STRUCTURE - A semiconductor device includes a dielectric material and an interconnect structure. The semiconductor device further includes a barrier layer positioned between the dielectric material and the interconnect structure. The barrier layer includes two or more metals. Each metal of the two or more metals of the barrier layer is phase segregated from each other metal of the two or more metals. | 05-19-2016 |
20160148867 | NANOSCALE INTERCONNECT STRUCTURE - An interconnect structure includes a first dielectric material having an undercut region located at an upper surface thereof. A first conductive structure is located above a first area of the undercut region. The first conductive structure comprises a first conductive metal portion having a diffusion barrier portion located on one sidewall surface of the first conductive metal portion and having a metal liner located on another sidewall surface and a bottom surface of the first conductive metal portion. A second conductive structure is located above a second area of the undercut region. The second conductive structure comprises a second conductive material portion having a diffusion barrier portion located on one sidewall surface of the second conductive material portion and having a metal liner located on another sidewall surface and a bottom surface of the second conductive metal portion. A gap is located between the first and second conductive structures. | 05-26-2016 |
20160148874 | Method for Forming Interconnect Structure that Avoids via Recess - A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. The dielectric material layer is patterned to form a plurality of vias therein. A first metal layer is formed on the dielectric material layer, wherein the first metal layer fills the plurality of vias. The first metal layer is planarized so that the top thereof is co-planar with the top of the dielectric material layer to form a plurality of first metal features. A stop layer is formed on top of each of the plurality of first metal features, wherein the stop layer stops a subsequent etch from etching into the plurality of the first metal features. | 05-26-2016 |
20160148883 | Bond Pad Having Ruthenium Covering Passivation Sidewall - A method of forming bond pads includes providing a substrate including an integrated circuit (IC) device formed thereon having an oxidizable uppermost metal interconnect layer which provides a plurality of bond pads that are coupled to circuit nodes on the IC device. The plurality of bond pads include a metal bond pad area. At least one passivation layer provides a trench including dielectric sidewalls above the metal bond pad area. A ruthenium (Ru) layer is deposited directly on the dielectric sidewalls and directly on the metal bond pad area, which removes the need for a barrier layer lining the dielectric sidewalls of the trench. The Ru layer is patterned to provide a bond pad surface for the plurality of bond pads. | 05-26-2016 |
20160155701 | INTERCONNECT STRUCTURE FOR AN INTEGRATED CIRCUIT AND METHOD OF FABRICATING AN INTERCONNECT STRUCTURE | 06-02-2016 |
20160163587 | SELF-ALIGNED VIA INTERCONNECT STRUCTURES - A self-aligned via interconnect structures and methods of manufacturing thereof are disclosed. The method includes forming a wiring structure in a dielectric material. The method further includes forming a cap layer over a surface of the wiring structure and the dielectric material. The method further includes forming an opening in the cap layer to expose a portion of the wiring structure. The method further includes selectively growing a metal or metal-alloy via interconnect structure material on the exposed portion of the wiring structure, through the opening in the cap layer. The method further includes forming an upper wiring structure in electrical contact with the metal or metal-alloy via interconnect structure. | 06-09-2016 |
20160163588 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a semiconductor device and a method for manufacturing the same. Disclosed is a semiconductor device including a substrate, a conductive line on the substrate, and a seed layer between the substrate and the conductive line, the seed layer including cobalt titanium nitride. | 06-09-2016 |
20160163640 | INTERCONNECT STRUCTURES WITH FULLY ALIGNED VIAS - A structure having fully aligned via connecting metal lines on different Mx levels. The structure may include a first metal line and a second metal line in a first ILD, a cap covering the first ILD, the second metal line and a portion of the first metal line, a second ILD on the cap, and a via that electrically connects the first metal line to a third metal line, wherein the third metal line is above the first metal line and runs perpendicular to the first metal line, the via is fully aligned to the first metal line and the third metal line, and the via electrically connects the first metal line to the third metal line. | 06-09-2016 |
20160163645 | SEMICONDUCTOR STRUCTURE WITH BOTTOM-FREE LINER FOR TOP CONTACT - A semiconductor structure includes a lined bottom contact filled with conductive material. The structure further includes a layer of dielectric material surrounding sides of the lined bottom contact, a top contact on the bottom contact, the top contact having a partial liner only along sides thereof with an absence of the liner at a bottom thereof and being filled with the conductive material, and a layer of the dielectric material surrounding sides of the partially lined top contact. Fabrication of the bottom-liner free top contact includes providing a starting structure, the structure including a lined bottom contact filled with conductive material, being surrounded by a layer of dielectric material and having a planarized top surface. The method further includes creating a top layer of dielectric material above the planarized top surface, creating a layer of liner material above the top dielectric layer, creating a top contact opening to the bottom contact, lining the top contact opening with a liner material, removing the liner at a bottom of the top contact opening, exposing the bottom contact, while preserving a portion of the liner on the top dielectric layer sufficient to allow adhesion of a subsequent conductive material, and filling the contact opening with the conductive material. | 06-09-2016 |
20160163647 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device comprises a conductive layer, a first insulating film, a barrier metal, a contact electrode, and a surface electrode. The first insulating film is located on the conductive layer and comprises a contact hole reaching the conductive layer. At least a surface part of the first insulating film is a BPSG film. The barrier metal covers an inner surface of the contact hole. The contact electrode is located in the contact hole and on the barrier metal. The surface electrode is located on the BPSG film and the contact electrode. The barrier metal is not interposed between the BPSG film and the surface electrode so that the surface electrode is directly in contact with the BPSG film. At least a part of the surface electrode is a bonding pad. | 06-09-2016 |
20160172301 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR | 06-16-2016 |
20160181151 | TITANIUM TUNGSTEN LINER USED WITH COPPER INTERCONNECTS | 06-23-2016 |
20160181184 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD | 06-23-2016 |
20160181196 | PRESERVATION OF FINE PITCH REDISTRIBUTION LINES | 06-23-2016 |
20160181203 | ELECTRIC CONTACT STRUCTURE HAVING A DIFFUSION BARRIER FOR AN ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE ELECTRIC CONTACT STRUCTURE | 06-23-2016 |
20160190065 | INTERCONNECT STRUCTURE WITH MISALIGNED METAL LINES COUPLED USING DIFFERENT INTERCONNECT LAYER - In some embodiments, an interconnect structure includes a first metal line, a second metal line and a first connection structure. The first metal line is formed in a first interconnect layer, extends in length substantially along a first direction and ends at a first end portion. The second metal line is formed in the first interconnect layer, starts from a second end portion and extends in length substantially along the first direction. The second metal line is misaligned with the first metal line in the first direction. The first connection structure couples the first metal line to the second metal line. The first connection structure includes a first end-to-end portion formed in a second interconnect layer different from the first interconnect layer, and is overlapped with the first end portion and the second end portion. | 06-30-2016 |
20160197038 | SELF-ALIGNED VIA INTERCONNECT STRUCTURES | 07-07-2016 |
20160197042 | SEMICONDUCTOR DEVICES INCLUDING SPACERS | 07-07-2016 |
20160204059 | Conductive Lines with Protective Sidewalls | 07-14-2016 |
20160204060 | SELF-ALIGNED REPAIRING PROCESS FOR BARRIER LAYER | 07-14-2016 |
20160204066 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF | 07-14-2016 |
20160204068 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD | 07-14-2016 |
20160204069 | SEMICONDUCTOR DEVICE WITH REDUCED VIA RESISTANCE | 07-14-2016 |
20160254222 | METALLIZATION OF THE WAFER EDGE FOR OPTIMIZED ELECTROPLATING PERFORMANCE ON RESISTIVE SUBSTRATES | 09-01-2016 |
20160254225 | COPPER ETCHING INTEGRATION SCHEME | 09-01-2016 |
20160254226 | CAPPING LAYER FOR IMPROVED DEPOSITION SELECTIVITY | 09-01-2016 |
20160379926 | Semiconductor Wafer Backside Metallization With Improved Backside Metal Adhesion - A method of fabricating a semiconductor structure includes: grinding a backside surface of a semiconductor substrate such that the backside surface has a relatively high average roughness (Ra) (when compared with a backside surface subjected to chemical mechanical polishing (CMP)), and then, forming a backside metal structure on the backside surface while the backside surface has the relatively high average roughness. The backside surface can have an average roughness in the range of about 5 to 100 nanometers (or alternately, in the range of about 20 to 40 nanometers) when the backside metal structure is formed. The backside metal structure may be electrically coupled to through silicon vias (TSVs), which supply ground to semiconductor devices fabricated on a front side of the semiconductor substrate. | 12-29-2016 |
20160379927 | OPTIMIZED WIRES FOR RESISTANCE OR ELECTROMIGRATION - Optimized metal wires for resistance or electromigration, methods of manufacturing thereof and design methodologies are disclosed. The method includes depositing metal material within openings and on a surface of dielectric material resulting in metal filled openings and a topography of recessed areas aligned with the metal filled openings. The method further includes depositing an alloying material over the metal material, including within the recessed areas. The method further includes planarizing the metal material, leaving the alloying material within the recessed areas. The method further includes diffusing the alloying material into the metal material forming alloyed regions self-aligned with the metal filled openings. | 12-29-2016 |
20170236748 | ION FLOW BARRIER STRUCTURE FOR INTERCONNECT METALLIZATION | 08-17-2017 |
20170236749 | SELF-FORMING BARRIER FOR COBALT INTERCONNECTS | 08-17-2017 |
20170236781 | SELF-FORMING BARRIER FOR COBALT INTERCONNECTS | 08-17-2017 |
20170236784 | ION FLOW BARRIER STRUCTURE FOR INTERCONNECT METALLIZATION | 08-17-2017 |
20180025941 | INTERCONNECT STRUCTURE AND FABRICATION THEREOF | 01-25-2018 |
20180025969 | METAL CAP INTEGRATION BY LOCAL ALLOYING | 01-25-2018 |
20180025989 | FORMATION OF LINER AND METAL CONDUCTOR | 01-25-2018 |
20190148150 | METHODS FOR FORMING CAPPING PROTECTION FOR AN INTERCONNECTION STRUCTURE | 05-16-2019 |
20190148153 | Atomic Layer Deposition Based Process for Contact Barrier Layer | 05-16-2019 |
20190148303 | Low-Temperature Diffusion Doping of Copper Interconnects Independent of Seed Layer Composition | 05-16-2019 |
20190148307 | CAPPING LAYER FOR IMPROVED DEPOSITION SELECTIVITY | 05-16-2019 |