Class / Patent application number | Description | Number of patent applications / Date published |
257684000 | With semiconductor element forming part (e.g., base, of housing) | 40 |
20080211076 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device capable of elevating a yield rate of products to improve the productivity and also ensuring high reliability in production and a manufacturing method of the semiconductor device are provided. The semiconductor device includes a semiconductor substrate | 09-04-2008 |
20080224292 | INTERPOSER STRUCTURE WITH EMBEDDED CAPACITOR STRUCTURE, AND METHODS OF MAKING SAME - A device is disclosed which includes an interposer, at least one capacitor formed at least partially within an opening formed in the interposer and an integrated circuit that is operatively coupled to the interposer. A method is disclosed which includes obtaining an interposer having at least one capacitor formed at least partially within an opening in the interposer and operatively coupling an integrated circuit to the interposer. A method is also disclosed which includes obtaining an interposer comprising a dielectric material, forming an opening in the interposer and forming a capacitor that is positioned at least partially within the opening. | 09-18-2008 |
20080237822 | Microelectronic die having nano-particle containing passivation layer and package including same - A microelectronic die and a package including the die. The die comprises a die substrate including a base and a die passivation layer disposed on the base. The die passivation layer includes a nanocomposite including a matrix and nanoparticles dispersed within the matrix. | 10-02-2008 |
20080283990 | METHOD OF FABRICATION OF AI/GE BONDING IN A WAFER PACKAGING ENVIRONMENT AND A PRODUCT PRODUCED THEREFROM - A method of bonding of germanium to aluminum between two substrates to create a robust electrical and mechanical contact is disclosed. An aluminum-germanium bond has the following unique combination of attributes: (1) it can form a hermetic seal; (2) it can be used to create an electrically conductive path between two substrates; (3) it can be patterned so that this conduction path is localized; (4) the bond can be made with the aluminum that is available as standard foundry CMOS process. This has the significant advantage of allowing for wafer-level bonding or packaging without the addition of any additional process layers to the CMOS wafer. | 11-20-2008 |
20080290490 | Semiconductor device and method for manufacturing the same - A semiconductor device includes: a first substrate made of semiconductor and having first regions, which are insulated from each other and disposed in the first substrate; and a second substrate having electric conductivity and having second regions and insulation trenches. Each insulation trench penetrates the second substrate so that the second regions are insulated from each other. The first substrate provides a base substrate, and the second substrate provides a cap substrate. The second substrate is bonded to the first substrate so that a sealed space is provided between a predetermined surface region of the first substrate and the second substrate. The second regions include an extraction conductive region, which is coupled with a corresponding first region. | 11-27-2008 |
20090121335 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE INTEGRATION - An integrated circuit package system comprising: providing a substrate having a cavity; sealing a package over the cavity of the substrate; and forming an encapsulant over the package and a portion of the substrate substantially preventing the encapsulant from forming in the cavity. | 05-14-2009 |
20090174050 | IN-PLANE SILICON HEAT SPREADER AND METHOD THEREFOR - A method of (and heat spreader for) dissipating heat from a heat source, includes providing a plurality of heat flux paths from the heat source, to remove the heat from the heat source. | 07-09-2009 |
20090267204 | EDGE SEAL FOR A SEMICONDUCTOR DEVICE AND METHOD THEREFOR - In one embodiment, an edge seal region of a semiconductor die is formed by forming a first dielectric layer on a surface of a semiconductor substrate near an edge of the semiconductor die and extending across into a scribe grid region of the semiconductor substrate. Another dielectric layer is formed overlying the first dielectric layer. An opening is formed through the first and second dielectric layers. The second dielectric layer is used as a mask for forming a doped region on the semiconductor substrate through the opening. A metal is formed that electrically contacts the doped region and an exterior edge of the first dielectric layer within the opening. | 10-29-2009 |
20090321903 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - This invention is directed to offer a semiconductor device in which a cavity space is easily provided in a specific region when a supporting member is bonded to a semiconductor substrate through an adhesive layer, and its manufacturing method. A resist layer is applied to an entire top surface of the semiconductor substrate | 12-31-2009 |
20090321904 | Semiconductor device and semiconductor integrated circuit - The present invention provides a semiconductor device, including: a semiconductor substrate having a circuit formed thereon; a mounting substrate cemented to a rear face of the semiconductor substrate; a plurality of pads arranged in a linearly juxtaposed relationship with each other in a direction perpendicular to a peripheral edge side of the semiconductor substrate which is nearest to the pads on a main face of the semiconductor substrate and electrically connected to the circuit in a corresponding relationship to a signal, a power supply voltage and a reference signal; a plurality of wires individually cemented at one end thereof to the pads; and a plurality of wire cemented elements formed on the mounting substrate and cemented to the other end of the wires. | 12-31-2009 |
20100109137 | Layered chip package with heat sink - A layered chip package includes: a plurality of layer portions stacked, each of the layer portions including a semiconductor chip; and a heat sink. Each of the plurality of layer portions has a top surface, a bottom surface, and four side surfaces. The heat sink has at least one first portion, and a second portion coupled to the at least one first portion. The at least one first portion is adjacent to the top surface or the bottom surface of at least one of the layer portions. The second portion is adjacent to one of the side surfaces of each of at least two of the plurality of layer portions. | 05-06-2010 |
20100117208 | SEMICONDUCTOR PACKAGE FOR IMPROVING CHARACTERISTICS FOR TRANSMITTING SIGNALS AND POWER - A semiconductor package includes a semiconductor chip having a first region and a second region. Bonding pads are formed and through-holes are defined in the first and second regions. Insulation layers are formed on sidewalls of the through-holes, and through-electrodes formed in the through-holes and connected with corresponding bonding pads. The insulation layers formed in the first and second regions have different thicknesses or dielectric constants. | 05-13-2010 |
20100127371 | POWER SEMICONDUCTOR MODULE WITH SEGMENTED BASE PLATE - A power semiconductor module with segmented base plate. One embodiment provides a semiconductor module including a base plate and at least two circuit carriers. The base plate includes at least two base plate segments spaced distant from one another. Each of the circuit carriers includes a ceramic substrate provided with at least a first metallization layer. Each of the circuit carriers is arranged on exactly one of the base plate segments. At least two of the circuit carriers are spaced distant from one another. | 05-27-2010 |
20100148333 | PACKAGING MILLIMETER WAVE MODULES - A module, which in one embodiment may be a packaged millimeter waver module, includes a semiconductor lid portion; a packaging portion attached to the lid portion, wherein the packaging portion comprises a plurality of vias, a carrier portion, wherein a first semiconductor die is attached to the carrier portion, the packaging portion is attached to the carrier portion so that the packaging portion is over the carrier portion and the semiconductor die is within an opening in the packaging portion, and the lid portion and the carrier portion form an first air gap around the first semiconductor device. | 06-17-2010 |
20100187669 | PROCESS FOR PACKAGING COMPONENTS, AND PACKAGED COMPONENTS - A wafer level packaging process for packaging components is provided. The process includes permanently connecting a functional side of a base substrate to a covering substrate at wafer level so that a plurality of functional regions on the functional side are in each case packaged to form a wafer level package, the plurality of functional regions being spaced apart from one another on the functional side; producing contact-connection recesses in the base substrate to uncover contact surfaces on the base substrate from a back surface of the base substrate; dividing the base substrate into body regions and connection regions; thinning the body regions or the connection regions until the wafer level package has different thicknesses in the body regions and the connection regions; and dicing wafer level package into chips along predefined cutting lines between the plurality of functional regions. | 07-29-2010 |
20100314733 | APPARATUS FOR RESTRICTING MOISTURE INGRESS - Apparatus and methods to protect circuitry from moisture ingress, e.g., using a metallic structure as part of a moisture ingress barrier. | 12-16-2010 |
20110018113 | Method for packaging micromachined devices - A method for packaging micromachined devices fabricated by MEMS and semiconductor process is disclosed in this invention. The method employed etching technique to etch a trench surrounding the micromachined components on each chip of the first wafer down to the bottom interconnection metal layer. The said trench can accommodate the solder of flip-chip packaging. On each chip of the second wafer, or called as the second chip, a surrounding copper pillar wall corresponding to the trench on the first chip is deposited. By wafer-level packaging, the trench on the first chip is aligned to the pillar wall, and then bonded together with elevated temperature. The face-to-face chamber formed between two chips can allow the movement of the micromachined structures. Further, the signal or power connections between two chips can be established by providing several discrete pillar bumps. | 01-27-2011 |
20110024887 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THROUGH SILICON VIA BASE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base having a through-conductor spanning the height of the base, and having an insulator protecting the base and the through-conductor; mounting a chip over the base and connected to the base with a first interconnect; forming a second interconnect above the base and horizontally beside the chip; and encapsulating the chip, the first interconnect, and the second interconnect with an encapsulation. | 02-03-2011 |
20110180917 | MICROELECTRONIC ASSEMBLY WITH AN EMBEDDED WAVEGUIDE ADAPTER AND METHOD FOR FORMING THE SAME - A microelectronic assembly and a method for forming a microelectronic assembly are provided. A semiconductor substrate ( | 07-28-2011 |
20110193210 | IMAGE SENSOR PACKAGE WITH TRENCH INSULATOR AND FABRICATION METHOD THEREOF - The invention provides a chip package and a fabrication method thereof. In one embodiment, the chip package includes: a substrate having a semiconductor device and a conductive pad thereon; an insulator ring filling a trench formed in the substrate, wherein the insulator ring surrounds an intermediate layer below the conductive pad; and a conductive layer disposed below a backside of the substrate and electrically connected to the conductive pad. | 08-11-2011 |
20110210435 | MEMS DEVICES - A method of manufacturing a MEMS device comprises forming a MEMS device element | 09-01-2011 |
20120056312 | Semiconductor Device and Method of Forming TSV Semiconductor Wafer with Embedded Semiconductor Die - A semiconductor device has a TSV semiconductor wafer with a cavity formed in a first surface of the wafer. A second cavity can be formed in a second surface of the wafer. A plurality of semiconductor die is mounted within the cavities. The semiconductor die can be mounted side-by-side and/or stacked within the cavity. Conductive TSV can be formed through the die. An encapsulant is deposited within the cavity over the die. A CTE of the die is similar to a CTE of the encapsulant. A first interconnect structure is formed over a first surface of the encapsulant and wafer. A second interconnect structure is formed over a second surface of the encapsulant and wafer. The first and second interconnect structure are electrically connected to the TSV wafer. A second semiconductor die can be mounted over the first interconnect structure with encapsulant deposited over the second die. | 03-08-2012 |
20120068325 | SUBSTRATE BONDING WITH METAL GERMANIUM SILICON MATERIAL - In one embodiment, a semiconductor structure including a first substrate, a semiconductor device on the first substrate, a second substrate, and a conductive bond between the first substrate and the second substrate that surrounds the semiconductor device to seal the semiconductor device between the first substrate and the second substrate. The conductive bond comprises metal, silicon, and germanium. A percentage by atomic weight of silicon in the conductive bond is greater than 5%. | 03-22-2012 |
20120074554 | BOND RING FOR A FIRST AND SECOND SUBSTRATE - The present disclosure provides a device having a plurality of bonded substrates. The substrates are bonded by a first bond ring and a second bond ring. In an embodiment, the first bond ring is a eutectic bond and the second bond ring is at least one of an organic material and a eutectic bond. The second bond ring encircles the first bond ring. The first bond ring provides a hermetic region of the device. In a further embodiment, a plurality of wafers are bonded which include a third bond ring disposed at the periphery of the wafers. | 03-29-2012 |
20120074555 | SEMICONDUCTOR PACKAGE INCLUDING CAP - A semiconductor package comprises: a substrate comprising a semiconductor device; a cap comprising a seal ring disposed over a surface of the cap; and a gap between the substrate and the surface of the cap. The seal ring comprises a tread comprising at least two columns. | 03-29-2012 |
20120112335 | NOVEL BONDING PROCESS AND BONDED STRUCTURES - A sealing and bonding material structure for joining semiconductor wafers having monolithically integrated components. The sealing and bonding material are provided in strips forming closed loops. There are provided at least two concentric sealing strips on one wafer. The strips are laid out so as to surround the component(s) on the wafers to be sealed off when wafers are bonded together. The material in the strips is a material bonding the semiconductor wafers together and sealing off the monolithically integrated components when subjected to force and optionally heating. A monolithically integrated electrical and/or mechanical and/or fluidic and/or optical device including a first substrate and a second substrate, bonded together with the sealing and bonding structure, and a method of providing a sealing and bonding material structure on at least one of two wafers and applying a force and optionally heat to the wafers to join them are described. | 05-10-2012 |
20120235290 | POWER MODULE FOR AN AUTOMOBILE - The invention relates to a power module ( | 09-20-2012 |
20120261809 | CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - An embodiment of the invention provides a manufacturing method of a chip package including: providing a semiconductor wafer having a plurality of device regions separated by a plurality of scribe lines; bonding a package substrate to the semiconductor wafer wherein a spacer layer is disposed therebetween and defines a plurality of cavities respectively exposing the device regions and the spacer layer has a plurality of through holes neighboring the edge of the semiconductor wafer; filling an adhesive material in the through holes wherein the material of the spacer layer is adhesive and different from the adhesive material; and dicing the semiconductor wafer, the package substrate and the spacer layer along the scribe lines to form a plurality of chip packages separated from each other. | 10-18-2012 |
20130154077 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A chip package includes: a substrate having a first and a second surfaces; a device region formed in or disposed on the substrate; a dielectric layer disposed on the first surface; at least one conducting pad disposed in the dielectric layer and electrically connected to the device region; a planar layer disposed on the dielectric layer, wherein a vertical distance between upper surfaces of the planar layer and the conducting pad is larger than about 2 μm; a transparent substrate disposed on the first surface; a first spacer layer disposed between the transparent substrate and the planar layer; and a second spacer layer disposed between the transparent substrate and the substrate and extending into an opening of the dielectric layer to contact with the conducting pad, wherein there is substantially no gap between the second spacer layer and the conducting pad. | 06-20-2013 |
20130285228 | Glass Frit Wafer Bond Protective Structure - A bonded semiconductor device comprising a support substrate, a semiconductor device located with respect to one side of the support substrate, a cap substrate overlying the support substrate and the device, a glass frit bond ring between the support substrate and the cap substrate, an electrically conductive ring between the support substrate and the cap substrate. The electrically conductive ring forms an inner ring around the semiconductor device and the glass frit bond ring forms an outer bond ring around the semiconductor device. | 10-31-2013 |
20140008779 | WAFER LEVEL PACKAGE, CHIP SIZE PACKAGE DEVICE AND METHOD OF MANUFACTURING WAFER LEVEL PACKAGE - A wafer level package has a first wafer having a plurality of chips mounted or formed thereon in a plane, and a second wafer that is opposed to the first wafer. The first wafer and the second wafer are joined while a seal frame that seals a periphery of each chip is interposed therebetween. A gap is formed between the seal frames of the chips adjacent to each other. A partial connect part that partially connects the seal frames to each other is provided in the gap formed between the seal frames of the chips adjacent to each other. | 01-09-2014 |
20140021595 | SEMICONDUCTOR COMPONENT SUPPORT AND SEMICONDUCTOR DEVICE - A semiconductor component support is provided which includes a component support portion for a semiconductor component to be mounted on the semiconductor component support portion. The component support portion includes a metal part that includes an opening in plan view. The opening of the metal part includes first and second sections. The second section communicates with the first section, and is arranged outside the first section. The second section is wider than the first section. The first section can be at least partially positioned directly under a mount-side main surface of the semiconductor component. | 01-23-2014 |
20140084439 | SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a semiconductor chip mounted on the substrate, a plate-like member that is fixed on the semiconductor chip and has a thermal expansion coefficient different from that of the substrate, and a first adhesive that is provided between the substrate and the plate-like member, the first adhesive being connected to the plate-like member and separated from the substrate, or being separated from the plate-like member and connected to the substrate. | 03-27-2014 |
20140131850 | MICROCHIP WITH BLOCKING APPARATUS AND METHOD OF FABRICATING MICROCHIP - A microchip has a base die with a conductive interconnect and an isolation trench around at least a portion of the conductive interconnect, and a cap die secured to the base die. A seal, formed from a metal material, is positioned between the base die and the cap die to secure them together. The microchip also has a blocking apparatus, between the isolation trench and the metal seal, that at least in part prevents the metal material from contacting the interconnect. | 05-15-2014 |
20140203422 | Microchip with Blocking Apparatus and Method of Fabricating Microchip - A microchip has a base die with a conductive interconnect and an isolation trench around at least a portion of the conductive interconnect, and a cap die secured to the base die. A seal, formed from a metal material, is positioned between the base die and the cap die to secure them together. The microchip also has a blocking apparatus, between the isolation trench and the metal seal, that at least in part prevents the metal material from contacting the interconnect. | 07-24-2014 |
20140353810 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate provided with a predetermined element and having wirings formed on its main surface connected to back wirings by a plurality of through silicon vias (TSVs), and a conductive cover which covers the main surface of the semiconductor substrate. The semiconductor substrate and the conductive cover are bonded to each other with a conductive bonding member. The TSV bonded to the conductive cover with the conductive bonding member is connected to an external electrode pad to which a ground potential is supplied. | 12-04-2014 |
20160148879 | METHOD FOR FABRICATING AN ELECTRONIC DEVICE AND A STACKED ELECTRONIC DEVICE - A method for fabricating an electronic device, and an electronic device in a stacked configuration, includes a rear face of an integrated-circuit chip that is fixed to a front face of a support wafer. A protective wafer is located facing and at a distance from the front face of the chip, and an infused adhesive is interposed between the chip and the protective wafer and located on a zone of the front face of the chip outside a central region of this front face. The infused adhesive includes a curable adhesive and solid spacer elements infused in the curable adhesive. An obstruction barrier is arranged between the chip and the protective wafer and is disposed outside the central region of the front face of the chip. An encapsulation ring surrounds the chip, the protective wafer and the obstruction barrier. | 05-26-2016 |
20160181229 | MOUNTING STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | 06-23-2016 |
20160204057 | SEMICONDUCTOR DEVICE | 07-14-2016 |
20190148261 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF | 05-16-2019 |